drivers/net/ethernet/microchip/encx24j600_hw.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /**
   3  * encx24j600_hw.h: Register definitions
   4  *
   5  */
   6
   7 #ifndef _ENCX24J600_HW_H
   8 #define _ENCX24J600_HW_H
   9
  10 struct encx24j600_context {
  11         struct spi_device *spi;
  12         struct regmap *regmap;
  13         struct regmap *phymap;
  14         struct mutex mutex; /* mutex to protect access to regmap */
  15         int bank;
  16 };
  17
  18 void devm_regmap_init_encx24j600(struct device *dev,
  19                                  struct encx24j600_context *ctx);
  20
  21 /* Single-byte instructions */
  22 #define BANK_SELECT(bank) (0xC0 | ((bank & (BANK_MASK >> BANK_SHIFT)) << 1))
  23 #define B0SEL 0xC0              /* Bank 0 Select */
  24 #define B1SEL 0xC2              /* Bank 1 Select */
  25 #define B2SEL 0xC4              /* Bank 2 Select */
  26 #define B3SEL 0xC6              /* Bank 3 Select */
  27 #define SETETHRST 0xCA          /* System Reset */
  28 #define FCDISABLE 0xE0          /* Flow Control Disable */
  29 #define FCSINGLE 0xE2           /* Flow Control Single */
  30 #define FCMULTIPLE 0xE4         /* Flow Control Multiple */
  31 #define FCCLEAR 0xE6            /* Flow Control Clear */
  32 #define SETPKTDEC 0xCC          /* Decrement Packet Counter */
  33 #define DMASTOP 0xD2            /* DMA Stop */
  34 #define DMACKSUM 0xD8           /* DMA Start Checksum */
  35 #define DMACKSUMS 0xDA          /* DMA Start Checksum with Seed */
  36 #define DMACOPY 0xDC            /* DMA Start Copy */
  37 #define DMACOPYS 0xDE           /* DMA Start Copy and Checksum with Seed */
  38 #define SETTXRTS 0xD4           /* Request Packet Transmission */
  39 #define ENABLERX 0xE8           /* Enable RX */
  40 #define DISABLERX 0xEA          /* Disable RX */
  41 #define SETEIE 0xEC             /* Enable Interrupts */
  42 #define CLREIE 0xEE             /* Disable Interrupts */
  43
  44 /* Two byte instructions */
  45 #define RBSEL 0xC8              /* Read Bank Select */
  46
  47 /* Three byte instructions */
  48 #define WGPRDPT 0x60            /* Write EGPRDPT */
  49 #define RGPRDPT 0x62            /* Read EGPRDPT */
  50 #define WRXRDPT 0x64            /* Write ERXRDPT */
  51 #define RRXRDPT 0x66            /* Read ERXRDPT */
  52 #define WUDARDPT 0x68           /* Write EUDARDPT */
  53 #define RUDARDPT 0x6A           /* Read EUDARDPT */
  54 #define WGPWRPT 0x6C            /* Write EGPWRPT */
  55 #define RGPWRPT 0x6E            /* Read EGPWRPT */
  56 #define WRXWRPT 0x70            /* Write ERXWRPT */
  57 #define RRXWRPT 0x72            /* Read ERXWRPT */
  58 #define WUDAWRPT 0x74           /* Write EUDAWRPT */
  59 #define RUDAWRPT 0x76           /* Read EUDAWRPT */
  60
  61 /* n byte instructions */
  62 #define RCRCODE 0x00
  63 #define WCRCODE 0x40
  64 #define BFSCODE 0x80
  65 #define BFCCODE 0xA0
  66 #define RCR(addr) (RCRCODE | (addr & ADDR_MASK)) /* Read Control Register */
  67 #define WCR(addr) (WCRCODE | (addr & ADDR_MASK)) /* Write Control Register */
  68 #define RCRU 0x20               /* Read Control Register Unbanked */
  69 #define WCRU 0x22               /* Write Control Register Unbanked */
  70 #define BFS(addr) (BFSCODE | (addr & ADDR_MASK)) /* Bit Field Set */
  71 #define BFC(addr) (BFCCODE | (addr & ADDR_MASK)) /* Bit Field Clear */
  72 #define BFSU 0x24               /* Bit Field Set Unbanked */
  73 #define BFCU 0x26               /* Bit Field Clear Unbanked */
  74 #define RGPDATA 0x28            /* Read EGPDATA */
  75 #define WGPDATA 0x2A            /* Write EGPDATA */
  76 #define RRXDATA 0x2C            /* Read ERXDATA */
  77 #define WRXDATA 0x2E            /* Write ERXDATA */
  78 #define RUDADATA 0x30           /* Read EUDADATA */
  79 #define WUDADATA 0x32           /* Write EUDADATA */
  80
  81 #define SFR_REG_COUNT   0xA0
  82
  83 /* ENC424J600 Control Registers
  84  * Control register definitions are a combination of address
  85  * and bank number
  86  * - Register address (bits 0-4)
  87  * - Bank number (bits 5-6)
  88  */
  89 #define ADDR_MASK 0x1F
  90 #define BANK_MASK 0x60
  91 #define BANK_SHIFT 5
  92
  93 /* All-bank registers */
  94 #define EUDAST 0x16
  95 #define EUDAND 0x18
  96 #define ESTAT 0x1A
  97 #define EIR 0x1C
  98 #define ECON1 0x1E
  99
 100 /* Bank 0 registers */
 101 #define ETXST (0x00 | 0x00)
 102 #define ETXLEN (0x02 | 0x00)
 103 #define ERXST (0x04 | 0x00)
 104 #define ERXTAIL (0x06 | 0x00)
 105 #define ERXHEAD (0x08 | 0x00)
 106 #define EDMAST (0x0A | 0x00)
 107 #define EDMALEN (0x0C | 0x00)
 108 #define EDMADST (0x0E | 0x00)
 109 #define EDMACS (0x10 | 0x00)
 110 #define ETXSTAT (0x12 | 0x00)
 111 #define ETXWIRE (0x14 | 0x00)
 112
 113 /* Bank 1 registers */
 114 #define EHT1 (0x00 | 0x20)
 115 #define EHT2 (0x02 | 0x20)
 116 #define EHT3 (0x04 | 0x20)
 117 #define EHT4 (0x06 | 0x20)
 118 #define EPMM1 (0x08 | 0x20)
 119 #define EPMM2 (0x0A | 0x20)
 120 #define EPMM3 (0x0C | 0x20)
 121 #define EPMM4 (0x0E | 0x20)
 122 #define EPMCS (0x10 | 0x20)
 123 #define EPMO (0x12 | 0x20)
 124 #define ERXFCON (0x14 | 0x20)
 125
 126 /* Bank 2 registers */
 127 #define MACON1 (0x00 | 0x40)
 128 #define MACON2 (0x02 | 0x40)
 129 #define MABBIPG (0x04 | 0x40)
 130 #define MAIPG (0x06 | 0x40)
 131 #define MACLCON (0x08 | 0x40)
 132 #define MAMXFL (0x0A | 0x40)
 133 #define MICMD (0x12 | 0x40)
 134 #define MIREGADR (0x14 | 0x40)
 135
 136 /* Bank 3 registers */
 137 #define MAADR3 (0x00 | 0x60)
 138 #define MAADR2 (0x02 | 0x60)
 139 #define MAADR1 (0x04 | 0x60)
 140 #define MIWR (0x06 | 0x60)
 141 #define MIRD (0x08 | 0x60)
 142 #define MISTAT (0x0A | 0x60)
 143 #define EPAUS (0x0C | 0x60)
 144 #define ECON2 (0x0E | 0x60)
 145 #define ERXWM (0x10 | 0x60)
 146 #define EIE (0x12 | 0x60)
 147 #define EIDLED (0x14 | 0x60)
 148
 149 /* Unbanked registers */
 150 #define EGPDATA (0x00 | 0x80)
 151 #define ERXDATA (0x02 | 0x80)
 152 #define EUDADATA (0x04 | 0x80)
 153 #define EGPRDPT (0x06 | 0x80)
 154 #define EGPWRPT (0x08 | 0x80)
 155 #define ERXRDPT (0x0A | 0x80)
 156 #define ERXWRPT (0x0C | 0x80)
 157 #define EUDARDPT (0x0E | 0x80)
 158 #define EUDAWRPT (0x10 | 0x80)
 159
 160
 161 /* Register bit definitions */
 162 /* ESTAT */
 163 #define INT (1 << 15)
 164 #define FCIDLE (1 << 14)
 165 #define RXBUSY (1 << 13)
 166 #define CLKRDY (1 << 12)
 167 #define PHYDPX (1 << 10)
 168 #define PHYLNK (1 << 8)
 169
 170 /* EIR */
 171 #define CRYPTEN (1 << 15)
 172 #define MODEXIF (1 << 14)
 173 #define HASHIF (1 << 13)
 174 #define AESIF (1 << 12)
 175 #define LINKIF (1 << 11)
 176 #define PKTIF (1 << 6)
 177 #define DMAIF (1 << 5)
 178 #define TXIF (1 << 3)
 179 #define TXABTIF (1 << 2)
 180 #define RXABTIF (1 << 1)
 181 #define PCFULIF (1 << 0)
 182
 183 /* ECON1 */
 184 #define MODEXST (1 << 15)
 185 #define HASHEN (1 << 14)
 186 #define HASHOP (1 << 13)
 187 #define HASHLST (1 << 12)
 188 #define AESST (1 << 11)
 189 #define AESOP1 (1 << 10)
 190 #define AESOP0 (1 << 9)
 191 #define PKTDEC (1 << 8)
 192 #define FCOP1 (1 << 7)
 193 #define FCOP0 (1 << 6)
 194 #define DMAST (1 << 5)
 195 #define DMACPY (1 << 4)
 196 #define DMACSSD (1 << 3)
 197 #define DMANOCS (1 << 2)
 198 #define TXRTS (1 << 1)
 199 #define RXEN (1 << 0)
 200
 201 /* ETXSTAT */
 202 #define LATECOL (1 << 10)
 203 #define MAXCOL (1 << 9)
 204 #define EXDEFER (1 << 8)
 205 #define ETXSTATL_DEFER (1 << 7)
 206 #define CRCBAD (1 << 4)
 207 #define COLCNT_MASK 0xF
 208
 209 /* ERXFCON */
 210 #define HTEN (1 << 15)
 211 #define MPEN (1 << 14)
 212 #define NOTPM (1 << 12)
 213 #define PMEN3 (1 << 11)
 214 #define PMEN2 (1 << 10)
 215 #define PMEN1 (1 << 9)
 216 #define PMEN0 (1 << 8)
 217 #define CRCEEN (1 << 7)
 218 #define CRCEN (1 << 6)
 219 #define RUNTEEN (1 << 5)
 220 #define RUNTEN (1 << 4)
 221 #define UCEN (1 << 3)
 222 #define NOTMEEN (1 << 2)
 223 #define MCEN (1 << 1)
 224 #define BCEN (1 << 0)
 225
 226 /* MACON1 */
 227 #define LOOPBK (1 << 4)
 228 #define RXPAUS (1 << 2)
 229 #define PASSALL (1 << 1)
 230
 231 /* MACON2 */
 232 #define MACON2_DEFER (1 << 14)
 233 #define BPEN (1 << 13)
 234 #define NOBKOFF (1 << 12)
 235 #define PADCFG2 (1 << 7)
 236 #define PADCFG1 (1 << 6)
 237 #define PADCFG0 (1 << 5)
 238 #define TXCRCEN (1 << 4)
 239 #define PHDREN (1 << 3)
 240 #define HFRMEN (1 << 2)
 241 #define MACON2_RSV1 (1 << 1)
 242 #define FULDPX (1 << 0)
 243
 244 /* MAIPG */
 245 /* value of the high byte is given by the reserved bits,
 246  * value of the low byte is recomended setting of the
 247  * IPG parameter.
 248  */
 249 #define MAIPGH_VAL 0x0C
 250 #define MAIPGL_VAL 0x12
 251
 252 /* MIREGADRH */
 253 #define MIREGADR_VAL (1 << 8)
 254
 255 /* MIREGADRL */
 256 #define PHREG_MASK 0x1F
 257
 258 /* MICMD */
 259 #define MIISCAN (1 << 1)
 260 #define MIIRD (1 << 0)
 261
 262 /* MISTAT */
 263 #define NVALID (1 << 2)
 264 #define SCAN (1 << 1)
 265 #define BUSY (1 << 0)
 266
 267 /* ECON2 */
 268 #define ETHEN (1 << 15)
 269 #define STRCH (1 << 14)
 270 #define TXMAC (1 << 13)
 271 #define SHA1MD5 (1 << 12)
 272 #define COCON3 (1 << 11)
 273 #define COCON2 (1 << 10)
 274 #define COCON1 (1 << 9)
 275 #define COCON0 (1 << 8)
 276 #define AUTOFC (1 << 7)
 277 #define TXRST (1 << 6)
 278 #define RXRST (1 << 5)
 279 #define ETHRST (1 << 4)
 280 #define MODLEN1 (1 << 3)
 281 #define MODLEN0 (1 << 2)
 282 #define AESLEN1 (1 << 1)
 283 #define AESLEN0 (1 << 0)
 284
 285 /* EIE */
 286 #define INTIE (1 << 15)
 287 #define MODEXIE (1 << 14)
 288 #define HASHIE (1 << 13)
 289 #define AESIE (1 << 12)
 290 #define LINKIE (1 << 11)
 291 #define PKTIE (1 << 6)
 292 #define DMAIE (1 << 5)
 293 #define TXIE (1 << 3)
 294 #define TXABTIE (1 << 2)
 295 #define RXABTIE (1 << 1)
 296 #define PCFULIE (1 << 0)
 297
 298 /* EIDLED */
 299 #define LACFG3 (1 << 15)
 300 #define LACFG2 (1 << 14)
 301 #define LACFG1 (1 << 13)
 302 #define LACFG0 (1 << 12)
 303 #define LBCFG3 (1 << 11)
 304 #define LBCFG2 (1 << 10)
 305 #define LBCFG1 (1 << 9)
 306 #define LBCFG0 (1 << 8)
 307 #define DEVID_SHIFT 5
 308 #define DEVID_MASK (0x7 << DEVID_SHIFT)
 309 #define REVID_SHIFT 0
 310 #define REVID_MASK (0x1F << REVID_SHIFT)
 311
 312 /* PHY registers */
 313 #define PHCON1 0x00
 314 #define PHSTAT1 0x01
 315 #define PHANA 0x04
 316 #define PHANLPA 0x05
 317 #define PHANE 0x06
 318 #define PHCON2 0x11
 319 #define PHSTAT2 0x1B
 320 #define PHSTAT3 0x1F
 321
 322 /* PHCON1 */
 323 #define PRST (1 << 15)
 324 #define PLOOPBK (1 << 14)
 325 #define SPD100 (1 << 13)
 326 #define ANEN (1 << 12)
 327 #define PSLEEP (1 << 11)
 328 #define RENEG (1 << 9)
 329 #define PFULDPX (1 << 8)
 330
 331 /* PHSTAT1 */
 332 #define FULL100 (1 << 14)
 333 #define HALF100 (1 << 13)
 334 #define FULL10 (1 << 12)
 335 #define HALF10 (1 << 11)
 336 #define ANDONE (1 << 5)
 337 #define LRFAULT (1 << 4)
 338 #define ANABLE (1 << 3)
 339 #define LLSTAT (1 << 2)
 340 #define EXTREGS (1 << 0)
 341
 342 /* PHSTAT2 */
 343 #define PLRITY (1 << 4)
 344
 345 /* PHSTAT3 */
 346 #define PHY3SPD100 (1 << 3)
 347 #define PHY3DPX (1 << 4)
 348 #define SPDDPX_SHIFT 2
 349 #define SPDDPX_MASK (0x7 << SPDDPX_SHIFT)
 350
 351 /* PHANA */
 352 /* Default value for PHY initialization*/
 353 #define PHANA_DEFAULT 0x05E1
 354
 355 /* PHANE */
 356 #define PDFLT (1 << 4)
 357 #define LPARCD (1 << 1)
 358 #define LPANABL (1 << 0)
 359
 360 #define EUDAST_TEST_VAL 0x1234
 361
 362 #define TSV_SIZE 7
 363
 364 #define ENCX24J600_DEV_ID 0x1
 365
 366 /* Configuration */
 367
 368 /* Led is on when the link is present and driven low
 369  * temporarily when packet is TX'd or RX'd
 370  */
 371 #define LED_A_SETTINGS 0xC
 372
 373 /* Led is on if the link is in 100 Mbps mode */
 374 #define LED_B_SETTINGS 0x8
 375
 376 /* maximum ethernet frame length
 377  * Currently not used as a limit anywhere
 378  * (we're using the "huge frame enable" feature of
 379  * enc424j600).
 380  */
 381 #define MAX_FRAMELEN 1518
 382
 383 /* Size in bytes of the receive buffer in enc424j600.
 384  * Must be word aligned (even).
 385  */
 386 #define RX_BUFFER_SIZE (15 * MAX_FRAMELEN)
 387
 388 /* Start of the general purpose area in sram */
 389 #define SRAM_GP_START 0x0
 390
 391 /* SRAM size */
 392 #define SRAM_SIZE 0x6000
 393
 394 /* Start of the receive buffer */
 395 #define ERXST_VAL (SRAM_SIZE - RX_BUFFER_SIZE)
 396
 397 #define RSV_RXLONGEVDROPEV      16
 398 #define RSV_CARRIEREV           18
 399 #define RSV_CRCERROR            20
 400 #define RSV_LENCHECKERR         21
 401 #define RSV_LENOUTOFRANGE       22
 402 #define RSV_RXOK                23
 403 #define RSV_RXMULTICAST         24
 404 #define RSV_RXBROADCAST         25
 405 #define RSV_DRIBBLENIBBLE       26
 406 #define RSV_RXCONTROLFRAME      27
 407 #define RSV_RXPAUSEFRAME        28
 408 #define RSV_RXUNKNOWNOPCODE     29
 409 #define RSV_RXTYPEVLAN          30
 410
 411 #define RSV_RUNTFILTERMATCH     31
 412 #define RSV_NOTMEFILTERMATCH    32
 413 #define RSV_HASHFILTERMATCH     33
 414 #define RSV_MAGICPKTFILTERMATCH 34
 415 #define RSV_PTRNMTCHFILTERMATCH 35
 416 #define RSV_UNICASTFILTERMATCH  36
 417
 418 #define RSV_SIZE                8
 419 #define RSV_BITMASK(x)          (1 << ((x) - 16))
 420 #define RSV_GETBIT(x, y)        (((x) & RSV_BITMASK(y)) ? 1 : 0)
 421
 422 struct rsv {
 423         u16 next_packet;
 424         u16 len;
 425         u32 rxstat;
 426 };
 427
 428 /* Put RX buffer at 0 as suggested by the Errata datasheet */
 429
 430 #define RXSTART_INIT            ERXST_VAL
 431 #define RXEND_INIT              0x5FFF
 432
 433 int regmap_encx24j600_spi_write(void *context, u8 reg, const u8 *data,
 434                                 size_t count);
 435 int regmap_encx24j600_spi_read(void *context, u8 reg, u8 *data, size_t count);
 436
 437
 438 #endif