drivers/net/ethernet/myricom/myri10ge/myri10ge_mcp.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef __MYRI10GE_MCP_H__
   3 #define __MYRI10GE_MCP_H__
   4
   5 #define MXGEFW_VERSION_MAJOR    1
   6 #define MXGEFW_VERSION_MINOR    4
   7
   8 /* 8 Bytes */
   9 struct mcp_dma_addr {
  10         __be32 high;
  11         __be32 low;
  12 };
  13
  14 /* 4 Bytes */
  15 struct mcp_slot {
  16         __sum16 checksum;
  17         __be16 length;
  18 };
  19
  20 /* 64 Bytes */
  21 struct mcp_cmd {
  22         __be32 cmd;
  23         __be32 data0;           /* will be low portion if data > 32 bits */
  24         /* 8 */
  25         __be32 data1;           /* will be high portion if data > 32 bits */
  26         __be32 data2;           /* currently unused.. */
  27         /* 16 */
  28         struct mcp_dma_addr response_addr;
  29         /* 24 */
  30         u8 pad[40];
  31 };
  32
  33 /* 8 Bytes */
  34 struct mcp_cmd_response {
  35         __be32 data;
  36         __be32 result;
  37 };
  38
  39 /*
  40  * flags used in mcp_kreq_ether_send_t:
  41  *
  42  * The SMALL flag is only needed in the first segment. It is raised
  43  * for packets that are total less or equal 512 bytes.
  44  *
  45  * The CKSUM flag must be set in all segments.
  46  *
  47  * The PADDED flags is set if the packet needs to be padded, and it
  48  * must be set for all segments.
  49  *
  50  * The  MXGEFW_FLAGS_ALIGN_ODD must be set if the cumulative
  51  * length of all previous segments was odd.
  52  */
  53
  54 #define MXGEFW_FLAGS_SMALL      0x1
  55 #define MXGEFW_FLAGS_TSO_HDR    0x1
  56 #define MXGEFW_FLAGS_FIRST      0x2
  57 #define MXGEFW_FLAGS_ALIGN_ODD  0x4
  58 #define MXGEFW_FLAGS_CKSUM      0x8
  59 #define MXGEFW_FLAGS_TSO_LAST   0x8
  60 #define MXGEFW_FLAGS_NO_TSO     0x10
  61 #define MXGEFW_FLAGS_TSO_CHOP   0x10
  62 #define MXGEFW_FLAGS_TSO_PLD    0x20
  63
  64 #define MXGEFW_SEND_SMALL_SIZE  1520
  65 #define MXGEFW_MAX_MTU          9400
  66
  67 union mcp_pso_or_cumlen {
  68         u16 pseudo_hdr_offset;
  69         u16 cum_len;
  70 };
  71
  72 #define MXGEFW_MAX_SEND_DESC 12
  73 #define MXGEFW_PAD          2
  74
  75 /* 16 Bytes */
  76 struct mcp_kreq_ether_send {
  77         __be32 addr_high;
  78         __be32 addr_low;
  79         __be16 pseudo_hdr_offset;
  80         __be16 length;
  81         u8 pad;
  82         u8 rdma_count;
  83         u8 cksum_offset;        /* where to start computing cksum */
  84         u8 flags;               /* as defined above */
  85 };
  86
  87 /* 8 Bytes */
  88 struct mcp_kreq_ether_recv {
  89         __be32 addr_high;
  90         __be32 addr_low;
  91 };
  92
  93 /* Commands */
  94
  95 #define MXGEFW_BOOT_HANDOFF     0xfc0000
  96 #define MXGEFW_BOOT_DUMMY_RDMA  0xfc01c0
  97
  98 #define MXGEFW_ETH_CMD          0xf80000
  99 #define MXGEFW_ETH_SEND_4       0x200000
 100 #define MXGEFW_ETH_SEND_1       0x240000
 101 #define MXGEFW_ETH_SEND_2       0x280000
 102 #define MXGEFW_ETH_SEND_3       0x2c0000
 103 #define MXGEFW_ETH_RECV_SMALL   0x300000
 104 #define MXGEFW_ETH_RECV_BIG     0x340000
 105 #define MXGEFW_ETH_SEND_GO      0x380000
 106 #define MXGEFW_ETH_SEND_STOP    0x3C0000
 107
 108 #define MXGEFW_ETH_SEND(n)              (0x200000 + (((n) & 0x03) * 0x40000))
 109 #define MXGEFW_ETH_SEND_OFFSET(n)       (MXGEFW_ETH_SEND(n) - MXGEFW_ETH_SEND_4)
 110
 111 enum myri10ge_mcp_cmd_type {
 112         MXGEFW_CMD_NONE = 0,
 113         /* Reset the mcp, it is left in a safe state, waiting
 114          * for the driver to set all its parameters */
 115         MXGEFW_CMD_RESET = 1,
 116
 117         /* get the version number of the current firmware..
 118          * (may be available in the eeprom strings..? */
 119         MXGEFW_GET_MCP_VERSION = 2,
 120
 121         /* Parameters which must be set by the driver before it can
 122          * issue MXGEFW_CMD_ETHERNET_UP. They persist until the next
 123          * MXGEFW_CMD_RESET is issued */
 124
 125         MXGEFW_CMD_SET_INTRQ_DMA = 3,
 126         /* data0 = LSW of the host address
 127          * data1 = MSW of the host address
 128          * data2 = slice number if multiple slices are used
 129          */
 130
 131         MXGEFW_CMD_SET_BIG_BUFFER_SIZE = 4,     /* in bytes, power of 2 */
 132         MXGEFW_CMD_SET_SMALL_BUFFER_SIZE = 5,   /* in bytes */
 133
 134         /* Parameters which refer to lanai SRAM addresses where the
 135          * driver must issue PIO writes for various things */
 136
 137         MXGEFW_CMD_GET_SEND_OFFSET = 6,
 138         MXGEFW_CMD_GET_SMALL_RX_OFFSET = 7,
 139         MXGEFW_CMD_GET_BIG_RX_OFFSET = 8,
 140         /* data0 = slice number if multiple slices are used */
 141
 142         MXGEFW_CMD_GET_IRQ_ACK_OFFSET = 9,
 143         MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET = 10,
 144
 145         /* Parameters which refer to rings stored on the MCP,
 146          * and whose size is controlled by the mcp */
 147
 148         MXGEFW_CMD_GET_SEND_RING_SIZE = 11,     /* in bytes */
 149         MXGEFW_CMD_GET_RX_RING_SIZE = 12,       /* in bytes */
 150
 151         /* Parameters which refer to rings stored in the host,
 152          * and whose size is controlled by the host.  Note that
 153          * all must be physically contiguous and must contain
 154          * a power of 2 number of entries.  */
 155
 156         MXGEFW_CMD_SET_INTRQ_SIZE = 13, /* in bytes */
 157 #define MXGEFW_CMD_SET_INTRQ_SIZE_FLAG_NO_STRICT_SIZE_CHECK  (1 << 31)
 158
 159         /* command to bring ethernet interface up.  Above parameters
 160          * (plus mtu & mac address) must have been exchanged prior
 161          * to issuing this command  */
 162         MXGEFW_CMD_ETHERNET_UP = 14,
 163
 164         /* command to bring ethernet interface down.  No further sends
 165          * or receives may be processed until an MXGEFW_CMD_ETHERNET_UP
 166          * is issued, and all interrupt queues must be flushed prior
 167          * to ack'ing this command */
 168
 169         MXGEFW_CMD_ETHERNET_DOWN = 15,
 170
 171         /* commands the driver may issue live, without resetting
 172          * the nic.  Note that increasing the mtu "live" should
 173          * only be done if the driver has already supplied buffers
 174          * sufficiently large to handle the new mtu.  Decreasing
 175          * the mtu live is safe */
 176
 177         MXGEFW_CMD_SET_MTU = 16,
 178         MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET = 17,     /* in microseconds */
 179         MXGEFW_CMD_SET_STATS_INTERVAL = 18,     /* in microseconds */
 180         MXGEFW_CMD_SET_STATS_DMA_OBSOLETE = 19, /* replaced by SET_STATS_DMA_V2 */
 181
 182         MXGEFW_ENABLE_PROMISC = 20,
 183         MXGEFW_DISABLE_PROMISC = 21,
 184         MXGEFW_SET_MAC_ADDRESS = 22,
 185
 186         MXGEFW_ENABLE_FLOW_CONTROL = 23,
 187         MXGEFW_DISABLE_FLOW_CONTROL = 24,
 188
 189         /* do a DMA test
 190          * data0,data1 = DMA address
 191          * data2       = RDMA length (MSH), WDMA length (LSH)
 192          * command return data = repetitions (MSH), 0.5-ms ticks (LSH)
 193          */
 194         MXGEFW_DMA_TEST = 25,
 195
 196         MXGEFW_ENABLE_ALLMULTI = 26,
 197         MXGEFW_DISABLE_ALLMULTI = 27,
 198
 199         /* returns MXGEFW_CMD_ERROR_MULTICAST
 200          * if there is no room in the cache
 201          * data0,MSH(data1) = multicast group address */
 202         MXGEFW_JOIN_MULTICAST_GROUP = 28,
 203         /* returns MXGEFW_CMD_ERROR_MULTICAST
 204          * if the address is not in the cache,
 205          * or is equal to FF-FF-FF-FF-FF-FF
 206          * data0,MSH(data1) = multicast group address */
 207         MXGEFW_LEAVE_MULTICAST_GROUP = 29,
 208         MXGEFW_LEAVE_ALL_MULTICAST_GROUPS = 30,
 209
 210         MXGEFW_CMD_SET_STATS_DMA_V2 = 31,
 211         /* data0, data1 = bus addr,
 212          * data2 = sizeof(struct mcp_irq_data) from driver point of view, allows
 213          * adding new stuff to mcp_irq_data without changing the ABI
 214          *
 215          * If multiple slices are used, data2 contains both the size of the
 216          * structure (in the lower 16 bits) and the slice number
 217          * (in the upper 16 bits).
 218          */
 219
 220         MXGEFW_CMD_UNALIGNED_TEST = 32,
 221         /* same than DMA_TEST (same args) but abort with UNALIGNED on unaligned
 222          * chipset */
 223
 224         MXGEFW_CMD_UNALIGNED_STATUS = 33,
 225         /* return data = boolean, true if the chipset is known to be unaligned */
 226
 227         MXGEFW_CMD_ALWAYS_USE_N_BIG_BUFFERS = 34,
 228         /* data0 = number of big buffers to use.  It must be 0 or a power of 2.
 229          * 0 indicates that the NIC consumes as many buffers as they are required
 230          * for packet. This is the default behavior.
 231          * A power of 2 number indicates that the NIC always uses the specified
 232          * number of buffers for each big receive packet.
 233          * It is up to the driver to ensure that this value is big enough for
 234          * the NIC to be able to receive maximum-sized packets.
 235          */
 236
 237         MXGEFW_CMD_GET_MAX_RSS_QUEUES = 35,
 238         MXGEFW_CMD_ENABLE_RSS_QUEUES = 36,
 239         /* data0 = number of slices n (0, 1, ..., n-1) to enable
 240          * data1 = interrupt mode | use of multiple transmit queues.
 241          * 0=share one INTx/MSI.
 242          * 1=use one MSI-X per queue.
 243          * If all queues share one interrupt, the driver must have set
 244          * RSS_SHARED_INTERRUPT_DMA before enabling queues.
 245          * 2=enable both receive and send queues.
 246          * Without this bit set, only one send queue (slice 0's send queue)
 247          * is enabled.  The receive queues are always enabled.
 248          */
 249 #define MXGEFW_SLICE_INTR_MODE_SHARED          0x0
 250 #define MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE   0x1
 251 #define MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES 0x2
 252
 253         MXGEFW_CMD_GET_RSS_SHARED_INTERRUPT_MASK_OFFSET = 37,
 254         MXGEFW_CMD_SET_RSS_SHARED_INTERRUPT_DMA = 38,
 255         /* data0, data1 = bus address lsw, msw */
 256         MXGEFW_CMD_GET_RSS_TABLE_OFFSET = 39,
 257         /* get the offset of the indirection table */
 258         MXGEFW_CMD_SET_RSS_TABLE_SIZE = 40,
 259         /* set the size of the indirection table */
 260         MXGEFW_CMD_GET_RSS_KEY_OFFSET = 41,
 261         /* get the offset of the secret key */
 262         MXGEFW_CMD_RSS_KEY_UPDATED = 42,
 263         /* tell nic that the secret key's been updated */
 264         MXGEFW_CMD_SET_RSS_ENABLE = 43,
 265         /* data0 = enable/disable rss
 266          * 0: disable rss.  nic does not distribute receive packets.
 267          * 1: enable rss.  nic distributes receive packets among queues.
 268          * data1 = hash type
 269          * 1: IPV4            (required by RSS)
 270          * 2: TCP_IPV4        (required by RSS)
 271          * 3: IPV4 | TCP_IPV4 (required by RSS)
 272          * 4: source port
 273          * 5: source port + destination port
 274          */
 275 #define MXGEFW_RSS_HASH_TYPE_IPV4      0x1
 276 #define MXGEFW_RSS_HASH_TYPE_TCP_IPV4  0x2
 277 #define MXGEFW_RSS_HASH_TYPE_SRC_PORT  0x4
 278 #define MXGEFW_RSS_HASH_TYPE_SRC_DST_PORT 0x5
 279 #define MXGEFW_RSS_HASH_TYPE_MAX 0x5
 280
 281         MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE = 44,
 282         /* Return data = the max. size of the entire headers of a IPv6 TSO packet.
 283          * If the header size of a IPv6 TSO packet is larger than the specified
 284          * value, then the driver must not use TSO.
 285          * This size restriction only applies to IPv6 TSO.
 286          * For IPv4 TSO, the maximum size of the headers is fixed, and the NIC
 287          * always has enough header buffer to store maximum-sized headers.
 288          */
 289
 290         MXGEFW_CMD_SET_TSO_MODE = 45,
 291         /* data0 = TSO mode.
 292          * 0: Linux/FreeBSD style (NIC default)
 293          * 1: NDIS/NetBSD style
 294          */
 295 #define MXGEFW_TSO_MODE_LINUX  0
 296 #define MXGEFW_TSO_MODE_NDIS   1
 297
 298         MXGEFW_CMD_MDIO_READ = 46,
 299         /* data0 = dev_addr (PMA/PMD or PCS ...), data1 = register/addr */
 300         MXGEFW_CMD_MDIO_WRITE = 47,
 301         /* data0 = dev_addr,  data1 = register/addr, data2 = value  */
 302
 303         MXGEFW_CMD_I2C_READ = 48,
 304         /* Starts to get a fresh copy of one byte or of the module i2c table, the
 305          * obtained data is cached inside the xaui-xfi chip :
 306          *   data0 :  0 => get one byte, 1=> get 256 bytes
 307          *   data1 :  If data0 == 0: location to refresh
 308          *               bit 7:0  register location
 309          *               bit 8:15 is the i2c slave addr (0 is interpreted as 0xA1)
 310          *               bit 23:16 is the i2c bus number (for multi-port NICs)
 311          *            If data0 == 1: unused
 312          * The operation might take ~1ms for a single byte or ~65ms when refreshing all 256 bytes
 313          * During the i2c operation,  MXGEFW_CMD_I2C_READ or MXGEFW_CMD_I2C_BYTE attempts
 314          *  will return MXGEFW_CMD_ERROR_BUSY
 315          */
 316         MXGEFW_CMD_I2C_BYTE = 49,
 317         /* Return the last obtained copy of a given byte in the xfp i2c table
 318          * (copy cached during the last relevant MXGEFW_CMD_I2C_READ)
 319          *   data0 : index of the desired table entry
 320          *  Return data = the byte stored at the requested index in the table
 321          */
 322
 323         MXGEFW_CMD_GET_VPUMP_OFFSET = 50,
 324         /* Return data = NIC memory offset of mcp_vpump_public_global */
 325         MXGEFW_CMD_RESET_VPUMP = 51,
 326         /* Resets the VPUMP state */
 327
 328         MXGEFW_CMD_SET_RSS_MCP_SLOT_TYPE = 52,
 329         /* data0 = mcp_slot type to use.
 330          * 0 = the default 4B mcp_slot
 331          * 1 = 8B mcp_slot_8
 332          */
 333 #define MXGEFW_RSS_MCP_SLOT_TYPE_MIN        0
 334 #define MXGEFW_RSS_MCP_SLOT_TYPE_WITH_HASH  1
 335
 336         MXGEFW_CMD_SET_THROTTLE_FACTOR = 53,
 337         /* set the throttle factor for ethp_z8e
 338          * data0 = throttle_factor
 339          * throttle_factor = 256 * pcie-raw-speed / tx_speed
 340          * tx_speed = 256 * pcie-raw-speed / throttle_factor
 341          *
 342          * For PCI-E x8: pcie-raw-speed == 16Gb/s
 343          * For PCI-E x4: pcie-raw-speed == 8Gb/s
 344          *
 345          * ex1: throttle_factor == 0x1a0 (416), tx_speed == 1.23GB/s == 9.846 Gb/s
 346          * ex2: throttle_factor == 0x200 (512), tx_speed == 1.0GB/s == 8 Gb/s
 347          *
 348          * with tx_boundary == 2048, max-throttle-factor == 8191 => min-speed == 500Mb/s
 349          * with tx_boundary == 4096, max-throttle-factor == 4095 => min-speed == 1Gb/s
 350          */
 351
 352         MXGEFW_CMD_VPUMP_UP = 54,
 353         /* Allocates VPump Connection, Send Request and Zero copy buffer address tables */
 354         MXGEFW_CMD_GET_VPUMP_CLK = 55,
 355         /* Get the lanai clock */
 356
 357         MXGEFW_CMD_GET_DCA_OFFSET = 56,
 358         /* offset of dca control for WDMAs */
 359
 360         /* VMware NetQueue commands */
 361         MXGEFW_CMD_NETQ_GET_FILTERS_PER_QUEUE = 57,
 362         MXGEFW_CMD_NETQ_ADD_FILTER = 58,
 363         /* data0 = filter_id << 16 | queue << 8 | type */
 364         /* data1 = MS4 of MAC Addr */
 365         /* data2 = LS2_MAC << 16 | VLAN_tag */
 366         MXGEFW_CMD_NETQ_DEL_FILTER = 59,
 367         /* data0 = filter_id */
 368         MXGEFW_CMD_NETQ_QUERY1 = 60,
 369         MXGEFW_CMD_NETQ_QUERY2 = 61,
 370         MXGEFW_CMD_NETQ_QUERY3 = 62,
 371         MXGEFW_CMD_NETQ_QUERY4 = 63,
 372
 373         MXGEFW_CMD_RELAX_RXBUFFER_ALIGNMENT = 64,
 374         /* When set, small receive buffers can cross page boundaries.
 375          * Both small and big receive buffers may start at any address.
 376          * This option has performance implications, so use with caution.
 377          */
 378 };
 379
 380 enum myri10ge_mcp_cmd_status {
 381         MXGEFW_CMD_OK = 0,
 382         MXGEFW_CMD_UNKNOWN = 1,
 383         MXGEFW_CMD_ERROR_RANGE = 2,
 384         MXGEFW_CMD_ERROR_BUSY = 3,
 385         MXGEFW_CMD_ERROR_EMPTY = 4,
 386         MXGEFW_CMD_ERROR_CLOSED = 5,
 387         MXGEFW_CMD_ERROR_HASH_ERROR = 6,
 388         MXGEFW_CMD_ERROR_BAD_PORT = 7,
 389         MXGEFW_CMD_ERROR_RESOURCES = 8,
 390         MXGEFW_CMD_ERROR_MULTICAST = 9,
 391         MXGEFW_CMD_ERROR_UNALIGNED = 10,
 392         MXGEFW_CMD_ERROR_NO_MDIO = 11,
 393         MXGEFW_CMD_ERROR_I2C_FAILURE = 12,
 394         MXGEFW_CMD_ERROR_I2C_ABSENT = 13,
 395         MXGEFW_CMD_ERROR_BAD_PCIE_LINK = 14
 396 };
 397
 398 #define MXGEFW_OLD_IRQ_DATA_LEN 40
 399
 400 struct mcp_irq_data {
 401         /* add new counters at the beginning */
 402         __be32 future_use[1];
 403         __be32 dropped_pause;
 404         __be32 dropped_unicast_filtered;
 405         __be32 dropped_bad_crc32;
 406         __be32 dropped_bad_phy;
 407         __be32 dropped_multicast_filtered;
 408         /* 40 Bytes */
 409         __be32 send_done_count;
 410
 411 #define MXGEFW_LINK_DOWN 0
 412 #define MXGEFW_LINK_UP 1
 413 #define MXGEFW_LINK_MYRINET 2
 414 #define MXGEFW_LINK_UNKNOWN 3
 415         __be32 link_up;
 416         __be32 dropped_link_overflow;
 417         __be32 dropped_link_error_or_filtered;
 418         __be32 dropped_runt;
 419         __be32 dropped_overrun;
 420         __be32 dropped_no_small_buffer;
 421         __be32 dropped_no_big_buffer;
 422         __be32 rdma_tags_available;
 423
 424         u8 tx_stopped;
 425         u8 link_down;
 426         u8 stats_updated;
 427         u8 valid;
 428 };
 429
 430 /* definitions for NETQ filter type */
 431 #define MXGEFW_NETQ_FILTERTYPE_NONE 0
 432 #define MXGEFW_NETQ_FILTERTYPE_MACADDR 1
 433 #define MXGEFW_NETQ_FILTERTYPE_VLAN 2
 434 #define MXGEFW_NETQ_FILTERTYPE_VLANMACADDR 3
 435
 436 #endif                          /* __MYRI10GE_MCP_H__ */