| blob | 3dcb6ff58e73ad1184c2b8b5f639163cec98511c |
1 /* QLogic qed NIC Driver
2 * Copyright (c) 2015-2017 QLogic Corporation
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and /or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
33 #ifndef REG_ADDR_H
34 #define REG_ADDR_H
36 #define CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE_SHIFT \
37 0
39 #define CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE ( \
40 0xfff << 0)
42 #define CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE_SHIFT \
43 12
45 #define CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE ( \
46 0xfff << 12)
48 #define CDU_REG_CID_ADDR_PARAMS_NCIB_SHIFT \
49 24
51 #define CDU_REG_CID_ADDR_PARAMS_NCIB ( \
52 0xff << 24)
54 #define CDU_REG_SEGMENT0_PARAMS \
55 0x580904UL
56 #define CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK \
57 (0xfff << 0)
58 #define CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK_SHIFT \
59 0
60 #define CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE \
61 (0xff << 16)
62 #define CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE_SHIFT \
63 16
64 #define CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE \
65 (0xff << 24)
66 #define CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE_SHIFT \
67 24
68 #define CDU_REG_SEGMENT1_PARAMS \
69 0x580908UL
70 #define CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK \
71 (0xfff << 0)
72 #define CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK_SHIFT \
73 0
74 #define CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE \
75 (0xff << 16)
76 #define CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE_SHIFT \
77 16
78 #define CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE \
79 (0xff << 24)
80 #define CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE_SHIFT \
81 24
83 #define XSDM_REG_OPERATION_GEN \
84 0xf80408UL
85 #define NIG_REG_RX_BRB_OUT_EN \
86 0x500e18UL
87 #define NIG_REG_STORM_OUT_EN \
88 0x500e08UL
89 #define PSWRQ2_REG_L2P_VALIDATE_VFID \
90 0x240c50UL
91 #define PGLUE_B_REG_USE_CLIENTID_IN_TAG \
92 0x2aae04UL
93 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER \
94 0x2aa16cUL
95 #define PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR \
96 0x2aa118UL
97 #define PSWHST_REG_ZONE_PERMISSION_TABLE \
98 0x2a0800UL
99 #define BAR0_MAP_REG_MSDM_RAM \
100 0x1d00000UL
101 #define BAR0_MAP_REG_USDM_RAM \
102 0x1d80000UL
103 #define BAR0_MAP_REG_PSDM_RAM \
104 0x1f00000UL
105 #define BAR0_MAP_REG_TSDM_RAM \
106 0x1c80000UL
107 #define BAR0_MAP_REG_XSDM_RAM \
108 0x1e00000UL
109 #define BAR0_MAP_REG_YSDM_RAM \
110 0x1e80000UL
111 #define NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF \
112 0x5011f4UL
113 #define PRS_REG_SEARCH_RESP_INITIATOR_TYPE \
114 0x1f0164UL
115 #define PRS_REG_SEARCH_TCP \
116 0x1f0400UL
117 #define PRS_REG_SEARCH_UDP \
118 0x1f0404UL
119 #define PRS_REG_SEARCH_FCOE \
120 0x1f0408UL
121 #define PRS_REG_SEARCH_ROCE \
122 0x1f040cUL
123 #define PRS_REG_SEARCH_OPENFLOW \
124 0x1f0434UL
125 #define PRS_REG_SEARCH_TAG1 \
126 0x1f0444UL
127 #define PRS_REG_SEARCH_TENANT_ID \
128 0x1f044cUL
129 #define PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST \
130 0x1f0a0cUL
131 #define PRS_REG_SEARCH_TCP_FIRST_FRAG \
132 0x1f0410UL
133 #define TM_REG_PF_ENABLE_CONN \
134 0x2c043cUL
135 #define TM_REG_PF_ENABLE_TASK \
136 0x2c0444UL
137 #define TM_REG_PF_SCAN_ACTIVE_CONN \
138 0x2c04fcUL
139 #define TM_REG_PF_SCAN_ACTIVE_TASK \
140 0x2c0500UL
141 #define IGU_REG_LEADING_EDGE_LATCH \
142 0x18082cUL
143 #define IGU_REG_TRAILING_EDGE_LATCH \
144 0x180830UL
145 #define QM_REG_USG_CNT_PF_TX \
146 0x2f2eacUL
147 #define QM_REG_USG_CNT_PF_OTHER \
148 0x2f2eb0UL
149 #define DORQ_REG_PF_DB_ENABLE \
150 0x100508UL
151 #define DORQ_REG_VF_USAGE_CNT \
152 0x1009c4UL
153 #define QM_REG_PF_EN \
154 0x2f2ea4UL
155 #define TCFC_REG_WEAK_ENABLE_VF \
156 0x2d0704UL
157 #define TCFC_REG_STRONG_ENABLE_PF \
158 0x2d0708UL
159 #define TCFC_REG_STRONG_ENABLE_VF \
160 0x2d070cUL
161 #define CCFC_REG_WEAK_ENABLE_VF \
162 0x2e0704UL
163 #define CCFC_REG_STRONG_ENABLE_PF \
164 0x2e0708UL
165 #define PGLUE_B_REG_PGL_ADDR_88_F0_BB \
166 0x2aa404UL
167 #define PGLUE_B_REG_PGL_ADDR_8C_F0_BB \
168 0x2aa408UL
169 #define PGLUE_B_REG_PGL_ADDR_90_F0_BB \
170 0x2aa40cUL
171 #define PGLUE_B_REG_PGL_ADDR_94_F0_BB \
172 0x2aa410UL
173 #define PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR \
174 0x2aa138UL
175 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ \
176 0x2aa174UL
177 #define MISC_REG_GEN_PURP_CR0 \
178 0x008c80UL
179 #define MCP_REG_SCRATCH \
180 0xe20000UL
181 #define MCP_REG_SCRATCH_SIZE \
182 57344
183 #define CNIG_REG_NW_PORT_MODE_BB \
184 0x218200UL
185 #define MISCS_REG_CHIP_NUM \
186 0x00976cUL
187 #define MISCS_REG_CHIP_REV \
188 0x009770UL
189 #define MISCS_REG_CMT_ENABLED_FOR_PAIR \
190 0x00971cUL
191 #define MISCS_REG_CHIP_TEST_REG \
192 0x009778UL
193 #define MISCS_REG_CHIP_METAL \
194 0x009774UL
195 #define MISCS_REG_FUNCTION_HIDE \
196 0x0096f0UL
197 #define BRB_REG_HEADER_SIZE \
198 0x340804UL
199 #define BTB_REG_HEADER_SIZE \
200 0xdb0804UL
201 #define CAU_REG_LONG_TIMEOUT_THRESHOLD \
202 0x1c0708UL
203 #define CCFC_REG_ACTIVITY_COUNTER \
204 0x2e8800UL
205 #define CCFC_REG_STRONG_ENABLE_VF \
206 0x2e070cUL
207 #define CDU_REG_CCFC_CTX_VALID0 \
208 0x580400UL
209 #define CDU_REG_CCFC_CTX_VALID1 \
210 0x580404UL
211 #define CDU_REG_TCFC_CTX_VALID0 \
212 0x580408UL
213 #define CDU_REG_CID_ADDR_PARAMS \
214 0x580900UL
215 #define DBG_REG_CLIENT_ENABLE \
216 0x010004UL
217 #define DBG_REG_TIMESTAMP_VALID_EN \
218 0x010b58UL
219 #define DMAE_REG_INIT \
220 0x00c000UL
221 #define DORQ_REG_IFEN \
222 0x100040UL
223 #define DORQ_REG_TAG1_OVRD_MODE \
224 0x1008b4UL
225 #define DORQ_REG_PF_PCP_BB_K2 \
226 0x1008c4UL
227 #define DORQ_REG_PF_EXT_VID_BB_K2 \
228 0x1008c8UL
229 #define DORQ_REG_DB_DROP_REASON \
230 0x100a2cUL
231 #define DORQ_REG_DB_DROP_DETAILS \
232 0x100a24UL
233 #define DORQ_REG_DB_DROP_DETAILS_ADDRESS \
234 0x100a1cUL
235 #define GRC_REG_TIMEOUT_EN \
236 0x050404UL
237 #define GRC_REG_TIMEOUT_ATTN_ACCESS_VALID \
238 0x050054UL
239 #define GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_0 \
240 0x05004cUL
241 #define GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_1 \
242 0x050050UL
243 #define IGU_REG_BLOCK_CONFIGURATION \
244 0x180040UL
245 #define MCM_REG_INIT \
246 0x1200000UL
247 #define MCP2_REG_DBG_DWORD_ENABLE \
248 0x052404UL
249 #define MISC_REG_PORT_MODE \
250 0x008c00UL
251 #define MISCS_REG_CLK_100G_MODE \
252 0x009070UL
253 #define MSDM_REG_ENABLE_IN1 \
254 0xfc0004UL
255 #define MSEM_REG_ENABLE_IN \
256 0x1800004UL
257 #define NIG_REG_CM_HDR \
258 0x500840UL
259 #define NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR \
260 0x50196cUL
261 #define NIG_REG_LLH_PPFID2PFID_TBL_0 \
262 0x501970UL
263 #define NIG_REG_LLH_ENG_CLS_ROCE_QP_SEL \
264 0x50
265 #define NIG_REG_LLH_CLS_TYPE_DUALMODE \
266 0x501964UL
267 #define NIG_REG_LLH_FUNC_TAG_EN 0x5019b0UL
268 #define NIG_REG_LLH_FUNC_TAG_VALUE 0x5019d0UL
269 #define NIG_REG_LLH_FUNC_FILTER_VALUE \
270 0x501a00UL
271 #define NIG_REG_LLH_FUNC_FILTER_VALUE_SIZE \
272 32
273 #define NIG_REG_LLH_FUNC_FILTER_EN \
274 0x501a80UL
275 #define NIG_REG_LLH_FUNC_FILTER_EN_SIZE \
276 16
277 #define NIG_REG_LLH_FUNC_FILTER_MODE \
278 0x501ac0UL
279 #define NIG_REG_LLH_FUNC_FILTER_MODE_SIZE \
280 16
281 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE \
282 0x501b00UL
283 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_SIZE \
284 16
285 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL \
286 0x501b40UL
287 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_SIZE \
288 16
289 #define NCSI_REG_CONFIG \
290 0x040200UL
291 #define PBF_REG_INIT \
292 0xd80000UL
293 #define PBF_REG_NUM_BLOCKS_ALLOCATED_PROD_VOQ0 \
294 0xd806c8UL
295 #define PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ0 \
296 0xd806ccUL
297 #define PTU_REG_ATC_INIT_ARRAY \
298 0x560000UL
299 #define PCM_REG_INIT \
300 0x1100000UL
301 #define PGLUE_B_REG_ADMIN_PER_PF_REGION \
302 0x2a9000UL
303 #define PGLUE_B_REG_TX_ERR_WR_DETAILS2 \
304 0x2aa150UL
305 #define PGLUE_B_REG_TX_ERR_WR_ADD_31_0 \
306 0x2aa144UL
307 #define PGLUE_B_REG_TX_ERR_WR_ADD_63_32 \
308 0x2aa148UL
309 #define PGLUE_B_REG_TX_ERR_WR_DETAILS \
310 0x2aa14cUL
311 #define PGLUE_B_REG_TX_ERR_RD_ADD_31_0 \
312 0x2aa154UL
313 #define PGLUE_B_REG_TX_ERR_RD_ADD_63_32 \
314 0x2aa158UL
315 #define PGLUE_B_REG_TX_ERR_RD_DETAILS \
316 0x2aa15cUL
317 #define PGLUE_B_REG_TX_ERR_RD_DETAILS2 \
318 0x2aa160UL
319 #define PGLUE_B_REG_TX_ERR_WR_DETAILS_ICPL \
320 0x2aa164UL
321 #define PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS \
322 0x2aa54cUL
323 #define PGLUE_B_REG_MASTER_ZLR_ERR_ADD_31_0 \
324 0x2aa544UL
325 #define PGLUE_B_REG_MASTER_ZLR_ERR_ADD_63_32 \
326 0x2aa548UL
327 #define PGLUE_B_REG_VF_ILT_ERR_ADD_31_0 \
328 0x2aae74UL
329 #define PGLUE_B_REG_VF_ILT_ERR_ADD_63_32 \
330 0x2aae78UL
331 #define PGLUE_B_REG_VF_ILT_ERR_DETAILS \
332 0x2aae7cUL
333 #define PGLUE_B_REG_VF_ILT_ERR_DETAILS2 \
334 0x2aae80UL
335 #define PGLUE_B_REG_LATCHED_ERRORS_CLR \
336 0x2aa3bcUL
337 #define PRM_REG_DISABLE_PRM \
338 0x230000UL
339 #define PRS_REG_SOFT_RST \
340 0x1f0000UL
341 #define PRS_REG_MSG_INFO \
342 0x1f0a1cUL
343 #define PRS_REG_ROCE_DEST_QP_MAX_PF \
344 0x1f0430UL
345 #define PRS_REG_USE_LIGHT_L2 \
346 0x1f096cUL
347 #define PSDM_REG_ENABLE_IN1 \
348 0xfa0004UL
349 #define PSEM_REG_ENABLE_IN \
350 0x1600004UL
351 #define PSWRQ_REG_DBG_SELECT \
352 0x280020UL
353 #define PSWRQ2_REG_CDUT_P_SIZE \
354 0x24000cUL
355 #define PSWRQ2_REG_ILT_MEMORY \
356 0x260000UL
357 #define PSWRQ2_REG_ILT_MEMORY_SIZE_BB \
358 15200
359 #define PSWRQ2_REG_ILT_MEMORY_SIZE_K2 \
360 22000
361 #define PSWHST_REG_DISCARD_INTERNAL_WRITES \
362 0x2a0040UL
363 #define PSWHST2_REG_DBGSYN_ALMOST_FULL_THR \
364 0x29e050UL
365 #define PSWHST_REG_INCORRECT_ACCESS_VALID \
366 0x2a0070UL
367 #define PSWHST_REG_INCORRECT_ACCESS_ADDRESS \
368 0x2a0074UL
369 #define PSWHST_REG_INCORRECT_ACCESS_DATA \
370 0x2a0068UL
371 #define PSWHST_REG_INCORRECT_ACCESS_LENGTH \
372 0x2a006cUL
373 #define PSWRD_REG_DBG_SELECT \
374 0x29c040UL
375 #define PSWRD2_REG_CONF11 \
376 0x29d064UL
377 #define PSWWR_REG_USDM_FULL_TH \
378 0x29a040UL
379 #define PSWWR2_REG_CDU_FULL_TH2 \
380 0x29b040UL
381 #define QM_REG_MAXPQSIZE_0 \
382 0x2f0434UL
383 #define RSS_REG_RSS_INIT_EN \
384 0x238804UL
385 #define RDIF_REG_STOP_ON_ERROR \
386 0x300040UL
387 #define RDIF_REG_DEBUG_ERROR_INFO \
388 0x300400UL
389 #define RDIF_REG_DEBUG_ERROR_INFO_SIZE \
390 64
391 #define SRC_REG_SOFT_RST \
392 0x23874cUL
393 #define TCFC_REG_ACTIVITY_COUNTER \
394 0x2d8800UL
395 #define TCM_REG_INIT \
396 0x1180000UL
397 #define TM_REG_PXP_READ_DATA_FIFO_INIT \
398 0x2c0014UL
399 #define TSDM_REG_ENABLE_IN1 \
400 0xfb0004UL
401 #define TSEM_REG_ENABLE_IN \
402 0x1700004UL
403 #define TDIF_REG_STOP_ON_ERROR \
404 0x310040UL
405 #define TDIF_REG_DEBUG_ERROR_INFO \
406 0x310400UL
407 #define TDIF_REG_DEBUG_ERROR_INFO_SIZE \
408 64
409 #define UCM_REG_INIT \
410 0x1280000UL
411 #define UMAC_REG_IPG_HD_BKP_CNTL_BB_B0 \
412 0x051004UL
413 #define USDM_REG_ENABLE_IN1 \
414 0xfd0004UL
415 #define USEM_REG_ENABLE_IN \
416 0x1900004UL
417 #define XCM_REG_INIT \
418 0x1000000UL
419 #define XSDM_REG_ENABLE_IN1 \
420 0xf80004UL
421 #define XSEM_REG_ENABLE_IN \
422 0x1400004UL
423 #define YCM_REG_INIT \
424 0x1080000UL
425 #define YSDM_REG_ENABLE_IN1 \
426 0xf90004UL
427 #define YSEM_REG_ENABLE_IN \
428 0x1500004UL
429 #define XYLD_REG_SCBD_STRICT_PRIO \
430 0x4c0000UL
431 #define TMLD_REG_SCBD_STRICT_PRIO \
432 0x4d0000UL
433 #define MULD_REG_SCBD_STRICT_PRIO \
434 0x4e0000UL
435 #define YULD_REG_SCBD_STRICT_PRIO \
436 0x4c8000UL
437 #define MISC_REG_SHARED_MEM_ADDR \
438 0x008c20UL
439 #define DMAE_REG_GO_C0 \
440 0x00c048UL
441 #define DMAE_REG_GO_C1 \
442 0x00c04cUL
443 #define DMAE_REG_GO_C2 \
444 0x00c050UL
445 #define DMAE_REG_GO_C3 \
446 0x00c054UL
447 #define DMAE_REG_GO_C4 \
448 0x00c058UL
449 #define DMAE_REG_GO_C5 \
450 0x00c05cUL
451 #define DMAE_REG_GO_C6 \
452 0x00c060UL
453 #define DMAE_REG_GO_C7 \
454 0x00c064UL
455 #define DMAE_REG_GO_C8 \
456 0x00c068UL
457 #define DMAE_REG_GO_C9 \
458 0x00c06cUL
459 #define DMAE_REG_GO_C10 \
460 0x00c070UL
461 #define DMAE_REG_GO_C11 \
462 0x00c074UL
463 #define DMAE_REG_GO_C12 \
464 0x00c078UL
465 #define DMAE_REG_GO_C13 \
466 0x00c07cUL
467 #define DMAE_REG_GO_C14 \
468 0x00c080UL
469 #define DMAE_REG_GO_C15 \
470 0x00c084UL
471 #define DMAE_REG_GO_C16 \
472 0x00c088UL
473 #define DMAE_REG_GO_C17 \
474 0x00c08cUL
475 #define DMAE_REG_GO_C18 \
476 0x00c090UL
477 #define DMAE_REG_GO_C19 \
478 0x00c094UL
479 #define DMAE_REG_GO_C20 \
480 0x00c098UL
481 #define DMAE_REG_GO_C21 \
482 0x00c09cUL
483 #define DMAE_REG_GO_C22 \
484 0x00c0a0UL
485 #define DMAE_REG_GO_C23 \
486 0x00c0a4UL
487 #define DMAE_REG_GO_C24 \
488 0x00c0a8UL
489 #define DMAE_REG_GO_C25 \
490 0x00c0acUL
491 #define DMAE_REG_GO_C26 \
492 0x00c0b0UL
493 #define DMAE_REG_GO_C27 \
494 0x00c0b4UL
495 #define DMAE_REG_GO_C28 \
496 0x00c0b8UL
497 #define DMAE_REG_GO_C29 \
498 0x00c0bcUL
499 #define DMAE_REG_GO_C30 \
500 0x00c0c0UL
501 #define DMAE_REG_GO_C31 \
502 0x00c0c4UL
503 #define DMAE_REG_CMD_MEM \
504 0x00c800UL
505 #define QM_REG_MAXPQSIZETXSEL_0 \
506 0x2f0440UL
507 #define QM_REG_SDMCMDREADY \
508 0x2f1e10UL
509 #define QM_REG_SDMCMDADDR \
510 0x2f1e04UL
511 #define QM_REG_SDMCMDDATALSB \
512 0x2f1e08UL
513 #define QM_REG_SDMCMDDATAMSB \
514 0x2f1e0cUL
515 #define QM_REG_SDMCMDGO \
516 0x2f1e14UL
517 #define QM_REG_RLPFCRD \
518 0x2f4d80UL
519 #define QM_REG_RLPFINCVAL \
520 0x2f4c80UL
521 #define QM_REG_RLGLBLCRD \
522 0x2f4400UL
523 #define QM_REG_RLGLBLINCVAL \
524 0x2f3400UL
525 #define IGU_REG_ATTENTION_ENABLE \
526 0x18083cUL
527 #define IGU_REG_ATTN_MSG_ADDR_L \
528 0x180820UL
529 #define IGU_REG_ATTN_MSG_ADDR_H \
530 0x180824UL
531 #define MISC_REG_AEU_GENERAL_ATTN_0 \
532 0x008400UL
533 #define MISC_REG_AEU_GENERAL_ATTN_35 \
534 0x00848cUL
535 #define CAU_REG_SB_ADDR_MEMORY \
536 0x1c8000UL
537 #define CAU_REG_SB_VAR_MEMORY \
538 0x1c6000UL
539 #define CAU_REG_PI_MEMORY \
540 0x1d0000UL
541 #define IGU_REG_PF_CONFIGURATION \
542 0x180800UL
543 #define IGU_REG_VF_CONFIGURATION \
544 0x180804UL
545 #define MISC_REG_AEU_ENABLE1_IGU_OUT_0 \
546 0x00849cUL
547 #define MISC_REG_AEU_AFTER_INVERT_1_IGU \
548 0x0087b4UL
549 #define MISC_REG_AEU_MASK_ATTN_IGU \
550 0x008494UL
551 #define IGU_REG_CLEANUP_STATUS_0 \
552 0x180980UL
553 #define IGU_REG_CLEANUP_STATUS_1 \
554 0x180a00UL
555 #define IGU_REG_CLEANUP_STATUS_2 \
556 0x180a80UL
557 #define IGU_REG_CLEANUP_STATUS_3 \
558 0x180b00UL
559 #define IGU_REG_CLEANUP_STATUS_4 \
560 0x180b80UL
561 #define IGU_REG_COMMAND_REG_32LSB_DATA \
562 0x180840UL
563 #define IGU_REG_COMMAND_REG_CTRL \
564 0x180848UL
565 #define IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN ( \
566 0x1 << 1)
567 #define IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN ( \
568 0x1 << 0)
569 #define IGU_REG_MAPPING_MEMORY \
570 0x184000UL
571 #define IGU_REG_STATISTIC_NUM_VF_MSG_SENT \
572 0x180408UL
573 #define IGU_REG_WRITE_DONE_PENDING \
574 0x180900UL
575 #define MISCS_REG_GENERIC_POR_0 \
576 0x0096d4UL
577 #define MCP_REG_NVM_CFG4 \
578 0xe0642cUL
579 #define MCP_REG_NVM_CFG4_FLASH_SIZE ( \
580 0x7 << 0)
581 #define MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT \
582 0
583 #define MCP_REG_CPU_STATE \
584 0xe05004UL
585 #define MCP_REG_CPU_STATE_SOFT_HALTED (0x1UL << 10)
586 #define MCP_REG_CPU_EVENT_MASK \
587 0xe05008UL
588 #define MCP_REG_CPU_PROGRAM_COUNTER 0xe0501cUL
589 #define PGLUE_B_REG_PF_BAR0_SIZE \
590 0x2aae60UL
591 #define PGLUE_B_REG_PF_BAR1_SIZE \
592 0x2aae64UL
593 #define PGLUE_B_REG_VF_BAR1_SIZE 0x2aae68UL
594 #define PRS_REG_ENCAPSULATION_TYPE_EN 0x1f0730UL
595 #define PRS_REG_GRE_PROTOCOL 0x1f0734UL
596 #define PRS_REG_VXLAN_PORT 0x1f0738UL
597 #define PRS_REG_OUTPUT_FORMAT_4_0_BB_K2 0x1f099cUL
598 #define NIG_REG_ENC_TYPE_ENABLE 0x501058UL
600 #define NIG_REG_ENC_TYPE_ENABLE_ETH_OVER_GRE_ENABLE (0x1 << 0)
601 #define NIG_REG_ENC_TYPE_ENABLE_ETH_OVER_GRE_ENABLE_SHIFT 0
602 #define NIG_REG_ENC_TYPE_ENABLE_IP_OVER_GRE_ENABLE (0x1 << 1)
603 #define NIG_REG_ENC_TYPE_ENABLE_IP_OVER_GRE_ENABLE_SHIFT 1
604 #define NIG_REG_ENC_TYPE_ENABLE_VXLAN_ENABLE (0x1 << 2)
605 #define NIG_REG_ENC_TYPE_ENABLE_VXLAN_ENABLE_SHIFT 2
607 #define NIG_REG_VXLAN_CTRL 0x50105cUL
608 #define PBF_REG_VXLAN_PORT 0xd80518UL
609 #define PBF_REG_NGE_PORT 0xd8051cUL
610 #define PRS_REG_NGE_PORT 0x1f086cUL
611 #define NIG_REG_NGE_PORT 0x508b38UL
613 #define DORQ_REG_L2_EDPM_TUNNEL_GRE_ETH_EN 0x10090cUL
614 #define DORQ_REG_L2_EDPM_TUNNEL_GRE_IP_EN 0x100910UL
615 #define DORQ_REG_L2_EDPM_TUNNEL_VXLAN_EN 0x100914UL
616 #define DORQ_REG_L2_EDPM_TUNNEL_NGE_IP_EN_K2_E5 0x10092cUL
617 #define DORQ_REG_L2_EDPM_TUNNEL_NGE_ETH_EN_K2_E5 0x100930UL
619 #define NIG_REG_NGE_IP_ENABLE 0x508b28UL
620 #define NIG_REG_NGE_ETH_ENABLE 0x508b2cUL
621 #define NIG_REG_NGE_COMP_VER 0x508b30UL
622 #define PBF_REG_NGE_COMP_VER 0xd80524UL
623 #define PRS_REG_NGE_COMP_VER 0x1f0878UL
625 #define QM_REG_WFQPFWEIGHT 0x2f4e80UL
626 #define QM_REG_WFQVPWEIGHT 0x2fa000UL
628 #define PGLCS_REG_DBG_SELECT_K2_E5 \
629 0x001d14UL
630 #define PGLCS_REG_DBG_DWORD_ENABLE_K2_E5 \
631 0x001d18UL
632 #define PGLCS_REG_DBG_SHIFT_K2_E5 \
633 0x001d1cUL
634 #define PGLCS_REG_DBG_FORCE_VALID_K2_E5 \
635 0x001d20UL
636 #define PGLCS_REG_DBG_FORCE_FRAME_K2_E5 \
637 0x001d24UL
638 #define MISC_REG_RESET_PL_PDA_VMAIN_1 \
639 0x008070UL
640 #define MISC_REG_RESET_PL_PDA_VMAIN_2 \
641 0x008080UL
642 #define MISC_REG_RESET_PL_PDA_VAUX \
643 0x008090UL
644 #define MISCS_REG_RESET_PL_UA \
645 0x009050UL
646 #define MISCS_REG_RESET_PL_HV \
647 0x009060UL
648 #define MISCS_REG_RESET_PL_HV_2_K2_E5 \
649 0x009150UL
650 #define DMAE_REG_DBG_SELECT \
651 0x00c510UL
652 #define DMAE_REG_DBG_DWORD_ENABLE \
653 0x00c514UL
654 #define DMAE_REG_DBG_SHIFT \
655 0x00c518UL
656 #define DMAE_REG_DBG_FORCE_VALID \
657 0x00c51cUL
658 #define DMAE_REG_DBG_FORCE_FRAME \
659 0x00c520UL
660 #define NCSI_REG_DBG_SELECT \
661 0x040474UL
662 #define NCSI_REG_DBG_DWORD_ENABLE \
663 0x040478UL
664 #define NCSI_REG_DBG_SHIFT \
665 0x04047cUL
666 #define NCSI_REG_DBG_FORCE_VALID \
667 0x040480UL
668 #define NCSI_REG_DBG_FORCE_FRAME \
669 0x040484UL
670 #define GRC_REG_DBG_SELECT \
671 0x0500a4UL
672 #define GRC_REG_DBG_DWORD_ENABLE \
673 0x0500a8UL
674 #define GRC_REG_DBG_SHIFT \
675 0x0500acUL
676 #define GRC_REG_DBG_FORCE_VALID \
677 0x0500b0UL
678 #define GRC_REG_DBG_FORCE_FRAME \
679 0x0500b4UL
680 #define UMAC_REG_DBG_SELECT_K2_E5 \
681 0x051094UL
682 #define UMAC_REG_DBG_DWORD_ENABLE_K2_E5 \
683 0x051098UL
684 #define UMAC_REG_DBG_SHIFT_K2_E5 \
685 0x05109cUL
686 #define UMAC_REG_DBG_FORCE_VALID_K2_E5 \
687 0x0510a0UL
688 #define UMAC_REG_DBG_FORCE_FRAME_K2_E5 \
689 0x0510a4UL
690 #define MCP2_REG_DBG_SELECT \
691 0x052400UL
692 #define MCP2_REG_DBG_DWORD_ENABLE \
693 0x052404UL
694 #define MCP2_REG_DBG_SHIFT \
695 0x052408UL
696 #define MCP2_REG_DBG_FORCE_VALID \
697 0x052440UL
698 #define MCP2_REG_DBG_FORCE_FRAME \
699 0x052444UL
700 #define PCIE_REG_DBG_SELECT \
701 0x0547e8UL
702 #define PCIE_REG_DBG_DWORD_ENABLE \
703 0x0547ecUL
704 #define PCIE_REG_DBG_SHIFT \
705 0x0547f0UL
706 #define PCIE_REG_DBG_FORCE_VALID \
707 0x0547f4UL
708 #define PCIE_REG_DBG_FORCE_FRAME \
709 0x0547f8UL
710 #define DORQ_REG_DBG_SELECT \
711 0x100ad0UL
712 #define DORQ_REG_DBG_DWORD_ENABLE \
713 0x100ad4UL
714 #define DORQ_REG_DBG_SHIFT \
715 0x100ad8UL
716 #define DORQ_REG_DBG_FORCE_VALID \
717 0x100adcUL
718 #define DORQ_REG_DBG_FORCE_FRAME \
719 0x100ae0UL
720 #define IGU_REG_DBG_SELECT \
721 0x181578UL
722 #define IGU_REG_DBG_DWORD_ENABLE \
723 0x18157cUL
724 #define IGU_REG_DBG_SHIFT \
725 0x181580UL
726 #define IGU_REG_DBG_FORCE_VALID \
727 0x181584UL
728 #define IGU_REG_DBG_FORCE_FRAME \
729 0x181588UL
730 #define CAU_REG_DBG_SELECT \
731 0x1c0ea8UL
732 #define CAU_REG_DBG_DWORD_ENABLE \
733 0x1c0eacUL
734 #define CAU_REG_DBG_SHIFT \
735 0x1c0eb0UL
736 #define CAU_REG_DBG_FORCE_VALID \
737 0x1c0eb4UL
738 #define CAU_REG_DBG_FORCE_FRAME \
739 0x1c0eb8UL
740 #define PRS_REG_DBG_SELECT \
741 0x1f0b6cUL
742 #define PRS_REG_DBG_DWORD_ENABLE \
743 0x1f0b70UL
744 #define PRS_REG_DBG_SHIFT \
745 0x1f0b74UL
746 #define PRS_REG_DBG_FORCE_VALID \
747 0x1f0ba0UL
748 #define PRS_REG_DBG_FORCE_FRAME \
749 0x1f0ba4UL
750 #define CNIG_REG_DBG_SELECT_K2_E5 \
751 0x218254UL
752 #define CNIG_REG_DBG_DWORD_ENABLE_K2_E5 \
753 0x218258UL
754 #define CNIG_REG_DBG_SHIFT_K2_E5 \
755 0x21825cUL
756 #define CNIG_REG_DBG_FORCE_VALID_K2_E5 \
757 0x218260UL
758 #define CNIG_REG_DBG_FORCE_FRAME_K2_E5 \
759 0x218264UL
760 #define PRM_REG_DBG_SELECT \
761 0x2306a8UL
762 #define PRM_REG_DBG_DWORD_ENABLE \
763 0x2306acUL
764 #define PRM_REG_DBG_SHIFT \
765 0x2306b0UL
766 #define PRM_REG_DBG_FORCE_VALID \
767 0x2306b4UL
768 #define PRM_REG_DBG_FORCE_FRAME \
769 0x2306b8UL
770 #define SRC_REG_DBG_SELECT \
771 0x238700UL
772 #define SRC_REG_DBG_DWORD_ENABLE \
773 0x238704UL
774 #define SRC_REG_DBG_SHIFT \
775 0x238708UL
776 #define SRC_REG_DBG_FORCE_VALID \
777 0x23870cUL
778 #define SRC_REG_DBG_FORCE_FRAME \
779 0x238710UL
780 #define RSS_REG_DBG_SELECT \
781 0x238c4cUL
782 #define RSS_REG_DBG_DWORD_ENABLE \
783 0x238c50UL
784 #define RSS_REG_DBG_SHIFT \
785 0x238c54UL
786 #define RSS_REG_DBG_FORCE_VALID \
787 0x238c58UL
788 #define RSS_REG_DBG_FORCE_FRAME \
789 0x238c5cUL
790 #define RPB_REG_DBG_SELECT \
791 0x23c728UL
792 #define RPB_REG_DBG_DWORD_ENABLE \
793 0x23c72cUL
794 #define RPB_REG_DBG_SHIFT \
795 0x23c730UL
796 #define RPB_REG_DBG_FORCE_VALID \
797 0x23c734UL
798 #define RPB_REG_DBG_FORCE_FRAME \
799 0x23c738UL
800 #define PSWRQ2_REG_DBG_SELECT \
801 0x240100UL
802 #define PSWRQ2_REG_DBG_DWORD_ENABLE \
803 0x240104UL
804 #define PSWRQ2_REG_DBG_SHIFT \
805 0x240108UL
806 #define PSWRQ2_REG_DBG_FORCE_VALID \
807 0x24010cUL
808 #define PSWRQ2_REG_DBG_FORCE_FRAME \
809 0x240110UL
810 #define PSWRQ_REG_DBG_SELECT \
811 0x280020UL
812 #define PSWRQ_REG_DBG_DWORD_ENABLE \
813 0x280024UL
814 #define PSWRQ_REG_DBG_SHIFT \
815 0x280028UL
816 #define PSWRQ_REG_DBG_FORCE_VALID \
817 0x28002cUL
818 #define PSWRQ_REG_DBG_FORCE_FRAME \
819 0x280030UL
820 #define PSWWR_REG_DBG_SELECT \
821 0x29a084UL
822 #define PSWWR_REG_DBG_DWORD_ENABLE \
823 0x29a088UL
824 #define PSWWR_REG_DBG_SHIFT \
825 0x29a08cUL
826 #define PSWWR_REG_DBG_FORCE_VALID \
827 0x29a090UL
828 #define PSWWR_REG_DBG_FORCE_FRAME \
829 0x29a094UL
830 #define PSWRD_REG_DBG_SELECT \
831 0x29c040UL
832 #define PSWRD_REG_DBG_DWORD_ENABLE \
833 0x29c044UL
834 #define PSWRD_REG_DBG_SHIFT \
835 0x29c048UL
836 #define PSWRD_REG_DBG_FORCE_VALID \
837 0x29c04cUL
838 #define PSWRD_REG_DBG_FORCE_FRAME \
839 0x29c050UL
840 #define PSWRD2_REG_DBG_SELECT \
841 0x29d400UL
842 #define PSWRD2_REG_DBG_DWORD_ENABLE \
843 0x29d404UL
844 #define PSWRD2_REG_DBG_SHIFT \
845 0x29d408UL
846 #define PSWRD2_REG_DBG_FORCE_VALID \
847 0x29d40cUL
848 #define PSWRD2_REG_DBG_FORCE_FRAME \
849 0x29d410UL
850 #define PSWHST2_REG_DBG_SELECT \
851 0x29e058UL
852 #define PSWHST2_REG_DBG_DWORD_ENABLE \
853 0x29e05cUL
854 #define PSWHST2_REG_DBG_SHIFT \
855 0x29e060UL
856 #define PSWHST2_REG_DBG_FORCE_VALID \
857 0x29e064UL
858 #define PSWHST2_REG_DBG_FORCE_FRAME \
859 0x29e068UL
860 #define PSWHST_REG_DBG_SELECT \
861 0x2a0100UL
862 #define PSWHST_REG_DBG_DWORD_ENABLE \
863 0x2a0104UL
864 #define PSWHST_REG_DBG_SHIFT \
865 0x2a0108UL
866 #define PSWHST_REG_DBG_FORCE_VALID \
867 0x2a010cUL
868 #define PSWHST_REG_DBG_FORCE_FRAME \
869 0x2a0110UL
870 #define PGLUE_B_REG_DBG_SELECT \
871 0x2a8400UL
872 #define PGLUE_B_REG_DBG_DWORD_ENABLE \
873 0x2a8404UL
874 #define PGLUE_B_REG_DBG_SHIFT \
875 0x2a8408UL
876 #define PGLUE_B_REG_DBG_FORCE_VALID \
877 0x2a840cUL
878 #define PGLUE_B_REG_DBG_FORCE_FRAME \
879 0x2a8410UL
880 #define TM_REG_DBG_SELECT \
881 0x2c07a8UL
882 #define TM_REG_DBG_DWORD_ENABLE \
883 0x2c07acUL
884 #define TM_REG_DBG_SHIFT \
885 0x2c07b0UL
886 #define TM_REG_DBG_FORCE_VALID \
887 0x2c07b4UL
888 #define TM_REG_DBG_FORCE_FRAME \
889 0x2c07b8UL
890 #define TCFC_REG_DBG_SELECT \
891 0x2d0500UL
892 #define TCFC_REG_DBG_DWORD_ENABLE \
893 0x2d0504UL
894 #define TCFC_REG_DBG_SHIFT \
895 0x2d0508UL
896 #define TCFC_REG_DBG_FORCE_VALID \
897 0x2d050cUL
898 #define TCFC_REG_DBG_FORCE_FRAME \
899 0x2d0510UL
900 #define CCFC_REG_DBG_SELECT \
901 0x2e0500UL
902 #define CCFC_REG_DBG_DWORD_ENABLE \
903 0x2e0504UL
904 #define CCFC_REG_DBG_SHIFT \
905 0x2e0508UL
906 #define CCFC_REG_DBG_FORCE_VALID \
907 0x2e050cUL
908 #define CCFC_REG_DBG_FORCE_FRAME \
909 0x2e0510UL
910 #define QM_REG_DBG_SELECT \
911 0x2f2e74UL
912 #define QM_REG_DBG_DWORD_ENABLE \
913 0x2f2e78UL
914 #define QM_REG_DBG_SHIFT \
915 0x2f2e7cUL
916 #define QM_REG_DBG_FORCE_VALID \
917 0x2f2e80UL
918 #define QM_REG_DBG_FORCE_FRAME \
919 0x2f2e84UL
920 #define RDIF_REG_DBG_SELECT \
921 0x300500UL
922 #define RDIF_REG_DBG_DWORD_ENABLE \
923 0x300504UL
924 #define RDIF_REG_DBG_SHIFT \
925 0x300508UL
926 #define RDIF_REG_DBG_FORCE_VALID \
927 0x30050cUL
928 #define RDIF_REG_DBG_FORCE_FRAME \
929 0x300510UL
930 #define TDIF_REG_DBG_SELECT \
931 0x310500UL
932 #define TDIF_REG_DBG_DWORD_ENABLE \
933 0x310504UL
934 #define TDIF_REG_DBG_SHIFT \
935 0x310508UL
936 #define TDIF_REG_DBG_FORCE_VALID \
937 0x31050cUL
938 #define TDIF_REG_DBG_FORCE_FRAME \
939 0x310510UL
940 #define BRB_REG_DBG_SELECT \
941 0x340ed0UL
942 #define BRB_REG_DBG_DWORD_ENABLE \
943 0x340ed4UL
944 #define BRB_REG_DBG_SHIFT \
945 0x340ed8UL
946 #define BRB_REG_DBG_FORCE_VALID \
947 0x340edcUL
948 #define BRB_REG_DBG_FORCE_FRAME \
949 0x340ee0UL
950 #define XYLD_REG_DBG_SELECT \
951 0x4c1600UL
952 #define XYLD_REG_DBG_DWORD_ENABLE \
953 0x4c1604UL
954 #define XYLD_REG_DBG_SHIFT \
955 0x4c1608UL
956 #define XYLD_REG_DBG_FORCE_VALID \
957 0x4c160cUL
958 #define XYLD_REG_DBG_FORCE_FRAME \
959 0x4c1610UL
960 #define YULD_REG_DBG_SELECT_BB_K2 \
961 0x4c9600UL
962 #define YULD_REG_DBG_DWORD_ENABLE_BB_K2 \
963 0x4c9604UL
964 #define YULD_REG_DBG_SHIFT_BB_K2 \
965 0x4c9608UL
966 #define YULD_REG_DBG_FORCE_VALID_BB_K2 \
967 0x4c960cUL
968 #define YULD_REG_DBG_FORCE_FRAME_BB_K2 \
969 0x4c9610UL
970 #define TMLD_REG_DBG_SELECT \
971 0x4d1600UL
972 #define TMLD_REG_DBG_DWORD_ENABLE \
973 0x4d1604UL
974 #define TMLD_REG_DBG_SHIFT \
975 0x4d1608UL
976 #define TMLD_REG_DBG_FORCE_VALID \
977 0x4d160cUL
978 #define TMLD_REG_DBG_FORCE_FRAME \
979 0x4d1610UL
980 #define MULD_REG_DBG_SELECT \
981 0x4e1600UL
982 #define MULD_REG_DBG_DWORD_ENABLE \
983 0x4e1604UL
984 #define MULD_REG_DBG_SHIFT \
985 0x4e1608UL
986 #define MULD_REG_DBG_FORCE_VALID \
987 0x4e160cUL
988 #define MULD_REG_DBG_FORCE_FRAME \
989 0x4e1610UL
990 #define NIG_REG_DBG_SELECT \
991 0x502140UL
992 #define NIG_REG_DBG_DWORD_ENABLE \
993 0x502144UL
994 #define NIG_REG_DBG_SHIFT \
995 0x502148UL
996 #define NIG_REG_DBG_FORCE_VALID \
997 0x50214cUL
998 #define NIG_REG_DBG_FORCE_FRAME \
999 0x502150UL
1000 #define BMB_REG_DBG_SELECT \
1001 0x540a7cUL
1002 #define BMB_REG_DBG_DWORD_ENABLE \
1003 0x540a80UL
1004 #define BMB_REG_DBG_SHIFT \
1005 0x540a84UL
1006 #define BMB_REG_DBG_FORCE_VALID \
1007 0x540a88UL
1008 #define BMB_REG_DBG_FORCE_FRAME \
1009 0x540a8cUL
1010 #define PTU_REG_DBG_SELECT \
1011 0x560100UL
1012 #define PTU_REG_DBG_DWORD_ENABLE \
1013 0x560104UL
1014 #define PTU_REG_DBG_SHIFT \
1015 0x560108UL
1016 #define PTU_REG_DBG_FORCE_VALID \
1017 0x56010cUL
1018 #define PTU_REG_DBG_FORCE_FRAME \
1019 0x560110UL
1020 #define CDU_REG_DBG_SELECT \
1021 0x580704UL
1022 #define CDU_REG_DBG_DWORD_ENABLE \
1023 0x580708UL
1024 #define CDU_REG_DBG_SHIFT \
1025 0x58070cUL
1026 #define CDU_REG_DBG_FORCE_VALID \
1027 0x580710UL
1028 #define CDU_REG_DBG_FORCE_FRAME \
1029 0x580714UL
1030 #define WOL_REG_DBG_SELECT_K2_E5 \
1031 0x600140UL
1032 #define WOL_REG_DBG_DWORD_ENABLE_K2_E5 \
1033 0x600144UL
1034 #define WOL_REG_DBG_SHIFT_K2_E5 \
1035 0x600148UL
1036 #define WOL_REG_DBG_FORCE_VALID_K2_E5 \
1037 0x60014cUL
1038 #define WOL_REG_DBG_FORCE_FRAME_K2_E5 \
1039 0x600150UL
1040 #define BMBN_REG_DBG_SELECT_K2_E5 \
1041 0x610140UL
1042 #define BMBN_REG_DBG_DWORD_ENABLE_K2_E5 \
1043 0x610144UL
1044 #define BMBN_REG_DBG_SHIFT_K2_E5 \
1045 0x610148UL
1046 #define BMBN_REG_DBG_FORCE_VALID_K2_E5 \
1047 0x61014cUL
1048 #define BMBN_REG_DBG_FORCE_FRAME_K2_E5 \
1049 0x610150UL
1050 #define NWM_REG_DBG_SELECT_K2_E5 \
1051 0x8000ecUL
1052 #define NWM_REG_DBG_DWORD_ENABLE_K2_E5 \
1053 0x8000f0UL
1054 #define NWM_REG_DBG_SHIFT_K2_E5 \
1055 0x8000f4UL
1056 #define NWM_REG_DBG_FORCE_VALID_K2_E5 \
1057 0x8000f8UL
1058 #define NWM_REG_DBG_FORCE_FRAME_K2_E5 \
1059 0x8000fcUL
1060 #define PBF_REG_DBG_SELECT \
1061 0xd80060UL
1062 #define PBF_REG_DBG_DWORD_ENABLE \
1063 0xd80064UL
1064 #define PBF_REG_DBG_SHIFT \
1065 0xd80068UL
1066 #define PBF_REG_DBG_FORCE_VALID \
1067 0xd8006cUL
1068 #define PBF_REG_DBG_FORCE_FRAME \
1069 0xd80070UL
1070 #define PBF_PB1_REG_DBG_SELECT \
1071 0xda0728UL
1072 #define PBF_PB1_REG_DBG_DWORD_ENABLE \
1073 0xda072cUL
1074 #define PBF_PB1_REG_DBG_SHIFT \
1075 0xda0730UL
1076 #define PBF_PB1_REG_DBG_FORCE_VALID \
1077 0xda0734UL
1078 #define PBF_PB1_REG_DBG_FORCE_FRAME \
1079 0xda0738UL
1080 #define PBF_PB2_REG_DBG_SELECT \
1081 0xda4728UL
1082 #define PBF_PB2_REG_DBG_DWORD_ENABLE \
1083 0xda472cUL
1084 #define PBF_PB2_REG_DBG_SHIFT \
1085 0xda4730UL
1086 #define PBF_PB2_REG_DBG_FORCE_VALID \
1087 0xda4734UL
1088 #define PBF_PB2_REG_DBG_FORCE_FRAME \
1089 0xda4738UL
1090 #define BTB_REG_DBG_SELECT \
1091 0xdb08c8UL
1092 #define BTB_REG_DBG_DWORD_ENABLE \
1093 0xdb08ccUL
1094 #define BTB_REG_DBG_SHIFT \
1095 0xdb08d0UL
1096 #define BTB_REG_DBG_FORCE_VALID \
1097 0xdb08d4UL
1098 #define BTB_REG_DBG_FORCE_FRAME \
1099 0xdb08d8UL
1100 #define XSDM_REG_DBG_SELECT \
1101 0xf80e28UL
1102 #define XSDM_REG_DBG_DWORD_ENABLE \
1103 0xf80e2cUL
1104 #define XSDM_REG_DBG_SHIFT \
1105 0xf80e30UL
1106 #define XSDM_REG_DBG_FORCE_VALID \
1107 0xf80e34UL
1108 #define XSDM_REG_DBG_FORCE_FRAME \
1109 0xf80e38UL
1110 #define YSDM_REG_DBG_SELECT \
1111 0xf90e28UL
1112 #define YSDM_REG_DBG_DWORD_ENABLE \
1113 0xf90e2cUL
1114 #define YSDM_REG_DBG_SHIFT \
1115 0xf90e30UL
1116 #define YSDM_REG_DBG_FORCE_VALID \
1117 0xf90e34UL
1118 #define YSDM_REG_DBG_FORCE_FRAME \
1119 0xf90e38UL
1120 #define PSDM_REG_DBG_SELECT \
1121 0xfa0e28UL
1122 #define PSDM_REG_DBG_DWORD_ENABLE \
1123 0xfa0e2cUL
1124 #define PSDM_REG_DBG_SHIFT \
1125 0xfa0e30UL
1126 #define PSDM_REG_DBG_FORCE_VALID \
1127 0xfa0e34UL
1128 #define PSDM_REG_DBG_FORCE_FRAME \
1129 0xfa0e38UL
1130 #define TSDM_REG_DBG_SELECT \
1131 0xfb0e28UL
1132 #define TSDM_REG_DBG_DWORD_ENABLE \
1133 0xfb0e2cUL
1134 #define TSDM_REG_DBG_SHIFT \
1135 0xfb0e30UL
1136 #define TSDM_REG_DBG_FORCE_VALID \
1137 0xfb0e34UL
1138 #define TSDM_REG_DBG_FORCE_FRAME \
1139 0xfb0e38UL
1140 #define MSDM_REG_DBG_SELECT \
1141 0xfc0e28UL
1142 #define MSDM_REG_DBG_DWORD_ENABLE \
1143 0xfc0e2cUL
1144 #define MSDM_REG_DBG_SHIFT \
1145 0xfc0e30UL
1146 #define MSDM_REG_DBG_FORCE_VALID \
1147 0xfc0e34UL
1148 #define MSDM_REG_DBG_FORCE_FRAME \
1149 0xfc0e38UL
1150 #define USDM_REG_DBG_SELECT \
1151 0xfd0e28UL
1152 #define USDM_REG_DBG_DWORD_ENABLE \
1153 0xfd0e2cUL
1154 #define USDM_REG_DBG_SHIFT \
1155 0xfd0e30UL
1156 #define USDM_REG_DBG_FORCE_VALID \
1157 0xfd0e34UL
1158 #define USDM_REG_DBG_FORCE_FRAME \
1159 0xfd0e38UL
1160 #define XCM_REG_DBG_SELECT \
1161 0x1000040UL
1162 #define XCM_REG_DBG_DWORD_ENABLE \
1163 0x1000044UL
1164 #define XCM_REG_DBG_SHIFT \
1165 0x1000048UL
1166 #define XCM_REG_DBG_FORCE_VALID \
1167 0x100004cUL
1168 #define XCM_REG_DBG_FORCE_FRAME \
1169 0x1000050UL
1170 #define YCM_REG_DBG_SELECT \
1171 0x1080040UL
1172 #define YCM_REG_DBG_DWORD_ENABLE \
1173 0x1080044UL
1174 #define YCM_REG_DBG_SHIFT \
1175 0x1080048UL
1176 #define YCM_REG_DBG_FORCE_VALID \
1177 0x108004cUL
1178 #define YCM_REG_DBG_FORCE_FRAME \
1179 0x1080050UL
1180 #define PCM_REG_DBG_SELECT \
1181 0x1100040UL
1182 #define PCM_REG_DBG_DWORD_ENABLE \
1183 0x1100044UL
1184 #define PCM_REG_DBG_SHIFT \
1185 0x1100048UL
1186 #define PCM_REG_DBG_FORCE_VALID \
1187 0x110004cUL
1188 #define PCM_REG_DBG_FORCE_FRAME \
1189 0x1100050UL
1190 #define TCM_REG_DBG_SELECT \
1191 0x1180040UL
1192 #define TCM_REG_DBG_DWORD_ENABLE \
1193 0x1180044UL
1194 #define TCM_REG_DBG_SHIFT \
1195 0x1180048UL
1196 #define TCM_REG_DBG_FORCE_VALID \
1197 0x118004cUL
1198 #define TCM_REG_DBG_FORCE_FRAME \
1199 0x1180050UL
1200 #define MCM_REG_DBG_SELECT \
1201 0x1200040UL
1202 #define MCM_REG_DBG_DWORD_ENABLE \
1203 0x1200044UL
1204 #define MCM_REG_DBG_SHIFT \
1205 0x1200048UL
1206 #define MCM_REG_DBG_FORCE_VALID \
1207 0x120004cUL
1208 #define MCM_REG_DBG_FORCE_FRAME \
1209 0x1200050UL
1210 #define UCM_REG_DBG_SELECT \
1211 0x1280050UL
1212 #define UCM_REG_DBG_DWORD_ENABLE \
1213 0x1280054UL
1214 #define UCM_REG_DBG_SHIFT \
1215 0x1280058UL
1216 #define UCM_REG_DBG_FORCE_VALID \
1217 0x128005cUL
1218 #define UCM_REG_DBG_FORCE_FRAME \
1219 0x1280060UL
1220 #define XSEM_REG_DBG_SELECT \
1221 0x1401528UL
1222 #define XSEM_REG_DBG_DWORD_ENABLE \
1223 0x140152cUL
1224 #define XSEM_REG_DBG_SHIFT \
1225 0x1401530UL
1226 #define XSEM_REG_DBG_FORCE_VALID \
1227 0x1401534UL
1228 #define XSEM_REG_DBG_FORCE_FRAME \
1229 0x1401538UL
1230 #define YSEM_REG_DBG_SELECT \
1231 0x1501528UL
1232 #define YSEM_REG_DBG_DWORD_ENABLE \
1233 0x150152cUL
1234 #define YSEM_REG_DBG_SHIFT \
1235 0x1501530UL
1236 #define YSEM_REG_DBG_FORCE_VALID \
1237 0x1501534UL
1238 #define YSEM_REG_DBG_FORCE_FRAME \
1239 0x1501538UL
1240 #define PSEM_REG_DBG_SELECT \
1241 0x1601528UL
1242 #define PSEM_REG_DBG_DWORD_ENABLE \
1243 0x160152cUL
1244 #define PSEM_REG_DBG_SHIFT \
1245 0x1601530UL
1246 #define PSEM_REG_DBG_FORCE_VALID \
1247 0x1601534UL
1248 #define PSEM_REG_DBG_FORCE_FRAME \
1249 0x1601538UL
1250 #define TSEM_REG_DBG_SELECT \
1251 0x1701528UL
1252 #define TSEM_REG_DBG_DWORD_ENABLE \
1253 0x170152cUL
1254 #define TSEM_REG_DBG_SHIFT \
1255 0x1701530UL
1256 #define TSEM_REG_DBG_FORCE_VALID \
1257 0x1701534UL
1258 #define TSEM_REG_DBG_FORCE_FRAME \
1259 0x1701538UL
1260 #define DORQ_REG_PF_USAGE_CNT \
1261 0x1009c0UL
1262 #define DORQ_REG_PF_OVFL_STICKY \
1263 0x1009d0UL
1264 #define DORQ_REG_DPM_FORCE_ABORT \
1265 0x1009d8UL
1266 #define DORQ_REG_INT_STS \
1267 0x100180UL
1268 #define DORQ_REG_INT_STS_ADDRESS_ERROR \
1269 (0x1UL << 0)
1270 #define DORQ_REG_INT_STS_WR \
1271 0x100188UL
1272 #define DORQ_REG_DB_DROP_DETAILS_REL \
1273 0x100a28UL
1274 #define DORQ_REG_INT_STS_ADDRESS_ERROR_SHIFT \
1275 0
1276 #define DORQ_REG_INT_STS_DB_DROP \
1277 (0x1UL << 1)
1278 #define DORQ_REG_INT_STS_DB_DROP_SHIFT \
1279 1
1280 #define DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR \
1281 (0x1UL << 2)
1282 #define DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR_SHIFT \
1283 2
1284 #define DORQ_REG_INT_STS_DORQ_FIFO_AFULL\
1285 (0x1UL << 3)
1286 #define DORQ_REG_INT_STS_DORQ_FIFO_AFULL_SHIFT \
1287 3
1288 #define DORQ_REG_INT_STS_CFC_BYP_VALIDATION_ERR \
1289 (0x1UL << 4)
1290 #define DORQ_REG_INT_STS_CFC_BYP_VALIDATION_ERR_SHIFT \
1291 4
1292 #define DORQ_REG_INT_STS_CFC_LD_RESP_ERR \
1293 (0x1UL << 5)
1294 #define DORQ_REG_INT_STS_CFC_LD_RESP_ERR_SHIFT \
1295 5
1296 #define DORQ_REG_INT_STS_XCM_DONE_CNT_ERR \
1297 (0x1UL << 6)
1298 #define DORQ_REG_INT_STS_XCM_DONE_CNT_ERR_SHIFT \
1299 6
1300 #define DORQ_REG_INT_STS_CFC_LD_REQ_FIFO_OVFL_ERR \
1301 (0x1UL << 7)
1302 #define DORQ_REG_INT_STS_CFC_LD_REQ_FIFO_OVFL_ERR_SHIFT \
1303 7
1304 #define DORQ_REG_INT_STS_CFC_LD_REQ_FIFO_UNDER_ERR \
1305 (0x1UL << 8)
1306 #define DORQ_REG_INT_STS_CFC_LD_REQ_FIFO_UNDER_ERR_SHIFT \
1307 8
1308 #define DORQ_REG_DB_DROP_DETAILS_REASON \
1309 0x100a20UL
1310 #define MSEM_REG_DBG_SELECT \
1311 0x1801528UL
1312 #define MSEM_REG_DBG_DWORD_ENABLE \
1313 0x180152cUL
1314 #define MSEM_REG_DBG_SHIFT \
1315 0x1801530UL
1316 #define MSEM_REG_DBG_FORCE_VALID \
1317 0x1801534UL
1318 #define MSEM_REG_DBG_FORCE_FRAME \
1319 0x1801538UL
1320 #define USEM_REG_DBG_SELECT \
1321 0x1901528UL
1322 #define USEM_REG_DBG_DWORD_ENABLE \
1323 0x190152cUL
1324 #define USEM_REG_DBG_SHIFT \
1325 0x1901530UL
1326 #define USEM_REG_DBG_FORCE_VALID \
1327 0x1901534UL
1328 #define USEM_REG_DBG_FORCE_FRAME \
1329 0x1901538UL
1330 #define NWS_REG_DBG_SELECT_K2_E5 \
1331 0x700128UL
1332 #define NWS_REG_DBG_DWORD_ENABLE_K2_E5 \
1333 0x70012cUL
1334 #define NWS_REG_DBG_SHIFT_K2_E5 \
1335 0x700130UL
1336 #define NWS_REG_DBG_FORCE_VALID_K2_E5 \
1337 0x700134UL
1338 #define NWS_REG_DBG_FORCE_FRAME_K2_E5 \
1339 0x700138UL
1340 #define MS_REG_DBG_SELECT_K2_E5 \
1341 0x6a0228UL
1342 #define MS_REG_DBG_DWORD_ENABLE_K2_E5 \
1343 0x6a022cUL
1344 #define MS_REG_DBG_SHIFT_K2_E5 \
1345 0x6a0230UL
1346 #define MS_REG_DBG_FORCE_VALID_K2_E5 \
1347 0x6a0234UL
1348 #define MS_REG_DBG_FORCE_FRAME_K2_E5 \
1349 0x6a0238UL
1350 #define PCIE_REG_DBG_COMMON_SELECT_K2_E5 \
1351 0x054398UL
1352 #define PCIE_REG_DBG_COMMON_DWORD_ENABLE_K2_E5 \
1353 0x05439cUL
1354 #define PCIE_REG_DBG_COMMON_SHIFT_K2_E5 \
1355 0x0543a0UL
1356 #define PCIE_REG_DBG_COMMON_FORCE_VALID_K2_E5 \
1357 0x0543a4UL
1358 #define PCIE_REG_DBG_COMMON_FORCE_FRAME_K2_E5 \
1359 0x0543a8UL
1360 #define PTLD_REG_DBG_SELECT_E5 \
1361 0x5a1600UL
1362 #define PTLD_REG_DBG_DWORD_ENABLE_E5 \
1363 0x5a1604UL
1364 #define PTLD_REG_DBG_SHIFT_E5 \
1365 0x5a1608UL
1366 #define PTLD_REG_DBG_FORCE_VALID_E5 \
1367 0x5a160cUL
1368 #define PTLD_REG_DBG_FORCE_FRAME_E5 \
1369 0x5a1610UL
1370 #define YPLD_REG_DBG_SELECT_E5 \
1371 0x5c1600UL
1372 #define YPLD_REG_DBG_DWORD_ENABLE_E5 \
1373 0x5c1604UL
1374 #define YPLD_REG_DBG_SHIFT_E5 \
1375 0x5c1608UL
1376 #define YPLD_REG_DBG_FORCE_VALID_E5 \
1377 0x5c160cUL
1378 #define YPLD_REG_DBG_FORCE_FRAME_E5 \
1379 0x5c1610UL
1380 #define RGSRC_REG_DBG_SELECT_E5 \
1381 0x320040UL
1382 #define RGSRC_REG_DBG_DWORD_ENABLE_E5 \
1383 0x320044UL
1384 #define RGSRC_REG_DBG_SHIFT_E5 \
1385 0x320048UL
1386 #define RGSRC_REG_DBG_FORCE_VALID_E5 \
1387 0x32004cUL
1388 #define RGSRC_REG_DBG_FORCE_FRAME_E5 \
1389 0x320050UL
1390 #define TGSRC_REG_DBG_SELECT_E5 \
1391 0x322040UL
1392 #define TGSRC_REG_DBG_DWORD_ENABLE_E5 \
1393 0x322044UL
1394 #define TGSRC_REG_DBG_SHIFT_E5 \
1395 0x322048UL
1396 #define TGSRC_REG_DBG_FORCE_VALID_E5 \
1397 0x32204cUL
1398 #define TGSRC_REG_DBG_FORCE_FRAME_E5 \
1399 0x322050UL
1400 #define MISC_REG_RESET_PL_UA \
1401 0x008050UL
1402 #define MISC_REG_RESET_PL_HV \
1403 0x008060UL
1404 #define XCM_REG_CTX_RBC_ACCS \
1405 0x1001800UL
1406 #define XCM_REG_AGG_CON_CTX \
1407 0x1001804UL
1408 #define XCM_REG_SM_CON_CTX \
1409 0x1001808UL
1410 #define YCM_REG_CTX_RBC_ACCS \
1411 0x1081800UL
1412 #define YCM_REG_AGG_CON_CTX \
1413 0x1081804UL
1414 #define YCM_REG_AGG_TASK_CTX \
1415 0x1081808UL
1416 #define YCM_REG_SM_CON_CTX \
1417 0x108180cUL
1418 #define YCM_REG_SM_TASK_CTX \
1419 0x1081810UL
1420 #define PCM_REG_CTX_RBC_ACCS \
1421 0x1101440UL
1422 #define PCM_REG_SM_CON_CTX \
1423 0x1101444UL
1424 #define TCM_REG_CTX_RBC_ACCS \
1425 0x11814c0UL
1426 #define TCM_REG_AGG_CON_CTX \
1427 0x11814c4UL
1428 #define TCM_REG_AGG_TASK_CTX \
1429 0x11814c8UL
1430 #define TCM_REG_SM_CON_CTX \
1431 0x11814ccUL
1432 #define TCM_REG_SM_TASK_CTX \
1433 0x11814d0UL
1434 #define MCM_REG_CTX_RBC_ACCS \
1435 0x1201800UL
1436 #define MCM_REG_AGG_CON_CTX \
1437 0x1201804UL
1438 #define MCM_REG_AGG_TASK_CTX \
1439 0x1201808UL
1440 #define MCM_REG_SM_CON_CTX \
1441 0x120180cUL
1442 #define MCM_REG_SM_TASK_CTX \
1443 0x1201810UL
1444 #define UCM_REG_CTX_RBC_ACCS \
1445 0x1281700UL
1446 #define UCM_REG_AGG_CON_CTX \
1447 0x1281704UL
1448 #define UCM_REG_AGG_TASK_CTX \
1449 0x1281708UL
1450 #define UCM_REG_SM_CON_CTX \
1451 0x128170cUL
1452 #define UCM_REG_SM_TASK_CTX \
1453 0x1281710UL
1454 #define XSEM_REG_SLOW_DBG_EMPTY_BB_K2 \
1455 0x1401140UL
1456 #define XSEM_REG_SYNC_DBG_EMPTY \
1457 0x1401160UL
1458 #define XSEM_REG_SLOW_DBG_ACTIVE_BB_K2 \
1459 0x1401400UL
1460 #define XSEM_REG_SLOW_DBG_MODE_BB_K2 \
1461 0x1401404UL
1462 #define XSEM_REG_DBG_FRAME_MODE_BB_K2 \
1463 0x1401408UL
1464 #define XSEM_REG_DBG_GPRE_VECT \
1465 0x1401410UL
1466 #define XSEM_REG_DBG_MODE1_CFG_BB_K2 \
1467 0x1401420UL
1468 #define XSEM_REG_FAST_MEMORY \
1469 0x1440000UL
1470 #define YSEM_REG_SYNC_DBG_EMPTY \
1471 0x1501160UL
1472 #define YSEM_REG_SLOW_DBG_ACTIVE_BB_K2 \
1473 0x1501400UL
1474 #define YSEM_REG_SLOW_DBG_MODE_BB_K2 \
1475 0x1501404UL
1476 #define YSEM_REG_DBG_FRAME_MODE_BB_K2 \
1477 0x1501408UL
1478 #define YSEM_REG_DBG_GPRE_VECT \
1479 0x1501410UL
1480 #define YSEM_REG_DBG_MODE1_CFG_BB_K2 \
1481 0x1501420UL
1482 #define YSEM_REG_FAST_MEMORY \
1483 0x1540000UL
1484 #define PSEM_REG_SLOW_DBG_EMPTY_BB_K2 \
1485 0x1601140UL
1486 #define PSEM_REG_SYNC_DBG_EMPTY \
1487 0x1601160UL
1488 #define PSEM_REG_SLOW_DBG_ACTIVE_BB_K2 \
1489 0x1601400UL
1490 #define PSEM_REG_SLOW_DBG_MODE_BB_K2 \
1491 0x1601404UL
1492 #define PSEM_REG_DBG_FRAME_MODE_BB_K2 \
1493 0x1601408UL
1494 #define PSEM_REG_DBG_GPRE_VECT \
1495 0x1601410UL
1496 #define PSEM_REG_DBG_MODE1_CFG_BB_K2 \
1497 0x1601420UL
1498 #define PSEM_REG_FAST_MEMORY \
1499 0x1640000UL
1500 #define TSEM_REG_SLOW_DBG_EMPTY_BB_K2 \
1501 0x1701140UL
1502 #define TSEM_REG_SYNC_DBG_EMPTY \
1503 0x1701160UL
1504 #define TSEM_REG_SLOW_DBG_ACTIVE_BB_K2 \
1505 0x1701400UL
1506 #define TSEM_REG_SLOW_DBG_MODE_BB_K2 \
1507 0x1701404UL
1508 #define TSEM_REG_DBG_FRAME_MODE_BB_K2 \
1509 0x1701408UL
1510 #define TSEM_REG_DBG_GPRE_VECT \
1511 0x1701410UL
1512 #define TSEM_REG_DBG_MODE1_CFG_BB_K2 \
1513 0x1701420UL
1514 #define TSEM_REG_FAST_MEMORY \
1515 0x1740000UL
1516 #define MSEM_REG_SLOW_DBG_EMPTY_BB_K2 \
1517 0x1801140UL
1518 #define MSEM_REG_SYNC_DBG_EMPTY \
1519 0x1801160UL
1520 #define MSEM_REG_SLOW_DBG_ACTIVE_BB_K2 \
1521 0x1801400UL
1522 #define MSEM_REG_SLOW_DBG_MODE_BB_K2 \
1523 0x1801404UL
1524 #define MSEM_REG_DBG_FRAME_MODE_BB_K2 \
1525 0x1801408UL
1526 #define MSEM_REG_DBG_GPRE_VECT \
1527 0x1801410UL
1528 #define MSEM_REG_DBG_MODE1_CFG_BB_K2 \
1529 0x1801420UL
1530 #define MSEM_REG_FAST_MEMORY \
1531 0x1840000UL
1532 #define USEM_REG_SLOW_DBG_EMPTY_BB_K2 \
1533 0x1901140UL
1534 #define SEM_FAST_REG_INT_RAM_SIZE \
1535 20480
1536 #define USEM_REG_SYNC_DBG_EMPTY \
1537 0x1901160UL
1538 #define USEM_REG_SLOW_DBG_ACTIVE_BB_K2 \
1539 0x1901400UL
1540 #define USEM_REG_SLOW_DBG_MODE_BB_K2 \
1541 0x1901404UL
1542 #define USEM_REG_DBG_FRAME_MODE_BB_K2 \
1543 0x1901408UL
1544 #define USEM_REG_DBG_GPRE_VECT \
1545 0x1901410UL
1546 #define USEM_REG_DBG_MODE1_CFG_BB_K2 \
1547 0x1901420UL
1548 #define USEM_REG_FAST_MEMORY \
1549 0x1940000UL
1550 #define SEM_FAST_REG_DBG_MODE23_SRC_DISABLE \
1551 0x000748UL
1552 #define SEM_FAST_REG_DBG_MODE4_SRC_DISABLE \
1553 0x00074cUL
1554 #define SEM_FAST_REG_DBG_MODE6_SRC_DISABLE \
1555 0x000750UL
1556 #define SEM_FAST_REG_DEBUG_ACTIVE \
1557 0x000740UL
1558 #define SEM_FAST_REG_INT_RAM \
1559 0x020000UL
1560 #define SEM_FAST_REG_INT_RAM_SIZE_BB_K2 \
1561 20480
1562 #define SEM_FAST_REG_RECORD_FILTER_ENABLE \
1563 0x000768UL
1564 #define GRC_REG_TRACE_FIFO_VALID_DATA \
1565 0x050064UL
1566 #define GRC_REG_NUMBER_VALID_OVERRIDE_WINDOW \
1567 0x05040cUL
1568 #define GRC_REG_PROTECTION_OVERRIDE_WINDOW \
1569 0x050500UL
1570 #define IGU_REG_ERROR_HANDLING_MEMORY \
1571 0x181520UL
1572 #define MCP_REG_CPU_MODE \
1573 0xe05000UL
1574 #define MCP_REG_CPU_MODE_SOFT_HALT \
1575 (0x1 << 10)
1576 #define BRB_REG_BIG_RAM_ADDRESS \
1577 0x340800UL
1578 #define BRB_REG_BIG_RAM_DATA \
1579 0x341500UL
1580 #define BRB_REG_BIG_RAM_DATA_SIZE \
1581 64
1582 #define SEM_FAST_REG_STALL_0_BB_K2 \
1583 0x000488UL
1584 #define SEM_FAST_REG_STALLED \
1585 0x000494UL
1586 #define BTB_REG_BIG_RAM_ADDRESS \
1587 0xdb0800UL
1588 #define BTB_REG_BIG_RAM_DATA \
1589 0xdb0c00UL
1590 #define BMB_REG_BIG_RAM_ADDRESS \
1591 0x540800UL
1592 #define BMB_REG_BIG_RAM_DATA \
1593 0x540f00UL
1594 #define SEM_FAST_REG_STORM_REG_FILE \
1595 0x008000UL
1596 #define RSS_REG_RSS_RAM_ADDR \
1597 0x238c30UL
1598 #define MISCS_REG_BLOCK_256B_EN \
1599 0x009074UL
1600 #define MCP_REG_SCRATCH_SIZE_BB_K2 \
1601 57344
1602 #define MCP_REG_CPU_REG_FILE \
1603 0xe05200UL
1604 #define MCP_REG_CPU_REG_FILE_SIZE \
1605 32
1606 #define DBG_REG_DEBUG_TARGET \
1607 0x01005cUL
1608 #define DBG_REG_FULL_MODE \
1609 0x010060UL
1610 #define DBG_REG_CALENDAR_OUT_DATA \
1611 0x010480UL
1612 #define GRC_REG_TRACE_FIFO \
1613 0x050068UL
1614 #define IGU_REG_ERROR_HANDLING_DATA_VALID \
1615 0x181530UL
1616 #define DBG_REG_DBG_BLOCK_ON \
1617 0x010454UL
1618 #define DBG_REG_FILTER_ENABLE \
1619 0x0109d0UL
1620 #define DBG_REG_FRAMING_MODE \
1621 0x010058UL
1622 #define DBG_REG_TRIGGER_ENABLE \
1623 0x01054cUL
1624 #define SEM_FAST_REG_VFC_DATA_WR \
1625 0x000b40UL
1626 #define SEM_FAST_REG_VFC_ADDR \
1627 0x000b44UL
1628 #define SEM_FAST_REG_VFC_DATA_RD \
1629 0x000b48UL
1630 #define SEM_FAST_REG_VFC_STATUS \
1631 0x000b4cUL
1632 #define RSS_REG_RSS_RAM_DATA \
1633 0x238c20UL
1634 #define RSS_REG_RSS_RAM_DATA_SIZE \
1635 4
1636 #define MISC_REG_BLOCK_256B_EN \
1637 0x008c14UL
1638 #define NWS_REG_NWS_CMU_K2 \
1639 0x720000UL
1640 #define PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_7_0_K2_E5 \
1641 0x000680UL
1642 #define PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_15_8_K2_E5 \
1643 0x000684UL
1644 #define PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_7_0_K2_E5 \
1645 0x0006c0UL
1646 #define PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_11_8_K2_E5 \
1647 0x0006c4UL
1648 #define MS_REG_MS_CMU_K2_E5 \
1649 0x6a4000UL
1650 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X130_K2_E5 \
1651 0x000208UL
1652 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X131_K2_E5 \
1653 0x00020cUL
1654 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X132_K2_E5 \
1655 0x000210UL
1656 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X133_K2_E5 \
1657 0x000214UL
1658 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X130_K2_E5 \
1659 0x000208UL
1660 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X131_K2_E5 \
1661 0x00020cUL
1662 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X132_K2_E5 \
1663 0x000210UL
1664 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X133_K2_E5 \
1665 0x000214UL
1666 #define PHY_PCIE_REG_PHY0_K2_E5 \
1667 0x620000UL
1668 #define PHY_PCIE_REG_PHY1_K2_E5 \
1669 0x624000UL
1670 #define NIG_REG_ROCE_DUPLICATE_TO_HOST 0x5088f0UL
1671 #define NIG_REG_PPF_TO_ENGINE_SEL 0x508900UL
1672 #define NIG_REG_PPF_TO_ENGINE_SEL_SIZE 8
1673 #define PRS_REG_LIGHT_L2_ETHERTYPE_EN 0x1f0968UL
1674 #define NIG_REG_LLH_ENG_CLS_ENG_ID_TBL 0x501b90UL
1675 #define DORQ_REG_PF_DPM_ENABLE 0x100510UL
1676 #define DORQ_REG_PF_ICID_BIT_SHIFT_NORM 0x100448UL
1677 #define DORQ_REG_PF_MIN_ADDR_REG1 0x100400UL
1678 #define DORQ_REG_PF_DPI_BIT_SHIFT 0x100450UL
1679 #define NIG_REG_RX_PTP_EN 0x501900UL
1680 #define NIG_REG_TX_PTP_EN 0x501904UL
1681 #define NIG_REG_LLH_PTP_TO_HOST 0x501908UL
1682 #define NIG_REG_LLH_PTP_TO_MCP 0x50190cUL
1683 #define NIG_REG_PTP_SW_TXTSEN 0x501910UL
1684 #define NIG_REG_LLH_PTP_ETHERTYPE_1 0x501914UL
1685 #define NIG_REG_LLH_PTP_MAC_DA_2_LSB 0x501918UL
1686 #define NIG_REG_LLH_PTP_MAC_DA_2_MSB 0x50191cUL
1687 #define NIG_REG_LLH_PTP_PARAM_MASK 0x501920UL
1688 #define NIG_REG_LLH_PTP_RULE_MASK 0x501924UL
1689 #define NIG_REG_TX_LLH_PTP_PARAM_MASK 0x501928UL
1690 #define NIG_REG_TX_LLH_PTP_RULE_MASK 0x50192cUL
1691 #define NIG_REG_LLH_PTP_HOST_BUF_SEQID 0x501930UL
1692 #define NIG_REG_LLH_PTP_HOST_BUF_TS_LSB 0x501934UL
1693 #define NIG_REG_LLH_PTP_HOST_BUF_TS_MSB 0x501938UL
1694 #define NIG_REG_LLH_PTP_MCP_BUF_SEQID 0x50193cUL
1695 #define NIG_REG_LLH_PTP_MCP_BUF_TS_LSB 0x501940UL
1696 #define NIG_REG_LLH_PTP_MCP_BUF_TS_MSB 0x501944UL
1697 #define NIG_REG_TX_LLH_PTP_BUF_SEQID 0x501948UL
1698 #define NIG_REG_TX_LLH_PTP_BUF_TS_LSB 0x50194cUL
1699 #define NIG_REG_TX_LLH_PTP_BUF_TS_MSB 0x501950UL
1700 #define NIG_REG_RX_PTP_TS_MSB_ERR 0x501954UL
1701 #define NIG_REG_TX_PTP_TS_MSB_ERR 0x501958UL
1702 #define NIG_REG_TSGEN_SYNC_TIME_LSB 0x5088c0UL
1703 #define NIG_REG_TSGEN_SYNC_TIME_MSB 0x5088c4UL
1704 #define NIG_REG_TSGEN_RST_DRIFT_CNTR 0x5088d8UL
1705 #define NIG_REG_TSGEN_DRIFT_CNTR_CONF 0x5088dcUL
1706 #define NIG_REG_TS_OUTPUT_ENABLE_PDA 0x508870UL
1707 #define NIG_REG_TIMESYNC_GEN_REG_BB 0x500d00UL
1708 #define NIG_REG_TSGEN_FREE_CNT_VALUE_LSB 0x5088a8UL
1709 #define NIG_REG_TSGEN_FREE_CNT_VALUE_MSB 0x5088acUL
1710 #define NIG_REG_PTP_LATCH_OSTS_PKT_TIME 0x509040UL
1711 #define PSWRQ2_REG_WR_MBS0 0x240400UL
1713 #define PGLUE_B_REG_PGL_ADDR_E8_F0_K2 0x2aaf98UL
1714 #define PGLUE_B_REG_PGL_ADDR_EC_F0_K2 0x2aaf9cUL
1715 #define PGLUE_B_REG_PGL_ADDR_F0_F0_K2 0x2aafa0UL
1716 #define PGLUE_B_REG_PGL_ADDR_F4_F0_K2 0x2aafa4UL
1717 #define PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE 0x2aae30UL
1718 #define NIG_REG_TSGEN_FREECNT_UPDATE_K2 0x509008UL
1719 #define CNIG_REG_NIG_PORT0_CONF_K2 0x218200UL
1721 #define NIG_REG_TX_EDPM_CTRL 0x501f0cUL
1722 #define NIG_REG_TX_EDPM_CTRL_TX_EDPM_EN (0x1 << 0)
1723 #define NIG_REG_TX_EDPM_CTRL_TX_EDPM_EN_SHIFT 0
1724 #define NIG_REG_TX_EDPM_CTRL_TX_EDPM_TC_EN (0xff << 1)
1725 #define NIG_REG_TX_EDPM_CTRL_TX_EDPM_TC_EN_SHIFT 1
1727 #define PRS_REG_SEARCH_GFT 0x1f11bcUL
1728 #define PRS_REG_SEARCH_NON_IP_AS_GFT 0x1f11c0UL
1729 #define PRS_REG_CM_HDR_GFT 0x1f11c8UL
1730 #define PRS_REG_GFT_CAM 0x1f1100UL
1731 #define PRS_REG_GFT_PROFILE_MASK_RAM 0x1f1000UL
1732 #define PRS_REG_CM_HDR_GFT_EVENT_ID_SHIFT 0
1733 #define PRS_REG_CM_HDR_GFT_CM_HDR_SHIFT 8
1734 #define PRS_REG_LOAD_L2_FILTER 0x1f0198UL
1736 #endif