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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / net / ethernet / realtek / r8169_main.c
blobaaa316be6183ca69f85d2871a8b342ab5398ab84
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 *
5 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
7 * Copyright (c) a lot of people too. Please respect their work.
8 *
9 * See MAINTAINERS file for support contact information.
10 */
11
12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/pci.h>
15 #include <linux/netdevice.h>
16 #include <linux/etherdevice.h>
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/ethtool.h>
20 #include <linux/phy.h>
21 #include <linux/if_vlan.h>
22 #include <linux/crc32.h>
23 #include <linux/in.h>
24 #include <linux/io.h>
25 #include <linux/ip.h>
26 #include <linux/tcp.h>
27 #include <linux/interrupt.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/prefetch.h>
31 #include <linux/ipv6.h>
32 #include <net/ip6_checksum.h>
33
34 #include "r8169.h"
35 #include "r8169_firmware.h"
36
37 #define MODULENAME "r8169"
38
39 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
40 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
41 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
42 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
43 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
44 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
45 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
46 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
47 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
48 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
49 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
50 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
51 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
52 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
53 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
54 #define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw"
55 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
56 #define FIRMWARE_8168FP_3 "rtl_nic/rtl8168fp-3.fw"
57 #define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw"
58 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
59 #define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw"
60
61 #define R8169_MSG_DEFAULT \
62 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
63
64 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
65 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
66 #define MC_FILTER_LIMIT 32
67
68 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
69 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
70
71 #define R8169_REGS_SIZE 256
72 #define R8169_RX_BUF_SIZE (SZ_16K - 1)
73 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
74 #define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
75 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
76 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
77
78 #define RTL_CFG_NO_GBIT 1
79
80 /* write/read MMIO register */
81 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg))
82 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
83 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
84 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg))
85 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg))
86 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg))
87
88 #define JUMBO_4K (4*1024 - ETH_HLEN - 2)
89 #define JUMBO_6K (6*1024 - ETH_HLEN - 2)
90 #define JUMBO_7K (7*1024 - ETH_HLEN - 2)
91 #define JUMBO_9K (9*1024 - ETH_HLEN - 2)
92
93 static const struct {
94 const char *name;
95 const char *fw_name;
96 } rtl_chip_infos[] = {
97 /* PCI devices. */
98 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" },
99 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" },
100 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" },
101 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" },
102 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" },
103 /* PCI-E devices. */
104 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" },
105 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" },
106 [RTL_GIGA_MAC_VER_09] = {"RTL8102e/RTL8103e" },
107 [RTL_GIGA_MAC_VER_10] = {"RTL8101e" },
108 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" },
109 [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b" },
110 [RTL_GIGA_MAC_VER_13] = {"RTL8101e" },
111 [RTL_GIGA_MAC_VER_14] = {"RTL8100e" },
112 [RTL_GIGA_MAC_VER_15] = {"RTL8100e" },
113 [RTL_GIGA_MAC_VER_16] = {"RTL8101e" },
114 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" },
115 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" },
116 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" },
117 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" },
118 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" },
119 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" },
120 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" },
121 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" },
122 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1},
123 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2},
124 [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp" },
125 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" },
126 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1},
127 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1},
128 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" },
129 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1},
130 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2},
131 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3},
132 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1},
133 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2},
134 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 },
135 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 },
136 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1},
137 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2},
138 [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g" },
139 [RTL_GIGA_MAC_VER_42] = {"RTL8168gu/8111gu", FIRMWARE_8168G_3},
140 [RTL_GIGA_MAC_VER_43] = {"RTL8106eus", FIRMWARE_8106E_2},
141 [RTL_GIGA_MAC_VER_44] = {"RTL8411b", FIRMWARE_8411_2 },
142 [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h", FIRMWARE_8168H_1},
143 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2},
144 [RTL_GIGA_MAC_VER_47] = {"RTL8107e", FIRMWARE_8107E_1},
145 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2},
146 [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep" },
147 [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep" },
148 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" },
149 [RTL_GIGA_MAC_VER_52] = {"RTL8168fp/RTL8117", FIRMWARE_8168FP_3},
150 [RTL_GIGA_MAC_VER_60] = {"RTL8125" },
151 [RTL_GIGA_MAC_VER_61] = {"RTL8125", FIRMWARE_8125A_3},
152 };
153
154 static const struct pci_device_id rtl8169_pci_tbl[] = {
155 { PCI_VDEVICE(REALTEK, 0x2502) },
156 { PCI_VDEVICE(REALTEK, 0x2600) },
157 { PCI_VDEVICE(REALTEK, 0x8129) },
158 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT },
159 { PCI_VDEVICE(REALTEK, 0x8161) },
160 { PCI_VDEVICE(REALTEK, 0x8167) },
161 { PCI_VDEVICE(REALTEK, 0x8168) },
162 { PCI_VDEVICE(NCUBE, 0x8168) },
163 { PCI_VDEVICE(REALTEK, 0x8169) },
164 { PCI_VENDOR_ID_DLINK, 0x4300,
165 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 },
166 { PCI_VDEVICE(DLINK, 0x4300) },
167 { PCI_VDEVICE(DLINK, 0x4302) },
168 { PCI_VDEVICE(AT, 0xc107) },
169 { PCI_VDEVICE(USR, 0x0116) },
170 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 },
171 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 },
172 { PCI_VDEVICE(REALTEK, 0x8125) },
173 { PCI_VDEVICE(REALTEK, 0x3000) },
174 {}
175 };
176
177 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
178
179 static struct {
180 u32 msg_enable;
181 } debug = { -1 };
182
183 enum rtl_registers {
184 MAC0 = 0, /* Ethernet hardware address. */
185 MAC4 = 4,
186 MAR0 = 8, /* Multicast filter. */
187 CounterAddrLow = 0x10,
188 CounterAddrHigh = 0x14,
189 TxDescStartAddrLow = 0x20,
190 TxDescStartAddrHigh = 0x24,
191 TxHDescStartAddrLow = 0x28,
192 TxHDescStartAddrHigh = 0x2c,
193 FLASH = 0x30,
194 ERSR = 0x36,
195 ChipCmd = 0x37,
196 TxPoll = 0x38,
197 IntrMask = 0x3c,
198 IntrStatus = 0x3e,
199
200 TxConfig = 0x40,
201 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
202 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
203
204 RxConfig = 0x44,
205 #define RX128_INT_EN (1 << 15) /* 8111c and later */
206 #define RX_MULTI_EN (1 << 14) /* 8111c only */
207 #define RXCFG_FIFO_SHIFT 13
208 /* No threshold before first PCI xfer */
209 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
210 #define RX_EARLY_OFF (1 << 11)
211 #define RXCFG_DMA_SHIFT 8
212 /* Unlimited maximum PCI burst. */
213 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
214
215 RxMissed = 0x4c,
216 Cfg9346 = 0x50,
217 Config0 = 0x51,
218 Config1 = 0x52,
219 Config2 = 0x53,
220 #define PME_SIGNAL (1 << 5) /* 8168c and later */
221
222 Config3 = 0x54,
223 Config4 = 0x55,
224 Config5 = 0x56,
225 PHYAR = 0x60,
226 PHYstatus = 0x6c,
227 RxMaxSize = 0xda,
228 CPlusCmd = 0xe0,
229 IntrMitigate = 0xe2,
230
231 #define RTL_COALESCE_MASK 0x0f
232 #define RTL_COALESCE_SHIFT 4
233 #define RTL_COALESCE_T_MAX (RTL_COALESCE_MASK)
234 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_MASK << 2)
235
236 RxDescAddrLow = 0xe4,
237 RxDescAddrHigh = 0xe8,
238 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
239
240 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
241
242 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
243
244 #define TxPacketMax (8064 >> 7)
245 #define EarlySize 0x27
246
247 FuncEvent = 0xf0,
248 FuncEventMask = 0xf4,
249 FuncPresetState = 0xf8,
250 IBCR0 = 0xf8,
251 IBCR2 = 0xf9,
252 IBIMR0 = 0xfa,
253 IBISR0 = 0xfb,
254 FuncForceEvent = 0xfc,
255 };
256
257 enum rtl8168_8101_registers {
258 CSIDR = 0x64,
259 CSIAR = 0x68,
260 #define CSIAR_FLAG 0x80000000
261 #define CSIAR_WRITE_CMD 0x80000000
262 #define CSIAR_BYTE_ENABLE 0x0000f000
263 #define CSIAR_ADDR_MASK 0x00000fff
264 PMCH = 0x6f,
265 EPHYAR = 0x80,
266 #define EPHYAR_FLAG 0x80000000
267 #define EPHYAR_WRITE_CMD 0x80000000
268 #define EPHYAR_REG_MASK 0x1f
269 #define EPHYAR_REG_SHIFT 16
270 #define EPHYAR_DATA_MASK 0xffff
271 DLLPR = 0xd0,
272 #define PFM_EN (1 << 6)
273 #define TX_10M_PS_EN (1 << 7)
274 DBG_REG = 0xd1,
275 #define FIX_NAK_1 (1 << 4)
276 #define FIX_NAK_2 (1 << 3)
277 TWSI = 0xd2,
278 MCU = 0xd3,
279 #define NOW_IS_OOB (1 << 7)
280 #define TX_EMPTY (1 << 5)
281 #define RX_EMPTY (1 << 4)
282 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
283 #define EN_NDP (1 << 3)
284 #define EN_OOB_RESET (1 << 2)
285 #define LINK_LIST_RDY (1 << 1)
286 EFUSEAR = 0xdc,
287 #define EFUSEAR_FLAG 0x80000000
288 #define EFUSEAR_WRITE_CMD 0x80000000
289 #define EFUSEAR_READ_CMD 0x00000000
290 #define EFUSEAR_REG_MASK 0x03ff
291 #define EFUSEAR_REG_SHIFT 8
292 #define EFUSEAR_DATA_MASK 0xff
293 MISC_1 = 0xf2,
294 #define PFM_D3COLD_EN (1 << 6)
295 };
296
297 enum rtl8168_registers {
298 LED_FREQ = 0x1a,
299 EEE_LED = 0x1b,
300 ERIDR = 0x70,
301 ERIAR = 0x74,
302 #define ERIAR_FLAG 0x80000000
303 #define ERIAR_WRITE_CMD 0x80000000
304 #define ERIAR_READ_CMD 0x00000000
305 #define ERIAR_ADDR_BYTE_ALIGN 4
306 #define ERIAR_TYPE_SHIFT 16
307 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
308 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
309 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
310 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
311 #define ERIAR_MASK_SHIFT 12
312 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
313 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
314 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
315 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
316 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
317 EPHY_RXER_NUM = 0x7c,
318 OCPDR = 0xb0, /* OCP GPHY access */
319 #define OCPDR_WRITE_CMD 0x80000000
320 #define OCPDR_READ_CMD 0x00000000
321 #define OCPDR_REG_MASK 0x7f
322 #define OCPDR_GPHY_REG_SHIFT 16
323 #define OCPDR_DATA_MASK 0xffff
324 OCPAR = 0xb4,
325 #define OCPAR_FLAG 0x80000000
326 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
327 #define OCPAR_GPHY_READ_CMD 0x0000f060
328 GPHY_OCP = 0xb8,
329 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
330 MISC = 0xf0, /* 8168e only. */
331 #define TXPLA_RST (1 << 29)
332 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
333 #define PWM_EN (1 << 22)
334 #define RXDV_GATED_EN (1 << 19)
335 #define EARLY_TALLY_EN (1 << 16)
336 };
337
338 enum rtl8125_registers {
339 IntrMask_8125 = 0x38,
340 IntrStatus_8125 = 0x3c,
341 TxPoll_8125 = 0x90,
342 MAC0_BKP = 0x19e0,
343 };
344
345 #define RX_VLAN_INNER_8125 BIT(22)
346 #define RX_VLAN_OUTER_8125 BIT(23)
347 #define RX_VLAN_8125 (RX_VLAN_INNER_8125 | RX_VLAN_OUTER_8125)
348
349 #define RX_FETCH_DFLT_8125 (8 << 27)
350
351 enum rtl_register_content {
352 /* InterruptStatusBits */
353 SYSErr = 0x8000,
354 PCSTimeout = 0x4000,
355 SWInt = 0x0100,
356 TxDescUnavail = 0x0080,
357 RxFIFOOver = 0x0040,
358 LinkChg = 0x0020,
359 RxOverflow = 0x0010,
360 TxErr = 0x0008,
361 TxOK = 0x0004,
362 RxErr = 0x0002,
363 RxOK = 0x0001,
364
365 /* RxStatusDesc */
366 RxRWT = (1 << 22),
367 RxRES = (1 << 21),
368 RxRUNT = (1 << 20),
369 RxCRC = (1 << 19),
370
371 /* ChipCmdBits */
372 StopReq = 0x80,
373 CmdReset = 0x10,
374 CmdRxEnb = 0x08,
375 CmdTxEnb = 0x04,
376 RxBufEmpty = 0x01,
377
378 /* TXPoll register p.5 */
379 HPQ = 0x80, /* Poll cmd on the high prio queue */
380 NPQ = 0x40, /* Poll cmd on the low prio queue */
381 FSWInt = 0x01, /* Forced software interrupt */
382
383 /* Cfg9346Bits */
384 Cfg9346_Lock = 0x00,
385 Cfg9346_Unlock = 0xc0,
386
387 /* rx_mode_bits */
388 AcceptErr = 0x20,
389 AcceptRunt = 0x10,
390 AcceptBroadcast = 0x08,
391 AcceptMulticast = 0x04,
392 AcceptMyPhys = 0x02,
393 AcceptAllPhys = 0x01,
394 #define RX_CONFIG_ACCEPT_MASK 0x3f
395
396 /* TxConfigBits */
397 TxInterFrameGapShift = 24,
398 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
399
400 /* Config1 register p.24 */
401 LEDS1 = (1 << 7),
402 LEDS0 = (1 << 6),
403 Speed_down = (1 << 4),
404 MEMMAP = (1 << 3),
405 IOMAP = (1 << 2),
406 VPD = (1 << 1),
407 PMEnable = (1 << 0), /* Power Management Enable */
408
409 /* Config2 register p. 25 */
410 ClkReqEn = (1 << 7), /* Clock Request Enable */
411 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
412 PCI_Clock_66MHz = 0x01,
413 PCI_Clock_33MHz = 0x00,
414
415 /* Config3 register p.25 */
416 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
417 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
418 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
419 Rdy_to_L23 = (1 << 1), /* L23 Enable */
420 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
421
422 /* Config4 register */
423 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
424
425 /* Config5 register p.27 */
426 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
427 MWF = (1 << 5), /* Accept Multicast wakeup frame */
428 UWF = (1 << 4), /* Accept Unicast wakeup frame */
429 Spi_en = (1 << 3),
430 LanWake = (1 << 1), /* LanWake enable/disable */
431 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
432 ASPM_en = (1 << 0), /* ASPM enable */
433
434 /* CPlusCmd p.31 */
435 EnableBist = (1 << 15), // 8168 8101
436 Mac_dbgo_oe = (1 << 14), // 8168 8101
437 EnAnaPLL = (1 << 14), // 8169
438 Normal_mode = (1 << 13), // unused
439 Force_half_dup = (1 << 12), // 8168 8101
440 Force_rxflow_en = (1 << 11), // 8168 8101
441 Force_txflow_en = (1 << 10), // 8168 8101
442 Cxpl_dbg_sel = (1 << 9), // 8168 8101
443 ASF = (1 << 8), // 8168 8101
444 PktCntrDisable = (1 << 7), // 8168 8101
445 Mac_dbgo_sel = 0x001c, // 8168
446 RxVlan = (1 << 6),
447 RxChkSum = (1 << 5),
448 PCIDAC = (1 << 4),
449 PCIMulRW = (1 << 3),
450 #define INTT_MASK GENMASK(1, 0)
451 #define CPCMD_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
452
453 /* rtl8169_PHYstatus */
454 TBI_Enable = 0x80,
455 TxFlowCtrl = 0x40,
456 RxFlowCtrl = 0x20,
457 _1000bpsF = 0x10,
458 _100bps = 0x08,
459 _10bps = 0x04,
460 LinkStatus = 0x02,
461 FullDup = 0x01,
462
463 /* ResetCounterCommand */
464 CounterReset = 0x1,
465
466 /* DumpCounterCommand */
467 CounterDump = 0x8,
468
469 /* magic enable v2 */
470 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */
471 };
472
473 enum rtl_desc_bit {
474 /* First doubleword. */
475 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
476 RingEnd = (1 << 30), /* End of descriptor ring */
477 FirstFrag = (1 << 29), /* First segment of a packet */
478 LastFrag = (1 << 28), /* Final segment of a packet */
479 };
480
481 /* Generic case. */
482 enum rtl_tx_desc_bit {
483 /* First doubleword. */
484 TD_LSO = (1 << 27), /* Large Send Offload */
485 #define TD_MSS_MAX 0x07ffu /* MSS value */
486
487 /* Second doubleword. */
488 TxVlanTag = (1 << 17), /* Add VLAN tag */
489 };
490
491 /* 8169, 8168b and 810x except 8102e. */
492 enum rtl_tx_desc_bit_0 {
493 /* First doubleword. */
494 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
495 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
496 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
497 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
498 };
499
500 /* 8102e, 8168c and beyond. */
501 enum rtl_tx_desc_bit_1 {
502 /* First doubleword. */
503 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */
504 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */
505 #define GTTCPHO_SHIFT 18
506 #define GTTCPHO_MAX 0x7f
507
508 /* Second doubleword. */
509 #define TCPHO_SHIFT 18
510 #define TCPHO_MAX 0x3ff
511 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
512 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */
513 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */
514 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
515 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
516 };
517
518 enum rtl_rx_desc_bit {
519 /* Rx private */
520 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
521 PID0 = (1 << 17), /* Protocol ID bit 0/2 */
522
523 #define RxProtoUDP (PID1)
524 #define RxProtoTCP (PID0)
525 #define RxProtoIP (PID1 | PID0)
526 #define RxProtoMask RxProtoIP
527
528 IPFail = (1 << 16), /* IP checksum failed */
529 UDPFail = (1 << 15), /* UDP/IP checksum failed */
530 TCPFail = (1 << 14), /* TCP/IP checksum failed */
531 RxVlanTag = (1 << 16), /* VLAN tag available */
532 };
533
534 #define RsvdMask 0x3fffc000
535
536 #define RTL_GSO_MAX_SIZE_V1 32000
537 #define RTL_GSO_MAX_SEGS_V1 24
538 #define RTL_GSO_MAX_SIZE_V2 64000
539 #define RTL_GSO_MAX_SEGS_V2 64
540
541 struct TxDesc {
542 __le32 opts1;
543 __le32 opts2;
544 __le64 addr;
545 };
546
547 struct RxDesc {
548 __le32 opts1;
549 __le32 opts2;
550 __le64 addr;
551 };
552
553 struct ring_info {
554 struct sk_buff *skb;
555 u32 len;
556 };
557
558 struct rtl8169_counters {
559 __le64 tx_packets;
560 __le64 rx_packets;
561 __le64 tx_errors;
562 __le32 rx_errors;
563 __le16 rx_missed;
564 __le16 align_errors;
565 __le32 tx_one_collision;
566 __le32 tx_multi_collision;
567 __le64 rx_unicast;
568 __le64 rx_broadcast;
569 __le32 rx_multicast;
570 __le16 tx_aborted;
571 __le16 tx_underun;
572 };
573
574 struct rtl8169_tc_offsets {
575 bool inited;
576 __le64 tx_errors;
577 __le32 tx_multi_collision;
578 __le16 tx_aborted;
579 };
580
581 enum rtl_flag {
582 RTL_FLAG_TASK_ENABLED = 0,
583 RTL_FLAG_TASK_RESET_PENDING,
584 RTL_FLAG_MAX
585 };
586
587 struct rtl8169_stats {
588 u64 packets;
589 u64 bytes;
590 struct u64_stats_sync syncp;
591 };
592
593 struct rtl8169_private {
594 void __iomem *mmio_addr; /* memory map physical address */
595 struct pci_dev *pci_dev;
596 struct net_device *dev;
597 struct phy_device *phydev;
598 struct napi_struct napi;
599 u32 msg_enable;
600 enum mac_version mac_version;
601 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
602 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
603 u32 dirty_tx;
604 struct rtl8169_stats rx_stats;
605 struct rtl8169_stats tx_stats;
606 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
607 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
608 dma_addr_t TxPhyAddr;
609 dma_addr_t RxPhyAddr;
610 struct page *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
611 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
612 u16 cp_cmd;
613 u32 irq_mask;
614 struct clk *clk;
615
616 struct {
617 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
618 struct mutex mutex;
619 struct work_struct work;
620 } wk;
621
622 unsigned irq_enabled:1;
623 unsigned supports_gmii:1;
624 unsigned aspm_manageable:1;
625 dma_addr_t counters_phys_addr;
626 struct rtl8169_counters *counters;
627 struct rtl8169_tc_offsets tc_offset;
628 u32 saved_wolopts;
629 int eee_adv;
630
631 const char *fw_name;
632 struct rtl_fw *rtl_fw;
633
634 u32 ocp_base;
635 };
636
637 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp);
638
639 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
640 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
641 module_param_named(debug, debug.msg_enable, int, 0);
642 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
643 MODULE_SOFTDEP("pre: realtek");
644 MODULE_LICENSE("GPL");
645 MODULE_FIRMWARE(FIRMWARE_8168D_1);
646 MODULE_FIRMWARE(FIRMWARE_8168D_2);
647 MODULE_FIRMWARE(FIRMWARE_8168E_1);
648 MODULE_FIRMWARE(FIRMWARE_8168E_2);
649 MODULE_FIRMWARE(FIRMWARE_8168E_3);
650 MODULE_FIRMWARE(FIRMWARE_8105E_1);
651 MODULE_FIRMWARE(FIRMWARE_8168F_1);
652 MODULE_FIRMWARE(FIRMWARE_8168F_2);
653 MODULE_FIRMWARE(FIRMWARE_8402_1);
654 MODULE_FIRMWARE(FIRMWARE_8411_1);
655 MODULE_FIRMWARE(FIRMWARE_8411_2);
656 MODULE_FIRMWARE(FIRMWARE_8106E_1);
657 MODULE_FIRMWARE(FIRMWARE_8106E_2);
658 MODULE_FIRMWARE(FIRMWARE_8168G_2);
659 MODULE_FIRMWARE(FIRMWARE_8168G_3);
660 MODULE_FIRMWARE(FIRMWARE_8168H_1);
661 MODULE_FIRMWARE(FIRMWARE_8168H_2);
662 MODULE_FIRMWARE(FIRMWARE_8168FP_3);
663 MODULE_FIRMWARE(FIRMWARE_8107E_1);
664 MODULE_FIRMWARE(FIRMWARE_8107E_2);
665 MODULE_FIRMWARE(FIRMWARE_8125A_3);
666
667 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
668 {
669 return &tp->pci_dev->dev;
670 }
671
672 static void rtl_lock_work(struct rtl8169_private *tp)
673 {
674 mutex_lock(&tp->wk.mutex);
675 }
676
677 static void rtl_unlock_work(struct rtl8169_private *tp)
678 {
679 mutex_unlock(&tp->wk.mutex);
680 }
681
682 static void rtl_lock_config_regs(struct rtl8169_private *tp)
683 {
684 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
685 }
686
687 static void rtl_unlock_config_regs(struct rtl8169_private *tp)
688 {
689 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
690 }
691
692 static bool rtl_is_8125(struct rtl8169_private *tp)
693 {
694 return tp->mac_version >= RTL_GIGA_MAC_VER_60;
695 }
696
697 static bool rtl_is_8168evl_up(struct rtl8169_private *tp)
698 {
699 return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
700 tp->mac_version != RTL_GIGA_MAC_VER_39 &&
701 tp->mac_version <= RTL_GIGA_MAC_VER_52;
702 }
703
704 static bool rtl_supports_eee(struct rtl8169_private *tp)
705 {
706 return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
707 tp->mac_version != RTL_GIGA_MAC_VER_37 &&
708 tp->mac_version != RTL_GIGA_MAC_VER_39;
709 }
710
711 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg)
712 {
713 int i;
714
715 for (i = 0; i < ETH_ALEN; i++)
716 mac[i] = RTL_R8(tp, reg + i);
717 }
718
719 struct rtl_cond {
720 bool (*check)(struct rtl8169_private *);
721 const char *msg;
722 };
723
724 static void rtl_udelay(unsigned int d)
725 {
726 udelay(d);
727 }
728
729 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
730 void (*delay)(unsigned int), unsigned int d, int n,
731 bool high)
732 {
733 int i;
734
735 for (i = 0; i < n; i++) {
736 if (c->check(tp) == high)
737 return true;
738 delay(d);
739 }
740 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
741 c->msg, !high, n, d);
742 return false;
743 }
744
745 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
746 const struct rtl_cond *c,
747 unsigned int d, int n)
748 {
749 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
750 }
751
752 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
753 const struct rtl_cond *c,
754 unsigned int d, int n)
755 {
756 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
757 }
758
759 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
760 const struct rtl_cond *c,
761 unsigned int d, int n)
762 {
763 return rtl_loop_wait(tp, c, msleep, d, n, true);
764 }
765
766 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
767 const struct rtl_cond *c,
768 unsigned int d, int n)
769 {
770 return rtl_loop_wait(tp, c, msleep, d, n, false);
771 }
772
773 #define DECLARE_RTL_COND(name) \
774 static bool name ## _check(struct rtl8169_private *); \
775 \
776 static const struct rtl_cond name = { \
777 .check = name ## _check, \
778 .msg = #name \
779 }; \
780 \
781 static bool name ## _check(struct rtl8169_private *tp)
782
783 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
784 {
785 if (reg & 0xffff0001) {
786 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
787 return true;
788 }
789 return false;
790 }
791
792 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
793 {
794 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
795 }
796
797 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
798 {
799 if (rtl_ocp_reg_failure(tp, reg))
800 return;
801
802 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
803
804 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
805 }
806
807 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
808 {
809 if (rtl_ocp_reg_failure(tp, reg))
810 return 0;
811
812 RTL_W32(tp, GPHY_OCP, reg << 15);
813
814 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
815 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT;
816 }
817
818 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
819 {
820 if (rtl_ocp_reg_failure(tp, reg))
821 return;
822
823 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
824 }
825
826 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
827 {
828 if (rtl_ocp_reg_failure(tp, reg))
829 return 0;
830
831 RTL_W32(tp, OCPDR, reg << 15);
832
833 return RTL_R32(tp, OCPDR);
834 }
835
836 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask,
837 u16 set)
838 {
839 u16 data = r8168_mac_ocp_read(tp, reg);
840
841 r8168_mac_ocp_write(tp, reg, (data & ~mask) | set);
842 }
843
844 #define OCP_STD_PHY_BASE 0xa400
845
846 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
847 {
848 if (reg == 0x1f) {
849 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
850 return;
851 }
852
853 if (tp->ocp_base != OCP_STD_PHY_BASE)
854 reg -= 0x10;
855
856 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
857 }
858
859 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
860 {
861 if (reg == 0x1f)
862 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4;
863
864 if (tp->ocp_base != OCP_STD_PHY_BASE)
865 reg -= 0x10;
866
867 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
868 }
869
870 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
871 {
872 if (reg == 0x1f) {
873 tp->ocp_base = value << 4;
874 return;
875 }
876
877 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
878 }
879
880 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
881 {
882 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
883 }
884
885 DECLARE_RTL_COND(rtl_phyar_cond)
886 {
887 return RTL_R32(tp, PHYAR) & 0x80000000;
888 }
889
890 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
891 {
892 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
893
894 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
895 /*
896 * According to hardware specs a 20us delay is required after write
897 * complete indication, but before sending next command.
898 */
899 udelay(20);
900 }
901
902 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
903 {
904 int value;
905
906 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
907
908 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
909 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT;
910
911 /*
912 * According to hardware specs a 20us delay is required after read
913 * complete indication, but before sending next command.
914 */
915 udelay(20);
916
917 return value;
918 }
919
920 DECLARE_RTL_COND(rtl_ocpar_cond)
921 {
922 return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
923 }
924
925 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
926 {
927 RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
928 RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
929 RTL_W32(tp, EPHY_RXER_NUM, 0);
930
931 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
932 }
933
934 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
935 {
936 r8168dp_1_mdio_access(tp, reg,
937 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
938 }
939
940 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
941 {
942 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
943
944 mdelay(1);
945 RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
946 RTL_W32(tp, EPHY_RXER_NUM, 0);
947
948 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
949 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : -ETIMEDOUT;
950 }
951
952 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
953
954 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
955 {
956 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
957 }
958
959 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
960 {
961 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
962 }
963
964 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
965 {
966 r8168dp_2_mdio_start(tp);
967
968 r8169_mdio_write(tp, reg, value);
969
970 r8168dp_2_mdio_stop(tp);
971 }
972
973 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
974 {
975 int value;
976
977 /* Work around issue with chip reporting wrong PHY ID */
978 if (reg == MII_PHYSID2)
979 return 0xc912;
980
981 r8168dp_2_mdio_start(tp);
982
983 value = r8169_mdio_read(tp, reg);
984
985 r8168dp_2_mdio_stop(tp);
986
987 return value;
988 }
989
990 static void rtl_writephy(struct rtl8169_private *tp, int location, int val)
991 {
992 switch (tp->mac_version) {
993 case RTL_GIGA_MAC_VER_27:
994 r8168dp_1_mdio_write(tp, location, val);
995 break;
996 case RTL_GIGA_MAC_VER_28:
997 case RTL_GIGA_MAC_VER_31:
998 r8168dp_2_mdio_write(tp, location, val);
999 break;
1000 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_61:
1001 r8168g_mdio_write(tp, location, val);
1002 break;
1003 default:
1004 r8169_mdio_write(tp, location, val);
1005 break;
1006 }
1007 }
1008
1009 static int rtl_readphy(struct rtl8169_private *tp, int location)
1010 {
1011 switch (tp->mac_version) {
1012 case RTL_GIGA_MAC_VER_27:
1013 return r8168dp_1_mdio_read(tp, location);
1014 case RTL_GIGA_MAC_VER_28:
1015 case RTL_GIGA_MAC_VER_31:
1016 return r8168dp_2_mdio_read(tp, location);
1017 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_61:
1018 return r8168g_mdio_read(tp, location);
1019 default:
1020 return r8169_mdio_read(tp, location);
1021 }
1022 }
1023
1024 DECLARE_RTL_COND(rtl_ephyar_cond)
1025 {
1026 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1027 }
1028
1029 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1030 {
1031 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1032 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1033
1034 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1035
1036 udelay(10);
1037 }
1038
1039 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1040 {
1041 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1042
1043 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1044 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1045 }
1046
1047 DECLARE_RTL_COND(rtl_eriar_cond)
1048 {
1049 return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
1050 }
1051
1052 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1053 u32 val, int type)
1054 {
1055 BUG_ON((addr & 3) || (mask == 0));
1056 RTL_W32(tp, ERIDR, val);
1057 RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1058
1059 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1060 }
1061
1062 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1063 u32 val)
1064 {
1065 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC);
1066 }
1067
1068 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1069 {
1070 RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1071
1072 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1073 RTL_R32(tp, ERIDR) : ~0;
1074 }
1075
1076 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr)
1077 {
1078 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC);
1079 }
1080
1081 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1082 u32 m)
1083 {
1084 u32 val;
1085
1086 val = rtl_eri_read(tp, addr);
1087 rtl_eri_write(tp, addr, mask, (val & ~m) | p);
1088 }
1089
1090 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 mask,
1091 u32 p)
1092 {
1093 rtl_w0w1_eri(tp, addr, mask, p, 0);
1094 }
1095
1096 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 mask,
1097 u32 m)
1098 {
1099 rtl_w0w1_eri(tp, addr, mask, 0, m);
1100 }
1101
1102 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1103 {
1104 RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1105 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1106 RTL_R32(tp, OCPDR) : ~0;
1107 }
1108
1109 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1110 {
1111 return _rtl_eri_read(tp, reg, ERIAR_OOB);
1112 }
1113
1114 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1115 u32 data)
1116 {
1117 RTL_W32(tp, OCPDR, data);
1118 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1119 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1120 }
1121
1122 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1123 u32 data)
1124 {
1125 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1126 data, ERIAR_OOB);
1127 }
1128
1129 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)
1130 {
1131 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd);
1132
1133 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);
1134 }
1135
1136 #define OOB_CMD_RESET 0x00
1137 #define OOB_CMD_DRIVER_START 0x05
1138 #define OOB_CMD_DRIVER_STOP 0x06
1139
1140 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1141 {
1142 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1143 }
1144
1145 DECLARE_RTL_COND(rtl_dp_ocp_read_cond)
1146 {
1147 u16 reg;
1148
1149 reg = rtl8168_get_ocp_reg(tp);
1150
1151 return r8168dp_ocp_read(tp, 0x0f, reg) & 0x00000800;
1152 }
1153
1154 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1155 {
1156 return r8168ep_ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1157 }
1158
1159 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1160 {
1161 return RTL_R8(tp, IBISR0) & 0x20;
1162 }
1163
1164 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1165 {
1166 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1167 rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
1168 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1169 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1170 }
1171
1172 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1173 {
1174 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);
1175 rtl_msleep_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10, 10);
1176 }
1177
1178 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1179 {
1180 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1181 r8168ep_ocp_write(tp, 0x01, 0x30,
1182 r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
1183 rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1184 }
1185
1186 static void rtl8168_driver_start(struct rtl8169_private *tp)
1187 {
1188 switch (tp->mac_version) {
1189 case RTL_GIGA_MAC_VER_27:
1190 case RTL_GIGA_MAC_VER_28:
1191 case RTL_GIGA_MAC_VER_31:
1192 rtl8168dp_driver_start(tp);
1193 break;
1194 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52:
1195 rtl8168ep_driver_start(tp);
1196 break;
1197 default:
1198 BUG();
1199 break;
1200 }
1201 }
1202
1203 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1204 {
1205 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1206 rtl_msleep_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10, 10);
1207 }
1208
1209 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1210 {
1211 rtl8168ep_stop_cmac(tp);
1212 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1213 r8168ep_ocp_write(tp, 0x01, 0x30,
1214 r8168ep_ocp_read(tp, 0x01, 0x30) | 0x01);
1215 rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1216 }
1217
1218 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1219 {
1220 switch (tp->mac_version) {
1221 case RTL_GIGA_MAC_VER_27:
1222 case RTL_GIGA_MAC_VER_28:
1223 case RTL_GIGA_MAC_VER_31:
1224 rtl8168dp_driver_stop(tp);
1225 break;
1226 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52:
1227 rtl8168ep_driver_stop(tp);
1228 break;
1229 default:
1230 BUG();
1231 break;
1232 }
1233 }
1234
1235 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1236 {
1237 u16 reg = rtl8168_get_ocp_reg(tp);
1238
1239 return !!(r8168dp_ocp_read(tp, 0x0f, reg) & 0x00008000);
1240 }
1241
1242 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1243 {
1244 return !!(r8168ep_ocp_read(tp, 0x0f, 0x128) & 0x00000001);
1245 }
1246
1247 static bool r8168_check_dash(struct rtl8169_private *tp)
1248 {
1249 switch (tp->mac_version) {
1250 case RTL_GIGA_MAC_VER_27:
1251 case RTL_GIGA_MAC_VER_28:
1252 case RTL_GIGA_MAC_VER_31:
1253 return r8168dp_check_dash(tp);
1254 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52:
1255 return r8168ep_check_dash(tp);
1256 default:
1257 return false;
1258 }
1259 }
1260
1261 static void rtl_reset_packet_filter(struct rtl8169_private *tp)
1262 {
1263 rtl_eri_clear_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0));
1264 rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0));
1265 }
1266
1267 DECLARE_RTL_COND(rtl_efusear_cond)
1268 {
1269 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1270 }
1271
1272 u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1273 {
1274 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1275
1276 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1277 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1278 }
1279
1280 static u32 rtl_get_events(struct rtl8169_private *tp)
1281 {
1282 if (rtl_is_8125(tp))
1283 return RTL_R32(tp, IntrStatus_8125);
1284 else
1285 return RTL_R16(tp, IntrStatus);
1286 }
1287
1288 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits)
1289 {
1290 if (rtl_is_8125(tp))
1291 RTL_W32(tp, IntrStatus_8125, bits);
1292 else
1293 RTL_W16(tp, IntrStatus, bits);
1294 }
1295
1296 static void rtl_irq_disable(struct rtl8169_private *tp)
1297 {
1298 if (rtl_is_8125(tp))
1299 RTL_W32(tp, IntrMask_8125, 0);
1300 else
1301 RTL_W16(tp, IntrMask, 0);
1302 tp->irq_enabled = 0;
1303 }
1304
1305 #define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1306 #define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1307 #define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1308
1309 static void rtl_irq_enable(struct rtl8169_private *tp)
1310 {
1311 tp->irq_enabled = 1;
1312 if (rtl_is_8125(tp))
1313 RTL_W32(tp, IntrMask_8125, tp->irq_mask);
1314 else
1315 RTL_W16(tp, IntrMask, tp->irq_mask);
1316 }
1317
1318 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1319 {
1320 rtl_irq_disable(tp);
1321 rtl_ack_events(tp, 0xffffffff);
1322 /* PCI commit */
1323 RTL_R8(tp, ChipCmd);
1324 }
1325
1326 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1327 {
1328 struct net_device *dev = tp->dev;
1329 struct phy_device *phydev = tp->phydev;
1330
1331 if (!netif_running(dev))
1332 return;
1333
1334 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1335 tp->mac_version == RTL_GIGA_MAC_VER_38) {
1336 if (phydev->speed == SPEED_1000) {
1337 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1338 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1339 } else if (phydev->speed == SPEED_100) {
1340 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1341 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1342 } else {
1343 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1344 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1345 }
1346 rtl_reset_packet_filter(tp);
1347 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1348 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1349 if (phydev->speed == SPEED_1000) {
1350 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1351 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1352 } else {
1353 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1354 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1355 }
1356 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1357 if (phydev->speed == SPEED_10) {
1358 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02);
1359 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a);
1360 } else {
1361 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
1362 }
1363 }
1364 }
1365
1366 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1367
1368 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1369 {
1370 struct rtl8169_private *tp = netdev_priv(dev);
1371
1372 rtl_lock_work(tp);
1373 wol->supported = WAKE_ANY;
1374 wol->wolopts = tp->saved_wolopts;
1375 rtl_unlock_work(tp);
1376 }
1377
1378 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1379 {
1380 static const struct {
1381 u32 opt;
1382 u16 reg;
1383 u8 mask;
1384 } cfg[] = {
1385 { WAKE_PHY, Config3, LinkUp },
1386 { WAKE_UCAST, Config5, UWF },
1387 { WAKE_BCAST, Config5, BWF },
1388 { WAKE_MCAST, Config5, MWF },
1389 { WAKE_ANY, Config5, LanWake },
1390 { WAKE_MAGIC, Config3, MagicPacket }
1391 };
1392 unsigned int i, tmp = ARRAY_SIZE(cfg);
1393 u8 options;
1394
1395 rtl_unlock_config_regs(tp);
1396
1397 if (rtl_is_8168evl_up(tp)) {
1398 tmp--;
1399 if (wolopts & WAKE_MAGIC)
1400 rtl_eri_set_bits(tp, 0x0dc, ERIAR_MASK_0100,
1401 MagicPacket_v2);
1402 else
1403 rtl_eri_clear_bits(tp, 0x0dc, ERIAR_MASK_0100,
1404 MagicPacket_v2);
1405 } else if (rtl_is_8125(tp)) {
1406 tmp--;
1407 if (wolopts & WAKE_MAGIC)
1408 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0));
1409 else
1410 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0);
1411 }
1412
1413 for (i = 0; i < tmp; i++) {
1414 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1415 if (wolopts & cfg[i].opt)
1416 options |= cfg[i].mask;
1417 RTL_W8(tp, cfg[i].reg, options);
1418 }
1419
1420 switch (tp->mac_version) {
1421 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
1422 options = RTL_R8(tp, Config1) & ~PMEnable;
1423 if (wolopts)
1424 options |= PMEnable;
1425 RTL_W8(tp, Config1, options);
1426 break;
1427 case RTL_GIGA_MAC_VER_34:
1428 case RTL_GIGA_MAC_VER_37:
1429 case RTL_GIGA_MAC_VER_39 ... RTL_GIGA_MAC_VER_52:
1430 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
1431 if (wolopts)
1432 options |= PME_SIGNAL;
1433 RTL_W8(tp, Config2, options);
1434 break;
1435 default:
1436 break;
1437 }
1438
1439 rtl_lock_config_regs(tp);
1440
1441 device_set_wakeup_enable(tp_to_dev(tp), wolopts);
1442 tp->dev->wol_enabled = wolopts ? 1 : 0;
1443 }
1444
1445 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1446 {
1447 struct rtl8169_private *tp = netdev_priv(dev);
1448 struct device *d = tp_to_dev(tp);
1449
1450 if (wol->wolopts & ~WAKE_ANY)
1451 return -EINVAL;
1452
1453 pm_runtime_get_noresume(d);
1454
1455 rtl_lock_work(tp);
1456
1457 tp->saved_wolopts = wol->wolopts;
1458
1459 if (pm_runtime_active(d))
1460 __rtl8169_set_wol(tp, tp->saved_wolopts);
1461
1462 rtl_unlock_work(tp);
1463
1464 pm_runtime_put_noidle(d);
1465
1466 return 0;
1467 }
1468
1469 static void rtl8169_get_drvinfo(struct net_device *dev,
1470 struct ethtool_drvinfo *info)
1471 {
1472 struct rtl8169_private *tp = netdev_priv(dev);
1473 struct rtl_fw *rtl_fw = tp->rtl_fw;
1474
1475 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1476 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1477 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1478 if (rtl_fw)
1479 strlcpy(info->fw_version, rtl_fw->version,
1480 sizeof(info->fw_version));
1481 }
1482
1483 static int rtl8169_get_regs_len(struct net_device *dev)
1484 {
1485 return R8169_REGS_SIZE;
1486 }
1487
1488 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1489 netdev_features_t features)
1490 {
1491 struct rtl8169_private *tp = netdev_priv(dev);
1492
1493 if (dev->mtu > TD_MSS_MAX)
1494 features &= ~NETIF_F_ALL_TSO;
1495
1496 if (dev->mtu > ETH_DATA_LEN &&
1497 tp->mac_version > RTL_GIGA_MAC_VER_06)
1498 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_ALL_TSO);
1499
1500 return features;
1501 }
1502
1503 static int rtl8169_set_features(struct net_device *dev,
1504 netdev_features_t features)
1505 {
1506 struct rtl8169_private *tp = netdev_priv(dev);
1507 u32 rx_config;
1508
1509 rtl_lock_work(tp);
1510
1511 rx_config = RTL_R32(tp, RxConfig);
1512 if (features & NETIF_F_RXALL)
1513 rx_config |= (AcceptErr | AcceptRunt);
1514 else
1515 rx_config &= ~(AcceptErr | AcceptRunt);
1516
1517 if (rtl_is_8125(tp)) {
1518 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1519 rx_config |= RX_VLAN_8125;
1520 else
1521 rx_config &= ~RX_VLAN_8125;
1522 }
1523
1524 RTL_W32(tp, RxConfig, rx_config);
1525
1526 if (features & NETIF_F_RXCSUM)
1527 tp->cp_cmd |= RxChkSum;
1528 else
1529 tp->cp_cmd &= ~RxChkSum;
1530
1531 if (!rtl_is_8125(tp)) {
1532 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1533 tp->cp_cmd |= RxVlan;
1534 else
1535 tp->cp_cmd &= ~RxVlan;
1536 }
1537
1538 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1539 RTL_R16(tp, CPlusCmd);
1540
1541 rtl_unlock_work(tp);
1542
1543 return 0;
1544 }
1545
1546 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1547 {
1548 return (skb_vlan_tag_present(skb)) ?
1549 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1550 }
1551
1552 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1553 {
1554 u32 opts2 = le32_to_cpu(desc->opts2);
1555
1556 if (opts2 & RxVlanTag)
1557 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1558 }
1559
1560 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1561 void *p)
1562 {
1563 struct rtl8169_private *tp = netdev_priv(dev);
1564 u32 __iomem *data = tp->mmio_addr;
1565 u32 *dw = p;
1566 int i;
1567
1568 rtl_lock_work(tp);
1569 for (i = 0; i < R8169_REGS_SIZE; i += 4)
1570 memcpy_fromio(dw++, data++, 4);
1571 rtl_unlock_work(tp);
1572 }
1573
1574 static u32 rtl8169_get_msglevel(struct net_device *dev)
1575 {
1576 struct rtl8169_private *tp = netdev_priv(dev);
1577
1578 return tp->msg_enable;
1579 }
1580
1581 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1582 {
1583 struct rtl8169_private *tp = netdev_priv(dev);
1584
1585 tp->msg_enable = value;
1586 }
1587
1588 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1589 "tx_packets",
1590 "rx_packets",
1591 "tx_errors",
1592 "rx_errors",
1593 "rx_missed",
1594 "align_errors",
1595 "tx_single_collisions",
1596 "tx_multi_collisions",
1597 "unicast",
1598 "broadcast",
1599 "multicast",
1600 "tx_aborted",
1601 "tx_underrun",
1602 };
1603
1604 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1605 {
1606 switch (sset) {
1607 case ETH_SS_STATS:
1608 return ARRAY_SIZE(rtl8169_gstrings);
1609 default:
1610 return -EOPNOTSUPP;
1611 }
1612 }
1613
1614 DECLARE_RTL_COND(rtl_counters_cond)
1615 {
1616 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1617 }
1618
1619 static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1620 {
1621 dma_addr_t paddr = tp->counters_phys_addr;
1622 u32 cmd;
1623
1624 RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
1625 RTL_R32(tp, CounterAddrHigh);
1626 cmd = (u64)paddr & DMA_BIT_MASK(32);
1627 RTL_W32(tp, CounterAddrLow, cmd);
1628 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1629
1630 return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1631 }
1632
1633 static bool rtl8169_reset_counters(struct rtl8169_private *tp)
1634 {
1635 /*
1636 * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
1637 * tally counters.
1638 */
1639 if (tp->mac_version < RTL_GIGA_MAC_VER_19)
1640 return true;
1641
1642 return rtl8169_do_counters(tp, CounterReset);
1643 }
1644
1645 static bool rtl8169_update_counters(struct rtl8169_private *tp)
1646 {
1647 u8 val = RTL_R8(tp, ChipCmd);
1648
1649 /*
1650 * Some chips are unable to dump tally counters when the receiver
1651 * is disabled. If 0xff chip may be in a PCI power-save state.
1652 */
1653 if (!(val & CmdRxEnb) || val == 0xff)
1654 return true;
1655
1656 return rtl8169_do_counters(tp, CounterDump);
1657 }
1658
1659 static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1660 {
1661 struct rtl8169_counters *counters = tp->counters;
1662 bool ret = false;
1663
1664 /*
1665 * rtl8169_init_counter_offsets is called from rtl_open. On chip
1666 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1667 * reset by a power cycle, while the counter values collected by the
1668 * driver are reset at every driver unload/load cycle.
1669 *
1670 * To make sure the HW values returned by @get_stats64 match the SW
1671 * values, we collect the initial values at first open(*) and use them
1672 * as offsets to normalize the values returned by @get_stats64.
1673 *
1674 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1675 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1676 * set at open time by rtl_hw_start.
1677 */
1678
1679 if (tp->tc_offset.inited)
1680 return true;
1681
1682 /* If both, reset and update fail, propagate to caller. */
1683 if (rtl8169_reset_counters(tp))
1684 ret = true;
1685
1686 if (rtl8169_update_counters(tp))
1687 ret = true;
1688
1689 tp->tc_offset.tx_errors = counters->tx_errors;
1690 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1691 tp->tc_offset.tx_aborted = counters->tx_aborted;
1692 tp->tc_offset.inited = true;
1693
1694 return ret;
1695 }
1696
1697 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1698 struct ethtool_stats *stats, u64 *data)
1699 {
1700 struct rtl8169_private *tp = netdev_priv(dev);
1701 struct device *d = tp_to_dev(tp);
1702 struct rtl8169_counters *counters = tp->counters;
1703
1704 ASSERT_RTNL();
1705
1706 pm_runtime_get_noresume(d);
1707
1708 if (pm_runtime_active(d))
1709 rtl8169_update_counters(tp);
1710
1711 pm_runtime_put_noidle(d);
1712
1713 data[0] = le64_to_cpu(counters->tx_packets);
1714 data[1] = le64_to_cpu(counters->rx_packets);
1715 data[2] = le64_to_cpu(counters->tx_errors);
1716 data[3] = le32_to_cpu(counters->rx_errors);
1717 data[4] = le16_to_cpu(counters->rx_missed);
1718 data[5] = le16_to_cpu(counters->align_errors);
1719 data[6] = le32_to_cpu(counters->tx_one_collision);
1720 data[7] = le32_to_cpu(counters->tx_multi_collision);
1721 data[8] = le64_to_cpu(counters->rx_unicast);
1722 data[9] = le64_to_cpu(counters->rx_broadcast);
1723 data[10] = le32_to_cpu(counters->rx_multicast);
1724 data[11] = le16_to_cpu(counters->tx_aborted);
1725 data[12] = le16_to_cpu(counters->tx_underun);
1726 }
1727
1728 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1729 {
1730 switch(stringset) {
1731 case ETH_SS_STATS:
1732 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1733 break;
1734 }
1735 }
1736
1737 /*
1738 * Interrupt coalescing
1739 *
1740 * > 1 - the availability of the IntrMitigate (0xe2) register through the
1741 * > 8169, 8168 and 810x line of chipsets
1742 *
1743 * 8169, 8168, and 8136(810x) serial chipsets support it.
1744 *
1745 * > 2 - the Tx timer unit at gigabit speed
1746 *
1747 * The unit of the timer depends on both the speed and the setting of CPlusCmd
1748 * (0xe0) bit 1 and bit 0.
1749 *
1750 * For 8169
1751 * bit[1:0] \ speed 1000M 100M 10M
1752 * 0 0 320ns 2.56us 40.96us
1753 * 0 1 2.56us 20.48us 327.7us
1754 * 1 0 5.12us 40.96us 655.4us
1755 * 1 1 10.24us 81.92us 1.31ms
1756 *
1757 * For the other
1758 * bit[1:0] \ speed 1000M 100M 10M
1759 * 0 0 5us 2.56us 40.96us
1760 * 0 1 40us 20.48us 327.7us
1761 * 1 0 80us 40.96us 655.4us
1762 * 1 1 160us 81.92us 1.31ms
1763 */
1764
1765 /* rx/tx scale factors for one particular CPlusCmd[0:1] value */
1766 struct rtl_coalesce_scale {
1767 /* Rx / Tx */
1768 u32 nsecs[2];
1769 };
1770
1771 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1772 struct rtl_coalesce_info {
1773 u32 speed;
1774 struct rtl_coalesce_scale scalev[4]; /* each CPlusCmd[0:1] case */
1775 };
1776
1777 /* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
1778 #define rxtx_x1822(r, t) { \
1779 {{(r), (t)}}, \
1780 {{(r)*8, (t)*8}}, \
1781 {{(r)*8*2, (t)*8*2}}, \
1782 {{(r)*8*2*2, (t)*8*2*2}}, \
1783 }
1784 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1785 /* speed delays: rx00 tx00 */
1786 { SPEED_10, rxtx_x1822(40960, 40960) },
1787 { SPEED_100, rxtx_x1822( 2560, 2560) },
1788 { SPEED_1000, rxtx_x1822( 320, 320) },
1789 { 0 },
1790 };
1791
1792 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1793 /* speed delays: rx00 tx00 */
1794 { SPEED_10, rxtx_x1822(40960, 40960) },
1795 { SPEED_100, rxtx_x1822( 2560, 2560) },
1796 { SPEED_1000, rxtx_x1822( 5000, 5000) },
1797 { 0 },
1798 };
1799 #undef rxtx_x1822
1800
1801 /* get rx/tx scale vector corresponding to current speed */
1802 static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev)
1803 {
1804 struct rtl8169_private *tp = netdev_priv(dev);
1805 const struct rtl_coalesce_info *ci;
1806
1807 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1808 ci = rtl_coalesce_info_8169;
1809 else
1810 ci = rtl_coalesce_info_8168_8136;
1811
1812 for (; ci->speed; ci++) {
1813 if (tp->phydev->speed == ci->speed)
1814 return ci;
1815 }
1816
1817 return ERR_PTR(-ELNRNG);
1818 }
1819
1820 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1821 {
1822 struct rtl8169_private *tp = netdev_priv(dev);
1823 const struct rtl_coalesce_info *ci;
1824 const struct rtl_coalesce_scale *scale;
1825 struct {
1826 u32 *max_frames;
1827 u32 *usecs;
1828 } coal_settings [] = {
1829 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs },
1830 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs }
1831 }, *p = coal_settings;
1832 int i;
1833 u16 w;
1834
1835 if (rtl_is_8125(tp))
1836 return -EOPNOTSUPP;
1837
1838 memset(ec, 0, sizeof(*ec));
1839
1840 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1841 ci = rtl_coalesce_info(dev);
1842 if (IS_ERR(ci))
1843 return PTR_ERR(ci);
1844
1845 scale = &ci->scalev[tp->cp_cmd & INTT_MASK];
1846
1847 /* read IntrMitigate and adjust according to scale */
1848 for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) {
1849 *p->max_frames = (w & RTL_COALESCE_MASK) << 2;
1850 w >>= RTL_COALESCE_SHIFT;
1851 *p->usecs = w & RTL_COALESCE_MASK;
1852 }
1853
1854 for (i = 0; i < 2; i++) {
1855 p = coal_settings + i;
1856 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000;
1857
1858 /*
1859 * ethtool_coalesce says it is illegal to set both usecs and
1860 * max_frames to 0.
1861 */
1862 if (!*p->usecs && !*p->max_frames)
1863 *p->max_frames = 1;
1864 }
1865
1866 return 0;
1867 }
1868
1869 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
1870 static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale(
1871 struct net_device *dev, u32 nsec, u16 *cp01)
1872 {
1873 const struct rtl_coalesce_info *ci;
1874 u16 i;
1875
1876 ci = rtl_coalesce_info(dev);
1877 if (IS_ERR(ci))
1878 return ERR_CAST(ci);
1879
1880 for (i = 0; i < 4; i++) {
1881 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0],
1882 ci->scalev[i].nsecs[1]);
1883 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) {
1884 *cp01 = i;
1885 return &ci->scalev[i];
1886 }
1887 }
1888
1889 return ERR_PTR(-EINVAL);
1890 }
1891
1892 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1893 {
1894 struct rtl8169_private *tp = netdev_priv(dev);
1895 const struct rtl_coalesce_scale *scale;
1896 struct {
1897 u32 frames;
1898 u32 usecs;
1899 } coal_settings [] = {
1900 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs },
1901 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs }
1902 }, *p = coal_settings;
1903 u16 w = 0, cp01;
1904 int i;
1905
1906 if (rtl_is_8125(tp))
1907 return -EOPNOTSUPP;
1908
1909 scale = rtl_coalesce_choose_scale(dev,
1910 max(p[0].usecs, p[1].usecs) * 1000, &cp01);
1911 if (IS_ERR(scale))
1912 return PTR_ERR(scale);
1913
1914 for (i = 0; i < 2; i++, p++) {
1915 u32 units;
1916
1917 /*
1918 * accept max_frames=1 we returned in rtl_get_coalesce.
1919 * accept it not only when usecs=0 because of e.g. the following scenario:
1920 *
1921 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
1922 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
1923 * - then user does `ethtool -C eth0 rx-usecs 100`
1924 *
1925 * since ethtool sends to kernel whole ethtool_coalesce
1926 * settings, if we do not handle rx_usecs=!0, rx_frames=1
1927 * we'll reject it below in `frames % 4 != 0`.
1928 */
1929 if (p->frames == 1) {
1930 p->frames = 0;
1931 }
1932
1933 units = p->usecs * 1000 / scale->nsecs[i];
1934 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4)
1935 return -EINVAL;
1936
1937 w <<= RTL_COALESCE_SHIFT;
1938 w |= units;
1939 w <<= RTL_COALESCE_SHIFT;
1940 w |= p->frames >> 2;
1941 }
1942
1943 rtl_lock_work(tp);
1944
1945 RTL_W16(tp, IntrMitigate, swab16(w));
1946
1947 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
1948 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1949 RTL_R16(tp, CPlusCmd);
1950
1951 rtl_unlock_work(tp);
1952
1953 return 0;
1954 }
1955
1956 static int rtl8169_get_eee(struct net_device *dev, struct ethtool_eee *data)
1957 {
1958 struct rtl8169_private *tp = netdev_priv(dev);
1959 struct device *d = tp_to_dev(tp);
1960 int ret;
1961
1962 if (!rtl_supports_eee(tp))
1963 return -EOPNOTSUPP;
1964
1965 pm_runtime_get_noresume(d);
1966
1967 if (!pm_runtime_active(d)) {
1968 ret = -EOPNOTSUPP;
1969 } else {
1970 ret = phy_ethtool_get_eee(tp->phydev, data);
1971 }
1972
1973 pm_runtime_put_noidle(d);
1974
1975 return ret;
1976 }
1977
1978 static int rtl8169_set_eee(struct net_device *dev, struct ethtool_eee *data)
1979 {
1980 struct rtl8169_private *tp = netdev_priv(dev);
1981 struct device *d = tp_to_dev(tp);
1982 int ret;
1983
1984 if (!rtl_supports_eee(tp))
1985 return -EOPNOTSUPP;
1986
1987 pm_runtime_get_noresume(d);
1988
1989 if (!pm_runtime_active(d)) {
1990 ret = -EOPNOTSUPP;
1991 goto out;
1992 }
1993
1994 if (dev->phydev->autoneg == AUTONEG_DISABLE ||
1995 dev->phydev->duplex != DUPLEX_FULL) {
1996 ret = -EPROTONOSUPPORT;
1997 goto out;
1998 }
1999
2000 ret = phy_ethtool_set_eee(tp->phydev, data);
2001
2002 if (!ret)
2003 tp->eee_adv = phy_read_mmd(dev->phydev, MDIO_MMD_AN,
2004 MDIO_AN_EEE_ADV);
2005 out:
2006 pm_runtime_put_noidle(d);
2007 return ret;
2008 }
2009
2010 static const struct ethtool_ops rtl8169_ethtool_ops = {
2011 .get_drvinfo = rtl8169_get_drvinfo,
2012 .get_regs_len = rtl8169_get_regs_len,
2013 .get_link = ethtool_op_get_link,
2014 .get_coalesce = rtl_get_coalesce,
2015 .set_coalesce = rtl_set_coalesce,
2016 .get_msglevel = rtl8169_get_msglevel,
2017 .set_msglevel = rtl8169_set_msglevel,
2018 .get_regs = rtl8169_get_regs,
2019 .get_wol = rtl8169_get_wol,
2020 .set_wol = rtl8169_set_wol,
2021 .get_strings = rtl8169_get_strings,
2022 .get_sset_count = rtl8169_get_sset_count,
2023 .get_ethtool_stats = rtl8169_get_ethtool_stats,
2024 .get_ts_info = ethtool_op_get_ts_info,
2025 .nway_reset = phy_ethtool_nway_reset,
2026 .get_eee = rtl8169_get_eee,
2027 .set_eee = rtl8169_set_eee,
2028 .get_link_ksettings = phy_ethtool_get_link_ksettings,
2029 .set_link_ksettings = phy_ethtool_set_link_ksettings,
2030 };
2031
2032 static void rtl_enable_eee(struct rtl8169_private *tp)
2033 {
2034 struct phy_device *phydev = tp->phydev;
2035 int adv;
2036
2037 /* respect EEE advertisement the user may have set */
2038 if (tp->eee_adv >= 0)
2039 adv = tp->eee_adv;
2040 else
2041 adv = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
2042
2043 if (adv >= 0)
2044 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, adv);
2045 }
2046
2047 static void rtl8169_get_mac_version(struct rtl8169_private *tp)
2048 {
2049 /*
2050 * The driver currently handles the 8168Bf and the 8168Be identically
2051 * but they can be identified more specifically through the test below
2052 * if needed:
2053 *
2054 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2055 *
2056 * Same thing for the 8101Eb and the 8101Ec:
2057 *
2058 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2059 */
2060 static const struct rtl_mac_info {
2061 u16 mask;
2062 u16 val;
2063 u16 mac_version;
2064 } mac_info[] = {
2065 /* 8125 family. */
2066 { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 },
2067 { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 },
2068
2069 /* RTL8117 */
2070 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 },
2071
2072 /* 8168EP family. */
2073 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 },
2074 { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 },
2075 { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 },
2076
2077 /* 8168H family. */
2078 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 },
2079 { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 },
2080
2081 /* 8168G family. */
2082 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 },
2083 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 },
2084 { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 },
2085 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 },
2086
2087 /* 8168F family. */
2088 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 },
2089 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 },
2090 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 },
2091
2092 /* 8168E family. */
2093 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 },
2094 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 },
2095 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 },
2096
2097 /* 8168D family. */
2098 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 },
2099 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 },
2100
2101 /* 8168DP family. */
2102 { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 },
2103 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 },
2104 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 },
2105
2106 /* 8168C family. */
2107 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 },
2108 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 },
2109 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 },
2110 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 },
2111 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 },
2112 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 },
2113 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 },
2114
2115 /* 8168B family. */
2116 { 0x7cf, 0x380, RTL_GIGA_MAC_VER_12 },
2117 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 },
2118 { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 },
2119
2120 /* 8101 family. */
2121 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 },
2122 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 },
2123 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 },
2124 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 },
2125 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 },
2126 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 },
2127 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 },
2128 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 },
2129 { 0x7cf, 0x340, RTL_GIGA_MAC_VER_13 },
2130 { 0x7cf, 0x343, RTL_GIGA_MAC_VER_10 },
2131 { 0x7cf, 0x342, RTL_GIGA_MAC_VER_16 },
2132 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 },
2133 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 },
2134 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_16 },
2135 /* FIXME: where did these entries come from ? -- FR */
2136 { 0xfc8, 0x388, RTL_GIGA_MAC_VER_15 },
2137 { 0xfc8, 0x308, RTL_GIGA_MAC_VER_14 },
2138
2139 /* 8110 family. */
2140 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 },
2141 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 },
2142 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 },
2143 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 },
2144 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 },
2145
2146 /* Catch-all */
2147 { 0x000, 0x000, RTL_GIGA_MAC_NONE }
2148 };
2149 const struct rtl_mac_info *p = mac_info;
2150 u16 reg = RTL_R32(tp, TxConfig) >> 20;
2151
2152 while ((reg & p->mask) != p->val)
2153 p++;
2154 tp->mac_version = p->mac_version;
2155
2156 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2157 dev_err(tp_to_dev(tp), "unknown chip XID %03x\n", reg & 0xfcf);
2158 } else if (!tp->supports_gmii) {
2159 if (tp->mac_version == RTL_GIGA_MAC_VER_42)
2160 tp->mac_version = RTL_GIGA_MAC_VER_43;
2161 else if (tp->mac_version == RTL_GIGA_MAC_VER_45)
2162 tp->mac_version = RTL_GIGA_MAC_VER_47;
2163 else if (tp->mac_version == RTL_GIGA_MAC_VER_46)
2164 tp->mac_version = RTL_GIGA_MAC_VER_48;
2165 }
2166 }
2167
2168 static void rtl_release_firmware(struct rtl8169_private *tp)
2169 {
2170 if (tp->rtl_fw) {
2171 rtl_fw_release_firmware(tp->rtl_fw);
2172 kfree(tp->rtl_fw);
2173 tp->rtl_fw = NULL;
2174 }
2175 }
2176
2177 void r8169_apply_firmware(struct rtl8169_private *tp)
2178 {
2179 /* TODO: release firmware if rtl_fw_write_firmware signals failure. */
2180 if (tp->rtl_fw)
2181 rtl_fw_write_firmware(tp, tp->rtl_fw);
2182 }
2183
2184 static void rtl8168_config_eee_mac(struct rtl8169_private *tp)
2185 {
2186 /* Adjust EEE LED frequency */
2187 if (tp->mac_version != RTL_GIGA_MAC_VER_38)
2188 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
2189
2190 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_1111, 0x0003);
2191 }
2192
2193 static void rtl8125_config_eee_mac(struct rtl8169_private *tp)
2194 {
2195 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));
2196 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1));
2197 }
2198
2199 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
2200 {
2201 const u16 w[] = {
2202 addr[0] | (addr[1] << 8),
2203 addr[2] | (addr[3] << 8),
2204 addr[4] | (addr[5] << 8)
2205 };
2206
2207 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, w[0] | (w[1] << 16));
2208 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, w[2]);
2209 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, w[0] << 16);
2210 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, w[1] | (w[2] << 16));
2211 }
2212
2213 u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp)
2214 {
2215 u16 data1, data2, ioffset;
2216
2217 r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
2218 data1 = r8168_mac_ocp_read(tp, 0xdd02);
2219 data2 = r8168_mac_ocp_read(tp, 0xdd00);
2220
2221 ioffset = (data2 >> 1) & 0x7ff8;
2222 ioffset |= data2 & 0x0007;
2223 if (data1 & BIT(7))
2224 ioffset |= BIT(15);
2225
2226 return ioffset;
2227 }
2228
2229 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
2230 {
2231 if (!test_and_set_bit(flag, tp->wk.flags))
2232 schedule_work(&tp->wk.work);
2233 }
2234
2235 static void rtl8169_init_phy(struct rtl8169_private *tp)
2236 {
2237 r8169_hw_phy_config(tp, tp->phydev, tp->mac_version);
2238
2239 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2240 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2241 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
2242 /* set undocumented MAC Reg C+CR Offset 0x82h */
2243 RTL_W8(tp, 0x82, 0x01);
2244 }
2245
2246 if (tp->mac_version == RTL_GIGA_MAC_VER_05 &&
2247 tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE &&
2248 tp->pci_dev->subsystem_device == 0xe000)
2249 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b);
2250
2251 /* We may have called phy_speed_down before */
2252 phy_speed_up(tp->phydev);
2253
2254 if (rtl_supports_eee(tp))
2255 rtl_enable_eee(tp);
2256
2257 genphy_soft_reset(tp->phydev);
2258 }
2259
2260 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2261 {
2262 rtl_lock_work(tp);
2263
2264 rtl_unlock_config_regs(tp);
2265
2266 RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);
2267 RTL_R32(tp, MAC4);
2268
2269 RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
2270 RTL_R32(tp, MAC0);
2271
2272 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
2273 rtl_rar_exgmac_set(tp, addr);
2274
2275 rtl_lock_config_regs(tp);
2276
2277 rtl_unlock_work(tp);
2278 }
2279
2280 static int rtl_set_mac_address(struct net_device *dev, void *p)
2281 {
2282 struct rtl8169_private *tp = netdev_priv(dev);
2283 struct device *d = tp_to_dev(tp);
2284 int ret;
2285
2286 ret = eth_mac_addr(dev, p);
2287 if (ret)
2288 return ret;
2289
2290 pm_runtime_get_noresume(d);
2291
2292 if (pm_runtime_active(d))
2293 rtl_rar_set(tp, dev->dev_addr);
2294
2295 pm_runtime_put_noidle(d);
2296
2297 return 0;
2298 }
2299
2300 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
2301 {
2302 switch (tp->mac_version) {
2303 case RTL_GIGA_MAC_VER_25:
2304 case RTL_GIGA_MAC_VER_26:
2305 case RTL_GIGA_MAC_VER_29:
2306 case RTL_GIGA_MAC_VER_30:
2307 case RTL_GIGA_MAC_VER_32:
2308 case RTL_GIGA_MAC_VER_33:
2309 case RTL_GIGA_MAC_VER_34:
2310 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_61:
2311 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
2312 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
2313 break;
2314 default:
2315 break;
2316 }
2317 }
2318
2319 static void rtl_pll_power_down(struct rtl8169_private *tp)
2320 {
2321 if (r8168_check_dash(tp))
2322 return;
2323
2324 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
2325 tp->mac_version == RTL_GIGA_MAC_VER_33)
2326 rtl_ephy_write(tp, 0x19, 0xff64);
2327
2328 if (device_may_wakeup(tp_to_dev(tp))) {
2329 phy_speed_down(tp->phydev, false);
2330 rtl_wol_suspend_quirk(tp);
2331 return;
2332 }
2333
2334 switch (tp->mac_version) {
2335 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
2336 case RTL_GIGA_MAC_VER_37:
2337 case RTL_GIGA_MAC_VER_39:
2338 case RTL_GIGA_MAC_VER_43:
2339 case RTL_GIGA_MAC_VER_44:
2340 case RTL_GIGA_MAC_VER_45:
2341 case RTL_GIGA_MAC_VER_46:
2342 case RTL_GIGA_MAC_VER_47:
2343 case RTL_GIGA_MAC_VER_48:
2344 case RTL_GIGA_MAC_VER_50:
2345 case RTL_GIGA_MAC_VER_51:
2346 case RTL_GIGA_MAC_VER_52:
2347 case RTL_GIGA_MAC_VER_60:
2348 case RTL_GIGA_MAC_VER_61:
2349 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
2350 break;
2351 case RTL_GIGA_MAC_VER_40:
2352 case RTL_GIGA_MAC_VER_41:
2353 case RTL_GIGA_MAC_VER_49:
2354 rtl_eri_clear_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000);
2355 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
2356 break;
2357 default:
2358 break;
2359 }
2360 }
2361
2362 static void rtl_pll_power_up(struct rtl8169_private *tp)
2363 {
2364 switch (tp->mac_version) {
2365 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
2366 case RTL_GIGA_MAC_VER_37:
2367 case RTL_GIGA_MAC_VER_39:
2368 case RTL_GIGA_MAC_VER_43:
2369 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
2370 break;
2371 case RTL_GIGA_MAC_VER_44:
2372 case RTL_GIGA_MAC_VER_45:
2373 case RTL_GIGA_MAC_VER_46:
2374 case RTL_GIGA_MAC_VER_47:
2375 case RTL_GIGA_MAC_VER_48:
2376 case RTL_GIGA_MAC_VER_50:
2377 case RTL_GIGA_MAC_VER_51:
2378 case RTL_GIGA_MAC_VER_52:
2379 case RTL_GIGA_MAC_VER_60:
2380 case RTL_GIGA_MAC_VER_61:
2381 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
2382 break;
2383 case RTL_GIGA_MAC_VER_40:
2384 case RTL_GIGA_MAC_VER_41:
2385 case RTL_GIGA_MAC_VER_49:
2386 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
2387 rtl_eri_set_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000);
2388 break;
2389 default:
2390 break;
2391 }
2392
2393 phy_resume(tp->phydev);
2394 /* give MAC/PHY some time to resume */
2395 msleep(20);
2396 }
2397
2398 static void rtl_init_rxcfg(struct rtl8169_private *tp)
2399 {
2400 switch (tp->mac_version) {
2401 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
2402 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
2403 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
2404 break;
2405 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
2406 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
2407 case RTL_GIGA_MAC_VER_38:
2408 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
2409 break;
2410 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_52:
2411 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
2412 break;
2413 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61:
2414 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_VLAN_8125 |
2415 RX_DMA_BURST);
2416 break;
2417 default:
2418 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
2419 break;
2420 }
2421 }
2422
2423 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2424 {
2425 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
2426 }
2427
2428 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
2429 {
2430 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2431 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
2432 }
2433
2434 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
2435 {
2436 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2437 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
2438 }
2439
2440 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
2441 {
2442 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2443 }
2444
2445 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
2446 {
2447 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2448 }
2449
2450 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
2451 {
2452 RTL_W8(tp, MaxTxPacketSize, 0x3f);
2453 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2454 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
2455 }
2456
2457 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
2458 {
2459 RTL_W8(tp, MaxTxPacketSize, 0x0c);
2460 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2461 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
2462 }
2463
2464 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
2465 {
2466 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
2467 }
2468
2469 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
2470 {
2471 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
2472 }
2473
2474 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
2475 {
2476 rtl_unlock_config_regs(tp);
2477 switch (tp->mac_version) {
2478 case RTL_GIGA_MAC_VER_12:
2479 case RTL_GIGA_MAC_VER_17:
2480 r8168b_1_hw_jumbo_enable(tp);
2481 break;
2482 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
2483 r8168c_hw_jumbo_enable(tp);
2484 break;
2485 case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28:
2486 r8168dp_hw_jumbo_enable(tp);
2487 break;
2488 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33:
2489 r8168e_hw_jumbo_enable(tp);
2490 break;
2491 default:
2492 break;
2493 }
2494 rtl_lock_config_regs(tp);
2495 }
2496
2497 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
2498 {
2499 rtl_unlock_config_regs(tp);
2500 switch (tp->mac_version) {
2501 case RTL_GIGA_MAC_VER_12:
2502 case RTL_GIGA_MAC_VER_17:
2503 r8168b_1_hw_jumbo_disable(tp);
2504 break;
2505 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26:
2506 r8168c_hw_jumbo_disable(tp);
2507 break;
2508 case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28:
2509 r8168dp_hw_jumbo_disable(tp);
2510 break;
2511 case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33:
2512 r8168e_hw_jumbo_disable(tp);
2513 break;
2514 default:
2515 break;
2516 }
2517 rtl_lock_config_regs(tp);
2518 }
2519
2520 static void rtl_jumbo_config(struct rtl8169_private *tp, int mtu)
2521 {
2522 if (mtu > ETH_DATA_LEN)
2523 rtl_hw_jumbo_enable(tp);
2524 else
2525 rtl_hw_jumbo_disable(tp);
2526 }
2527
2528 DECLARE_RTL_COND(rtl_chipcmd_cond)
2529 {
2530 return RTL_R8(tp, ChipCmd) & CmdReset;
2531 }
2532
2533 static void rtl_hw_reset(struct rtl8169_private *tp)
2534 {
2535 RTL_W8(tp, ChipCmd, CmdReset);
2536
2537 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
2538 }
2539
2540 static void rtl_request_firmware(struct rtl8169_private *tp)
2541 {
2542 struct rtl_fw *rtl_fw;
2543
2544 /* firmware loaded already or no firmware available */
2545 if (tp->rtl_fw || !tp->fw_name)
2546 return;
2547
2548 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
2549 if (!rtl_fw) {
2550 netif_warn(tp, ifup, tp->dev, "Unable to load firmware, out of memory\n");
2551 return;
2552 }
2553
2554 rtl_fw->phy_write = rtl_writephy;
2555 rtl_fw->phy_read = rtl_readphy;
2556 rtl_fw->mac_mcu_write = mac_mcu_write;
2557 rtl_fw->mac_mcu_read = mac_mcu_read;
2558 rtl_fw->fw_name = tp->fw_name;
2559 rtl_fw->dev = tp_to_dev(tp);
2560
2561 if (rtl_fw_request_firmware(rtl_fw))
2562 kfree(rtl_fw);
2563 else
2564 tp->rtl_fw = rtl_fw;
2565 }
2566
2567 static void rtl_rx_close(struct rtl8169_private *tp)
2568 {
2569 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
2570 }
2571
2572 DECLARE_RTL_COND(rtl_npq_cond)
2573 {
2574 return RTL_R8(tp, TxPoll) & NPQ;
2575 }
2576
2577 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
2578 {
2579 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
2580 }
2581
2582 static void rtl8169_hw_reset(struct rtl8169_private *tp)
2583 {
2584 /* Disable interrupts */
2585 rtl8169_irq_mask_and_ack(tp);
2586
2587 rtl_rx_close(tp);
2588
2589 switch (tp->mac_version) {
2590 case RTL_GIGA_MAC_VER_27:
2591 case RTL_GIGA_MAC_VER_28:
2592 case RTL_GIGA_MAC_VER_31:
2593 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
2594 break;
2595 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
2596 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_52:
2597 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
2598 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
2599 break;
2600 default:
2601 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
2602 udelay(100);
2603 break;
2604 }
2605
2606 rtl_hw_reset(tp);
2607 }
2608
2609 static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
2610 {
2611 u32 val = TX_DMA_BURST << TxDMAShift |
2612 InterFrameGap << TxInterFrameGapShift;
2613
2614 if (rtl_is_8168evl_up(tp))
2615 val |= TXCFG_AUTO_FIFO;
2616
2617 RTL_W32(tp, TxConfig, val);
2618 }
2619
2620 static void rtl_set_rx_max_size(struct rtl8169_private *tp)
2621 {
2622 /* Low hurts. Let's disable the filtering. */
2623 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
2624 }
2625
2626 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
2627 {
2628 /*
2629 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
2630 * register to be written before TxDescAddrLow to work.
2631 * Switching from MMIO to I/O access fixes the issue as well.
2632 */
2633 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
2634 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
2635 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
2636 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
2637 }
2638
2639 static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version)
2640 {
2641 u32 val;
2642
2643 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
2644 val = 0x000fff00;
2645 else if (tp->mac_version == RTL_GIGA_MAC_VER_06)
2646 val = 0x00ffff00;
2647 else
2648 return;
2649
2650 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)
2651 val |= 0xff;
2652
2653 RTL_W32(tp, 0x7c, val);
2654 }
2655
2656 static void rtl_set_rx_mode(struct net_device *dev)
2657 {
2658 u32 rx_mode = AcceptBroadcast | AcceptMyPhys | AcceptMulticast;
2659 /* Multicast hash filter */
2660 u32 mc_filter[2] = { 0xffffffff, 0xffffffff };
2661 struct rtl8169_private *tp = netdev_priv(dev);
2662 u32 tmp;
2663
2664 if (dev->flags & IFF_PROMISC) {
2665 /* Unconditionally log net taps. */
2666 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
2667 rx_mode |= AcceptAllPhys;
2668 } else if (netdev_mc_count(dev) > MC_FILTER_LIMIT ||
2669 dev->flags & IFF_ALLMULTI ||
2670 tp->mac_version == RTL_GIGA_MAC_VER_35) {
2671 /* accept all multicasts */
2672 } else if (netdev_mc_empty(dev)) {
2673 rx_mode &= ~AcceptMulticast;
2674 } else {
2675 struct netdev_hw_addr *ha;
2676
2677 mc_filter[1] = mc_filter[0] = 0;
2678 netdev_for_each_mc_addr(ha, dev) {
2679 u32 bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
2680 mc_filter[bit_nr >> 5] |= BIT(bit_nr & 31);
2681 }
2682
2683 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
2684 tmp = mc_filter[0];
2685 mc_filter[0] = swab32(mc_filter[1]);
2686 mc_filter[1] = swab32(tmp);
2687 }
2688 }
2689
2690 if (dev->features & NETIF_F_RXALL)
2691 rx_mode |= (AcceptErr | AcceptRunt);
2692
2693 RTL_W32(tp, MAR0 + 4, mc_filter[1]);
2694 RTL_W32(tp, MAR0 + 0, mc_filter[0]);
2695
2696 tmp = RTL_R32(tp, RxConfig);
2697 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_MASK) | rx_mode);
2698 }
2699
2700 DECLARE_RTL_COND(rtl_csiar_cond)
2701 {
2702 return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
2703 }
2704
2705 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
2706 {
2707 u32 func = PCI_FUNC(tp->pci_dev->devfn);
2708
2709 RTL_W32(tp, CSIDR, value);
2710 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
2711 CSIAR_BYTE_ENABLE | func << 16);
2712
2713 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
2714 }
2715
2716 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
2717 {
2718 u32 func = PCI_FUNC(tp->pci_dev->devfn);
2719
2720 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
2721 CSIAR_BYTE_ENABLE);
2722
2723 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
2724 RTL_R32(tp, CSIDR) : ~0;
2725 }
2726
2727 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val)
2728 {
2729 struct pci_dev *pdev = tp->pci_dev;
2730 u32 csi;
2731
2732 /* According to Realtek the value at config space address 0x070f
2733 * controls the L0s/L1 entrance latency. We try standard ECAM access
2734 * first and if it fails fall back to CSI.
2735 */
2736 if (pdev->cfg_size > 0x070f &&
2737 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
2738 return;
2739
2740 netdev_notice_once(tp->dev,
2741 "No native access to PCI extended config space, falling back to CSI\n");
2742 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
2743 rtl_csi_write(tp, 0x070c, csi | val << 24);
2744 }
2745
2746 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
2747 {
2748 rtl_csi_access_enable(tp, 0x27);
2749 }
2750
2751 struct ephy_info {
2752 unsigned int offset;
2753 u16 mask;
2754 u16 bits;
2755 };
2756
2757 static void __rtl_ephy_init(struct rtl8169_private *tp,
2758 const struct ephy_info *e, int len)
2759 {
2760 u16 w;
2761
2762 while (len-- > 0) {
2763 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
2764 rtl_ephy_write(tp, e->offset, w);
2765 e++;
2766 }
2767 }
2768
2769 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a))
2770
2771 static void rtl_disable_clock_request(struct rtl8169_private *tp)
2772 {
2773 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
2774 PCI_EXP_LNKCTL_CLKREQ_EN);
2775 }
2776
2777 static void rtl_enable_clock_request(struct rtl8169_private *tp)
2778 {
2779 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
2780 PCI_EXP_LNKCTL_CLKREQ_EN);
2781 }
2782
2783 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp)
2784 {
2785 /* work around an issue when PCI reset occurs during L2/L3 state */
2786 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23);
2787 }
2788
2789 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
2790 {
2791 /* Don't enable ASPM in the chip if OS can't control ASPM */
2792 if (enable && tp->aspm_manageable) {
2793 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
2794 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
2795 } else {
2796 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
2797 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
2798 }
2799
2800 udelay(10);
2801 }
2802
2803 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat,
2804 u16 tx_stat, u16 rx_dyn, u16 tx_dyn)
2805 {
2806 /* Usage of dynamic vs. static FIFO is controlled by bit
2807 * TXCFG_AUTO_FIFO. Exact meaning of FIFO values isn't known.
2808 */
2809 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn);
2810 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn);
2811 }
2812
2813 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp,
2814 u8 low, u8 high)
2815 {
2816 /* FIFO thresholds for pause flow control */
2817 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low);
2818 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high);
2819 }
2820
2821 static void rtl_hw_start_8168b(struct rtl8169_private *tp)
2822 {
2823 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2824 }
2825
2826 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
2827 {
2828 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
2829
2830 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2831
2832 rtl_disable_clock_request(tp);
2833 }
2834
2835 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
2836 {
2837 static const struct ephy_info e_info_8168cp[] = {
2838 { 0x01, 0, 0x0001 },
2839 { 0x02, 0x0800, 0x1000 },
2840 { 0x03, 0, 0x0042 },
2841 { 0x06, 0x0080, 0x0000 },
2842 { 0x07, 0, 0x2000 }
2843 };
2844
2845 rtl_set_def_aspm_entry_latency(tp);
2846
2847 rtl_ephy_init(tp, e_info_8168cp);
2848
2849 __rtl_hw_start_8168cp(tp);
2850 }
2851
2852 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
2853 {
2854 rtl_set_def_aspm_entry_latency(tp);
2855
2856 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2857 }
2858
2859 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
2860 {
2861 rtl_set_def_aspm_entry_latency(tp);
2862
2863 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2864
2865 /* Magic. */
2866 RTL_W8(tp, DBG_REG, 0x20);
2867 }
2868
2869 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
2870 {
2871 static const struct ephy_info e_info_8168c_1[] = {
2872 { 0x02, 0x0800, 0x1000 },
2873 { 0x03, 0, 0x0002 },
2874 { 0x06, 0x0080, 0x0000 }
2875 };
2876
2877 rtl_set_def_aspm_entry_latency(tp);
2878
2879 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
2880
2881 rtl_ephy_init(tp, e_info_8168c_1);
2882
2883 __rtl_hw_start_8168cp(tp);
2884 }
2885
2886 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
2887 {
2888 static const struct ephy_info e_info_8168c_2[] = {
2889 { 0x01, 0, 0x0001 },
2890 { 0x03, 0x0400, 0x0020 }
2891 };
2892
2893 rtl_set_def_aspm_entry_latency(tp);
2894
2895 rtl_ephy_init(tp, e_info_8168c_2);
2896
2897 __rtl_hw_start_8168cp(tp);
2898 }
2899
2900 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
2901 {
2902 rtl_hw_start_8168c_2(tp);
2903 }
2904
2905 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
2906 {
2907 rtl_set_def_aspm_entry_latency(tp);
2908
2909 __rtl_hw_start_8168cp(tp);
2910 }
2911
2912 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
2913 {
2914 rtl_set_def_aspm_entry_latency(tp);
2915
2916 rtl_disable_clock_request(tp);
2917 }
2918
2919 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
2920 {
2921 static const struct ephy_info e_info_8168d_4[] = {
2922 { 0x0b, 0x0000, 0x0048 },
2923 { 0x19, 0x0020, 0x0050 },
2924 { 0x0c, 0x0100, 0x0020 },
2925 { 0x10, 0x0004, 0x0000 },
2926 };
2927
2928 rtl_set_def_aspm_entry_latency(tp);
2929
2930 rtl_ephy_init(tp, e_info_8168d_4);
2931
2932 rtl_enable_clock_request(tp);
2933 }
2934
2935 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
2936 {
2937 static const struct ephy_info e_info_8168e_1[] = {
2938 { 0x00, 0x0200, 0x0100 },
2939 { 0x00, 0x0000, 0x0004 },
2940 { 0x06, 0x0002, 0x0001 },
2941 { 0x06, 0x0000, 0x0030 },
2942 { 0x07, 0x0000, 0x2000 },
2943 { 0x00, 0x0000, 0x0020 },
2944 { 0x03, 0x5800, 0x2000 },
2945 { 0x03, 0x0000, 0x0001 },
2946 { 0x01, 0x0800, 0x1000 },
2947 { 0x07, 0x0000, 0x4000 },
2948 { 0x1e, 0x0000, 0x2000 },
2949 { 0x19, 0xffff, 0xfe6c },
2950 { 0x0a, 0x0000, 0x0040 }
2951 };
2952
2953 rtl_set_def_aspm_entry_latency(tp);
2954
2955 rtl_ephy_init(tp, e_info_8168e_1);
2956
2957 rtl_disable_clock_request(tp);
2958
2959 /* Reset tx FIFO pointer */
2960 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
2961 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
2962
2963 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
2964 }
2965
2966 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
2967 {
2968 static const struct ephy_info e_info_8168e_2[] = {
2969 { 0x09, 0x0000, 0x0080 },
2970 { 0x19, 0x0000, 0x0224 },
2971 { 0x00, 0x0000, 0x0004 },
2972 { 0x0c, 0x3df0, 0x0200 },
2973 };
2974
2975 rtl_set_def_aspm_entry_latency(tp);
2976
2977 rtl_ephy_init(tp, e_info_8168e_2);
2978
2979 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
2980 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
2981 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
2982 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
2983 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060);
2984 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4));
2985 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00);
2986
2987 rtl_disable_clock_request(tp);
2988
2989 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
2990
2991 rtl8168_config_eee_mac(tp);
2992
2993 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
2994 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
2995 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
2996
2997 rtl_hw_aspm_clkreq_enable(tp, true);
2998 }
2999
3000 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
3001 {
3002 rtl_set_def_aspm_entry_latency(tp);
3003
3004 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3005 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3006 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
3007 rtl_reset_packet_filter(tp);
3008 rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4));
3009 rtl_eri_set_bits(tp, 0x1d0, ERIAR_MASK_0001, BIT(4));
3010 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
3011 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060);
3012
3013 rtl_disable_clock_request(tp);
3014
3015 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
3016 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
3017 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
3018 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
3019
3020 rtl8168_config_eee_mac(tp);
3021 }
3022
3023 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
3024 {
3025 static const struct ephy_info e_info_8168f_1[] = {
3026 { 0x06, 0x00c0, 0x0020 },
3027 { 0x08, 0x0001, 0x0002 },
3028 { 0x09, 0x0000, 0x0080 },
3029 { 0x19, 0x0000, 0x0224 },
3030 { 0x00, 0x0000, 0x0004 },
3031 { 0x0c, 0x3df0, 0x0200 },
3032 };
3033
3034 rtl_hw_start_8168f(tp);
3035
3036 rtl_ephy_init(tp, e_info_8168f_1);
3037
3038 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00);
3039 }
3040
3041 static void rtl_hw_start_8411(struct rtl8169_private *tp)
3042 {
3043 static const struct ephy_info e_info_8168f_1[] = {
3044 { 0x06, 0x00c0, 0x0020 },
3045 { 0x0f, 0xffff, 0x5200 },
3046 { 0x19, 0x0000, 0x0224 },
3047 { 0x00, 0x0000, 0x0004 },
3048 { 0x0c, 0x3df0, 0x0200 },
3049 };
3050
3051 rtl_hw_start_8168f(tp);
3052 rtl_pcie_state_l2l3_disable(tp);
3053
3054 rtl_ephy_init(tp, e_info_8168f_1);
3055
3056 rtl_eri_set_bits(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00);
3057 }
3058
3059 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
3060 {
3061 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3062 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
3063
3064 rtl_set_def_aspm_entry_latency(tp);
3065
3066 rtl_reset_packet_filter(tp);
3067 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f);
3068
3069 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
3070
3071 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3072 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3073
3074 rtl8168_config_eee_mac(tp);
3075
3076 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06);
3077 rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12));
3078
3079 rtl_pcie_state_l2l3_disable(tp);
3080 }
3081
3082 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
3083 {
3084 static const struct ephy_info e_info_8168g_1[] = {
3085 { 0x00, 0x0008, 0x0000 },
3086 { 0x0c, 0x3ff0, 0x0820 },
3087 { 0x1e, 0x0000, 0x0001 },
3088 { 0x19, 0x8000, 0x0000 }
3089 };
3090
3091 rtl_hw_start_8168g(tp);
3092
3093 /* disable aspm and clock request before access ephy */
3094 rtl_hw_aspm_clkreq_enable(tp, false);
3095 rtl_ephy_init(tp, e_info_8168g_1);
3096 rtl_hw_aspm_clkreq_enable(tp, true);
3097 }
3098
3099 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
3100 {
3101 static const struct ephy_info e_info_8168g_2[] = {
3102 { 0x00, 0x0008, 0x0000 },
3103 { 0x0c, 0x3ff0, 0x0820 },
3104 { 0x19, 0xffff, 0x7c00 },
3105 { 0x1e, 0xffff, 0x20eb },
3106 { 0x0d, 0xffff, 0x1666 },
3107 { 0x00, 0xffff, 0x10a3 },
3108 { 0x06, 0xffff, 0xf050 },
3109 { 0x04, 0x0000, 0x0010 },
3110 { 0x1d, 0x4000, 0x0000 },
3111 };
3112
3113 rtl_hw_start_8168g(tp);
3114
3115 /* disable aspm and clock request before access ephy */
3116 rtl_hw_aspm_clkreq_enable(tp, false);
3117 rtl_ephy_init(tp, e_info_8168g_2);
3118 }
3119
3120 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
3121 {
3122 static const struct ephy_info e_info_8411_2[] = {
3123 { 0x00, 0x0008, 0x0000 },
3124 { 0x0c, 0x37d0, 0x0820 },
3125 { 0x1e, 0x0000, 0x0001 },
3126 { 0x19, 0x8021, 0x0000 },
3127 { 0x1e, 0x0000, 0x2000 },
3128 { 0x0d, 0x0100, 0x0200 },
3129 { 0x00, 0x0000, 0x0080 },
3130 { 0x06, 0x0000, 0x0010 },
3131 { 0x04, 0x0000, 0x0010 },
3132 { 0x1d, 0x0000, 0x4000 },
3133 };
3134
3135 rtl_hw_start_8168g(tp);
3136
3137 /* disable aspm and clock request before access ephy */
3138 rtl_hw_aspm_clkreq_enable(tp, false);
3139 rtl_ephy_init(tp, e_info_8411_2);
3140
3141 /* The following Realtek-provided magic fixes an issue with the RX unit
3142 * getting confused after the PHY having been powered-down.
3143 */
3144 r8168_mac_ocp_write(tp, 0xFC28, 0x0000);
3145 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000);
3146 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000);
3147 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000);
3148 r8168_mac_ocp_write(tp, 0xFC30, 0x0000);
3149 r8168_mac_ocp_write(tp, 0xFC32, 0x0000);
3150 r8168_mac_ocp_write(tp, 0xFC34, 0x0000);
3151 r8168_mac_ocp_write(tp, 0xFC36, 0x0000);
3152 mdelay(3);
3153 r8168_mac_ocp_write(tp, 0xFC26, 0x0000);
3154
3155 r8168_mac_ocp_write(tp, 0xF800, 0xE008);
3156 r8168_mac_ocp_write(tp, 0xF802, 0xE00A);
3157 r8168_mac_ocp_write(tp, 0xF804, 0xE00C);
3158 r8168_mac_ocp_write(tp, 0xF806, 0xE00E);
3159 r8168_mac_ocp_write(tp, 0xF808, 0xE027);
3160 r8168_mac_ocp_write(tp, 0xF80A, 0xE04F);
3161 r8168_mac_ocp_write(tp, 0xF80C, 0xE05E);
3162 r8168_mac_ocp_write(tp, 0xF80E, 0xE065);
3163 r8168_mac_ocp_write(tp, 0xF810, 0xC602);
3164 r8168_mac_ocp_write(tp, 0xF812, 0xBE00);
3165 r8168_mac_ocp_write(tp, 0xF814, 0x0000);
3166 r8168_mac_ocp_write(tp, 0xF816, 0xC502);
3167 r8168_mac_ocp_write(tp, 0xF818, 0xBD00);
3168 r8168_mac_ocp_write(tp, 0xF81A, 0x074C);
3169 r8168_mac_ocp_write(tp, 0xF81C, 0xC302);
3170 r8168_mac_ocp_write(tp, 0xF81E, 0xBB00);
3171 r8168_mac_ocp_write(tp, 0xF820, 0x080A);
3172 r8168_mac_ocp_write(tp, 0xF822, 0x6420);
3173 r8168_mac_ocp_write(tp, 0xF824, 0x48C2);
3174 r8168_mac_ocp_write(tp, 0xF826, 0x8C20);
3175 r8168_mac_ocp_write(tp, 0xF828, 0xC516);
3176 r8168_mac_ocp_write(tp, 0xF82A, 0x64A4);
3177 r8168_mac_ocp_write(tp, 0xF82C, 0x49C0);
3178 r8168_mac_ocp_write(tp, 0xF82E, 0xF009);
3179 r8168_mac_ocp_write(tp, 0xF830, 0x74A2);
3180 r8168_mac_ocp_write(tp, 0xF832, 0x8CA5);
3181 r8168_mac_ocp_write(tp, 0xF834, 0x74A0);
3182 r8168_mac_ocp_write(tp, 0xF836, 0xC50E);
3183 r8168_mac_ocp_write(tp, 0xF838, 0x9CA2);
3184 r8168_mac_ocp_write(tp, 0xF83A, 0x1C11);
3185 r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0);
3186 r8168_mac_ocp_write(tp, 0xF83E, 0xE006);
3187 r8168_mac_ocp_write(tp, 0xF840, 0x74F8);
3188 r8168_mac_ocp_write(tp, 0xF842, 0x48C4);
3189 r8168_mac_ocp_write(tp, 0xF844, 0x8CF8);
3190 r8168_mac_ocp_write(tp, 0xF846, 0xC404);
3191 r8168_mac_ocp_write(tp, 0xF848, 0xBC00);
3192 r8168_mac_ocp_write(tp, 0xF84A, 0xC403);
3193 r8168_mac_ocp_write(tp, 0xF84C, 0xBC00);
3194 r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2);
3195 r8168_mac_ocp_write(tp, 0xF850, 0x0C0A);
3196 r8168_mac_ocp_write(tp, 0xF852, 0xE434);
3197 r8168_mac_ocp_write(tp, 0xF854, 0xD3C0);
3198 r8168_mac_ocp_write(tp, 0xF856, 0x49D9);
3199 r8168_mac_ocp_write(tp, 0xF858, 0xF01F);
3200 r8168_mac_ocp_write(tp, 0xF85A, 0xC526);
3201 r8168_mac_ocp_write(tp, 0xF85C, 0x64A5);
3202 r8168_mac_ocp_write(tp, 0xF85E, 0x1400);
3203 r8168_mac_ocp_write(tp, 0xF860, 0xF007);
3204 r8168_mac_ocp_write(tp, 0xF862, 0x0C01);
3205 r8168_mac_ocp_write(tp, 0xF864, 0x8CA5);
3206 r8168_mac_ocp_write(tp, 0xF866, 0x1C15);
3207 r8168_mac_ocp_write(tp, 0xF868, 0xC51B);
3208 r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0);
3209 r8168_mac_ocp_write(tp, 0xF86C, 0xE013);
3210 r8168_mac_ocp_write(tp, 0xF86E, 0xC519);
3211 r8168_mac_ocp_write(tp, 0xF870, 0x74A0);
3212 r8168_mac_ocp_write(tp, 0xF872, 0x48C4);
3213 r8168_mac_ocp_write(tp, 0xF874, 0x8CA0);
3214 r8168_mac_ocp_write(tp, 0xF876, 0xC516);
3215 r8168_mac_ocp_write(tp, 0xF878, 0x74A4);
3216 r8168_mac_ocp_write(tp, 0xF87A, 0x48C8);
3217 r8168_mac_ocp_write(tp, 0xF87C, 0x48CA);
3218 r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4);
3219 r8168_mac_ocp_write(tp, 0xF880, 0xC512);
3220 r8168_mac_ocp_write(tp, 0xF882, 0x1B00);
3221 r8168_mac_ocp_write(tp, 0xF884, 0x9BA0);
3222 r8168_mac_ocp_write(tp, 0xF886, 0x1B1C);
3223 r8168_mac_ocp_write(tp, 0xF888, 0x483F);
3224 r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2);
3225 r8168_mac_ocp_write(tp, 0xF88C, 0x1B04);
3226 r8168_mac_ocp_write(tp, 0xF88E, 0xC508);
3227 r8168_mac_ocp_write(tp, 0xF890, 0x9BA0);
3228 r8168_mac_ocp_write(tp, 0xF892, 0xC505);
3229 r8168_mac_ocp_write(tp, 0xF894, 0xBD00);
3230 r8168_mac_ocp_write(tp, 0xF896, 0xC502);
3231 r8168_mac_ocp_write(tp, 0xF898, 0xBD00);
3232 r8168_mac_ocp_write(tp, 0xF89A, 0x0300);
3233 r8168_mac_ocp_write(tp, 0xF89C, 0x051E);
3234 r8168_mac_ocp_write(tp, 0xF89E, 0xE434);
3235 r8168_mac_ocp_write(tp, 0xF8A0, 0xE018);
3236 r8168_mac_ocp_write(tp, 0xF8A2, 0xE092);
3237 r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20);
3238 r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0);
3239 r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F);
3240 r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4);
3241 r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3);
3242 r8168_mac_ocp_write(tp, 0xF8AE, 0xF007);
3243 r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0);
3244 r8168_mac_ocp_write(tp, 0xF8B2, 0xF103);
3245 r8168_mac_ocp_write(tp, 0xF8B4, 0xC607);
3246 r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00);
3247 r8168_mac_ocp_write(tp, 0xF8B8, 0xC606);
3248 r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00);
3249 r8168_mac_ocp_write(tp, 0xF8BC, 0xC602);
3250 r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00);
3251 r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C);
3252 r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28);
3253 r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C);
3254 r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00);
3255 r8168_mac_ocp_write(tp, 0xF8C8, 0xC707);
3256 r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00);
3257 r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2);
3258 r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1);
3259 r8168_mac_ocp_write(tp, 0xF8D0, 0xC502);
3260 r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00);
3261 r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA);
3262 r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0);
3263 r8168_mac_ocp_write(tp, 0xF8D8, 0xC502);
3264 r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00);
3265 r8168_mac_ocp_write(tp, 0xF8DC, 0x0132);
3266
3267 r8168_mac_ocp_write(tp, 0xFC26, 0x8000);
3268
3269 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743);
3270 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801);
3271 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9);
3272 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD);
3273 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25);
3274 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9);
3275 r8168_mac_ocp_write(tp, 0xFC36, 0x012D);
3276
3277 rtl_hw_aspm_clkreq_enable(tp, true);
3278 }
3279
3280 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
3281 {
3282 static const struct ephy_info e_info_8168h_1[] = {
3283 { 0x1e, 0x0800, 0x0001 },
3284 { 0x1d, 0x0000, 0x0800 },
3285 { 0x05, 0xffff, 0x2089 },
3286 { 0x06, 0xffff, 0x5881 },
3287 { 0x04, 0xffff, 0x854a },
3288 { 0x01, 0xffff, 0x068b }
3289 };
3290 int rg_saw_cnt;
3291
3292 /* disable aspm and clock request before access ephy */
3293 rtl_hw_aspm_clkreq_enable(tp, false);
3294 rtl_ephy_init(tp, e_info_8168h_1);
3295
3296 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3297 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
3298
3299 rtl_set_def_aspm_entry_latency(tp);
3300
3301 rtl_reset_packet_filter(tp);
3302
3303 rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_1111, BIT(4));
3304
3305 rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f00);
3306
3307 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3308
3309 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
3310
3311 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3312 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3313
3314 rtl8168_config_eee_mac(tp);
3315
3316 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3317 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3318
3319 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3320
3321 rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12));
3322
3323 rtl_pcie_state_l2l3_disable(tp);
3324
3325 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff;
3326 if (rg_saw_cnt > 0) {
3327 u16 sw_cnt_1ms_ini;
3328
3329 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
3330 sw_cnt_1ms_ini &= 0x0fff;
3331 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
3332 }
3333
3334 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
3335 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008);
3336 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f);
3337 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
3338
3339 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
3340 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
3341 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
3342 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
3343
3344 rtl_hw_aspm_clkreq_enable(tp, true);
3345 }
3346
3347 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
3348 {
3349 rtl8168ep_stop_cmac(tp);
3350
3351 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3352 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
3353
3354 rtl_set_def_aspm_entry_latency(tp);
3355
3356 rtl_reset_packet_filter(tp);
3357
3358 rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f80);
3359
3360 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3361
3362 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
3363
3364 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3365 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3366
3367 rtl8168_config_eee_mac(tp);
3368
3369 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06);
3370
3371 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3372
3373 rtl_pcie_state_l2l3_disable(tp);
3374 }
3375
3376 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
3377 {
3378 static const struct ephy_info e_info_8168ep_1[] = {
3379 { 0x00, 0xffff, 0x10ab },
3380 { 0x06, 0xffff, 0xf030 },
3381 { 0x08, 0xffff, 0x2006 },
3382 { 0x0d, 0xffff, 0x1666 },
3383 { 0x0c, 0x3ff0, 0x0000 }
3384 };
3385
3386 /* disable aspm and clock request before access ephy */
3387 rtl_hw_aspm_clkreq_enable(tp, false);
3388 rtl_ephy_init(tp, e_info_8168ep_1);
3389
3390 rtl_hw_start_8168ep(tp);
3391
3392 rtl_hw_aspm_clkreq_enable(tp, true);
3393 }
3394
3395 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
3396 {
3397 static const struct ephy_info e_info_8168ep_2[] = {
3398 { 0x00, 0xffff, 0x10a3 },
3399 { 0x19, 0xffff, 0xfc00 },
3400 { 0x1e, 0xffff, 0x20ea }
3401 };
3402
3403 /* disable aspm and clock request before access ephy */
3404 rtl_hw_aspm_clkreq_enable(tp, false);
3405 rtl_ephy_init(tp, e_info_8168ep_2);
3406
3407 rtl_hw_start_8168ep(tp);
3408
3409 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3410 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3411
3412 rtl_hw_aspm_clkreq_enable(tp, true);
3413 }
3414
3415 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
3416 {
3417 static const struct ephy_info e_info_8168ep_3[] = {
3418 { 0x00, 0x0000, 0x0080 },
3419 { 0x0d, 0x0100, 0x0200 },
3420 { 0x19, 0x8021, 0x0000 },
3421 { 0x1e, 0x0000, 0x2000 },
3422 };
3423
3424 /* disable aspm and clock request before access ephy */
3425 rtl_hw_aspm_clkreq_enable(tp, false);
3426 rtl_ephy_init(tp, e_info_8168ep_3);
3427
3428 rtl_hw_start_8168ep(tp);
3429
3430 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3431 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3432
3433 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271);
3434 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
3435 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
3436
3437 rtl_hw_aspm_clkreq_enable(tp, true);
3438 }
3439
3440 static void rtl_hw_start_8117(struct rtl8169_private *tp)
3441 {
3442 static const struct ephy_info e_info_8117[] = {
3443 { 0x19, 0x0040, 0x1100 },
3444 { 0x59, 0x0040, 0x1100 },
3445 };
3446 int rg_saw_cnt;
3447
3448 rtl8168ep_stop_cmac(tp);
3449
3450 /* disable aspm and clock request before access ephy */
3451 rtl_hw_aspm_clkreq_enable(tp, false);
3452 rtl_ephy_init(tp, e_info_8117);
3453
3454 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3455 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
3456
3457 rtl_set_def_aspm_entry_latency(tp);
3458
3459 rtl_reset_packet_filter(tp);
3460
3461 rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f90);
3462
3463 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3464
3465 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
3466
3467 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3468 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3469
3470 rtl8168_config_eee_mac(tp);
3471
3472 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3473 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3474
3475 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3476
3477 rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12));
3478
3479 rtl_pcie_state_l2l3_disable(tp);
3480
3481 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff;
3482 if (rg_saw_cnt > 0) {
3483 u16 sw_cnt_1ms_ini;
3484
3485 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff;
3486 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
3487 }
3488
3489 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
3490 r8168_mac_ocp_write(tp, 0xea80, 0x0003);
3491 r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009);
3492 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
3493
3494 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
3495 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
3496 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
3497 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
3498
3499 /* firmware is for MAC only */
3500 r8169_apply_firmware(tp);
3501
3502 rtl_hw_aspm_clkreq_enable(tp, true);
3503 }
3504
3505 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
3506 {
3507 static const struct ephy_info e_info_8102e_1[] = {
3508 { 0x01, 0, 0x6e65 },
3509 { 0x02, 0, 0x091f },
3510 { 0x03, 0, 0xc2f9 },
3511 { 0x06, 0, 0xafb5 },
3512 { 0x07, 0, 0x0e00 },
3513 { 0x19, 0, 0xec80 },
3514 { 0x01, 0, 0x2e65 },
3515 { 0x01, 0, 0x6e65 }
3516 };
3517 u8 cfg1;
3518
3519 rtl_set_def_aspm_entry_latency(tp);
3520
3521 RTL_W8(tp, DBG_REG, FIX_NAK_1);
3522
3523 RTL_W8(tp, Config1,
3524 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
3525 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3526
3527 cfg1 = RTL_R8(tp, Config1);
3528 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
3529 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
3530
3531 rtl_ephy_init(tp, e_info_8102e_1);
3532 }
3533
3534 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
3535 {
3536 rtl_set_def_aspm_entry_latency(tp);
3537
3538 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
3539 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3540 }
3541
3542 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
3543 {
3544 rtl_hw_start_8102e_2(tp);
3545
3546 rtl_ephy_write(tp, 0x03, 0xc2f9);
3547 }
3548
3549 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
3550 {
3551 static const struct ephy_info e_info_8105e_1[] = {
3552 { 0x07, 0, 0x4000 },
3553 { 0x19, 0, 0x0200 },
3554 { 0x19, 0, 0x0020 },
3555 { 0x1e, 0, 0x2000 },
3556 { 0x03, 0, 0x0001 },
3557 { 0x19, 0, 0x0100 },
3558 { 0x19, 0, 0x0004 },
3559 { 0x0a, 0, 0x0020 }
3560 };
3561
3562 /* Force LAN exit from ASPM if Rx/Tx are not idle */
3563 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3564
3565 /* Disable Early Tally Counter */
3566 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
3567
3568 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
3569 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
3570
3571 rtl_ephy_init(tp, e_info_8105e_1);
3572
3573 rtl_pcie_state_l2l3_disable(tp);
3574 }
3575
3576 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
3577 {
3578 rtl_hw_start_8105e_1(tp);
3579 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
3580 }
3581
3582 static void rtl_hw_start_8402(struct rtl8169_private *tp)
3583 {
3584 static const struct ephy_info e_info_8402[] = {
3585 { 0x19, 0xffff, 0xff64 },
3586 { 0x1e, 0, 0x4000 }
3587 };
3588
3589 rtl_set_def_aspm_entry_latency(tp);
3590
3591 /* Force LAN exit from ASPM if Rx/Tx are not idle */
3592 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3593
3594 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
3595
3596 rtl_ephy_init(tp, e_info_8402);
3597
3598 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06);
3599 rtl_reset_packet_filter(tp);
3600 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3601 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3602 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00);
3603
3604 /* disable EEE */
3605 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3606
3607 rtl_pcie_state_l2l3_disable(tp);
3608 }
3609
3610 static void rtl_hw_start_8106(struct rtl8169_private *tp)
3611 {
3612 rtl_hw_aspm_clkreq_enable(tp, false);
3613
3614 /* Force LAN exit from ASPM if Rx/Tx are not idle */
3615 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3616
3617 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
3618 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
3619 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3620
3621 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
3622
3623 /* disable EEE */
3624 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3625
3626 rtl_pcie_state_l2l3_disable(tp);
3627 rtl_hw_aspm_clkreq_enable(tp, true);
3628 }
3629
3630 DECLARE_RTL_COND(rtl_mac_ocp_e00e_cond)
3631 {
3632 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13);
3633 }
3634
3635 static void rtl_hw_start_8125_common(struct rtl8169_private *tp)
3636 {
3637 rtl_pcie_state_l2l3_disable(tp);
3638
3639 RTL_W16(tp, 0x382, 0x221b);
3640 RTL_W8(tp, 0x4500, 0);
3641 RTL_W16(tp, 0x4800, 0);
3642
3643 /* disable UPS */
3644 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000);
3645
3646 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10);
3647
3648 r8168_mac_ocp_write(tp, 0xc140, 0xffff);
3649 r8168_mac_ocp_write(tp, 0xc142, 0xffff);
3650
3651 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9);
3652 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
3653 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
3654
3655 /* disable new tx descriptor format */
3656 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000);
3657
3658 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400);
3659 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020);
3660 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c);
3661 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033);
3662 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040);
3663 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030);
3664 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000);
3665 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403);
3666 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0067);
3667 r8168_mac_ocp_modify(tp, 0xc0ac, 0x0080, 0x1f00);
3668 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f);
3669 r8168_mac_ocp_modify(tp, 0xe84c, 0x0000, 0x00c0);
3670 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000);
3671 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001);
3672 udelay(1);
3673 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000);
3674 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030);
3675
3676 r8168_mac_ocp_write(tp, 0xe098, 0xc302);
3677
3678 rtl_udelay_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10);
3679
3680 rtl8125_config_eee_mac(tp);
3681
3682 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
3683 udelay(10);
3684 }
3685
3686 static void rtl_hw_start_8125_1(struct rtl8169_private *tp)
3687 {
3688 static const struct ephy_info e_info_8125_1[] = {
3689 { 0x01, 0xffff, 0xa812 },
3690 { 0x09, 0xffff, 0x520c },
3691 { 0x04, 0xffff, 0xd000 },
3692 { 0x0d, 0xffff, 0xf702 },
3693 { 0x0a, 0xffff, 0x8653 },
3694 { 0x06, 0xffff, 0x001e },
3695 { 0x08, 0xffff, 0x3595 },
3696 { 0x20, 0xffff, 0x9455 },
3697 { 0x21, 0xffff, 0x99ff },
3698 { 0x02, 0xffff, 0x6046 },
3699 { 0x29, 0xffff, 0xfe00 },
3700 { 0x23, 0xffff, 0xab62 },
3701
3702 { 0x41, 0xffff, 0xa80c },
3703 { 0x49, 0xffff, 0x520c },
3704 { 0x44, 0xffff, 0xd000 },
3705 { 0x4d, 0xffff, 0xf702 },
3706 { 0x4a, 0xffff, 0x8653 },
3707 { 0x46, 0xffff, 0x001e },
3708 { 0x48, 0xffff, 0x3595 },
3709 { 0x60, 0xffff, 0x9455 },
3710 { 0x61, 0xffff, 0x99ff },
3711 { 0x42, 0xffff, 0x6046 },
3712 { 0x69, 0xffff, 0xfe00 },
3713 { 0x63, 0xffff, 0xab62 },
3714 };
3715
3716 rtl_set_def_aspm_entry_latency(tp);
3717
3718 /* disable aspm and clock request before access ephy */
3719 rtl_hw_aspm_clkreq_enable(tp, false);
3720 rtl_ephy_init(tp, e_info_8125_1);
3721
3722 rtl_hw_start_8125_common(tp);
3723 }
3724
3725 static void rtl_hw_start_8125_2(struct rtl8169_private *tp)
3726 {
3727 static const struct ephy_info e_info_8125_2[] = {
3728 { 0x04, 0xffff, 0xd000 },
3729 { 0x0a, 0xffff, 0x8653 },
3730 { 0x23, 0xffff, 0xab66 },
3731 { 0x20, 0xffff, 0x9455 },
3732 { 0x21, 0xffff, 0x99ff },
3733 { 0x29, 0xffff, 0xfe04 },
3734
3735 { 0x44, 0xffff, 0xd000 },
3736 { 0x4a, 0xffff, 0x8653 },
3737 { 0x63, 0xffff, 0xab66 },
3738 { 0x60, 0xffff, 0x9455 },
3739 { 0x61, 0xffff, 0x99ff },
3740 { 0x69, 0xffff, 0xfe04 },
3741 };
3742
3743 rtl_set_def_aspm_entry_latency(tp);
3744
3745 /* disable aspm and clock request before access ephy */
3746 rtl_hw_aspm_clkreq_enable(tp, false);
3747 rtl_ephy_init(tp, e_info_8125_2);
3748
3749 rtl_hw_start_8125_common(tp);
3750 }
3751
3752 static void rtl_hw_config(struct rtl8169_private *tp)
3753 {
3754 static const rtl_generic_fct hw_configs[] = {
3755 [RTL_GIGA_MAC_VER_07] = rtl_hw_start_8102e_1,
3756 [RTL_GIGA_MAC_VER_08] = rtl_hw_start_8102e_3,
3757 [RTL_GIGA_MAC_VER_09] = rtl_hw_start_8102e_2,
3758 [RTL_GIGA_MAC_VER_10] = NULL,
3759 [RTL_GIGA_MAC_VER_11] = rtl_hw_start_8168b,
3760 [RTL_GIGA_MAC_VER_12] = rtl_hw_start_8168b,
3761 [RTL_GIGA_MAC_VER_13] = NULL,
3762 [RTL_GIGA_MAC_VER_14] = NULL,
3763 [RTL_GIGA_MAC_VER_15] = NULL,
3764 [RTL_GIGA_MAC_VER_16] = NULL,
3765 [RTL_GIGA_MAC_VER_17] = rtl_hw_start_8168b,
3766 [RTL_GIGA_MAC_VER_18] = rtl_hw_start_8168cp_1,
3767 [RTL_GIGA_MAC_VER_19] = rtl_hw_start_8168c_1,
3768 [RTL_GIGA_MAC_VER_20] = rtl_hw_start_8168c_2,
3769 [RTL_GIGA_MAC_VER_21] = rtl_hw_start_8168c_3,
3770 [RTL_GIGA_MAC_VER_22] = rtl_hw_start_8168c_4,
3771 [RTL_GIGA_MAC_VER_23] = rtl_hw_start_8168cp_2,
3772 [RTL_GIGA_MAC_VER_24] = rtl_hw_start_8168cp_3,
3773 [RTL_GIGA_MAC_VER_25] = rtl_hw_start_8168d,
3774 [RTL_GIGA_MAC_VER_26] = rtl_hw_start_8168d,
3775 [RTL_GIGA_MAC_VER_27] = rtl_hw_start_8168d,
3776 [RTL_GIGA_MAC_VER_28] = rtl_hw_start_8168d_4,
3777 [RTL_GIGA_MAC_VER_29] = rtl_hw_start_8105e_1,
3778 [RTL_GIGA_MAC_VER_30] = rtl_hw_start_8105e_2,
3779 [RTL_GIGA_MAC_VER_31] = rtl_hw_start_8168d,
3780 [RTL_GIGA_MAC_VER_32] = rtl_hw_start_8168e_1,
3781 [RTL_GIGA_MAC_VER_33] = rtl_hw_start_8168e_1,
3782 [RTL_GIGA_MAC_VER_34] = rtl_hw_start_8168e_2,
3783 [RTL_GIGA_MAC_VER_35] = rtl_hw_start_8168f_1,
3784 [RTL_GIGA_MAC_VER_36] = rtl_hw_start_8168f_1,
3785 [RTL_GIGA_MAC_VER_37] = rtl_hw_start_8402,
3786 [RTL_GIGA_MAC_VER_38] = rtl_hw_start_8411,
3787 [RTL_GIGA_MAC_VER_39] = rtl_hw_start_8106,
3788 [RTL_GIGA_MAC_VER_40] = rtl_hw_start_8168g_1,
3789 [RTL_GIGA_MAC_VER_41] = rtl_hw_start_8168g_1,
3790 [RTL_GIGA_MAC_VER_42] = rtl_hw_start_8168g_2,
3791 [RTL_GIGA_MAC_VER_43] = rtl_hw_start_8168g_2,
3792 [RTL_GIGA_MAC_VER_44] = rtl_hw_start_8411_2,
3793 [RTL_GIGA_MAC_VER_45] = rtl_hw_start_8168h_1,
3794 [RTL_GIGA_MAC_VER_46] = rtl_hw_start_8168h_1,
3795 [RTL_GIGA_MAC_VER_47] = rtl_hw_start_8168h_1,
3796 [RTL_GIGA_MAC_VER_48] = rtl_hw_start_8168h_1,
3797 [RTL_GIGA_MAC_VER_49] = rtl_hw_start_8168ep_1,
3798 [RTL_GIGA_MAC_VER_50] = rtl_hw_start_8168ep_2,
3799 [RTL_GIGA_MAC_VER_51] = rtl_hw_start_8168ep_3,
3800 [RTL_GIGA_MAC_VER_52] = rtl_hw_start_8117,
3801 [RTL_GIGA_MAC_VER_60] = rtl_hw_start_8125_1,
3802 [RTL_GIGA_MAC_VER_61] = rtl_hw_start_8125_2,
3803 };
3804
3805 if (hw_configs[tp->mac_version])
3806 hw_configs[tp->mac_version](tp);
3807 }
3808
3809 static void rtl_hw_start_8125(struct rtl8169_private *tp)
3810 {
3811 int i;
3812
3813 /* disable interrupt coalescing */
3814 for (i = 0xa00; i < 0xb00; i += 4)
3815 RTL_W32(tp, i, 0);
3816
3817 rtl_hw_config(tp);
3818 }
3819
3820 static void rtl_hw_start_8168(struct rtl8169_private *tp)
3821 {
3822 if (rtl_is_8168evl_up(tp))
3823 RTL_W8(tp, MaxTxPacketSize, EarlySize);
3824 else
3825 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
3826
3827 rtl_hw_config(tp);
3828
3829 /* disable interrupt coalescing */
3830 RTL_W16(tp, IntrMitigate, 0x0000);
3831 }
3832
3833 static void rtl_hw_start_8169(struct rtl8169_private *tp)
3834 {
3835 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3836 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
3837
3838 RTL_W8(tp, EarlyTxThres, NoEarlyTx);
3839
3840 tp->cp_cmd |= PCIMulRW;
3841
3842 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3843 tp->mac_version == RTL_GIGA_MAC_VER_03)
3844 tp->cp_cmd |= EnAnaPLL;
3845
3846 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
3847
3848 rtl8169_set_magic_reg(tp, tp->mac_version);
3849
3850 RTL_W32(tp, RxMissed, 0);
3851
3852 /* disable interrupt coalescing */
3853 RTL_W16(tp, IntrMitigate, 0x0000);
3854 }
3855
3856 static void rtl_hw_start(struct rtl8169_private *tp)
3857 {
3858 rtl_unlock_config_regs(tp);
3859
3860 tp->cp_cmd &= CPCMD_MASK;
3861 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
3862
3863 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3864 rtl_hw_start_8169(tp);
3865 else if (rtl_is_8125(tp))
3866 rtl_hw_start_8125(tp);
3867 else
3868 rtl_hw_start_8168(tp);
3869
3870 rtl_set_rx_max_size(tp);
3871 rtl_set_rx_tx_desc_registers(tp);
3872 rtl_lock_config_regs(tp);
3873
3874 rtl_jumbo_config(tp, tp->dev->mtu);
3875
3876 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3877 RTL_R16(tp, CPlusCmd);
3878 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
3879 rtl_init_rxcfg(tp);
3880 rtl_set_tx_config_registers(tp);
3881 rtl_set_rx_mode(tp->dev);
3882 rtl_irq_enable(tp);
3883 }
3884
3885 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
3886 {
3887 struct rtl8169_private *tp = netdev_priv(dev);
3888
3889 rtl_jumbo_config(tp, new_mtu);
3890
3891 dev->mtu = new_mtu;
3892 netdev_update_features(dev);
3893
3894 return 0;
3895 }
3896
3897 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
3898 {
3899 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
3900 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
3901 }
3902
3903 static inline void rtl8169_mark_to_asic(struct RxDesc *desc)
3904 {
3905 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
3906
3907 /* Force memory writes to complete before releasing descriptor */
3908 dma_wmb();
3909
3910 desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE);
3911 }
3912
3913 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
3914 struct RxDesc *desc)
3915 {
3916 struct device *d = tp_to_dev(tp);
3917 int node = dev_to_node(d);
3918 dma_addr_t mapping;
3919 struct page *data;
3920
3921 data = alloc_pages_node(node, GFP_KERNEL, get_order(R8169_RX_BUF_SIZE));
3922 if (!data)
3923 return NULL;
3924
3925 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
3926 if (unlikely(dma_mapping_error(d, mapping))) {
3927 if (net_ratelimit())
3928 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
3929 __free_pages(data, get_order(R8169_RX_BUF_SIZE));
3930 return NULL;
3931 }
3932
3933 desc->addr = cpu_to_le64(mapping);
3934 rtl8169_mark_to_asic(desc);
3935
3936 return data;
3937 }
3938
3939 static void rtl8169_rx_clear(struct rtl8169_private *tp)
3940 {
3941 unsigned int i;
3942
3943 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) {
3944 dma_unmap_page(tp_to_dev(tp),
3945 le64_to_cpu(tp->RxDescArray[i].addr),
3946 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
3947 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE));
3948 tp->Rx_databuff[i] = NULL;
3949 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
3950 }
3951 }
3952
3953 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
3954 {
3955 desc->opts1 |= cpu_to_le32(RingEnd);
3956 }
3957
3958 static int rtl8169_rx_fill(struct rtl8169_private *tp)
3959 {
3960 unsigned int i;
3961
3962 for (i = 0; i < NUM_RX_DESC; i++) {
3963 struct page *data;
3964
3965 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
3966 if (!data) {
3967 rtl8169_rx_clear(tp);
3968 return -ENOMEM;
3969 }
3970 tp->Rx_databuff[i] = data;
3971 }
3972
3973 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
3974
3975 return 0;
3976 }
3977
3978 static int rtl8169_init_ring(struct rtl8169_private *tp)
3979 {
3980 rtl8169_init_ring_indexes(tp);
3981
3982 memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
3983 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
3984
3985 return rtl8169_rx_fill(tp);
3986 }
3987
3988 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
3989 struct TxDesc *desc)
3990 {
3991 unsigned int len = tx_skb->len;
3992
3993 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
3994
3995 desc->opts1 = 0x00;
3996 desc->opts2 = 0x00;
3997 desc->addr = 0x00;
3998 tx_skb->len = 0;
3999 }
4000
4001 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4002 unsigned int n)
4003 {
4004 unsigned int i;
4005
4006 for (i = 0; i < n; i++) {
4007 unsigned int entry = (start + i) % NUM_TX_DESC;
4008 struct ring_info *tx_skb = tp->tx_skb + entry;
4009 unsigned int len = tx_skb->len;
4010
4011 if (len) {
4012 struct sk_buff *skb = tx_skb->skb;
4013
4014 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
4015 tp->TxDescArray + entry);
4016 if (skb) {
4017 dev_consume_skb_any(skb);
4018 tx_skb->skb = NULL;
4019 }
4020 }
4021 }
4022 }
4023
4024 static void rtl8169_tx_clear(struct rtl8169_private *tp)
4025 {
4026 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
4027 tp->cur_tx = tp->dirty_tx = 0;
4028 netdev_reset_queue(tp->dev);
4029 }
4030
4031 static void rtl_reset_work(struct rtl8169_private *tp)
4032 {
4033 struct net_device *dev = tp->dev;
4034 int i;
4035
4036 napi_disable(&tp->napi);
4037 netif_stop_queue(dev);
4038 synchronize_rcu();
4039
4040 rtl8169_hw_reset(tp);
4041
4042 for (i = 0; i < NUM_RX_DESC; i++)
4043 rtl8169_mark_to_asic(tp->RxDescArray + i);
4044
4045 rtl8169_tx_clear(tp);
4046 rtl8169_init_ring_indexes(tp);
4047
4048 napi_enable(&tp->napi);
4049 rtl_hw_start(tp);
4050 netif_wake_queue(dev);
4051 }
4052
4053 static void rtl8169_tx_timeout(struct net_device *dev, unsigned int txqueue)
4054 {
4055 struct rtl8169_private *tp = netdev_priv(dev);
4056
4057 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
4058 }
4059
4060 static __le32 rtl8169_get_txd_opts1(u32 opts0, u32 len, unsigned int entry)
4061 {
4062 u32 status = opts0 | len;
4063
4064 if (entry == NUM_TX_DESC - 1)
4065 status |= RingEnd;
4066
4067 return cpu_to_le32(status);
4068 }
4069
4070 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4071 u32 *opts)
4072 {
4073 struct skb_shared_info *info = skb_shinfo(skb);
4074 unsigned int cur_frag, entry;
4075 struct TxDesc *uninitialized_var(txd);
4076 struct device *d = tp_to_dev(tp);
4077
4078 entry = tp->cur_tx;
4079 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4080 const skb_frag_t *frag = info->frags + cur_frag;
4081 dma_addr_t mapping;
4082 u32 len;
4083 void *addr;
4084
4085 entry = (entry + 1) % NUM_TX_DESC;
4086
4087 txd = tp->TxDescArray + entry;
4088 len = skb_frag_size(frag);
4089 addr = skb_frag_address(frag);
4090 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
4091 if (unlikely(dma_mapping_error(d, mapping))) {
4092 if (net_ratelimit())
4093 netif_err(tp, drv, tp->dev,
4094 "Failed to map TX fragments DMA!\n");
4095 goto err_out;
4096 }
4097
4098 txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
4099 txd->opts2 = cpu_to_le32(opts[1]);
4100 txd->addr = cpu_to_le64(mapping);
4101
4102 tp->tx_skb[entry].len = len;
4103 }
4104
4105 if (cur_frag) {
4106 tp->tx_skb[entry].skb = skb;
4107 txd->opts1 |= cpu_to_le32(LastFrag);
4108 }
4109
4110 return cur_frag;
4111
4112 err_out:
4113 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4114 return -EIO;
4115 }
4116
4117 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
4118 {
4119 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
4120 }
4121
4122 /* msdn_giant_send_check()
4123 * According to the document of microsoft, the TCP Pseudo Header excludes the
4124 * packet length for IPv6 TCP large packets.
4125 */
4126 static int msdn_giant_send_check(struct sk_buff *skb)
4127 {
4128 const struct ipv6hdr *ipv6h;
4129 struct tcphdr *th;
4130 int ret;
4131
4132 ret = skb_cow_head(skb, 0);
4133 if (ret)
4134 return ret;
4135
4136 ipv6h = ipv6_hdr(skb);
4137 th = tcp_hdr(skb);
4138
4139 th->check = 0;
4140 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
4141
4142 return ret;
4143 }
4144
4145 static void rtl8169_tso_csum_v1(struct sk_buff *skb, u32 *opts)
4146 {
4147 u32 mss = skb_shinfo(skb)->gso_size;
4148
4149 if (mss) {
4150 opts[0] |= TD_LSO;
4151 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
4152 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4153 const struct iphdr *ip = ip_hdr(skb);
4154
4155 if (ip->protocol == IPPROTO_TCP)
4156 opts[0] |= TD0_IP_CS | TD0_TCP_CS;
4157 else if (ip->protocol == IPPROTO_UDP)
4158 opts[0] |= TD0_IP_CS | TD0_UDP_CS;
4159 else
4160 WARN_ON_ONCE(1);
4161 }
4162 }
4163
4164 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
4165 struct sk_buff *skb, u32 *opts)
4166 {
4167 u32 transport_offset = (u32)skb_transport_offset(skb);
4168 u32 mss = skb_shinfo(skb)->gso_size;
4169
4170 if (mss) {
4171 switch (vlan_get_protocol(skb)) {
4172 case htons(ETH_P_IP):
4173 opts[0] |= TD1_GTSENV4;
4174 break;
4175
4176 case htons(ETH_P_IPV6):
4177 if (msdn_giant_send_check(skb))
4178 return false;
4179
4180 opts[0] |= TD1_GTSENV6;
4181 break;
4182
4183 default:
4184 WARN_ON_ONCE(1);
4185 break;
4186 }
4187
4188 opts[0] |= transport_offset << GTTCPHO_SHIFT;
4189 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
4190 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4191 u8 ip_protocol;
4192
4193 switch (vlan_get_protocol(skb)) {
4194 case htons(ETH_P_IP):
4195 opts[1] |= TD1_IPv4_CS;
4196 ip_protocol = ip_hdr(skb)->protocol;
4197 break;
4198
4199 case htons(ETH_P_IPV6):
4200 opts[1] |= TD1_IPv6_CS;
4201 ip_protocol = ipv6_hdr(skb)->nexthdr;
4202 break;
4203
4204 default:
4205 ip_protocol = IPPROTO_RAW;
4206 break;
4207 }
4208
4209 if (ip_protocol == IPPROTO_TCP)
4210 opts[1] |= TD1_TCP_CS;
4211 else if (ip_protocol == IPPROTO_UDP)
4212 opts[1] |= TD1_UDP_CS;
4213 else
4214 WARN_ON_ONCE(1);
4215
4216 opts[1] |= transport_offset << TCPHO_SHIFT;
4217 } else {
4218 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
4219 return !eth_skb_pad(skb);
4220 }
4221
4222 return true;
4223 }
4224
4225 static bool rtl_tx_slots_avail(struct rtl8169_private *tp,
4226 unsigned int nr_frags)
4227 {
4228 unsigned int slots_avail = tp->dirty_tx + NUM_TX_DESC - tp->cur_tx;
4229
4230 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
4231 return slots_avail > nr_frags;
4232 }
4233
4234 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
4235 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
4236 {
4237 switch (tp->mac_version) {
4238 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
4239 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
4240 return false;
4241 default:
4242 return true;
4243 }
4244 }
4245
4246 static void rtl8169_doorbell(struct rtl8169_private *tp)
4247 {
4248 if (rtl_is_8125(tp))
4249 RTL_W16(tp, TxPoll_8125, BIT(0));
4250 else
4251 RTL_W8(tp, TxPoll, NPQ);
4252 }
4253
4254 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4255 struct net_device *dev)
4256 {
4257 struct rtl8169_private *tp = netdev_priv(dev);
4258 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
4259 struct TxDesc *txd = tp->TxDescArray + entry;
4260 struct device *d = tp_to_dev(tp);
4261 dma_addr_t mapping;
4262 u32 opts[2], len;
4263 bool stop_queue;
4264 bool door_bell;
4265 int frags;
4266
4267 if (unlikely(!rtl_tx_slots_avail(tp, skb_shinfo(skb)->nr_frags))) {
4268 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
4269 goto err_stop_0;
4270 }
4271
4272 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
4273 goto err_stop_0;
4274
4275 opts[1] = rtl8169_tx_vlan_tag(skb);
4276 opts[0] = DescOwn;
4277
4278 if (rtl_chip_supports_csum_v2(tp)) {
4279 if (!rtl8169_tso_csum_v2(tp, skb, opts))
4280 goto err_dma_0;
4281 } else {
4282 rtl8169_tso_csum_v1(skb, opts);
4283 }
4284
4285 len = skb_headlen(skb);
4286 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
4287 if (unlikely(dma_mapping_error(d, mapping))) {
4288 if (net_ratelimit())
4289 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
4290 goto err_dma_0;
4291 }
4292
4293 tp->tx_skb[entry].len = len;
4294 txd->addr = cpu_to_le64(mapping);
4295
4296 frags = rtl8169_xmit_frags(tp, skb, opts);
4297 if (frags < 0)
4298 goto err_dma_1;
4299 else if (frags)
4300 opts[0] |= FirstFrag;
4301 else {
4302 opts[0] |= FirstFrag | LastFrag;
4303 tp->tx_skb[entry].skb = skb;
4304 }
4305
4306 txd->opts2 = cpu_to_le32(opts[1]);
4307
4308 skb_tx_timestamp(skb);
4309
4310 /* Force memory writes to complete before releasing descriptor */
4311 dma_wmb();
4312
4313 door_bell = __netdev_sent_queue(dev, skb->len, netdev_xmit_more());
4314
4315 txd->opts1 = rtl8169_get_txd_opts1(opts[0], len, entry);
4316
4317 /* Force all memory writes to complete before notifying device */
4318 wmb();
4319
4320 tp->cur_tx += frags + 1;
4321
4322 stop_queue = !rtl_tx_slots_avail(tp, MAX_SKB_FRAGS);
4323 if (unlikely(stop_queue)) {
4324 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
4325 * not miss a ring update when it notices a stopped queue.
4326 */
4327 smp_wmb();
4328 netif_stop_queue(dev);
4329 door_bell = true;
4330 }
4331
4332 if (door_bell)
4333 rtl8169_doorbell(tp);
4334
4335 if (unlikely(stop_queue)) {
4336 /* Sync with rtl_tx:
4337 * - publish queue status and cur_tx ring index (write barrier)
4338 * - refresh dirty_tx ring index (read barrier).
4339 * May the current thread have a pessimistic view of the ring
4340 * status and forget to wake up queue, a racing rtl_tx thread
4341 * can't.
4342 */
4343 smp_mb();
4344 if (rtl_tx_slots_avail(tp, MAX_SKB_FRAGS))
4345 netif_start_queue(dev);
4346 }
4347
4348 return NETDEV_TX_OK;
4349
4350 err_dma_1:
4351 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
4352 err_dma_0:
4353 dev_kfree_skb_any(skb);
4354 dev->stats.tx_dropped++;
4355 return NETDEV_TX_OK;
4356
4357 err_stop_0:
4358 netif_stop_queue(dev);
4359 dev->stats.tx_dropped++;
4360 return NETDEV_TX_BUSY;
4361 }
4362
4363 static netdev_features_t rtl8169_features_check(struct sk_buff *skb,
4364 struct net_device *dev,
4365 netdev_features_t features)
4366 {
4367 int transport_offset = skb_transport_offset(skb);
4368 struct rtl8169_private *tp = netdev_priv(dev);
4369
4370 if (skb_is_gso(skb)) {
4371 if (transport_offset > GTTCPHO_MAX &&
4372 rtl_chip_supports_csum_v2(tp))
4373 features &= ~NETIF_F_ALL_TSO;
4374 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4375 if (skb->len < ETH_ZLEN) {
4376 switch (tp->mac_version) {
4377 case RTL_GIGA_MAC_VER_11:
4378 case RTL_GIGA_MAC_VER_12:
4379 case RTL_GIGA_MAC_VER_17:
4380 case RTL_GIGA_MAC_VER_34:
4381 features &= ~NETIF_F_CSUM_MASK;
4382 break;
4383 default:
4384 break;
4385 }
4386 }
4387
4388 if (transport_offset > TCPHO_MAX &&
4389 rtl_chip_supports_csum_v2(tp))
4390 features &= ~NETIF_F_CSUM_MASK;
4391 }
4392
4393 return vlan_features_check(skb, features);
4394 }
4395
4396 static void rtl8169_pcierr_interrupt(struct net_device *dev)
4397 {
4398 struct rtl8169_private *tp = netdev_priv(dev);
4399 struct pci_dev *pdev = tp->pci_dev;
4400 u16 pci_status, pci_cmd;
4401
4402 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4403 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
4404
4405 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
4406 pci_cmd, pci_status);
4407
4408 /*
4409 * The recovery sequence below admits a very elaborated explanation:
4410 * - it seems to work;
4411 * - I did not see what else could be done;
4412 * - it makes iop3xx happy.
4413 *
4414 * Feel free to adjust to your needs.
4415 */
4416 if (pdev->broken_parity_status)
4417 pci_cmd &= ~PCI_COMMAND_PARITY;
4418 else
4419 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
4420
4421 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
4422
4423 pci_write_config_word(pdev, PCI_STATUS,
4424 pci_status & (PCI_STATUS_DETECTED_PARITY |
4425 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
4426 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
4427
4428 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
4429 }
4430
4431 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp,
4432 int budget)
4433 {
4434 unsigned int dirty_tx, tx_left, bytes_compl = 0, pkts_compl = 0;
4435
4436 dirty_tx = tp->dirty_tx;
4437 smp_rmb();
4438 tx_left = tp->cur_tx - dirty_tx;
4439
4440 while (tx_left > 0) {
4441 unsigned int entry = dirty_tx % NUM_TX_DESC;
4442 struct ring_info *tx_skb = tp->tx_skb + entry;
4443 u32 status;
4444
4445 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4446 if (status & DescOwn)
4447 break;
4448
4449 /* This barrier is needed to keep us from reading
4450 * any other fields out of the Tx descriptor until
4451 * we know the status of DescOwn
4452 */
4453 dma_rmb();
4454
4455 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
4456 tp->TxDescArray + entry);
4457 if (tx_skb->skb) {
4458 pkts_compl++;
4459 bytes_compl += tx_skb->skb->len;
4460 napi_consume_skb(tx_skb->skb, budget);
4461 tx_skb->skb = NULL;
4462 }
4463 dirty_tx++;
4464 tx_left--;
4465 }
4466
4467 if (tp->dirty_tx != dirty_tx) {
4468 netdev_completed_queue(dev, pkts_compl, bytes_compl);
4469
4470 u64_stats_update_begin(&tp->tx_stats.syncp);
4471 tp->tx_stats.packets += pkts_compl;
4472 tp->tx_stats.bytes += bytes_compl;
4473 u64_stats_update_end(&tp->tx_stats.syncp);
4474
4475 tp->dirty_tx = dirty_tx;
4476 /* Sync with rtl8169_start_xmit:
4477 * - publish dirty_tx ring index (write barrier)
4478 * - refresh cur_tx ring index and queue status (read barrier)
4479 * May the current thread miss the stopped queue condition,
4480 * a racing xmit thread can only have a right view of the
4481 * ring status.
4482 */
4483 smp_mb();
4484 if (netif_queue_stopped(dev) &&
4485 rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) {
4486 netif_wake_queue(dev);
4487 }
4488 /*
4489 * 8168 hack: TxPoll requests are lost when the Tx packets are
4490 * too close. Let's kick an extra TxPoll request when a burst
4491 * of start_xmit activity is detected (if it is not detected,
4492 * it is slow enough). -- FR
4493 */
4494 if (tp->cur_tx != dirty_tx)
4495 rtl8169_doorbell(tp);
4496 }
4497 }
4498
4499 static inline int rtl8169_fragmented_frame(u32 status)
4500 {
4501 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4502 }
4503
4504 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
4505 {
4506 u32 status = opts1 & RxProtoMask;
4507
4508 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
4509 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
4510 skb->ip_summed = CHECKSUM_UNNECESSARY;
4511 else
4512 skb_checksum_none_assert(skb);
4513 }
4514
4515 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
4516 {
4517 unsigned int cur_rx, rx_left;
4518 unsigned int count;
4519
4520 cur_rx = tp->cur_rx;
4521
4522 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
4523 unsigned int entry = cur_rx % NUM_RX_DESC;
4524 const void *rx_buf = page_address(tp->Rx_databuff[entry]);
4525 struct RxDesc *desc = tp->RxDescArray + entry;
4526 u32 status;
4527
4528 status = le32_to_cpu(desc->opts1);
4529 if (status & DescOwn)
4530 break;
4531
4532 /* This barrier is needed to keep us from reading
4533 * any other fields out of the Rx descriptor until
4534 * we know the status of DescOwn
4535 */
4536 dma_rmb();
4537
4538 if (unlikely(status & RxRES)) {
4539 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
4540 status);
4541 dev->stats.rx_errors++;
4542 if (status & (RxRWT | RxRUNT))
4543 dev->stats.rx_length_errors++;
4544 if (status & RxCRC)
4545 dev->stats.rx_crc_errors++;
4546 if (status & (RxRUNT | RxCRC) && !(status & RxRWT) &&
4547 dev->features & NETIF_F_RXALL) {
4548 goto process_pkt;
4549 }
4550 } else {
4551 unsigned int pkt_size;
4552 struct sk_buff *skb;
4553
4554 process_pkt:
4555 pkt_size = status & GENMASK(13, 0);
4556 if (likely(!(dev->features & NETIF_F_RXFCS)))
4557 pkt_size -= ETH_FCS_LEN;
4558 /*
4559 * The driver does not support incoming fragmented
4560 * frames. They are seen as a symptom of over-mtu
4561 * sized frames.
4562 */
4563 if (unlikely(rtl8169_fragmented_frame(status))) {
4564 dev->stats.rx_dropped++;
4565 dev->stats.rx_length_errors++;
4566 goto release_descriptor;
4567 }
4568
4569 skb = napi_alloc_skb(&tp->napi, pkt_size);
4570 if (unlikely(!skb)) {
4571 dev->stats.rx_dropped++;
4572 goto release_descriptor;
4573 }
4574
4575 dma_sync_single_for_cpu(tp_to_dev(tp),
4576 le64_to_cpu(desc->addr),
4577 pkt_size, DMA_FROM_DEVICE);
4578 prefetch(rx_buf);
4579 skb_copy_to_linear_data(skb, rx_buf, pkt_size);
4580 skb->tail += pkt_size;
4581 skb->len = pkt_size;
4582
4583 dma_sync_single_for_device(tp_to_dev(tp),
4584 le64_to_cpu(desc->addr),
4585 pkt_size, DMA_FROM_DEVICE);
4586
4587 rtl8169_rx_csum(skb, status);
4588 skb->protocol = eth_type_trans(skb, dev);
4589
4590 rtl8169_rx_vlan_tag(desc, skb);
4591
4592 if (skb->pkt_type == PACKET_MULTICAST)
4593 dev->stats.multicast++;
4594
4595 napi_gro_receive(&tp->napi, skb);
4596
4597 u64_stats_update_begin(&tp->rx_stats.syncp);
4598 tp->rx_stats.packets++;
4599 tp->rx_stats.bytes += pkt_size;
4600 u64_stats_update_end(&tp->rx_stats.syncp);
4601 }
4602 release_descriptor:
4603 desc->opts2 = 0;
4604 rtl8169_mark_to_asic(desc);
4605 }
4606
4607 count = cur_rx - tp->cur_rx;
4608 tp->cur_rx = cur_rx;
4609
4610 return count;
4611 }
4612
4613 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
4614 {
4615 struct rtl8169_private *tp = dev_instance;
4616 u32 status = rtl_get_events(tp);
4617
4618 if (!tp->irq_enabled || (status & 0xffff) == 0xffff ||
4619 !(status & tp->irq_mask))
4620 return IRQ_NONE;
4621
4622 if (unlikely(status & SYSErr)) {
4623 rtl8169_pcierr_interrupt(tp->dev);
4624 goto out;
4625 }
4626
4627 if (status & LinkChg)
4628 phy_mac_interrupt(tp->phydev);
4629
4630 if (unlikely(status & RxFIFOOver &&
4631 tp->mac_version == RTL_GIGA_MAC_VER_11)) {
4632 netif_stop_queue(tp->dev);
4633 /* XXX - Hack alert. See rtl_task(). */
4634 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
4635 }
4636
4637 rtl_irq_disable(tp);
4638 napi_schedule_irqoff(&tp->napi);
4639 out:
4640 rtl_ack_events(tp, status);
4641
4642 return IRQ_HANDLED;
4643 }
4644
4645 static void rtl_task(struct work_struct *work)
4646 {
4647 static const struct {
4648 int bitnr;
4649 void (*action)(struct rtl8169_private *);
4650 } rtl_work[] = {
4651 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
4652 };
4653 struct rtl8169_private *tp =
4654 container_of(work, struct rtl8169_private, wk.work);
4655 struct net_device *dev = tp->dev;
4656 int i;
4657
4658 rtl_lock_work(tp);
4659
4660 if (!netif_running(dev) ||
4661 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
4662 goto out_unlock;
4663
4664 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
4665 bool pending;
4666
4667 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
4668 if (pending)
4669 rtl_work[i].action(tp);
4670 }
4671
4672 out_unlock:
4673 rtl_unlock_work(tp);
4674 }
4675
4676 static int rtl8169_poll(struct napi_struct *napi, int budget)
4677 {
4678 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
4679 struct net_device *dev = tp->dev;
4680 int work_done;
4681
4682 work_done = rtl_rx(dev, tp, (u32) budget);
4683
4684 rtl_tx(dev, tp, budget);
4685
4686 if (work_done < budget) {
4687 napi_complete_done(napi, work_done);
4688 rtl_irq_enable(tp);
4689 }
4690
4691 return work_done;
4692 }
4693
4694 static void rtl8169_rx_missed(struct net_device *dev)
4695 {
4696 struct rtl8169_private *tp = netdev_priv(dev);
4697
4698 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
4699 return;
4700
4701 dev->stats.rx_missed_errors += RTL_R32(tp, RxMissed) & 0xffffff;
4702 RTL_W32(tp, RxMissed, 0);
4703 }
4704
4705 static void r8169_phylink_handler(struct net_device *ndev)
4706 {
4707 struct rtl8169_private *tp = netdev_priv(ndev);
4708
4709 if (netif_carrier_ok(ndev)) {
4710 rtl_link_chg_patch(tp);
4711 pm_request_resume(&tp->pci_dev->dev);
4712 } else {
4713 pm_runtime_idle(&tp->pci_dev->dev);
4714 }
4715
4716 if (net_ratelimit())
4717 phy_print_status(tp->phydev);
4718 }
4719
4720 static int r8169_phy_connect(struct rtl8169_private *tp)
4721 {
4722 struct phy_device *phydev = tp->phydev;
4723 phy_interface_t phy_mode;
4724 int ret;
4725
4726 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
4727 PHY_INTERFACE_MODE_MII;
4728
4729 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
4730 phy_mode);
4731 if (ret)
4732 return ret;
4733
4734 if (!tp->supports_gmii)
4735 phy_set_max_speed(phydev, SPEED_100);
4736
4737 phy_support_asym_pause(phydev);
4738
4739 phy_attached_info(phydev);
4740
4741 return 0;
4742 }
4743
4744 static void rtl8169_down(struct net_device *dev)
4745 {
4746 struct rtl8169_private *tp = netdev_priv(dev);
4747
4748 phy_stop(tp->phydev);
4749
4750 napi_disable(&tp->napi);
4751 netif_stop_queue(dev);
4752
4753 rtl8169_hw_reset(tp);
4754 /*
4755 * At this point device interrupts can not be enabled in any function,
4756 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
4757 * and napi is disabled (rtl8169_poll).
4758 */
4759 rtl8169_rx_missed(dev);
4760
4761 /* Give a racing hard_start_xmit a few cycles to complete. */
4762 synchronize_rcu();
4763
4764 rtl8169_tx_clear(tp);
4765
4766 rtl8169_rx_clear(tp);
4767
4768 rtl_pll_power_down(tp);
4769 }
4770
4771 static int rtl8169_close(struct net_device *dev)
4772 {
4773 struct rtl8169_private *tp = netdev_priv(dev);
4774 struct pci_dev *pdev = tp->pci_dev;
4775
4776 pm_runtime_get_sync(&pdev->dev);
4777
4778 /* Update counters before going down */
4779 rtl8169_update_counters(tp);
4780
4781 rtl_lock_work(tp);
4782 /* Clear all task flags */
4783 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
4784
4785 rtl8169_down(dev);
4786 rtl_unlock_work(tp);
4787
4788 cancel_work_sync(&tp->wk.work);
4789
4790 phy_disconnect(tp->phydev);
4791
4792 pci_free_irq(pdev, 0, tp);
4793
4794 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4795 tp->RxPhyAddr);
4796 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4797 tp->TxPhyAddr);
4798 tp->TxDescArray = NULL;
4799 tp->RxDescArray = NULL;
4800
4801 pm_runtime_put_sync(&pdev->dev);
4802
4803 return 0;
4804 }
4805
4806 #ifdef CONFIG_NET_POLL_CONTROLLER
4807 static void rtl8169_netpoll(struct net_device *dev)
4808 {
4809 struct rtl8169_private *tp = netdev_priv(dev);
4810
4811 rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
4812 }
4813 #endif
4814
4815 static int rtl_open(struct net_device *dev)
4816 {
4817 struct rtl8169_private *tp = netdev_priv(dev);
4818 struct pci_dev *pdev = tp->pci_dev;
4819 int retval = -ENOMEM;
4820
4821 pm_runtime_get_sync(&pdev->dev);
4822
4823 /*
4824 * Rx and Tx descriptors needs 256 bytes alignment.
4825 * dma_alloc_coherent provides more.
4826 */
4827 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
4828 &tp->TxPhyAddr, GFP_KERNEL);
4829 if (!tp->TxDescArray)
4830 goto err_pm_runtime_put;
4831
4832 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
4833 &tp->RxPhyAddr, GFP_KERNEL);
4834 if (!tp->RxDescArray)
4835 goto err_free_tx_0;
4836
4837 retval = rtl8169_init_ring(tp);
4838 if (retval < 0)
4839 goto err_free_rx_1;
4840
4841 rtl_request_firmware(tp);
4842
4843 retval = pci_request_irq(pdev, 0, rtl8169_interrupt, NULL, tp,
4844 dev->name);
4845 if (retval < 0)
4846 goto err_release_fw_2;
4847
4848 retval = r8169_phy_connect(tp);
4849 if (retval)
4850 goto err_free_irq;
4851
4852 rtl_lock_work(tp);
4853
4854 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
4855
4856 napi_enable(&tp->napi);
4857
4858 rtl8169_init_phy(tp);
4859
4860 rtl_pll_power_up(tp);
4861
4862 rtl_hw_start(tp);
4863
4864 if (!rtl8169_init_counter_offsets(tp))
4865 netif_warn(tp, hw, dev, "counter reset/update failed\n");
4866
4867 phy_start(tp->phydev);
4868 netif_start_queue(dev);
4869
4870 rtl_unlock_work(tp);
4871
4872 pm_runtime_put_sync(&pdev->dev);
4873 out:
4874 return retval;
4875
4876 err_free_irq:
4877 pci_free_irq(pdev, 0, tp);
4878 err_release_fw_2:
4879 rtl_release_firmware(tp);
4880 rtl8169_rx_clear(tp);
4881 err_free_rx_1:
4882 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4883 tp->RxPhyAddr);
4884 tp->RxDescArray = NULL;
4885 err_free_tx_0:
4886 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4887 tp->TxPhyAddr);
4888 tp->TxDescArray = NULL;
4889 err_pm_runtime_put:
4890 pm_runtime_put_noidle(&pdev->dev);
4891 goto out;
4892 }
4893
4894 static void
4895 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
4896 {
4897 struct rtl8169_private *tp = netdev_priv(dev);
4898 struct pci_dev *pdev = tp->pci_dev;
4899 struct rtl8169_counters *counters = tp->counters;
4900 unsigned int start;
4901
4902 pm_runtime_get_noresume(&pdev->dev);
4903
4904 if (netif_running(dev) && pm_runtime_active(&pdev->dev))
4905 rtl8169_rx_missed(dev);
4906
4907 do {
4908 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
4909 stats->rx_packets = tp->rx_stats.packets;
4910 stats->rx_bytes = tp->rx_stats.bytes;
4911 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
4912
4913 do {
4914 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
4915 stats->tx_packets = tp->tx_stats.packets;
4916 stats->tx_bytes = tp->tx_stats.bytes;
4917 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
4918
4919 stats->rx_dropped = dev->stats.rx_dropped;
4920 stats->tx_dropped = dev->stats.tx_dropped;
4921 stats->rx_length_errors = dev->stats.rx_length_errors;
4922 stats->rx_errors = dev->stats.rx_errors;
4923 stats->rx_crc_errors = dev->stats.rx_crc_errors;
4924 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
4925 stats->rx_missed_errors = dev->stats.rx_missed_errors;
4926 stats->multicast = dev->stats.multicast;
4927
4928 /*
4929 * Fetch additional counter values missing in stats collected by driver
4930 * from tally counters.
4931 */
4932 if (pm_runtime_active(&pdev->dev))
4933 rtl8169_update_counters(tp);
4934
4935 /*
4936 * Subtract values fetched during initalization.
4937 * See rtl8169_init_counter_offsets for a description why we do that.
4938 */
4939 stats->tx_errors = le64_to_cpu(counters->tx_errors) -
4940 le64_to_cpu(tp->tc_offset.tx_errors);
4941 stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
4942 le32_to_cpu(tp->tc_offset.tx_multi_collision);
4943 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
4944 le16_to_cpu(tp->tc_offset.tx_aborted);
4945
4946 pm_runtime_put_noidle(&pdev->dev);
4947 }
4948
4949 static void rtl8169_net_suspend(struct net_device *dev)
4950 {
4951 struct rtl8169_private *tp = netdev_priv(dev);
4952
4953 if (!netif_running(dev))
4954 return;
4955
4956 phy_stop(tp->phydev);
4957 netif_device_detach(dev);
4958
4959 rtl_lock_work(tp);
4960 napi_disable(&tp->napi);
4961 /* Clear all task flags */
4962 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
4963
4964 rtl_unlock_work(tp);
4965
4966 rtl_pll_power_down(tp);
4967 }
4968
4969 #ifdef CONFIG_PM
4970
4971 static int rtl8169_suspend(struct device *device)
4972 {
4973 struct net_device *dev = dev_get_drvdata(device);
4974 struct rtl8169_private *tp = netdev_priv(dev);
4975
4976 rtl8169_net_suspend(dev);
4977 clk_disable_unprepare(tp->clk);
4978
4979 return 0;
4980 }
4981
4982 static void __rtl8169_resume(struct net_device *dev)
4983 {
4984 struct rtl8169_private *tp = netdev_priv(dev);
4985
4986 netif_device_attach(dev);
4987
4988 rtl_pll_power_up(tp);
4989 rtl8169_init_phy(tp);
4990
4991 phy_start(tp->phydev);
4992
4993 rtl_lock_work(tp);
4994 napi_enable(&tp->napi);
4995 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
4996 rtl_reset_work(tp);
4997 rtl_unlock_work(tp);
4998 }
4999
5000 static int rtl8169_resume(struct device *device)
5001 {
5002 struct net_device *dev = dev_get_drvdata(device);
5003 struct rtl8169_private *tp = netdev_priv(dev);
5004
5005 rtl_rar_set(tp, dev->dev_addr);
5006
5007 clk_prepare_enable(tp->clk);
5008
5009 if (netif_running(dev))
5010 __rtl8169_resume(dev);
5011
5012 return 0;
5013 }
5014
5015 static int rtl8169_runtime_suspend(struct device *device)
5016 {
5017 struct net_device *dev = dev_get_drvdata(device);
5018 struct rtl8169_private *tp = netdev_priv(dev);
5019
5020 if (!tp->TxDescArray)
5021 return 0;
5022
5023 rtl_lock_work(tp);
5024 __rtl8169_set_wol(tp, WAKE_ANY);
5025 rtl_unlock_work(tp);
5026
5027 rtl8169_net_suspend(dev);
5028
5029 /* Update counters before going runtime suspend */
5030 rtl8169_rx_missed(dev);
5031 rtl8169_update_counters(tp);
5032
5033 return 0;
5034 }
5035
5036 static int rtl8169_runtime_resume(struct device *device)
5037 {
5038 struct net_device *dev = dev_get_drvdata(device);
5039 struct rtl8169_private *tp = netdev_priv(dev);
5040
5041 rtl_rar_set(tp, dev->dev_addr);
5042
5043 if (!tp->TxDescArray)
5044 return 0;
5045
5046 rtl_lock_work(tp);
5047 __rtl8169_set_wol(tp, tp->saved_wolopts);
5048 rtl_unlock_work(tp);
5049
5050 __rtl8169_resume(dev);
5051
5052 return 0;
5053 }
5054
5055 static int rtl8169_runtime_idle(struct device *device)
5056 {
5057 struct net_device *dev = dev_get_drvdata(device);
5058
5059 if (!netif_running(dev) || !netif_carrier_ok(dev))
5060 pm_schedule_suspend(device, 10000);
5061
5062 return -EBUSY;
5063 }
5064
5065 static const struct dev_pm_ops rtl8169_pm_ops = {
5066 .suspend = rtl8169_suspend,
5067 .resume = rtl8169_resume,
5068 .freeze = rtl8169_suspend,
5069 .thaw = rtl8169_resume,
5070 .poweroff = rtl8169_suspend,
5071 .restore = rtl8169_resume,
5072 .runtime_suspend = rtl8169_runtime_suspend,
5073 .runtime_resume = rtl8169_runtime_resume,
5074 .runtime_idle = rtl8169_runtime_idle,
5075 };
5076
5077 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
5078
5079 #else /* !CONFIG_PM */
5080
5081 #define RTL8169_PM_OPS NULL
5082
5083 #endif /* !CONFIG_PM */
5084
5085 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
5086 {
5087 /* WoL fails with 8168b when the receiver is disabled. */
5088 switch (tp->mac_version) {
5089 case RTL_GIGA_MAC_VER_11:
5090 case RTL_GIGA_MAC_VER_12:
5091 case RTL_GIGA_MAC_VER_17:
5092 pci_clear_master(tp->pci_dev);
5093
5094 RTL_W8(tp, ChipCmd, CmdRxEnb);
5095 /* PCI commit */
5096 RTL_R8(tp, ChipCmd);
5097 break;
5098 default:
5099 break;
5100 }
5101 }
5102
5103 static void rtl_shutdown(struct pci_dev *pdev)
5104 {
5105 struct net_device *dev = pci_get_drvdata(pdev);
5106 struct rtl8169_private *tp = netdev_priv(dev);
5107
5108 rtl8169_net_suspend(dev);
5109
5110 /* Restore original MAC address */
5111 rtl_rar_set(tp, dev->perm_addr);
5112
5113 rtl8169_hw_reset(tp);
5114
5115 if (system_state == SYSTEM_POWER_OFF) {
5116 if (tp->saved_wolopts) {
5117 rtl_wol_suspend_quirk(tp);
5118 rtl_wol_shutdown_quirk(tp);
5119 }
5120
5121 pci_wake_from_d3(pdev, true);
5122 pci_set_power_state(pdev, PCI_D3hot);
5123 }
5124 }
5125
5126 static void rtl_remove_one(struct pci_dev *pdev)
5127 {
5128 struct net_device *dev = pci_get_drvdata(pdev);
5129 struct rtl8169_private *tp = netdev_priv(dev);
5130
5131 if (r8168_check_dash(tp))
5132 rtl8168_driver_stop(tp);
5133
5134 netif_napi_del(&tp->napi);
5135
5136 unregister_netdev(dev);
5137 mdiobus_unregister(tp->phydev->mdio.bus);
5138
5139 rtl_release_firmware(tp);
5140
5141 if (pci_dev_run_wake(pdev))
5142 pm_runtime_get_noresume(&pdev->dev);
5143
5144 /* restore original MAC address */
5145 rtl_rar_set(tp, dev->perm_addr);
5146 }
5147
5148 static const struct net_device_ops rtl_netdev_ops = {
5149 .ndo_open = rtl_open,
5150 .ndo_stop = rtl8169_close,
5151 .ndo_get_stats64 = rtl8169_get_stats64,
5152 .ndo_start_xmit = rtl8169_start_xmit,
5153 .ndo_features_check = rtl8169_features_check,
5154 .ndo_tx_timeout = rtl8169_tx_timeout,
5155 .ndo_validate_addr = eth_validate_addr,
5156 .ndo_change_mtu = rtl8169_change_mtu,
5157 .ndo_fix_features = rtl8169_fix_features,
5158 .ndo_set_features = rtl8169_set_features,
5159 .ndo_set_mac_address = rtl_set_mac_address,
5160 .ndo_do_ioctl = phy_do_ioctl_running,
5161 .ndo_set_rx_mode = rtl_set_rx_mode,
5162 #ifdef CONFIG_NET_POLL_CONTROLLER
5163 .ndo_poll_controller = rtl8169_netpoll,
5164 #endif
5165
5166 };
5167
5168 static void rtl_set_irq_mask(struct rtl8169_private *tp)
5169 {
5170 tp->irq_mask = RTL_EVENT_NAPI | LinkChg;
5171
5172 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
5173 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver;
5174 else if (tp->mac_version == RTL_GIGA_MAC_VER_11)
5175 /* special workaround needed */
5176 tp->irq_mask |= RxFIFOOver;
5177 else
5178 tp->irq_mask |= RxOverflow;
5179 }
5180
5181 static int rtl_alloc_irq(struct rtl8169_private *tp)
5182 {
5183 unsigned int flags;
5184
5185 switch (tp->mac_version) {
5186 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
5187 rtl_unlock_config_regs(tp);
5188 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
5189 rtl_lock_config_regs(tp);
5190 /* fall through */
5191 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_24:
5192 flags = PCI_IRQ_LEGACY;
5193 break;
5194 default:
5195 flags = PCI_IRQ_ALL_TYPES;
5196 break;
5197 }
5198
5199 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
5200 }
5201
5202 static void rtl_read_mac_address(struct rtl8169_private *tp,
5203 u8 mac_addr[ETH_ALEN])
5204 {
5205 /* Get MAC address */
5206 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) {
5207 u32 value = rtl_eri_read(tp, 0xe0);
5208
5209 mac_addr[0] = (value >> 0) & 0xff;
5210 mac_addr[1] = (value >> 8) & 0xff;
5211 mac_addr[2] = (value >> 16) & 0xff;
5212 mac_addr[3] = (value >> 24) & 0xff;
5213
5214 value = rtl_eri_read(tp, 0xe4);
5215 mac_addr[4] = (value >> 0) & 0xff;
5216 mac_addr[5] = (value >> 8) & 0xff;
5217 } else if (rtl_is_8125(tp)) {
5218 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP);
5219 }
5220 }
5221
5222 DECLARE_RTL_COND(rtl_link_list_ready_cond)
5223 {
5224 return RTL_R8(tp, MCU) & LINK_LIST_RDY;
5225 }
5226
5227 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
5228 {
5229 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
5230 }
5231
5232 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
5233 {
5234 struct rtl8169_private *tp = mii_bus->priv;
5235
5236 if (phyaddr > 0)
5237 return -ENODEV;
5238
5239 return rtl_readphy(tp, phyreg);
5240 }
5241
5242 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
5243 int phyreg, u16 val)
5244 {
5245 struct rtl8169_private *tp = mii_bus->priv;
5246
5247 if (phyaddr > 0)
5248 return -ENODEV;
5249
5250 rtl_writephy(tp, phyreg, val);
5251
5252 return 0;
5253 }
5254
5255 static int r8169_mdio_register(struct rtl8169_private *tp)
5256 {
5257 struct pci_dev *pdev = tp->pci_dev;
5258 struct mii_bus *new_bus;
5259 int ret;
5260
5261 new_bus = devm_mdiobus_alloc(&pdev->dev);
5262 if (!new_bus)
5263 return -ENOMEM;
5264
5265 new_bus->name = "r8169";
5266 new_bus->priv = tp;
5267 new_bus->parent = &pdev->dev;
5268 new_bus->irq[0] = PHY_IGNORE_INTERRUPT;
5269 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x", pci_dev_id(pdev));
5270
5271 new_bus->read = r8169_mdio_read_reg;
5272 new_bus->write = r8169_mdio_write_reg;
5273
5274 ret = mdiobus_register(new_bus);
5275 if (ret)
5276 return ret;
5277
5278 tp->phydev = mdiobus_get_phy(new_bus, 0);
5279 if (!tp->phydev) {
5280 mdiobus_unregister(new_bus);
5281 return -ENODEV;
5282 }
5283
5284 /* PHY will be woken up in rtl_open() */
5285 phy_suspend(tp->phydev);
5286
5287 return 0;
5288 }
5289
5290 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
5291 {
5292 tp->ocp_base = OCP_STD_PHY_BASE;
5293
5294 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
5295
5296 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
5297 return;
5298
5299 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
5300 return;
5301
5302 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
5303 msleep(1);
5304 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5305
5306 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
5307
5308 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
5309 return;
5310
5311 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15));
5312
5313 rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);
5314 }
5315
5316 static void rtl_hw_init_8125(struct rtl8169_private *tp)
5317 {
5318 tp->ocp_base = OCP_STD_PHY_BASE;
5319
5320 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
5321
5322 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
5323 return;
5324
5325 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
5326 msleep(1);
5327 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5328
5329 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
5330
5331 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
5332 return;
5333
5334 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0);
5335 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150);
5336 r8168_mac_ocp_write(tp, 0xc01e, 0x5555);
5337
5338 rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);
5339 }
5340
5341 static void rtl_hw_initialize(struct rtl8169_private *tp)
5342 {
5343 switch (tp->mac_version) {
5344 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_52:
5345 rtl8168ep_stop_cmac(tp);
5346 /* fall through */
5347 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
5348 rtl_hw_init_8168g(tp);
5349 break;
5350 case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_61:
5351 rtl_hw_init_8125(tp);
5352 break;
5353 default:
5354 break;
5355 }
5356 }
5357
5358 static int rtl_jumbo_max(struct rtl8169_private *tp)
5359 {
5360 /* Non-GBit versions don't support jumbo frames */
5361 if (!tp->supports_gmii)
5362 return 0;
5363
5364 switch (tp->mac_version) {
5365 /* RTL8169 */
5366 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
5367 return JUMBO_7K;
5368 /* RTL8168b */
5369 case RTL_GIGA_MAC_VER_11:
5370 case RTL_GIGA_MAC_VER_12:
5371 case RTL_GIGA_MAC_VER_17:
5372 return JUMBO_4K;
5373 /* RTL8168c */
5374 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
5375 return JUMBO_6K;
5376 default:
5377 return JUMBO_9K;
5378 }
5379 }
5380
5381 static void rtl_disable_clk(void *data)
5382 {
5383 clk_disable_unprepare(data);
5384 }
5385
5386 static int rtl_get_ether_clk(struct rtl8169_private *tp)
5387 {
5388 struct device *d = tp_to_dev(tp);
5389 struct clk *clk;
5390 int rc;
5391
5392 clk = devm_clk_get(d, "ether_clk");
5393 if (IS_ERR(clk)) {
5394 rc = PTR_ERR(clk);
5395 if (rc == -ENOENT)
5396 /* clk-core allows NULL (for suspend / resume) */
5397 rc = 0;
5398 else if (rc != -EPROBE_DEFER)
5399 dev_err(d, "failed to get clk: %d\n", rc);
5400 } else {
5401 tp->clk = clk;
5402 rc = clk_prepare_enable(clk);
5403 if (rc)
5404 dev_err(d, "failed to enable clk: %d\n", rc);
5405 else
5406 rc = devm_add_action_or_reset(d, rtl_disable_clk, clk);
5407 }
5408
5409 return rc;
5410 }
5411
5412 static void rtl_init_mac_address(struct rtl8169_private *tp)
5413 {
5414 struct net_device *dev = tp->dev;
5415 u8 *mac_addr = dev->dev_addr;
5416 int rc;
5417
5418 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr);
5419 if (!rc)
5420 goto done;
5421
5422 rtl_read_mac_address(tp, mac_addr);
5423 if (is_valid_ether_addr(mac_addr))
5424 goto done;
5425
5426 rtl_read_mac_from_reg(tp, mac_addr, MAC0);
5427 if (is_valid_ether_addr(mac_addr))
5428 goto done;
5429
5430 eth_hw_addr_random(dev);
5431 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n");
5432 done:
5433 rtl_rar_set(tp, mac_addr);
5434 }
5435
5436 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
5437 {
5438 struct rtl8169_private *tp;
5439 struct net_device *dev;
5440 int chipset, region;
5441 int jumbo_max, rc;
5442
5443 /* Some tools for creating an initramfs don't consider softdeps, then
5444 * r8169.ko may be in initramfs, but realtek.ko not. Then the generic
5445 * PHY driver is used that doesn't work with most chip versions.
5446 */
5447 if (!driver_find("RTL8201CP Ethernet", &mdio_bus_type)) {
5448 dev_err(&pdev->dev, "realtek.ko not loaded, maybe it needs to be added to initramfs?\n");
5449 return -ENOENT;
5450 }
5451
5452 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
5453 if (!dev)
5454 return -ENOMEM;
5455
5456 SET_NETDEV_DEV(dev, &pdev->dev);
5457 dev->netdev_ops = &rtl_netdev_ops;
5458 tp = netdev_priv(dev);
5459 tp->dev = dev;
5460 tp->pci_dev = pdev;
5461 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
5462 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1;
5463 tp->eee_adv = -1;
5464
5465 /* Get the *optional* external "ether_clk" used on some boards */
5466 rc = rtl_get_ether_clk(tp);
5467 if (rc)
5468 return rc;
5469
5470 /* Disable ASPM completely as that cause random device stop working
5471 * problems as well as full system hangs for some PCIe devices users.
5472 */
5473 rc = pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
5474 PCIE_LINK_STATE_L1);
5475 tp->aspm_manageable = !rc;
5476
5477 /* enable device (incl. PCI PM wakeup and hotplug setup) */
5478 rc = pcim_enable_device(pdev);
5479 if (rc < 0) {
5480 dev_err(&pdev->dev, "enable failure\n");
5481 return rc;
5482 }
5483
5484 if (pcim_set_mwi(pdev) < 0)
5485 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
5486
5487 /* use first MMIO region */
5488 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
5489 if (region < 0) {
5490 dev_err(&pdev->dev, "no MMIO resource found\n");
5491 return -ENODEV;
5492 }
5493
5494 /* check for weird/broken PCI region reporting */
5495 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
5496 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
5497 return -ENODEV;
5498 }
5499
5500 rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME);
5501 if (rc < 0) {
5502 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
5503 return rc;
5504 }
5505
5506 tp->mmio_addr = pcim_iomap_table(pdev)[region];
5507
5508 /* Identify chip attached to board */
5509 rtl8169_get_mac_version(tp);
5510 if (tp->mac_version == RTL_GIGA_MAC_NONE)
5511 return -ENODEV;
5512
5513 tp->cp_cmd = RTL_R16(tp, CPlusCmd);
5514
5515 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 &&
5516 !dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)))
5517 dev->features |= NETIF_F_HIGHDMA;
5518
5519 rtl_init_rxcfg(tp);
5520
5521 rtl8169_irq_mask_and_ack(tp);
5522
5523 rtl_hw_initialize(tp);
5524
5525 rtl_hw_reset(tp);
5526
5527 pci_set_master(pdev);
5528
5529 chipset = tp->mac_version;
5530
5531 rc = rtl_alloc_irq(tp);
5532 if (rc < 0) {
5533 dev_err(&pdev->dev, "Can't allocate interrupt\n");
5534 return rc;
5535 }
5536
5537 mutex_init(&tp->wk.mutex);
5538 INIT_WORK(&tp->wk.work, rtl_task);
5539 u64_stats_init(&tp->rx_stats.syncp);
5540 u64_stats_init(&tp->tx_stats.syncp);
5541
5542 rtl_init_mac_address(tp);
5543
5544 dev->ethtool_ops = &rtl8169_ethtool_ops;
5545
5546 netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
5547
5548 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
5549 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
5550 NETIF_F_HW_VLAN_CTAG_RX;
5551 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
5552 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
5553 NETIF_F_HW_VLAN_CTAG_RX;
5554 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
5555 NETIF_F_HIGHDMA;
5556 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
5557
5558 tp->cp_cmd |= RxChkSum;
5559 /* RTL8125 uses register RxConfig for VLAN offloading config */
5560 if (!rtl_is_8125(tp))
5561 tp->cp_cmd |= RxVlan;
5562 /*
5563 * Pretend we are using VLANs; This bypasses a nasty bug where
5564 * Interrupts stop flowing on high load on 8110SCd controllers.
5565 */
5566 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
5567 /* Disallow toggling */
5568 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
5569
5570 if (rtl_chip_supports_csum_v2(tp)) {
5571 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
5572 dev->features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
5573 dev->gso_max_size = RTL_GSO_MAX_SIZE_V2;
5574 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V2;
5575 } else {
5576 dev->gso_max_size = RTL_GSO_MAX_SIZE_V1;
5577 dev->gso_max_segs = RTL_GSO_MAX_SEGS_V1;
5578 }
5579
5580 /* RTL8168e-vl and one RTL8168c variant are known to have a
5581 * HW issue with TSO.
5582 */
5583 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
5584 tp->mac_version == RTL_GIGA_MAC_VER_22) {
5585 dev->vlan_features &= ~(NETIF_F_ALL_TSO | NETIF_F_SG);
5586 dev->hw_features &= ~(NETIF_F_ALL_TSO | NETIF_F_SG);
5587 dev->features &= ~(NETIF_F_ALL_TSO | NETIF_F_SG);
5588 }
5589
5590 dev->hw_features |= NETIF_F_RXALL;
5591 dev->hw_features |= NETIF_F_RXFCS;
5592
5593 jumbo_max = rtl_jumbo_max(tp);
5594 if (jumbo_max)
5595 dev->max_mtu = jumbo_max;
5596
5597 rtl_set_irq_mask(tp);
5598
5599 tp->fw_name = rtl_chip_infos[chipset].fw_name;
5600
5601 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
5602 &tp->counters_phys_addr,
5603 GFP_KERNEL);
5604 if (!tp->counters)
5605 return -ENOMEM;
5606
5607 pci_set_drvdata(pdev, dev);
5608
5609 rc = r8169_mdio_register(tp);
5610 if (rc)
5611 return rc;
5612
5613 /* chip gets powered up in rtl_open() */
5614 rtl_pll_power_down(tp);
5615
5616 rc = register_netdev(dev);
5617 if (rc)
5618 goto err_mdio_unregister;
5619
5620 netif_info(tp, probe, dev, "%s, %pM, XID %03x, IRQ %d\n",
5621 rtl_chip_infos[chipset].name, dev->dev_addr,
5622 (RTL_R32(tp, TxConfig) >> 20) & 0xfcf,
5623 pci_irq_vector(pdev, 0));
5624
5625 if (jumbo_max)
5626 netif_info(tp, probe, dev,
5627 "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
5628 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
5629 "ok" : "ko");
5630
5631 if (r8168_check_dash(tp))
5632 rtl8168_driver_start(tp);
5633
5634 if (pci_dev_run_wake(pdev))
5635 pm_runtime_put_sync(&pdev->dev);
5636
5637 return 0;
5638
5639 err_mdio_unregister:
5640 mdiobus_unregister(tp->phydev->mdio.bus);
5641 return rc;
5642 }
5643
5644 static struct pci_driver rtl8169_pci_driver = {
5645 .name = MODULENAME,
5646 .id_table = rtl8169_pci_tbl,
5647 .probe = rtl_init_one,
5648 .remove = rtl_remove_one,
5649 .shutdown = rtl_shutdown,
5650 .driver.pm = RTL8169_PM_OPS,
5651 };
5652
5653 module_pci_driver(rtl8169_pci_driver);
Linux with added FPC-III support