drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 // Copyright (c) 2018-19, Linaro Limited
   3
   4 #include <linux/module.h>
   5 #include <linux/of.h>
   6 #include <linux/of_device.h>
   7 #include <linux/platform_device.h>
   8 #include <linux/phy.h>
   9 #include "stmmac.h"
  10 #include "stmmac_platform.h"
  11
  12 #define RGMII_IO_MACRO_CONFIG           0x0
  13 #define SDCC_HC_REG_DLL_CONFIG          0x4
  14 #define SDCC_HC_REG_DDR_CONFIG          0xC
  15 #define SDCC_HC_REG_DLL_CONFIG2         0x10
  16 #define SDC4_STATUS                     0x14
  17 #define SDCC_USR_CTL                    0x18
  18 #define RGMII_IO_MACRO_CONFIG2          0x1C
  19 #define RGMII_IO_MACRO_DEBUG1           0x20
  20 #define EMAC_SYSTEM_LOW_POWER_DEBUG     0x28
  21
  22 /* RGMII_IO_MACRO_CONFIG fields */
  23 #define RGMII_CONFIG_FUNC_CLK_EN                BIT(30)
  24 #define RGMII_CONFIG_POS_NEG_DATA_SEL           BIT(23)
  25 #define RGMII_CONFIG_GPIO_CFG_RX_INT            GENMASK(21, 20)
  26 #define RGMII_CONFIG_GPIO_CFG_TX_INT            GENMASK(19, 17)
  27 #define RGMII_CONFIG_MAX_SPD_PRG_9              GENMASK(16, 8)
  28 #define RGMII_CONFIG_MAX_SPD_PRG_2              GENMASK(7, 6)
  29 #define RGMII_CONFIG_INTF_SEL                   GENMASK(5, 4)
  30 #define RGMII_CONFIG_BYPASS_TX_ID_EN            BIT(3)
  31 #define RGMII_CONFIG_LOOPBACK_EN                BIT(2)
  32 #define RGMII_CONFIG_PROG_SWAP                  BIT(1)
  33 #define RGMII_CONFIG_DDR_MODE                   BIT(0)
  34
  35 /* SDCC_HC_REG_DLL_CONFIG fields */
  36 #define SDCC_DLL_CONFIG_DLL_RST                 BIT(30)
  37 #define SDCC_DLL_CONFIG_PDN                     BIT(29)
  38 #define SDCC_DLL_CONFIG_MCLK_FREQ               GENMASK(26, 24)
  39 #define SDCC_DLL_CONFIG_CDR_SELEXT              GENMASK(23, 20)
  40 #define SDCC_DLL_CONFIG_CDR_EXT_EN              BIT(19)
  41 #define SDCC_DLL_CONFIG_CK_OUT_EN               BIT(18)
  42 #define SDCC_DLL_CONFIG_CDR_EN                  BIT(17)
  43 #define SDCC_DLL_CONFIG_DLL_EN                  BIT(16)
  44 #define SDCC_DLL_MCLK_GATING_EN                 BIT(5)
  45 #define SDCC_DLL_CDR_FINE_PHASE                 GENMASK(3, 2)
  46
  47 /* SDCC_HC_REG_DDR_CONFIG fields */
  48 #define SDCC_DDR_CONFIG_PRG_DLY_EN              BIT(31)
  49 #define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY        GENMASK(26, 21)
  50 #define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE   GENMASK(29, 27)
  51 #define SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN     BIT(30)
  52 #define SDCC_DDR_CONFIG_PRG_RCLK_DLY            GENMASK(8, 0)
  53
  54 /* SDCC_HC_REG_DLL_CONFIG2 fields */
  55 #define SDCC_DLL_CONFIG2_DLL_CLOCK_DIS          BIT(21)
  56 #define SDCC_DLL_CONFIG2_MCLK_FREQ_CALC         GENMASK(17, 10)
  57 #define SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SEL   GENMASK(3, 2)
  58 #define SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW    BIT(1)
  59 #define SDCC_DLL_CONFIG2_DDR_CAL_EN             BIT(0)
  60
  61 /* SDC4_STATUS bits */
  62 #define SDC4_STATUS_DLL_LOCK                    BIT(7)
  63
  64 /* RGMII_IO_MACRO_CONFIG2 fields */
  65 #define RGMII_CONFIG2_RSVD_CONFIG15             GENMASK(31, 17)
  66 #define RGMII_CONFIG2_RGMII_CLK_SEL_CFG         BIT(16)
  67 #define RGMII_CONFIG2_TX_TO_RX_LOOPBACK_EN      BIT(13)
  68 #define RGMII_CONFIG2_CLK_DIVIDE_SEL            BIT(12)
  69 #define RGMII_CONFIG2_RX_PROG_SWAP              BIT(7)
  70 #define RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL       BIT(6)
  71 #define RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN     BIT(5)
  72
  73 struct ethqos_emac_por {
  74         unsigned int offset;
  75         unsigned int value;
  76 };
  77
  78 struct qcom_ethqos {
  79         struct platform_device *pdev;
  80         void __iomem *rgmii_base;
  81
  82         unsigned int rgmii_clk_rate;
  83         struct clk *rgmii_clk;
  84         unsigned int speed;
  85
  86         const struct ethqos_emac_por *por;
  87         unsigned int num_por;
  88 };
  89
  90 static int rgmii_readl(struct qcom_ethqos *ethqos, unsigned int offset)
  91 {
  92         return readl(ethqos->rgmii_base + offset);
  93 }
  94
  95 static void rgmii_writel(struct qcom_ethqos *ethqos,
  96                          int value, unsigned int offset)
  97 {
  98         writel(value, ethqos->rgmii_base + offset);
  99 }
 100
 101 static void rgmii_updatel(struct qcom_ethqos *ethqos,
 102                           int mask, int val, unsigned int offset)
 103 {
 104         unsigned int temp;
 105
 106         temp =  rgmii_readl(ethqos, offset);
 107         temp = (temp & ~(mask)) | val;
 108         rgmii_writel(ethqos, temp, offset);
 109 }
 110
 111 static void rgmii_dump(struct qcom_ethqos *ethqos)
 112 {
 113         dev_dbg(&ethqos->pdev->dev, "Rgmii register dump\n");
 114         dev_dbg(&ethqos->pdev->dev, "RGMII_IO_MACRO_CONFIG: %x\n",
 115                 rgmii_readl(ethqos, RGMII_IO_MACRO_CONFIG));
 116         dev_dbg(&ethqos->pdev->dev, "SDCC_HC_REG_DLL_CONFIG: %x\n",
 117                 rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG));
 118         dev_dbg(&ethqos->pdev->dev, "SDCC_HC_REG_DDR_CONFIG: %x\n",
 119                 rgmii_readl(ethqos, SDCC_HC_REG_DDR_CONFIG));
 120         dev_dbg(&ethqos->pdev->dev, "SDCC_HC_REG_DLL_CONFIG2: %x\n",
 121                 rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG2));
 122         dev_dbg(&ethqos->pdev->dev, "SDC4_STATUS: %x\n",
 123                 rgmii_readl(ethqos, SDC4_STATUS));
 124         dev_dbg(&ethqos->pdev->dev, "SDCC_USR_CTL: %x\n",
 125                 rgmii_readl(ethqos, SDCC_USR_CTL));
 126         dev_dbg(&ethqos->pdev->dev, "RGMII_IO_MACRO_CONFIG2: %x\n",
 127                 rgmii_readl(ethqos, RGMII_IO_MACRO_CONFIG2));
 128         dev_dbg(&ethqos->pdev->dev, "RGMII_IO_MACRO_DEBUG1: %x\n",
 129                 rgmii_readl(ethqos, RGMII_IO_MACRO_DEBUG1));
 130         dev_dbg(&ethqos->pdev->dev, "EMAC_SYSTEM_LOW_POWER_DEBUG: %x\n",
 131                 rgmii_readl(ethqos, EMAC_SYSTEM_LOW_POWER_DEBUG));
 132 }
 133
 134 /* Clock rates */
 135 #define RGMII_1000_NOM_CLK_FREQ                 (250 * 1000 * 1000UL)
 136 #define RGMII_ID_MODE_100_LOW_SVS_CLK_FREQ       (50 * 1000 * 1000UL)
 137 #define RGMII_ID_MODE_10_LOW_SVS_CLK_FREQ         (5 * 1000 * 1000UL)
 138
 139 static void
 140 ethqos_update_rgmii_clk(struct qcom_ethqos *ethqos, unsigned int speed)
 141 {
 142         switch (speed) {
 143         case SPEED_1000:
 144                 ethqos->rgmii_clk_rate =  RGMII_1000_NOM_CLK_FREQ;
 145                 break;
 146
 147         case SPEED_100:
 148                 ethqos->rgmii_clk_rate =  RGMII_ID_MODE_100_LOW_SVS_CLK_FREQ;
 149                 break;
 150
 151         case SPEED_10:
 152                 ethqos->rgmii_clk_rate =  RGMII_ID_MODE_10_LOW_SVS_CLK_FREQ;
 153                 break;
 154         }
 155
 156         clk_set_rate(ethqos->rgmii_clk, ethqos->rgmii_clk_rate);
 157 }
 158
 159 static void ethqos_set_func_clk_en(struct qcom_ethqos *ethqos)
 160 {
 161         rgmii_updatel(ethqos, RGMII_CONFIG_FUNC_CLK_EN,
 162                       RGMII_CONFIG_FUNC_CLK_EN, RGMII_IO_MACRO_CONFIG);
 163 }
 164
 165 static const struct ethqos_emac_por emac_v2_3_0_por[] = {
 166         { .offset = RGMII_IO_MACRO_CONFIG,      .value = 0x00C01343 },
 167         { .offset = SDCC_HC_REG_DLL_CONFIG,     .value = 0x2004642C },
 168         { .offset = SDCC_HC_REG_DDR_CONFIG,     .value = 0x00000000 },
 169         { .offset = SDCC_HC_REG_DLL_CONFIG2,    .value = 0x00200000 },
 170         { .offset = SDCC_USR_CTL,               .value = 0x00010800 },
 171         { .offset = RGMII_IO_MACRO_CONFIG2,     .value = 0x00002060 },
 172 };
 173
 174 static int ethqos_dll_configure(struct qcom_ethqos *ethqos)
 175 {
 176         unsigned int val;
 177         int retry = 1000;
 178
 179         /* Set CDR_EN */
 180         rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CDR_EN,
 181                       SDCC_DLL_CONFIG_CDR_EN, SDCC_HC_REG_DLL_CONFIG);
 182
 183         /* Set CDR_EXT_EN */
 184         rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CDR_EXT_EN,
 185                       SDCC_DLL_CONFIG_CDR_EXT_EN, SDCC_HC_REG_DLL_CONFIG);
 186
 187         /* Clear CK_OUT_EN */
 188         rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN,
 189                       0, SDCC_HC_REG_DLL_CONFIG);
 190
 191         /* Set DLL_EN */
 192         rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_EN,
 193                       SDCC_DLL_CONFIG_DLL_EN, SDCC_HC_REG_DLL_CONFIG);
 194
 195         rgmii_updatel(ethqos, SDCC_DLL_MCLK_GATING_EN,
 196                       0, SDCC_HC_REG_DLL_CONFIG);
 197
 198         rgmii_updatel(ethqos, SDCC_DLL_CDR_FINE_PHASE,
 199                       0, SDCC_HC_REG_DLL_CONFIG);
 200
 201         /* Wait for CK_OUT_EN clear */
 202         do {
 203                 val = rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG);
 204                 val &= SDCC_DLL_CONFIG_CK_OUT_EN;
 205                 if (!val)
 206                         break;
 207                 mdelay(1);
 208                 retry--;
 209         } while (retry > 0);
 210         if (!retry)
 211                 dev_err(&ethqos->pdev->dev, "Clear CK_OUT_EN timedout\n");
 212
 213         /* Set CK_OUT_EN */
 214         rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN,
 215                       SDCC_DLL_CONFIG_CK_OUT_EN, SDCC_HC_REG_DLL_CONFIG);
 216
 217         /* Wait for CK_OUT_EN set */
 218         retry = 1000;
 219         do {
 220                 val = rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG);
 221                 val &= SDCC_DLL_CONFIG_CK_OUT_EN;
 222                 if (val)
 223                         break;
 224                 mdelay(1);
 225                 retry--;
 226         } while (retry > 0);
 227         if (!retry)
 228                 dev_err(&ethqos->pdev->dev, "Set CK_OUT_EN timedout\n");
 229
 230         /* Set DDR_CAL_EN */
 231         rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_CAL_EN,
 232                       SDCC_DLL_CONFIG2_DDR_CAL_EN, SDCC_HC_REG_DLL_CONFIG2);
 233
 234         rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DLL_CLOCK_DIS,
 235                       0, SDCC_HC_REG_DLL_CONFIG2);
 236
 237         rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_MCLK_FREQ_CALC,
 238                       0x1A << 10, SDCC_HC_REG_DLL_CONFIG2);
 239
 240         rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SEL,
 241                       BIT(2), SDCC_HC_REG_DLL_CONFIG2);
 242
 243         rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW,
 244                       SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW,
 245                       SDCC_HC_REG_DLL_CONFIG2);
 246
 247         return 0;
 248 }
 249
 250 static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos)
 251 {
 252         /* Disable loopback mode */
 253         rgmii_updatel(ethqos, RGMII_CONFIG2_TX_TO_RX_LOOPBACK_EN,
 254                       0, RGMII_IO_MACRO_CONFIG2);
 255
 256         /* Select RGMII, write 0 to interface select */
 257         rgmii_updatel(ethqos, RGMII_CONFIG_INTF_SEL,
 258                       0, RGMII_IO_MACRO_CONFIG);
 259
 260         switch (ethqos->speed) {
 261         case SPEED_1000:
 262                 rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE,
 263                               RGMII_CONFIG_DDR_MODE, RGMII_IO_MACRO_CONFIG);
 264                 rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN,
 265                               0, RGMII_IO_MACRO_CONFIG);
 266                 rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL,
 267                               RGMII_CONFIG_POS_NEG_DATA_SEL,
 268                               RGMII_IO_MACRO_CONFIG);
 269                 rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP,
 270                               RGMII_CONFIG_PROG_SWAP, RGMII_IO_MACRO_CONFIG);
 271                 rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL,
 272                               0, RGMII_IO_MACRO_CONFIG2);
 273                 rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN,
 274                               RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN,
 275                               RGMII_IO_MACRO_CONFIG2);
 276                 rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15,
 277                               0, RGMII_IO_MACRO_CONFIG2);
 278                 rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
 279                               RGMII_CONFIG2_RX_PROG_SWAP,
 280                               RGMII_IO_MACRO_CONFIG2);
 281
 282                 /* Set PRG_RCLK_DLY to 57 for 1.8 ns delay */
 283                 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_RCLK_DLY,
 284                               57, SDCC_HC_REG_DDR_CONFIG);
 285                 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_DLY_EN,
 286                               SDCC_DDR_CONFIG_PRG_DLY_EN,
 287                               SDCC_HC_REG_DDR_CONFIG);
 288                 rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,
 289                               RGMII_CONFIG_LOOPBACK_EN, RGMII_IO_MACRO_CONFIG);
 290                 break;
 291
 292         case SPEED_100:
 293                 rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE,
 294                               RGMII_CONFIG_DDR_MODE, RGMII_IO_MACRO_CONFIG);
 295                 rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN,
 296                               RGMII_CONFIG_BYPASS_TX_ID_EN,
 297                               RGMII_IO_MACRO_CONFIG);
 298                 rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL,
 299                               0, RGMII_IO_MACRO_CONFIG);
 300                 rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP,
 301                               0, RGMII_IO_MACRO_CONFIG);
 302                 rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL,
 303                               0, RGMII_IO_MACRO_CONFIG2);
 304                 rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN,
 305                               RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN,
 306                               RGMII_IO_MACRO_CONFIG2);
 307                 rgmii_updatel(ethqos, RGMII_CONFIG_MAX_SPD_PRG_2,
 308                               BIT(6), RGMII_IO_MACRO_CONFIG);
 309                 rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15,
 310                               0, RGMII_IO_MACRO_CONFIG2);
 311                 rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
 312                               0, RGMII_IO_MACRO_CONFIG2);
 313                 /* Write 0x5 to PRG_RCLK_DLY_CODE */
 314                 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE,
 315                               (BIT(29) | BIT(27)), SDCC_HC_REG_DDR_CONFIG);
 316                 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY,
 317                               SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY,
 318                               SDCC_HC_REG_DDR_CONFIG);
 319                 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,
 320                               SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,
 321                               SDCC_HC_REG_DDR_CONFIG);
 322                 rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,
 323                               RGMII_CONFIG_LOOPBACK_EN, RGMII_IO_MACRO_CONFIG);
 324                 break;
 325
 326         case SPEED_10:
 327                 rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE,
 328                               RGMII_CONFIG_DDR_MODE, RGMII_IO_MACRO_CONFIG);
 329                 rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN,
 330                               RGMII_CONFIG_BYPASS_TX_ID_EN,
 331                               RGMII_IO_MACRO_CONFIG);
 332                 rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL,
 333                               0, RGMII_IO_MACRO_CONFIG);
 334                 rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP,
 335                               0, RGMII_IO_MACRO_CONFIG);
 336                 rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL,
 337                               0, RGMII_IO_MACRO_CONFIG2);
 338                 rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN,
 339                               0, RGMII_IO_MACRO_CONFIG2);
 340                 rgmii_updatel(ethqos, RGMII_CONFIG_MAX_SPD_PRG_9,
 341                               BIT(12) | GENMASK(9, 8),
 342                               RGMII_IO_MACRO_CONFIG);
 343                 rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15,
 344                               0, RGMII_IO_MACRO_CONFIG2);
 345                 rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
 346                               0, RGMII_IO_MACRO_CONFIG2);
 347                 /* Write 0x5 to PRG_RCLK_DLY_CODE */
 348                 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE,
 349                               (BIT(29) | BIT(27)), SDCC_HC_REG_DDR_CONFIG);
 350                 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY,
 351                               SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY,
 352                               SDCC_HC_REG_DDR_CONFIG);
 353                 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,
 354                               SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,
 355                               SDCC_HC_REG_DDR_CONFIG);
 356                 rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,
 357                               RGMII_CONFIG_LOOPBACK_EN, RGMII_IO_MACRO_CONFIG);
 358                 break;
 359         default:
 360                 dev_err(&ethqos->pdev->dev,
 361                         "Invalid speed %d\n", ethqos->speed);
 362                 return -EINVAL;
 363         }
 364
 365         return 0;
 366 }
 367
 368 static int ethqos_configure(struct qcom_ethqos *ethqos)
 369 {
 370         volatile unsigned int dll_lock;
 371         unsigned int i, retry = 1000;
 372
 373         /* Reset to POR values and enable clk */
 374         for (i = 0; i < ethqos->num_por; i++)
 375                 rgmii_writel(ethqos, ethqos->por[i].value,
 376                              ethqos->por[i].offset);
 377         ethqos_set_func_clk_en(ethqos);
 378
 379         /* Initialize the DLL first */
 380
 381         /* Set DLL_RST */
 382         rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_RST,
 383                       SDCC_DLL_CONFIG_DLL_RST, SDCC_HC_REG_DLL_CONFIG);
 384
 385         /* Set PDN */
 386         rgmii_updatel(ethqos, SDCC_DLL_CONFIG_PDN,
 387                       SDCC_DLL_CONFIG_PDN, SDCC_HC_REG_DLL_CONFIG);
 388
 389         /* Clear DLL_RST */
 390         rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_RST, 0,
 391                       SDCC_HC_REG_DLL_CONFIG);
 392
 393         /* Clear PDN */
 394         rgmii_updatel(ethqos, SDCC_DLL_CONFIG_PDN, 0,
 395                       SDCC_HC_REG_DLL_CONFIG);
 396
 397         if (ethqos->speed != SPEED_100 && ethqos->speed != SPEED_10) {
 398                 /* Set DLL_EN */
 399                 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_EN,
 400                               SDCC_DLL_CONFIG_DLL_EN, SDCC_HC_REG_DLL_CONFIG);
 401
 402                 /* Set CK_OUT_EN */
 403                 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN,
 404                               SDCC_DLL_CONFIG_CK_OUT_EN,
 405                               SDCC_HC_REG_DLL_CONFIG);
 406
 407                 /* Set USR_CTL bit 26 with mask of 3 bits */
 408                 rgmii_updatel(ethqos, GENMASK(26, 24), BIT(26), SDCC_USR_CTL);
 409
 410                 /* wait for DLL LOCK */
 411                 do {
 412                         mdelay(1);
 413                         dll_lock = rgmii_readl(ethqos, SDC4_STATUS);
 414                         if (dll_lock & SDC4_STATUS_DLL_LOCK)
 415                                 break;
 416                 } while (retry > 0);
 417                 if (!retry)
 418                         dev_err(&ethqos->pdev->dev,
 419                                 "Timeout while waiting for DLL lock\n");
 420         }
 421
 422         if (ethqos->speed == SPEED_1000)
 423                 ethqos_dll_configure(ethqos);
 424
 425         ethqos_rgmii_macro_init(ethqos);
 426
 427         return 0;
 428 }
 429
 430 static void ethqos_fix_mac_speed(void *priv, unsigned int speed)
 431 {
 432         struct qcom_ethqos *ethqos = priv;
 433
 434         ethqos->speed = speed;
 435         ethqos_update_rgmii_clk(ethqos, speed);
 436         ethqos_configure(ethqos);
 437 }
 438
 439 static int qcom_ethqos_probe(struct platform_device *pdev)
 440 {
 441         struct device_node *np = pdev->dev.of_node;
 442         struct plat_stmmacenet_data *plat_dat;
 443         struct stmmac_resources stmmac_res;
 444         struct qcom_ethqos *ethqos;
 445         struct resource *res;
 446         int ret;
 447
 448         ret = stmmac_get_platform_resources(pdev, &stmmac_res);
 449         if (ret)
 450                 return ret;
 451
 452         plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac);
 453         if (IS_ERR(plat_dat)) {
 454                 dev_err(&pdev->dev, "dt configuration failed\n");
 455                 return PTR_ERR(plat_dat);
 456         }
 457
 458         ethqos = devm_kzalloc(&pdev->dev, sizeof(*ethqos), GFP_KERNEL);
 459         if (!ethqos) {
 460                 ret = -ENOMEM;
 461                 goto err_mem;
 462         }
 463
 464         ethqos->pdev = pdev;
 465         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rgmii");
 466         ethqos->rgmii_base = devm_ioremap_resource(&pdev->dev, res);
 467         if (IS_ERR(ethqos->rgmii_base)) {
 468                 dev_err(&pdev->dev, "Can't get rgmii base\n");
 469                 ret = PTR_ERR(ethqos->rgmii_base);
 470                 goto err_mem;
 471         }
 472
 473         ethqos->por = of_device_get_match_data(&pdev->dev);
 474
 475         ethqos->rgmii_clk = devm_clk_get(&pdev->dev, "rgmii");
 476         if (IS_ERR(ethqos->rgmii_clk)) {
 477                 ret = PTR_ERR(ethqos->rgmii_clk);
 478                 goto err_mem;
 479         }
 480
 481         ret = clk_prepare_enable(ethqos->rgmii_clk);
 482         if (ret)
 483                 goto err_mem;
 484
 485         ethqos->speed = SPEED_1000;
 486         ethqos_update_rgmii_clk(ethqos, SPEED_1000);
 487         ethqos_set_func_clk_en(ethqos);
 488
 489         plat_dat->bsp_priv = ethqos;
 490         plat_dat->fix_mac_speed = ethqos_fix_mac_speed;
 491         plat_dat->has_gmac4 = 1;
 492         plat_dat->pmt = 1;
 493         plat_dat->tso_en = of_property_read_bool(np, "snps,tso");
 494
 495         ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
 496         if (ret)
 497                 goto err_clk;
 498
 499         rgmii_dump(ethqos);
 500
 501         return ret;
 502
 503 err_clk:
 504         clk_disable_unprepare(ethqos->rgmii_clk);
 505
 506 err_mem:
 507         stmmac_remove_config_dt(pdev, plat_dat);
 508
 509         return ret;
 510 }
 511
 512 static int qcom_ethqos_remove(struct platform_device *pdev)
 513 {
 514         struct qcom_ethqos *ethqos;
 515         int ret;
 516
 517         ethqos = get_stmmac_bsp_priv(&pdev->dev);
 518         if (!ethqos)
 519                 return -ENODEV;
 520
 521         ret = stmmac_pltfr_remove(pdev);
 522         clk_disable_unprepare(ethqos->rgmii_clk);
 523
 524         return ret;
 525 }
 526
 527 static const struct of_device_id qcom_ethqos_match[] = {
 528         { .compatible = "qcom,qcs404-ethqos", .data = &emac_v2_3_0_por},
 529         { }
 530 };
 531 MODULE_DEVICE_TABLE(of, qcom_ethqos_match);
 532
 533 static struct platform_driver qcom_ethqos_driver = {
 534         .probe  = qcom_ethqos_probe,
 535         .remove = qcom_ethqos_remove,
 536         .driver = {
 537                 .name           = "qcom-ethqos",
 538                 .pm             = &stmmac_pltfr_pm_ops,
 539                 .of_match_table = of_match_ptr(qcom_ethqos_match),
 540         },
 541 };
 542 module_platform_driver(qcom_ethqos_driver);
 543
 544 MODULE_DESCRIPTION("Qualcomm ETHQOS driver");
 545 MODULE_LICENSE("GPL v2");