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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / net / ethernet / stmicro / stmmac / dwmac1000_core.c
blobd0356fbd1e4309056919926a9aa677dc9586af2a
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*******************************************************************************
3 This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
4 DWC Ether MAC 10/100/1000 Universal version 3.41a has been used for
5 developing this code.
6
7 This only implements the mac core functions for this chip.
8
9 Copyright (C) 2007-2009 STMicroelectronics Ltd
10
11
12 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
13 *******************************************************************************/
14
15 #include <linux/crc32.h>
16 #include <linux/slab.h>
17 #include <linux/ethtool.h>
18 #include <net/dsa.h>
19 #include <asm/io.h>
20 #include "stmmac.h"
21 #include "stmmac_pcs.h"
22 #include "dwmac1000.h"
23
24 static void dwmac1000_core_init(struct mac_device_info *hw,
25 struct net_device *dev)
26 {
27 void __iomem *ioaddr = hw->pcsr;
28 u32 value = readl(ioaddr + GMAC_CONTROL);
29 int mtu = dev->mtu;
30
31 /* Configure GMAC core */
32 value |= GMAC_CORE_INIT;
33
34 /* Clear ACS bit because Ethernet switch tagging formats such as
35 * Broadcom tags can look like invalid LLC/SNAP packets and cause the
36 * hardware to truncate packets on reception.
37 */
38 if (netdev_uses_dsa(dev))
39 value &= ~GMAC_CONTROL_ACS;
40
41 if (mtu > 1500)
42 value |= GMAC_CONTROL_2K;
43 if (mtu > 2000)
44 value |= GMAC_CONTROL_JE;
45
46 if (hw->ps) {
47 value |= GMAC_CONTROL_TE;
48
49 value &= ~hw->link.speed_mask;
50 switch (hw->ps) {
51 case SPEED_1000:
52 value |= hw->link.speed1000;
53 break;
54 case SPEED_100:
55 value |= hw->link.speed100;
56 break;
57 case SPEED_10:
58 value |= hw->link.speed10;
59 break;
60 }
61 }
62
63 writel(value, ioaddr + GMAC_CONTROL);
64
65 /* Mask GMAC interrupts */
66 value = GMAC_INT_DEFAULT_MASK;
67
68 if (hw->pcs)
69 value &= ~GMAC_INT_DISABLE_PCS;
70
71 writel(value, ioaddr + GMAC_INT_MASK);
72
73 #ifdef STMMAC_VLAN_TAG_USED
74 /* Tag detection without filtering */
75 writel(0x0, ioaddr + GMAC_VLAN_TAG);
76 #endif
77 }
78
79 static int dwmac1000_rx_ipc_enable(struct mac_device_info *hw)
80 {
81 void __iomem *ioaddr = hw->pcsr;
82 u32 value = readl(ioaddr + GMAC_CONTROL);
83
84 if (hw->rx_csum)
85 value |= GMAC_CONTROL_IPC;
86 else
87 value &= ~GMAC_CONTROL_IPC;
88
89 writel(value, ioaddr + GMAC_CONTROL);
90
91 value = readl(ioaddr + GMAC_CONTROL);
92
93 return !!(value & GMAC_CONTROL_IPC);
94 }
95
96 static void dwmac1000_dump_regs(struct mac_device_info *hw, u32 *reg_space)
97 {
98 void __iomem *ioaddr = hw->pcsr;
99 int i;
100
101 for (i = 0; i < 55; i++)
102 reg_space[i] = readl(ioaddr + i * 4);
103 }
104
105 static void dwmac1000_set_umac_addr(struct mac_device_info *hw,
106 unsigned char *addr,
107 unsigned int reg_n)
108 {
109 void __iomem *ioaddr = hw->pcsr;
110 stmmac_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
111 GMAC_ADDR_LOW(reg_n));
112 }
113
114 static void dwmac1000_get_umac_addr(struct mac_device_info *hw,
115 unsigned char *addr,
116 unsigned int reg_n)
117 {
118 void __iomem *ioaddr = hw->pcsr;
119 stmmac_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
120 GMAC_ADDR_LOW(reg_n));
121 }
122
123 static void dwmac1000_set_mchash(void __iomem *ioaddr, u32 *mcfilterbits,
124 int mcbitslog2)
125 {
126 int numhashregs, regs;
127
128 switch (mcbitslog2) {
129 case 6:
130 writel(mcfilterbits[0], ioaddr + GMAC_HASH_LOW);
131 writel(mcfilterbits[1], ioaddr + GMAC_HASH_HIGH);
132 return;
133 case 7:
134 numhashregs = 4;
135 break;
136 case 8:
137 numhashregs = 8;
138 break;
139 default:
140 pr_debug("STMMAC: err in setting multicast filter\n");
141 return;
142 }
143 for (regs = 0; regs < numhashregs; regs++)
144 writel(mcfilterbits[regs],
145 ioaddr + GMAC_EXTHASH_BASE + regs * 4);
146 }
147
148 static void dwmac1000_set_filter(struct mac_device_info *hw,
149 struct net_device *dev)
150 {
151 void __iomem *ioaddr = (void __iomem *)dev->base_addr;
152 unsigned int value = 0;
153 unsigned int perfect_addr_number = hw->unicast_filter_entries;
154 u32 mc_filter[8];
155 int mcbitslog2 = hw->mcast_bits_log2;
156
157 pr_debug("%s: # mcasts %d, # unicast %d\n", __func__,
158 netdev_mc_count(dev), netdev_uc_count(dev));
159
160 memset(mc_filter, 0, sizeof(mc_filter));
161
162 if (dev->flags & IFF_PROMISC) {
163 value = GMAC_FRAME_FILTER_PR | GMAC_FRAME_FILTER_PCF;
164 } else if (dev->flags & IFF_ALLMULTI) {
165 value = GMAC_FRAME_FILTER_PM; /* pass all multi */
166 } else if (!netdev_mc_empty(dev)) {
167 struct netdev_hw_addr *ha;
168
169 /* Hash filter for multicast */
170 value = GMAC_FRAME_FILTER_HMC;
171
172 netdev_for_each_mc_addr(ha, dev) {
173 /* The upper n bits of the calculated CRC are used to
174 * index the contents of the hash table. The number of
175 * bits used depends on the hardware configuration
176 * selected at core configuration time.
177 */
178 int bit_nr = bitrev32(~crc32_le(~0, ha->addr,
179 ETH_ALEN)) >>
180 (32 - mcbitslog2);
181 /* The most significant bit determines the register to
182 * use (H/L) while the other 5 bits determine the bit
183 * within the register.
184 */
185 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
186 }
187 }
188
189 value |= GMAC_FRAME_FILTER_HPF;
190 dwmac1000_set_mchash(ioaddr, mc_filter, mcbitslog2);
191
192 /* Handle multiple unicast addresses (perfect filtering) */
193 if (netdev_uc_count(dev) > perfect_addr_number)
194 /* Switch to promiscuous mode if more than unicast
195 * addresses are requested than supported by hardware.
196 */
197 value |= GMAC_FRAME_FILTER_PR;
198 else {
199 int reg = 1;
200 struct netdev_hw_addr *ha;
201
202 netdev_for_each_uc_addr(ha, dev) {
203 stmmac_set_mac_addr(ioaddr, ha->addr,
204 GMAC_ADDR_HIGH(reg),
205 GMAC_ADDR_LOW(reg));
206 reg++;
207 }
208
209 while (reg <= perfect_addr_number) {
210 writel(0, ioaddr + GMAC_ADDR_HIGH(reg));
211 writel(0, ioaddr + GMAC_ADDR_LOW(reg));
212 reg++;
213 }
214 }
215
216 #ifdef FRAME_FILTER_DEBUG
217 /* Enable Receive all mode (to debug filtering_fail errors) */
218 value |= GMAC_FRAME_FILTER_RA;
219 #endif
220 writel(value, ioaddr + GMAC_FRAME_FILTER);
221 }
222
223
224 static void dwmac1000_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,
225 unsigned int fc, unsigned int pause_time,
226 u32 tx_cnt)
227 {
228 void __iomem *ioaddr = hw->pcsr;
229 /* Set flow such that DZPQ in Mac Register 6 is 0,
230 * and unicast pause detect is enabled.
231 */
232 unsigned int flow = GMAC_FLOW_CTRL_UP;
233
234 pr_debug("GMAC Flow-Control:\n");
235 if (fc & FLOW_RX) {
236 pr_debug("\tReceive Flow-Control ON\n");
237 flow |= GMAC_FLOW_CTRL_RFE;
238 }
239 if (fc & FLOW_TX) {
240 pr_debug("\tTransmit Flow-Control ON\n");
241 flow |= GMAC_FLOW_CTRL_TFE;
242 }
243
244 if (duplex) {
245 pr_debug("\tduplex mode: PAUSE %d\n", pause_time);
246 flow |= (pause_time << GMAC_FLOW_CTRL_PT_SHIFT);
247 }
248
249 writel(flow, ioaddr + GMAC_FLOW_CTRL);
250 }
251
252 static void dwmac1000_pmt(struct mac_device_info *hw, unsigned long mode)
253 {
254 void __iomem *ioaddr = hw->pcsr;
255 unsigned int pmt = 0;
256
257 if (mode & WAKE_MAGIC) {
258 pr_debug("GMAC: WOL Magic frame\n");
259 pmt |= power_down | magic_pkt_en;
260 }
261 if (mode & WAKE_UCAST) {
262 pr_debug("GMAC: WOL on global unicast\n");
263 pmt |= power_down | global_unicast | wake_up_frame_en;
264 }
265
266 writel(pmt, ioaddr + GMAC_PMT);
267 }
268
269 /* RGMII or SMII interface */
270 static void dwmac1000_rgsmii(void __iomem *ioaddr, struct stmmac_extra_stats *x)
271 {
272 u32 status;
273
274 status = readl(ioaddr + GMAC_RGSMIIIS);
275 x->irq_rgmii_n++;
276
277 /* Check the link status */
278 if (status & GMAC_RGSMIIIS_LNKSTS) {
279 int speed_value;
280
281 x->pcs_link = 1;
282
283 speed_value = ((status & GMAC_RGSMIIIS_SPEED) >>
284 GMAC_RGSMIIIS_SPEED_SHIFT);
285 if (speed_value == GMAC_RGSMIIIS_SPEED_125)
286 x->pcs_speed = SPEED_1000;
287 else if (speed_value == GMAC_RGSMIIIS_SPEED_25)
288 x->pcs_speed = SPEED_100;
289 else
290 x->pcs_speed = SPEED_10;
291
292 x->pcs_duplex = (status & GMAC_RGSMIIIS_LNKMOD_MASK);
293
294 pr_info("Link is Up - %d/%s\n", (int)x->pcs_speed,
295 x->pcs_duplex ? "Full" : "Half");
296 } else {
297 x->pcs_link = 0;
298 pr_info("Link is Down\n");
299 }
300 }
301
302 static int dwmac1000_irq_status(struct mac_device_info *hw,
303 struct stmmac_extra_stats *x)
304 {
305 void __iomem *ioaddr = hw->pcsr;
306 u32 intr_status = readl(ioaddr + GMAC_INT_STATUS);
307 u32 intr_mask = readl(ioaddr + GMAC_INT_MASK);
308 int ret = 0;
309
310 /* Discard masked bits */
311 intr_status &= ~intr_mask;
312
313 /* Not used events (e.g. MMC interrupts) are not handled. */
314 if ((intr_status & GMAC_INT_STATUS_MMCTIS))
315 x->mmc_tx_irq_n++;
316 if (unlikely(intr_status & GMAC_INT_STATUS_MMCRIS))
317 x->mmc_rx_irq_n++;
318 if (unlikely(intr_status & GMAC_INT_STATUS_MMCCSUM))
319 x->mmc_rx_csum_offload_irq_n++;
320 if (unlikely(intr_status & GMAC_INT_DISABLE_PMT)) {
321 /* clear the PMT bits 5 and 6 by reading the PMT status reg */
322 readl(ioaddr + GMAC_PMT);
323 x->irq_receive_pmt_irq_n++;
324 }
325
326 /* MAC tx/rx EEE LPI entry/exit interrupts */
327 if (intr_status & GMAC_INT_STATUS_LPIIS) {
328 /* Clean LPI interrupt by reading the Reg 12 */
329 ret = readl(ioaddr + LPI_CTRL_STATUS);
330
331 if (ret & LPI_CTRL_STATUS_TLPIEN)
332 x->irq_tx_path_in_lpi_mode_n++;
333 if (ret & LPI_CTRL_STATUS_TLPIEX)
334 x->irq_tx_path_exit_lpi_mode_n++;
335 if (ret & LPI_CTRL_STATUS_RLPIEN)
336 x->irq_rx_path_in_lpi_mode_n++;
337 if (ret & LPI_CTRL_STATUS_RLPIEX)
338 x->irq_rx_path_exit_lpi_mode_n++;
339 }
340
341 dwmac_pcs_isr(ioaddr, GMAC_PCS_BASE, intr_status, x);
342
343 if (intr_status & PCS_RGSMIIIS_IRQ)
344 dwmac1000_rgsmii(ioaddr, x);
345
346 return ret;
347 }
348
349 static void dwmac1000_set_eee_mode(struct mac_device_info *hw,
350 bool en_tx_lpi_clockgating)
351 {
352 void __iomem *ioaddr = hw->pcsr;
353 u32 value;
354
355 /*TODO - en_tx_lpi_clockgating treatment */
356
357 /* Enable the link status receive on RGMII, SGMII ore SMII
358 * receive path and instruct the transmit to enter in LPI
359 * state.
360 */
361 value = readl(ioaddr + LPI_CTRL_STATUS);
362 value |= LPI_CTRL_STATUS_LPIEN | LPI_CTRL_STATUS_LPITXA;
363 writel(value, ioaddr + LPI_CTRL_STATUS);
364 }
365
366 static void dwmac1000_reset_eee_mode(struct mac_device_info *hw)
367 {
368 void __iomem *ioaddr = hw->pcsr;
369 u32 value;
370
371 value = readl(ioaddr + LPI_CTRL_STATUS);
372 value &= ~(LPI_CTRL_STATUS_LPIEN | LPI_CTRL_STATUS_LPITXA);
373 writel(value, ioaddr + LPI_CTRL_STATUS);
374 }
375
376 static void dwmac1000_set_eee_pls(struct mac_device_info *hw, int link)
377 {
378 void __iomem *ioaddr = hw->pcsr;
379 u32 value;
380
381 value = readl(ioaddr + LPI_CTRL_STATUS);
382
383 if (link)
384 value |= LPI_CTRL_STATUS_PLS;
385 else
386 value &= ~LPI_CTRL_STATUS_PLS;
387
388 writel(value, ioaddr + LPI_CTRL_STATUS);
389 }
390
391 static void dwmac1000_set_eee_timer(struct mac_device_info *hw, int ls, int tw)
392 {
393 void __iomem *ioaddr = hw->pcsr;
394 int value = ((tw & 0xffff)) | ((ls & 0x7ff) << 16);
395
396 /* Program the timers in the LPI timer control register:
397 * LS: minimum time (ms) for which the link
398 * status from PHY should be ok before transmitting
399 * the LPI pattern.
400 * TW: minimum time (us) for which the core waits
401 * after it has stopped transmitting the LPI pattern.
402 */
403 writel(value, ioaddr + LPI_TIMER_CTRL);
404 }
405
406 static void dwmac1000_ctrl_ane(void __iomem *ioaddr, bool ane, bool srgmi_ral,
407 bool loopback)
408 {
409 dwmac_ctrl_ane(ioaddr, GMAC_PCS_BASE, ane, srgmi_ral, loopback);
410 }
411
412 static void dwmac1000_rane(void __iomem *ioaddr, bool restart)
413 {
414 dwmac_rane(ioaddr, GMAC_PCS_BASE, restart);
415 }
416
417 static void dwmac1000_get_adv_lp(void __iomem *ioaddr, struct rgmii_adv *adv)
418 {
419 dwmac_get_adv_lp(ioaddr, GMAC_PCS_BASE, adv);
420 }
421
422 static void dwmac1000_debug(void __iomem *ioaddr, struct stmmac_extra_stats *x,
423 u32 rx_queues, u32 tx_queues)
424 {
425 u32 value = readl(ioaddr + GMAC_DEBUG);
426
427 if (value & GMAC_DEBUG_TXSTSFSTS)
428 x->mtl_tx_status_fifo_full++;
429 if (value & GMAC_DEBUG_TXFSTS)
430 x->mtl_tx_fifo_not_empty++;
431 if (value & GMAC_DEBUG_TWCSTS)
432 x->mmtl_fifo_ctrl++;
433 if (value & GMAC_DEBUG_TRCSTS_MASK) {
434 u32 trcsts = (value & GMAC_DEBUG_TRCSTS_MASK)
435 >> GMAC_DEBUG_TRCSTS_SHIFT;
436 if (trcsts == GMAC_DEBUG_TRCSTS_WRITE)
437 x->mtl_tx_fifo_read_ctrl_write++;
438 else if (trcsts == GMAC_DEBUG_TRCSTS_TXW)
439 x->mtl_tx_fifo_read_ctrl_wait++;
440 else if (trcsts == GMAC_DEBUG_TRCSTS_READ)
441 x->mtl_tx_fifo_read_ctrl_read++;
442 else
443 x->mtl_tx_fifo_read_ctrl_idle++;
444 }
445 if (value & GMAC_DEBUG_TXPAUSED)
446 x->mac_tx_in_pause++;
447 if (value & GMAC_DEBUG_TFCSTS_MASK) {
448 u32 tfcsts = (value & GMAC_DEBUG_TFCSTS_MASK)
449 >> GMAC_DEBUG_TFCSTS_SHIFT;
450
451 if (tfcsts == GMAC_DEBUG_TFCSTS_XFER)
452 x->mac_tx_frame_ctrl_xfer++;
453 else if (tfcsts == GMAC_DEBUG_TFCSTS_GEN_PAUSE)
454 x->mac_tx_frame_ctrl_pause++;
455 else if (tfcsts == GMAC_DEBUG_TFCSTS_WAIT)
456 x->mac_tx_frame_ctrl_wait++;
457 else
458 x->mac_tx_frame_ctrl_idle++;
459 }
460 if (value & GMAC_DEBUG_TPESTS)
461 x->mac_gmii_tx_proto_engine++;
462 if (value & GMAC_DEBUG_RXFSTS_MASK) {
463 u32 rxfsts = (value & GMAC_DEBUG_RXFSTS_MASK)
464 >> GMAC_DEBUG_RRCSTS_SHIFT;
465
466 if (rxfsts == GMAC_DEBUG_RXFSTS_FULL)
467 x->mtl_rx_fifo_fill_level_full++;
468 else if (rxfsts == GMAC_DEBUG_RXFSTS_AT)
469 x->mtl_rx_fifo_fill_above_thresh++;
470 else if (rxfsts == GMAC_DEBUG_RXFSTS_BT)
471 x->mtl_rx_fifo_fill_below_thresh++;
472 else
473 x->mtl_rx_fifo_fill_level_empty++;
474 }
475 if (value & GMAC_DEBUG_RRCSTS_MASK) {
476 u32 rrcsts = (value & GMAC_DEBUG_RRCSTS_MASK) >>
477 GMAC_DEBUG_RRCSTS_SHIFT;
478
479 if (rrcsts == GMAC_DEBUG_RRCSTS_FLUSH)
480 x->mtl_rx_fifo_read_ctrl_flush++;
481 else if (rrcsts == GMAC_DEBUG_RRCSTS_RSTAT)
482 x->mtl_rx_fifo_read_ctrl_read_data++;
483 else if (rrcsts == GMAC_DEBUG_RRCSTS_RDATA)
484 x->mtl_rx_fifo_read_ctrl_status++;
485 else
486 x->mtl_rx_fifo_read_ctrl_idle++;
487 }
488 if (value & GMAC_DEBUG_RWCSTS)
489 x->mtl_rx_fifo_ctrl_active++;
490 if (value & GMAC_DEBUG_RFCFCSTS_MASK)
491 x->mac_rx_frame_ctrl_fifo = (value & GMAC_DEBUG_RFCFCSTS_MASK)
492 >> GMAC_DEBUG_RFCFCSTS_SHIFT;
493 if (value & GMAC_DEBUG_RPESTS)
494 x->mac_gmii_rx_proto_engine++;
495 }
496
497 static void dwmac1000_set_mac_loopback(void __iomem *ioaddr, bool enable)
498 {
499 u32 value = readl(ioaddr + GMAC_CONTROL);
500
501 if (enable)
502 value |= GMAC_CONTROL_LM;
503 else
504 value &= ~GMAC_CONTROL_LM;
505
506 writel(value, ioaddr + GMAC_CONTROL);
507 }
508
509 const struct stmmac_ops dwmac1000_ops = {
510 .core_init = dwmac1000_core_init,
511 .set_mac = stmmac_set_mac,
512 .rx_ipc = dwmac1000_rx_ipc_enable,
513 .dump_regs = dwmac1000_dump_regs,
514 .host_irq_status = dwmac1000_irq_status,
515 .set_filter = dwmac1000_set_filter,
516 .flow_ctrl = dwmac1000_flow_ctrl,
517 .pmt = dwmac1000_pmt,
518 .set_umac_addr = dwmac1000_set_umac_addr,
519 .get_umac_addr = dwmac1000_get_umac_addr,
520 .set_eee_mode = dwmac1000_set_eee_mode,
521 .reset_eee_mode = dwmac1000_reset_eee_mode,
522 .set_eee_timer = dwmac1000_set_eee_timer,
523 .set_eee_pls = dwmac1000_set_eee_pls,
524 .debug = dwmac1000_debug,
525 .pcs_ctrl_ane = dwmac1000_ctrl_ane,
526 .pcs_rane = dwmac1000_rane,
527 .pcs_get_adv_lp = dwmac1000_get_adv_lp,
528 .set_mac_loopback = dwmac1000_set_mac_loopback,
529 };
530
531 int dwmac1000_setup(struct stmmac_priv *priv)
532 {
533 struct mac_device_info *mac = priv->hw;
534
535 dev_info(priv->device, "\tDWMAC1000\n");
536
537 priv->dev->priv_flags |= IFF_UNICAST_FLT;
538 mac->pcsr = priv->ioaddr;
539 mac->multicast_filter_bins = priv->plat->multicast_filter_bins;
540 mac->unicast_filter_entries = priv->plat->unicast_filter_entries;
541 mac->mcast_bits_log2 = 0;
542
543 if (mac->multicast_filter_bins)
544 mac->mcast_bits_log2 = ilog2(mac->multicast_filter_bins);
545
546 mac->link.duplex = GMAC_CONTROL_DM;
547 mac->link.speed10 = GMAC_CONTROL_PS;
548 mac->link.speed100 = GMAC_CONTROL_PS | GMAC_CONTROL_FES;
549 mac->link.speed1000 = 0;
550 mac->link.speed_mask = GMAC_CONTROL_PS | GMAC_CONTROL_FES;
551 mac->mii.addr = GMAC_MII_ADDR;
552 mac->mii.data = GMAC_MII_DATA;
553 mac->mii.addr_shift = 11;
554 mac->mii.addr_mask = 0x0000F800;
555 mac->mii.reg_shift = 6;
556 mac->mii.reg_mask = 0x000007C0;
557 mac->mii.clk_csr_shift = 2;
558 mac->mii.clk_csr_mask = GENMASK(5, 2);
559
560 return 0;
561 }
Linux with added FPC-III support