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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / net / ethernet / ti / cpsw_ale.c
blobecdbde539eb7bd65fad702118d0719403b7f1796
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Texas Instruments N-Port Ethernet Switch Address Lookup Engine
4 *
5 * Copyright (C) 2012 Texas Instruments
6 *
7 */
8 #include <linux/bitmap.h>
9 #include <linux/if_vlan.h>
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/platform_device.h>
13 #include <linux/seq_file.h>
14 #include <linux/slab.h>
15 #include <linux/err.h>
16 #include <linux/io.h>
17 #include <linux/stat.h>
18 #include <linux/sysfs.h>
19 #include <linux/etherdevice.h>
20
21 #include "cpsw_ale.h"
22
23 #define BITMASK(bits) (BIT(bits) - 1)
24
25 #define ALE_VERSION_MAJOR(rev, mask) (((rev) >> 8) & (mask))
26 #define ALE_VERSION_MINOR(rev) (rev & 0xff)
27 #define ALE_VERSION_1R3 0x0103
28 #define ALE_VERSION_1R4 0x0104
29
30 /* ALE Registers */
31 #define ALE_IDVER 0x00
32 #define ALE_STATUS 0x04
33 #define ALE_CONTROL 0x08
34 #define ALE_PRESCALE 0x10
35 #define ALE_UNKNOWNVLAN 0x18
36 #define ALE_TABLE_CONTROL 0x20
37 #define ALE_TABLE 0x34
38 #define ALE_PORTCTL 0x40
39
40 /* ALE NetCP NU switch specific Registers */
41 #define ALE_UNKNOWNVLAN_MEMBER 0x90
42 #define ALE_UNKNOWNVLAN_UNREG_MCAST_FLOOD 0x94
43 #define ALE_UNKNOWNVLAN_REG_MCAST_FLOOD 0x98
44 #define ALE_UNKNOWNVLAN_FORCE_UNTAG_EGRESS 0x9C
45 #define ALE_VLAN_MASK_MUX(reg) (0xc0 + (0x4 * (reg)))
46
47 #define ALE_TABLE_WRITE BIT(31)
48
49 #define ALE_TYPE_FREE 0
50 #define ALE_TYPE_ADDR 1
51 #define ALE_TYPE_VLAN 2
52 #define ALE_TYPE_VLAN_ADDR 3
53
54 #define ALE_UCAST_PERSISTANT 0
55 #define ALE_UCAST_UNTOUCHED 1
56 #define ALE_UCAST_OUI 2
57 #define ALE_UCAST_TOUCHED 3
58
59 #define ALE_TABLE_SIZE_MULTIPLIER 1024
60 #define ALE_STATUS_SIZE_MASK 0x1f
61 #define ALE_TABLE_SIZE_DEFAULT 64
62
63 static inline int cpsw_ale_get_field(u32 *ale_entry, u32 start, u32 bits)
64 {
65 int idx;
66
67 idx = start / 32;
68 start -= idx * 32;
69 idx = 2 - idx; /* flip */
70 return (ale_entry[idx] >> start) & BITMASK(bits);
71 }
72
73 static inline void cpsw_ale_set_field(u32 *ale_entry, u32 start, u32 bits,
74 u32 value)
75 {
76 int idx;
77
78 value &= BITMASK(bits);
79 idx = start / 32;
80 start -= idx * 32;
81 idx = 2 - idx; /* flip */
82 ale_entry[idx] &= ~(BITMASK(bits) << start);
83 ale_entry[idx] |= (value << start);
84 }
85
86 #define DEFINE_ALE_FIELD(name, start, bits) \
87 static inline int cpsw_ale_get_##name(u32 *ale_entry) \
88 { \
89 return cpsw_ale_get_field(ale_entry, start, bits); \
90 } \
91 static inline void cpsw_ale_set_##name(u32 *ale_entry, u32 value) \
92 { \
93 cpsw_ale_set_field(ale_entry, start, bits, value); \
94 }
95
96 #define DEFINE_ALE_FIELD1(name, start) \
97 static inline int cpsw_ale_get_##name(u32 *ale_entry, u32 bits) \
98 { \
99 return cpsw_ale_get_field(ale_entry, start, bits); \
100 } \
101 static inline void cpsw_ale_set_##name(u32 *ale_entry, u32 value, \
102 u32 bits) \
103 { \
104 cpsw_ale_set_field(ale_entry, start, bits, value); \
105 }
106
107 DEFINE_ALE_FIELD(entry_type, 60, 2)
108 DEFINE_ALE_FIELD(vlan_id, 48, 12)
109 DEFINE_ALE_FIELD(mcast_state, 62, 2)
110 DEFINE_ALE_FIELD1(port_mask, 66)
111 DEFINE_ALE_FIELD(super, 65, 1)
112 DEFINE_ALE_FIELD(ucast_type, 62, 2)
113 DEFINE_ALE_FIELD1(port_num, 66)
114 DEFINE_ALE_FIELD(blocked, 65, 1)
115 DEFINE_ALE_FIELD(secure, 64, 1)
116 DEFINE_ALE_FIELD1(vlan_untag_force, 24)
117 DEFINE_ALE_FIELD1(vlan_reg_mcast, 16)
118 DEFINE_ALE_FIELD1(vlan_unreg_mcast, 8)
119 DEFINE_ALE_FIELD1(vlan_member_list, 0)
120 DEFINE_ALE_FIELD(mcast, 40, 1)
121 /* ALE NetCP nu switch specific */
122 DEFINE_ALE_FIELD(vlan_unreg_mcast_idx, 20, 3)
123 DEFINE_ALE_FIELD(vlan_reg_mcast_idx, 44, 3)
124
125 /* The MAC address field in the ALE entry cannot be macroized as above */
126 static inline void cpsw_ale_get_addr(u32 *ale_entry, u8 *addr)
127 {
128 int i;
129
130 for (i = 0; i < 6; i++)
131 addr[i] = cpsw_ale_get_field(ale_entry, 40 - 8*i, 8);
132 }
133
134 static inline void cpsw_ale_set_addr(u32 *ale_entry, const u8 *addr)
135 {
136 int i;
137
138 for (i = 0; i < 6; i++)
139 cpsw_ale_set_field(ale_entry, 40 - 8*i, 8, addr[i]);
140 }
141
142 static int cpsw_ale_read(struct cpsw_ale *ale, int idx, u32 *ale_entry)
143 {
144 int i;
145
146 WARN_ON(idx > ale->params.ale_entries);
147
148 writel_relaxed(idx, ale->params.ale_regs + ALE_TABLE_CONTROL);
149
150 for (i = 0; i < ALE_ENTRY_WORDS; i++)
151 ale_entry[i] = readl_relaxed(ale->params.ale_regs +
152 ALE_TABLE + 4 * i);
153
154 return idx;
155 }
156
157 static int cpsw_ale_write(struct cpsw_ale *ale, int idx, u32 *ale_entry)
158 {
159 int i;
160
161 WARN_ON(idx > ale->params.ale_entries);
162
163 for (i = 0; i < ALE_ENTRY_WORDS; i++)
164 writel_relaxed(ale_entry[i], ale->params.ale_regs +
165 ALE_TABLE + 4 * i);
166
167 writel_relaxed(idx | ALE_TABLE_WRITE, ale->params.ale_regs +
168 ALE_TABLE_CONTROL);
169
170 return idx;
171 }
172
173 static int cpsw_ale_match_addr(struct cpsw_ale *ale, const u8 *addr, u16 vid)
174 {
175 u32 ale_entry[ALE_ENTRY_WORDS];
176 int type, idx;
177
178 for (idx = 0; idx < ale->params.ale_entries; idx++) {
179 u8 entry_addr[6];
180
181 cpsw_ale_read(ale, idx, ale_entry);
182 type = cpsw_ale_get_entry_type(ale_entry);
183 if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
184 continue;
185 if (cpsw_ale_get_vlan_id(ale_entry) != vid)
186 continue;
187 cpsw_ale_get_addr(ale_entry, entry_addr);
188 if (ether_addr_equal(entry_addr, addr))
189 return idx;
190 }
191 return -ENOENT;
192 }
193
194 static int cpsw_ale_match_vlan(struct cpsw_ale *ale, u16 vid)
195 {
196 u32 ale_entry[ALE_ENTRY_WORDS];
197 int type, idx;
198
199 for (idx = 0; idx < ale->params.ale_entries; idx++) {
200 cpsw_ale_read(ale, idx, ale_entry);
201 type = cpsw_ale_get_entry_type(ale_entry);
202 if (type != ALE_TYPE_VLAN)
203 continue;
204 if (cpsw_ale_get_vlan_id(ale_entry) == vid)
205 return idx;
206 }
207 return -ENOENT;
208 }
209
210 static int cpsw_ale_match_free(struct cpsw_ale *ale)
211 {
212 u32 ale_entry[ALE_ENTRY_WORDS];
213 int type, idx;
214
215 for (idx = 0; idx < ale->params.ale_entries; idx++) {
216 cpsw_ale_read(ale, idx, ale_entry);
217 type = cpsw_ale_get_entry_type(ale_entry);
218 if (type == ALE_TYPE_FREE)
219 return idx;
220 }
221 return -ENOENT;
222 }
223
224 static int cpsw_ale_find_ageable(struct cpsw_ale *ale)
225 {
226 u32 ale_entry[ALE_ENTRY_WORDS];
227 int type, idx;
228
229 for (idx = 0; idx < ale->params.ale_entries; idx++) {
230 cpsw_ale_read(ale, idx, ale_entry);
231 type = cpsw_ale_get_entry_type(ale_entry);
232 if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR)
233 continue;
234 if (cpsw_ale_get_mcast(ale_entry))
235 continue;
236 type = cpsw_ale_get_ucast_type(ale_entry);
237 if (type != ALE_UCAST_PERSISTANT &&
238 type != ALE_UCAST_OUI)
239 return idx;
240 }
241 return -ENOENT;
242 }
243
244 static void cpsw_ale_flush_mcast(struct cpsw_ale *ale, u32 *ale_entry,
245 int port_mask)
246 {
247 int mask;
248
249 mask = cpsw_ale_get_port_mask(ale_entry,
250 ale->port_mask_bits);
251 if ((mask & port_mask) == 0)
252 return; /* ports dont intersect, not interested */
253 mask &= ~port_mask;
254
255 /* free if only remaining port is host port */
256 if (mask)
257 cpsw_ale_set_port_mask(ale_entry, mask,
258 ale->port_mask_bits);
259 else
260 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE);
261 }
262
263 int cpsw_ale_flush_multicast(struct cpsw_ale *ale, int port_mask, int vid)
264 {
265 u32 ale_entry[ALE_ENTRY_WORDS];
266 int ret, idx;
267
268 for (idx = 0; idx < ale->params.ale_entries; idx++) {
269 cpsw_ale_read(ale, idx, ale_entry);
270 ret = cpsw_ale_get_entry_type(ale_entry);
271 if (ret != ALE_TYPE_ADDR && ret != ALE_TYPE_VLAN_ADDR)
272 continue;
273
274 /* if vid passed is -1 then remove all multicast entry from
275 * the table irrespective of vlan id, if a valid vlan id is
276 * passed then remove only multicast added to that vlan id.
277 * if vlan id doesn't match then move on to next entry.
278 */
279 if (vid != -1 && cpsw_ale_get_vlan_id(ale_entry) != vid)
280 continue;
281
282 if (cpsw_ale_get_mcast(ale_entry)) {
283 u8 addr[6];
284
285 if (cpsw_ale_get_super(ale_entry))
286 continue;
287
288 cpsw_ale_get_addr(ale_entry, addr);
289 if (!is_broadcast_ether_addr(addr))
290 cpsw_ale_flush_mcast(ale, ale_entry, port_mask);
291 }
292
293 cpsw_ale_write(ale, idx, ale_entry);
294 }
295 return 0;
296 }
297
298 static inline void cpsw_ale_set_vlan_entry_type(u32 *ale_entry,
299 int flags, u16 vid)
300 {
301 if (flags & ALE_VLAN) {
302 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_VLAN_ADDR);
303 cpsw_ale_set_vlan_id(ale_entry, vid);
304 } else {
305 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR);
306 }
307 }
308
309 int cpsw_ale_add_ucast(struct cpsw_ale *ale, const u8 *addr, int port,
310 int flags, u16 vid)
311 {
312 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
313 int idx;
314
315 cpsw_ale_set_vlan_entry_type(ale_entry, flags, vid);
316
317 cpsw_ale_set_addr(ale_entry, addr);
318 cpsw_ale_set_ucast_type(ale_entry, ALE_UCAST_PERSISTANT);
319 cpsw_ale_set_secure(ale_entry, (flags & ALE_SECURE) ? 1 : 0);
320 cpsw_ale_set_blocked(ale_entry, (flags & ALE_BLOCKED) ? 1 : 0);
321 cpsw_ale_set_port_num(ale_entry, port, ale->port_num_bits);
322
323 idx = cpsw_ale_match_addr(ale, addr, (flags & ALE_VLAN) ? vid : 0);
324 if (idx < 0)
325 idx = cpsw_ale_match_free(ale);
326 if (idx < 0)
327 idx = cpsw_ale_find_ageable(ale);
328 if (idx < 0)
329 return -ENOMEM;
330
331 cpsw_ale_write(ale, idx, ale_entry);
332 return 0;
333 }
334
335 int cpsw_ale_del_ucast(struct cpsw_ale *ale, const u8 *addr, int port,
336 int flags, u16 vid)
337 {
338 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
339 int idx;
340
341 idx = cpsw_ale_match_addr(ale, addr, (flags & ALE_VLAN) ? vid : 0);
342 if (idx < 0)
343 return -ENOENT;
344
345 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE);
346 cpsw_ale_write(ale, idx, ale_entry);
347 return 0;
348 }
349
350 int cpsw_ale_add_mcast(struct cpsw_ale *ale, const u8 *addr, int port_mask,
351 int flags, u16 vid, int mcast_state)
352 {
353 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
354 int idx, mask;
355
356 idx = cpsw_ale_match_addr(ale, addr, (flags & ALE_VLAN) ? vid : 0);
357 if (idx >= 0)
358 cpsw_ale_read(ale, idx, ale_entry);
359
360 cpsw_ale_set_vlan_entry_type(ale_entry, flags, vid);
361
362 cpsw_ale_set_addr(ale_entry, addr);
363 cpsw_ale_set_super(ale_entry, (flags & ALE_SUPER) ? 1 : 0);
364 cpsw_ale_set_mcast_state(ale_entry, mcast_state);
365
366 mask = cpsw_ale_get_port_mask(ale_entry,
367 ale->port_mask_bits);
368 port_mask |= mask;
369 cpsw_ale_set_port_mask(ale_entry, port_mask,
370 ale->port_mask_bits);
371
372 if (idx < 0)
373 idx = cpsw_ale_match_free(ale);
374 if (idx < 0)
375 idx = cpsw_ale_find_ageable(ale);
376 if (idx < 0)
377 return -ENOMEM;
378
379 cpsw_ale_write(ale, idx, ale_entry);
380 return 0;
381 }
382
383 int cpsw_ale_del_mcast(struct cpsw_ale *ale, const u8 *addr, int port_mask,
384 int flags, u16 vid)
385 {
386 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
387 int mcast_members = 0;
388 int idx;
389
390 idx = cpsw_ale_match_addr(ale, addr, (flags & ALE_VLAN) ? vid : 0);
391 if (idx < 0)
392 return -ENOENT;
393
394 cpsw_ale_read(ale, idx, ale_entry);
395
396 if (port_mask) {
397 mcast_members = cpsw_ale_get_port_mask(ale_entry,
398 ale->port_mask_bits);
399 mcast_members &= ~port_mask;
400 }
401
402 if (mcast_members)
403 cpsw_ale_set_port_mask(ale_entry, mcast_members,
404 ale->port_mask_bits);
405 else
406 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE);
407
408 cpsw_ale_write(ale, idx, ale_entry);
409 return 0;
410 }
411
412 /* ALE NetCP NU switch specific vlan functions */
413 static void cpsw_ale_set_vlan_mcast(struct cpsw_ale *ale, u32 *ale_entry,
414 int reg_mcast, int unreg_mcast)
415 {
416 int idx;
417
418 /* Set VLAN registered multicast flood mask */
419 idx = cpsw_ale_get_vlan_reg_mcast_idx(ale_entry);
420 writel(reg_mcast, ale->params.ale_regs + ALE_VLAN_MASK_MUX(idx));
421
422 /* Set VLAN unregistered multicast flood mask */
423 idx = cpsw_ale_get_vlan_unreg_mcast_idx(ale_entry);
424 writel(unreg_mcast, ale->params.ale_regs + ALE_VLAN_MASK_MUX(idx));
425 }
426
427 static void cpsw_ale_set_vlan_untag(struct cpsw_ale *ale, u32 *ale_entry,
428 u16 vid, int untag_mask)
429 {
430 cpsw_ale_set_vlan_untag_force(ale_entry,
431 untag_mask, ale->vlan_field_bits);
432 if (untag_mask & ALE_PORT_HOST)
433 bitmap_set(ale->p0_untag_vid_mask, vid, 1);
434 else
435 bitmap_clear(ale->p0_untag_vid_mask, vid, 1);
436 }
437
438 int cpsw_ale_add_vlan(struct cpsw_ale *ale, u16 vid, int port_mask, int untag,
439 int reg_mcast, int unreg_mcast)
440 {
441 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
442 int idx;
443
444 idx = cpsw_ale_match_vlan(ale, vid);
445 if (idx >= 0)
446 cpsw_ale_read(ale, idx, ale_entry);
447
448 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_VLAN);
449 cpsw_ale_set_vlan_id(ale_entry, vid);
450 cpsw_ale_set_vlan_untag(ale, ale_entry, vid, untag);
451
452 if (!ale->params.nu_switch_ale) {
453 cpsw_ale_set_vlan_reg_mcast(ale_entry, reg_mcast,
454 ale->vlan_field_bits);
455 cpsw_ale_set_vlan_unreg_mcast(ale_entry, unreg_mcast,
456 ale->vlan_field_bits);
457 } else {
458 cpsw_ale_set_vlan_mcast(ale, ale_entry, reg_mcast, unreg_mcast);
459 }
460 cpsw_ale_set_vlan_member_list(ale_entry, port_mask,
461 ale->vlan_field_bits);
462
463 if (idx < 0)
464 idx = cpsw_ale_match_free(ale);
465 if (idx < 0)
466 idx = cpsw_ale_find_ageable(ale);
467 if (idx < 0)
468 return -ENOMEM;
469
470 cpsw_ale_write(ale, idx, ale_entry);
471 return 0;
472 }
473
474 static void cpsw_ale_del_vlan_modify(struct cpsw_ale *ale, u32 *ale_entry,
475 u16 vid, int port_mask)
476 {
477 int reg_mcast, unreg_mcast;
478 int members, untag;
479
480 members = cpsw_ale_get_vlan_member_list(ale_entry,
481 ale->vlan_field_bits);
482 members &= ~port_mask;
483 if (!members) {
484 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE);
485 return;
486 }
487
488 untag = cpsw_ale_get_vlan_untag_force(ale_entry,
489 ale->vlan_field_bits);
490 reg_mcast = cpsw_ale_get_vlan_reg_mcast(ale_entry,
491 ale->vlan_field_bits);
492 unreg_mcast = cpsw_ale_get_vlan_unreg_mcast(ale_entry,
493 ale->vlan_field_bits);
494 untag &= members;
495 reg_mcast &= members;
496 unreg_mcast &= members;
497
498 cpsw_ale_set_vlan_untag(ale, ale_entry, vid, untag);
499
500 if (!ale->params.nu_switch_ale) {
501 cpsw_ale_set_vlan_reg_mcast(ale_entry, reg_mcast,
502 ale->vlan_field_bits);
503 cpsw_ale_set_vlan_unreg_mcast(ale_entry, unreg_mcast,
504 ale->vlan_field_bits);
505 } else {
506 cpsw_ale_set_vlan_mcast(ale, ale_entry, reg_mcast,
507 unreg_mcast);
508 }
509 cpsw_ale_set_vlan_member_list(ale_entry, members,
510 ale->vlan_field_bits);
511 }
512
513 int cpsw_ale_del_vlan(struct cpsw_ale *ale, u16 vid, int port_mask)
514 {
515 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
516 int idx;
517
518 idx = cpsw_ale_match_vlan(ale, vid);
519 if (idx < 0)
520 return -ENOENT;
521
522 cpsw_ale_read(ale, idx, ale_entry);
523
524 if (port_mask) {
525 cpsw_ale_del_vlan_modify(ale, ale_entry, vid, port_mask);
526 } else {
527 cpsw_ale_set_vlan_untag(ale, ale_entry, vid, 0);
528 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_FREE);
529 }
530
531 cpsw_ale_write(ale, idx, ale_entry);
532
533 return 0;
534 }
535
536 int cpsw_ale_vlan_add_modify(struct cpsw_ale *ale, u16 vid, int port_mask,
537 int untag_mask, int reg_mask, int unreg_mask)
538 {
539 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0};
540 int reg_mcast_members, unreg_mcast_members;
541 int vlan_members, untag_members;
542 int idx, ret = 0;
543
544 idx = cpsw_ale_match_vlan(ale, vid);
545 if (idx >= 0)
546 cpsw_ale_read(ale, idx, ale_entry);
547
548 vlan_members = cpsw_ale_get_vlan_member_list(ale_entry,
549 ale->vlan_field_bits);
550 reg_mcast_members = cpsw_ale_get_vlan_reg_mcast(ale_entry,
551 ale->vlan_field_bits);
552 unreg_mcast_members =
553 cpsw_ale_get_vlan_unreg_mcast(ale_entry,
554 ale->vlan_field_bits);
555 untag_members = cpsw_ale_get_vlan_untag_force(ale_entry,
556 ale->vlan_field_bits);
557
558 vlan_members |= port_mask;
559 untag_members = (untag_members & ~port_mask) | untag_mask;
560 reg_mcast_members = (reg_mcast_members & ~port_mask) | reg_mask;
561 unreg_mcast_members = (unreg_mcast_members & ~port_mask) | unreg_mask;
562
563 ret = cpsw_ale_add_vlan(ale, vid, vlan_members, untag_members,
564 reg_mcast_members, unreg_mcast_members);
565 if (ret) {
566 dev_err(ale->params.dev, "Unable to add vlan\n");
567 return ret;
568 }
569 dev_dbg(ale->params.dev, "port mask 0x%x untag 0x%x\n", vlan_members,
570 untag_mask);
571
572 return ret;
573 }
574
575 void cpsw_ale_set_unreg_mcast(struct cpsw_ale *ale, int unreg_mcast_mask,
576 bool add)
577 {
578 u32 ale_entry[ALE_ENTRY_WORDS];
579 int unreg_members = 0;
580 int type, idx;
581
582 for (idx = 0; idx < ale->params.ale_entries; idx++) {
583 cpsw_ale_read(ale, idx, ale_entry);
584 type = cpsw_ale_get_entry_type(ale_entry);
585 if (type != ALE_TYPE_VLAN)
586 continue;
587
588 unreg_members =
589 cpsw_ale_get_vlan_unreg_mcast(ale_entry,
590 ale->vlan_field_bits);
591 if (add)
592 unreg_members |= unreg_mcast_mask;
593 else
594 unreg_members &= ~unreg_mcast_mask;
595 cpsw_ale_set_vlan_unreg_mcast(ale_entry, unreg_members,
596 ale->vlan_field_bits);
597 cpsw_ale_write(ale, idx, ale_entry);
598 }
599 }
600
601 void cpsw_ale_set_allmulti(struct cpsw_ale *ale, int allmulti, int port)
602 {
603 u32 ale_entry[ALE_ENTRY_WORDS];
604 int unreg_mcast = 0;
605 int type, idx;
606
607 for (idx = 0; idx < ale->params.ale_entries; idx++) {
608 int vlan_members;
609
610 cpsw_ale_read(ale, idx, ale_entry);
611 type = cpsw_ale_get_entry_type(ale_entry);
612 if (type != ALE_TYPE_VLAN)
613 continue;
614 vlan_members =
615 cpsw_ale_get_vlan_member_list(ale_entry,
616 ale->vlan_field_bits);
617
618 if (port != -1 && !(vlan_members & BIT(port)))
619 continue;
620
621 unreg_mcast =
622 cpsw_ale_get_vlan_unreg_mcast(ale_entry,
623 ale->vlan_field_bits);
624 if (allmulti)
625 unreg_mcast |= ALE_PORT_HOST;
626 else
627 unreg_mcast &= ~ALE_PORT_HOST;
628 cpsw_ale_set_vlan_unreg_mcast(ale_entry, unreg_mcast,
629 ale->vlan_field_bits);
630 cpsw_ale_write(ale, idx, ale_entry);
631 }
632 }
633
634 struct ale_control_info {
635 const char *name;
636 int offset, port_offset;
637 int shift, port_shift;
638 int bits;
639 };
640
641 static struct ale_control_info ale_controls[ALE_NUM_CONTROLS] = {
642 [ALE_ENABLE] = {
643 .name = "enable",
644 .offset = ALE_CONTROL,
645 .port_offset = 0,
646 .shift = 31,
647 .port_shift = 0,
648 .bits = 1,
649 },
650 [ALE_CLEAR] = {
651 .name = "clear",
652 .offset = ALE_CONTROL,
653 .port_offset = 0,
654 .shift = 30,
655 .port_shift = 0,
656 .bits = 1,
657 },
658 [ALE_AGEOUT] = {
659 .name = "ageout",
660 .offset = ALE_CONTROL,
661 .port_offset = 0,
662 .shift = 29,
663 .port_shift = 0,
664 .bits = 1,
665 },
666 [ALE_P0_UNI_FLOOD] = {
667 .name = "port0_unicast_flood",
668 .offset = ALE_CONTROL,
669 .port_offset = 0,
670 .shift = 8,
671 .port_shift = 0,
672 .bits = 1,
673 },
674 [ALE_VLAN_NOLEARN] = {
675 .name = "vlan_nolearn",
676 .offset = ALE_CONTROL,
677 .port_offset = 0,
678 .shift = 7,
679 .port_shift = 0,
680 .bits = 1,
681 },
682 [ALE_NO_PORT_VLAN] = {
683 .name = "no_port_vlan",
684 .offset = ALE_CONTROL,
685 .port_offset = 0,
686 .shift = 6,
687 .port_shift = 0,
688 .bits = 1,
689 },
690 [ALE_OUI_DENY] = {
691 .name = "oui_deny",
692 .offset = ALE_CONTROL,
693 .port_offset = 0,
694 .shift = 5,
695 .port_shift = 0,
696 .bits = 1,
697 },
698 [ALE_BYPASS] = {
699 .name = "bypass",
700 .offset = ALE_CONTROL,
701 .port_offset = 0,
702 .shift = 4,
703 .port_shift = 0,
704 .bits = 1,
705 },
706 [ALE_RATE_LIMIT_TX] = {
707 .name = "rate_limit_tx",
708 .offset = ALE_CONTROL,
709 .port_offset = 0,
710 .shift = 3,
711 .port_shift = 0,
712 .bits = 1,
713 },
714 [ALE_VLAN_AWARE] = {
715 .name = "vlan_aware",
716 .offset = ALE_CONTROL,
717 .port_offset = 0,
718 .shift = 2,
719 .port_shift = 0,
720 .bits = 1,
721 },
722 [ALE_AUTH_ENABLE] = {
723 .name = "auth_enable",
724 .offset = ALE_CONTROL,
725 .port_offset = 0,
726 .shift = 1,
727 .port_shift = 0,
728 .bits = 1,
729 },
730 [ALE_RATE_LIMIT] = {
731 .name = "rate_limit",
732 .offset = ALE_CONTROL,
733 .port_offset = 0,
734 .shift = 0,
735 .port_shift = 0,
736 .bits = 1,
737 },
738 [ALE_PORT_STATE] = {
739 .name = "port_state",
740 .offset = ALE_PORTCTL,
741 .port_offset = 4,
742 .shift = 0,
743 .port_shift = 0,
744 .bits = 2,
745 },
746 [ALE_PORT_DROP_UNTAGGED] = {
747 .name = "drop_untagged",
748 .offset = ALE_PORTCTL,
749 .port_offset = 4,
750 .shift = 2,
751 .port_shift = 0,
752 .bits = 1,
753 },
754 [ALE_PORT_DROP_UNKNOWN_VLAN] = {
755 .name = "drop_unknown",
756 .offset = ALE_PORTCTL,
757 .port_offset = 4,
758 .shift = 3,
759 .port_shift = 0,
760 .bits = 1,
761 },
762 [ALE_PORT_NOLEARN] = {
763 .name = "nolearn",
764 .offset = ALE_PORTCTL,
765 .port_offset = 4,
766 .shift = 4,
767 .port_shift = 0,
768 .bits = 1,
769 },
770 [ALE_PORT_NO_SA_UPDATE] = {
771 .name = "no_source_update",
772 .offset = ALE_PORTCTL,
773 .port_offset = 4,
774 .shift = 5,
775 .port_shift = 0,
776 .bits = 1,
777 },
778 [ALE_PORT_MCAST_LIMIT] = {
779 .name = "mcast_limit",
780 .offset = ALE_PORTCTL,
781 .port_offset = 4,
782 .shift = 16,
783 .port_shift = 0,
784 .bits = 8,
785 },
786 [ALE_PORT_BCAST_LIMIT] = {
787 .name = "bcast_limit",
788 .offset = ALE_PORTCTL,
789 .port_offset = 4,
790 .shift = 24,
791 .port_shift = 0,
792 .bits = 8,
793 },
794 [ALE_PORT_UNKNOWN_VLAN_MEMBER] = {
795 .name = "unknown_vlan_member",
796 .offset = ALE_UNKNOWNVLAN,
797 .port_offset = 0,
798 .shift = 0,
799 .port_shift = 0,
800 .bits = 6,
801 },
802 [ALE_PORT_UNKNOWN_MCAST_FLOOD] = {
803 .name = "unknown_mcast_flood",
804 .offset = ALE_UNKNOWNVLAN,
805 .port_offset = 0,
806 .shift = 8,
807 .port_shift = 0,
808 .bits = 6,
809 },
810 [ALE_PORT_UNKNOWN_REG_MCAST_FLOOD] = {
811 .name = "unknown_reg_flood",
812 .offset = ALE_UNKNOWNVLAN,
813 .port_offset = 0,
814 .shift = 16,
815 .port_shift = 0,
816 .bits = 6,
817 },
818 [ALE_PORT_UNTAGGED_EGRESS] = {
819 .name = "untagged_egress",
820 .offset = ALE_UNKNOWNVLAN,
821 .port_offset = 0,
822 .shift = 24,
823 .port_shift = 0,
824 .bits = 6,
825 },
826 };
827
828 int cpsw_ale_control_set(struct cpsw_ale *ale, int port, int control,
829 int value)
830 {
831 const struct ale_control_info *info;
832 int offset, shift;
833 u32 tmp, mask;
834
835 if (control < 0 || control >= ARRAY_SIZE(ale_controls))
836 return -EINVAL;
837
838 info = &ale_controls[control];
839 if (info->port_offset == 0 && info->port_shift == 0)
840 port = 0; /* global, port is a dont care */
841
842 if (port < 0 || port >= ale->params.ale_ports)
843 return -EINVAL;
844
845 mask = BITMASK(info->bits);
846 if (value & ~mask)
847 return -EINVAL;
848
849 offset = info->offset + (port * info->port_offset);
850 shift = info->shift + (port * info->port_shift);
851
852 tmp = readl_relaxed(ale->params.ale_regs + offset);
853 tmp = (tmp & ~(mask << shift)) | (value << shift);
854 writel_relaxed(tmp, ale->params.ale_regs + offset);
855
856 return 0;
857 }
858
859 int cpsw_ale_control_get(struct cpsw_ale *ale, int port, int control)
860 {
861 const struct ale_control_info *info;
862 int offset, shift;
863 u32 tmp;
864
865 if (control < 0 || control >= ARRAY_SIZE(ale_controls))
866 return -EINVAL;
867
868 info = &ale_controls[control];
869 if (info->port_offset == 0 && info->port_shift == 0)
870 port = 0; /* global, port is a dont care */
871
872 if (port < 0 || port >= ale->params.ale_ports)
873 return -EINVAL;
874
875 offset = info->offset + (port * info->port_offset);
876 shift = info->shift + (port * info->port_shift);
877
878 tmp = readl_relaxed(ale->params.ale_regs + offset) >> shift;
879 return tmp & BITMASK(info->bits);
880 }
881
882 static void cpsw_ale_timer(struct timer_list *t)
883 {
884 struct cpsw_ale *ale = from_timer(ale, t, timer);
885
886 cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
887
888 if (ale->ageout) {
889 ale->timer.expires = jiffies + ale->ageout;
890 add_timer(&ale->timer);
891 }
892 }
893
894 void cpsw_ale_start(struct cpsw_ale *ale)
895 {
896 cpsw_ale_control_set(ale, 0, ALE_ENABLE, 1);
897 cpsw_ale_control_set(ale, 0, ALE_CLEAR, 1);
898
899 timer_setup(&ale->timer, cpsw_ale_timer, 0);
900 if (ale->ageout) {
901 ale->timer.expires = jiffies + ale->ageout;
902 add_timer(&ale->timer);
903 }
904 }
905
906 void cpsw_ale_stop(struct cpsw_ale *ale)
907 {
908 del_timer_sync(&ale->timer);
909 cpsw_ale_control_set(ale, 0, ALE_CLEAR, 1);
910 cpsw_ale_control_set(ale, 0, ALE_ENABLE, 0);
911 }
912
913 struct cpsw_ale *cpsw_ale_create(struct cpsw_ale_params *params)
914 {
915 struct cpsw_ale *ale;
916 u32 rev, ale_entries;
917
918 ale = devm_kzalloc(params->dev, sizeof(*ale), GFP_KERNEL);
919 if (!ale)
920 return NULL;
921
922 ale->p0_untag_vid_mask =
923 devm_kmalloc_array(params->dev, BITS_TO_LONGS(VLAN_N_VID),
924 sizeof(unsigned long),
925 GFP_KERNEL);
926 if (!ale->p0_untag_vid_mask)
927 return ERR_PTR(-ENOMEM);
928
929 ale->params = *params;
930 ale->ageout = ale->params.ale_ageout * HZ;
931
932 rev = readl_relaxed(ale->params.ale_regs + ALE_IDVER);
933 if (!ale->params.major_ver_mask)
934 ale->params.major_ver_mask = 0xff;
935 ale->version =
936 (ALE_VERSION_MAJOR(rev, ale->params.major_ver_mask) << 8) |
937 ALE_VERSION_MINOR(rev);
938 dev_info(ale->params.dev, "initialized cpsw ale version %d.%d\n",
939 ALE_VERSION_MAJOR(rev, ale->params.major_ver_mask),
940 ALE_VERSION_MINOR(rev));
941
942 if (!ale->params.ale_entries) {
943 ale_entries =
944 readl_relaxed(ale->params.ale_regs + ALE_STATUS) &
945 ALE_STATUS_SIZE_MASK;
946 /* ALE available on newer NetCP switches has introduced
947 * a register, ALE_STATUS, to indicate the size of ALE
948 * table which shows the size as a multiple of 1024 entries.
949 * For these, params.ale_entries will be set to zero. So
950 * read the register and update the value of ale_entries.
951 * ALE table on NetCP lite, is much smaller and is indicated
952 * by a value of zero in ALE_STATUS. So use a default value
953 * of ALE_TABLE_SIZE_DEFAULT for this. Caller is expected
954 * to set the value of ale_entries for all other versions
955 * of ALE.
956 */
957 if (!ale_entries)
958 ale_entries = ALE_TABLE_SIZE_DEFAULT;
959 else
960 ale_entries *= ALE_TABLE_SIZE_MULTIPLIER;
961 ale->params.ale_entries = ale_entries;
962 }
963 dev_info(ale->params.dev,
964 "ALE Table size %ld\n", ale->params.ale_entries);
965
966 /* set default bits for existing h/w */
967 ale->port_mask_bits = ale->params.ale_ports;
968 ale->port_num_bits = order_base_2(ale->params.ale_ports);
969 ale->vlan_field_bits = ale->params.ale_ports;
970
971 /* Set defaults override for ALE on NetCP NU switch and for version
972 * 1R3
973 */
974 if (ale->params.nu_switch_ale) {
975 /* Separate registers for unknown vlan configuration.
976 * Also there are N bits, where N is number of ale
977 * ports and shift value should be 0
978 */
979 ale_controls[ALE_PORT_UNKNOWN_VLAN_MEMBER].bits =
980 ale->params.ale_ports;
981 ale_controls[ALE_PORT_UNKNOWN_VLAN_MEMBER].offset =
982 ALE_UNKNOWNVLAN_MEMBER;
983 ale_controls[ALE_PORT_UNKNOWN_MCAST_FLOOD].bits =
984 ale->params.ale_ports;
985 ale_controls[ALE_PORT_UNKNOWN_MCAST_FLOOD].shift = 0;
986 ale_controls[ALE_PORT_UNKNOWN_MCAST_FLOOD].offset =
987 ALE_UNKNOWNVLAN_UNREG_MCAST_FLOOD;
988 ale_controls[ALE_PORT_UNKNOWN_REG_MCAST_FLOOD].bits =
989 ale->params.ale_ports;
990 ale_controls[ALE_PORT_UNKNOWN_REG_MCAST_FLOOD].shift = 0;
991 ale_controls[ALE_PORT_UNKNOWN_REG_MCAST_FLOOD].offset =
992 ALE_UNKNOWNVLAN_REG_MCAST_FLOOD;
993 ale_controls[ALE_PORT_UNTAGGED_EGRESS].bits =
994 ale->params.ale_ports;
995 ale_controls[ALE_PORT_UNTAGGED_EGRESS].shift = 0;
996 ale_controls[ALE_PORT_UNTAGGED_EGRESS].offset =
997 ALE_UNKNOWNVLAN_FORCE_UNTAG_EGRESS;
998 }
999
1000 cpsw_ale_control_set(ale, 0, ALE_CLEAR, 1);
1001 return ale;
1002 }
1003
1004 void cpsw_ale_dump(struct cpsw_ale *ale, u32 *data)
1005 {
1006 int i;
1007
1008 for (i = 0; i < ale->params.ale_entries; i++) {
1009 cpsw_ale_read(ale, i, data);
1010 data += ALE_ENTRY_WORDS;
1011 }
1012 }
Linux with added FPC-III support