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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / net / ethernet / ti / davinci_emac.c
blob75d4e16c692b604d01ad835b9336162e55920d8f
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * DaVinci Ethernet Medium Access Controller
4 *
5 * DaVinci EMAC is based upon CPPI 3.0 TI DMA engine
6 *
7 * Copyright (C) 2009 Texas Instruments.
8 *
9 * ---------------------------------------------------------------------------
10 * History:
11 * 0-5 A number of folks worked on this driver in bits and pieces but the major
12 * contribution came from Suraj Iyer and Anant Gole
13 * 6.0 Anant Gole - rewrote the driver as per Linux conventions
14 * 6.1 Chaithrika U S - added support for Gigabit and RMII features,
15 * PHY layer usage
16 */
17
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/sched.h>
21 #include <linux/string.h>
22 #include <linux/timer.h>
23 #include <linux/errno.h>
24 #include <linux/in.h>
25 #include <linux/ioport.h>
26 #include <linux/slab.h>
27 #include <linux/mm.h>
28 #include <linux/interrupt.h>
29 #include <linux/init.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/skbuff.h>
33 #include <linux/ethtool.h>
34 #include <linux/highmem.h>
35 #include <linux/proc_fs.h>
36 #include <linux/ctype.h>
37 #include <linux/spinlock.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/clk.h>
40 #include <linux/platform_device.h>
41 #include <linux/regmap.h>
42 #include <linux/semaphore.h>
43 #include <linux/phy.h>
44 #include <linux/bitops.h>
45 #include <linux/io.h>
46 #include <linux/uaccess.h>
47 #include <linux/pm_runtime.h>
48 #include <linux/davinci_emac.h>
49 #include <linux/of.h>
50 #include <linux/of_address.h>
51 #include <linux/of_device.h>
52 #include <linux/of_mdio.h>
53 #include <linux/of_irq.h>
54 #include <linux/of_net.h>
55 #include <linux/mfd/syscon.h>
56
57 #include <asm/irq.h>
58 #include <asm/page.h>
59
60 #include "cpsw.h"
61 #include "davinci_cpdma.h"
62
63 static int debug_level;
64 module_param(debug_level, int, 0);
65 MODULE_PARM_DESC(debug_level, "DaVinci EMAC debug level (NETIF_MSG bits)");
66
67 /* Netif debug messages possible */
68 #define DAVINCI_EMAC_DEBUG (NETIF_MSG_DRV | \
69 NETIF_MSG_PROBE | \
70 NETIF_MSG_LINK | \
71 NETIF_MSG_TIMER | \
72 NETIF_MSG_IFDOWN | \
73 NETIF_MSG_IFUP | \
74 NETIF_MSG_RX_ERR | \
75 NETIF_MSG_TX_ERR | \
76 NETIF_MSG_TX_QUEUED | \
77 NETIF_MSG_INTR | \
78 NETIF_MSG_TX_DONE | \
79 NETIF_MSG_RX_STATUS | \
80 NETIF_MSG_PKTDATA | \
81 NETIF_MSG_HW | \
82 NETIF_MSG_WOL)
83
84 /* version info */
85 #define EMAC_MAJOR_VERSION 6
86 #define EMAC_MINOR_VERSION 1
87 #define EMAC_MODULE_VERSION "6.1"
88 MODULE_VERSION(EMAC_MODULE_VERSION);
89 static const char emac_version_string[] = "TI DaVinci EMAC Linux v6.1";
90
91 /* Configuration items */
92 #define EMAC_DEF_PASS_CRC (0) /* Do not pass CRC up to frames */
93 #define EMAC_DEF_QOS_EN (0) /* EMAC proprietary QoS disabled */
94 #define EMAC_DEF_NO_BUFF_CHAIN (0) /* No buffer chain */
95 #define EMAC_DEF_MACCTRL_FRAME_EN (0) /* Discard Maccontrol frames */
96 #define EMAC_DEF_SHORT_FRAME_EN (0) /* Discard short frames */
97 #define EMAC_DEF_ERROR_FRAME_EN (0) /* Discard error frames */
98 #define EMAC_DEF_PROM_EN (0) /* Promiscuous disabled */
99 #define EMAC_DEF_PROM_CH (0) /* Promiscuous channel is 0 */
100 #define EMAC_DEF_BCAST_EN (1) /* Broadcast enabled */
101 #define EMAC_DEF_BCAST_CH (0) /* Broadcast channel is 0 */
102 #define EMAC_DEF_MCAST_EN (1) /* Multicast enabled */
103 #define EMAC_DEF_MCAST_CH (0) /* Multicast channel is 0 */
104
105 #define EMAC_DEF_TXPRIO_FIXED (1) /* TX Priority is fixed */
106 #define EMAC_DEF_TXPACING_EN (0) /* TX pacing NOT supported*/
107
108 #define EMAC_DEF_BUFFER_OFFSET (0) /* Buffer offset to DMA (future) */
109 #define EMAC_DEF_MIN_ETHPKTSIZE (60) /* Minimum ethernet pkt size */
110 #define EMAC_DEF_MAX_FRAME_SIZE (1500 + 14 + 4 + 4)
111 #define EMAC_DEF_TX_CH (0) /* Default 0th channel */
112 #define EMAC_DEF_RX_CH (0) /* Default 0th channel */
113 #define EMAC_DEF_RX_NUM_DESC (128)
114 #define EMAC_DEF_MAX_TX_CH (1) /* Max TX channels configured */
115 #define EMAC_DEF_MAX_RX_CH (1) /* Max RX channels configured */
116 #define EMAC_POLL_WEIGHT (64) /* Default NAPI poll weight */
117
118 /* Buffer descriptor parameters */
119 #define EMAC_DEF_TX_MAX_SERVICE (32) /* TX max service BD's */
120 #define EMAC_DEF_RX_MAX_SERVICE (64) /* should = netdev->weight */
121
122 /* EMAC register related defines */
123 #define EMAC_ALL_MULTI_REG_VALUE (0xFFFFFFFF)
124 #define EMAC_NUM_MULTICAST_BITS (64)
125 #define EMAC_TX_CONTROL_TX_ENABLE_VAL (0x1)
126 #define EMAC_RX_CONTROL_RX_ENABLE_VAL (0x1)
127 #define EMAC_MAC_HOST_ERR_INTMASK_VAL (0x2)
128 #define EMAC_RX_UNICAST_CLEAR_ALL (0xFF)
129 #define EMAC_INT_MASK_CLEAR (0xFF)
130
131 /* RX MBP register bit positions */
132 #define EMAC_RXMBP_PASSCRC_MASK BIT(30)
133 #define EMAC_RXMBP_QOSEN_MASK BIT(29)
134 #define EMAC_RXMBP_NOCHAIN_MASK BIT(28)
135 #define EMAC_RXMBP_CMFEN_MASK BIT(24)
136 #define EMAC_RXMBP_CSFEN_MASK BIT(23)
137 #define EMAC_RXMBP_CEFEN_MASK BIT(22)
138 #define EMAC_RXMBP_CAFEN_MASK BIT(21)
139 #define EMAC_RXMBP_PROMCH_SHIFT (16)
140 #define EMAC_RXMBP_PROMCH_MASK (0x7 << 16)
141 #define EMAC_RXMBP_BROADEN_MASK BIT(13)
142 #define EMAC_RXMBP_BROADCH_SHIFT (8)
143 #define EMAC_RXMBP_BROADCH_MASK (0x7 << 8)
144 #define EMAC_RXMBP_MULTIEN_MASK BIT(5)
145 #define EMAC_RXMBP_MULTICH_SHIFT (0)
146 #define EMAC_RXMBP_MULTICH_MASK (0x7)
147 #define EMAC_RXMBP_CHMASK (0x7)
148
149 /* EMAC register definitions/bit maps used */
150 # define EMAC_MBP_RXPROMISC (0x00200000)
151 # define EMAC_MBP_PROMISCCH(ch) (((ch) & 0x7) << 16)
152 # define EMAC_MBP_RXBCAST (0x00002000)
153 # define EMAC_MBP_BCASTCHAN(ch) (((ch) & 0x7) << 8)
154 # define EMAC_MBP_RXMCAST (0x00000020)
155 # define EMAC_MBP_MCASTCHAN(ch) ((ch) & 0x7)
156
157 /* EMAC mac_control register */
158 #define EMAC_MACCONTROL_TXPTYPE BIT(9)
159 #define EMAC_MACCONTROL_TXPACEEN BIT(6)
160 #define EMAC_MACCONTROL_GMIIEN BIT(5)
161 #define EMAC_MACCONTROL_GIGABITEN BIT(7)
162 #define EMAC_MACCONTROL_FULLDUPLEXEN BIT(0)
163 #define EMAC_MACCONTROL_RMIISPEED_MASK BIT(15)
164
165 /* GIGABIT MODE related bits */
166 #define EMAC_DM646X_MACCONTORL_GIG BIT(7)
167 #define EMAC_DM646X_MACCONTORL_GIGFORCE BIT(17)
168
169 /* EMAC mac_status register */
170 #define EMAC_MACSTATUS_TXERRCODE_MASK (0xF00000)
171 #define EMAC_MACSTATUS_TXERRCODE_SHIFT (20)
172 #define EMAC_MACSTATUS_TXERRCH_MASK (0x7)
173 #define EMAC_MACSTATUS_TXERRCH_SHIFT (16)
174 #define EMAC_MACSTATUS_RXERRCODE_MASK (0xF000)
175 #define EMAC_MACSTATUS_RXERRCODE_SHIFT (12)
176 #define EMAC_MACSTATUS_RXERRCH_MASK (0x7)
177 #define EMAC_MACSTATUS_RXERRCH_SHIFT (8)
178
179 /* EMAC RX register masks */
180 #define EMAC_RX_MAX_LEN_MASK (0xFFFF)
181 #define EMAC_RX_BUFFER_OFFSET_MASK (0xFFFF)
182
183 /* MAC_IN_VECTOR (0x180) register bit fields */
184 #define EMAC_DM644X_MAC_IN_VECTOR_HOST_INT BIT(17)
185 #define EMAC_DM644X_MAC_IN_VECTOR_STATPEND_INT BIT(16)
186 #define EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC BIT(8)
187 #define EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC BIT(0)
188
189 /** NOTE:: For DM646x the IN_VECTOR has changed */
190 #define EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC BIT(EMAC_DEF_RX_CH)
191 #define EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC BIT(16 + EMAC_DEF_TX_CH)
192 #define EMAC_DM646X_MAC_IN_VECTOR_HOST_INT BIT(26)
193 #define EMAC_DM646X_MAC_IN_VECTOR_STATPEND_INT BIT(27)
194
195 /* CPPI bit positions */
196 #define EMAC_CPPI_SOP_BIT BIT(31)
197 #define EMAC_CPPI_EOP_BIT BIT(30)
198 #define EMAC_CPPI_OWNERSHIP_BIT BIT(29)
199 #define EMAC_CPPI_EOQ_BIT BIT(28)
200 #define EMAC_CPPI_TEARDOWN_COMPLETE_BIT BIT(27)
201 #define EMAC_CPPI_PASS_CRC_BIT BIT(26)
202 #define EMAC_RX_BD_BUF_SIZE (0xFFFF)
203 #define EMAC_BD_LENGTH_FOR_CACHE (16) /* only CPPI bytes */
204 #define EMAC_RX_BD_PKT_LENGTH_MASK (0xFFFF)
205
206 /* Max hardware defines */
207 #define EMAC_MAX_TXRX_CHANNELS (8) /* Max hardware channels */
208 #define EMAC_DEF_MAX_MULTICAST_ADDRESSES (64) /* Max mcast addr's */
209
210 /* EMAC Peripheral Device Register Memory Layout structure */
211 #define EMAC_MACINVECTOR 0x90
212
213 #define EMAC_DM646X_MACEOIVECTOR 0x94
214
215 #define EMAC_MACINTSTATRAW 0xB0
216 #define EMAC_MACINTSTATMASKED 0xB4
217 #define EMAC_MACINTMASKSET 0xB8
218 #define EMAC_MACINTMASKCLEAR 0xBC
219
220 #define EMAC_RXMBPENABLE 0x100
221 #define EMAC_RXUNICASTSET 0x104
222 #define EMAC_RXUNICASTCLEAR 0x108
223 #define EMAC_RXMAXLEN 0x10C
224 #define EMAC_RXBUFFEROFFSET 0x110
225 #define EMAC_RXFILTERLOWTHRESH 0x114
226
227 #define EMAC_MACCONTROL 0x160
228 #define EMAC_MACSTATUS 0x164
229 #define EMAC_EMCONTROL 0x168
230 #define EMAC_FIFOCONTROL 0x16C
231 #define EMAC_MACCONFIG 0x170
232 #define EMAC_SOFTRESET 0x174
233 #define EMAC_MACSRCADDRLO 0x1D0
234 #define EMAC_MACSRCADDRHI 0x1D4
235 #define EMAC_MACHASH1 0x1D8
236 #define EMAC_MACHASH2 0x1DC
237 #define EMAC_MACADDRLO 0x500
238 #define EMAC_MACADDRHI 0x504
239 #define EMAC_MACINDEX 0x508
240
241 /* EMAC statistics registers */
242 #define EMAC_RXGOODFRAMES 0x200
243 #define EMAC_RXBCASTFRAMES 0x204
244 #define EMAC_RXMCASTFRAMES 0x208
245 #define EMAC_RXPAUSEFRAMES 0x20C
246 #define EMAC_RXCRCERRORS 0x210
247 #define EMAC_RXALIGNCODEERRORS 0x214
248 #define EMAC_RXOVERSIZED 0x218
249 #define EMAC_RXJABBER 0x21C
250 #define EMAC_RXUNDERSIZED 0x220
251 #define EMAC_RXFRAGMENTS 0x224
252 #define EMAC_RXFILTERED 0x228
253 #define EMAC_RXQOSFILTERED 0x22C
254 #define EMAC_RXOCTETS 0x230
255 #define EMAC_TXGOODFRAMES 0x234
256 #define EMAC_TXBCASTFRAMES 0x238
257 #define EMAC_TXMCASTFRAMES 0x23C
258 #define EMAC_TXPAUSEFRAMES 0x240
259 #define EMAC_TXDEFERRED 0x244
260 #define EMAC_TXCOLLISION 0x248
261 #define EMAC_TXSINGLECOLL 0x24C
262 #define EMAC_TXMULTICOLL 0x250
263 #define EMAC_TXEXCESSIVECOLL 0x254
264 #define EMAC_TXLATECOLL 0x258
265 #define EMAC_TXUNDERRUN 0x25C
266 #define EMAC_TXCARRIERSENSE 0x260
267 #define EMAC_TXOCTETS 0x264
268 #define EMAC_NETOCTETS 0x280
269 #define EMAC_RXSOFOVERRUNS 0x284
270 #define EMAC_RXMOFOVERRUNS 0x288
271 #define EMAC_RXDMAOVERRUNS 0x28C
272
273 /* EMAC DM644x control registers */
274 #define EMAC_CTRL_EWCTL (0x4)
275 #define EMAC_CTRL_EWINTTCNT (0x8)
276
277 /* EMAC DM644x control module masks */
278 #define EMAC_DM644X_EWINTCNT_MASK 0x1FFFF
279 #define EMAC_DM644X_INTMIN_INTVL 0x1
280 #define EMAC_DM644X_INTMAX_INTVL (EMAC_DM644X_EWINTCNT_MASK)
281
282 /* EMAC DM646X control module registers */
283 #define EMAC_DM646X_CMINTCTRL 0x0C
284 #define EMAC_DM646X_CMRXINTEN 0x14
285 #define EMAC_DM646X_CMTXINTEN 0x18
286 #define EMAC_DM646X_CMRXINTMAX 0x70
287 #define EMAC_DM646X_CMTXINTMAX 0x74
288
289 /* EMAC DM646X control module masks */
290 #define EMAC_DM646X_INTPACEEN (0x3 << 16)
291 #define EMAC_DM646X_INTPRESCALE_MASK (0x7FF << 0)
292 #define EMAC_DM646X_CMINTMAX_CNT 63
293 #define EMAC_DM646X_CMINTMIN_CNT 2
294 #define EMAC_DM646X_CMINTMAX_INTVL (1000 / EMAC_DM646X_CMINTMIN_CNT)
295 #define EMAC_DM646X_CMINTMIN_INTVL ((1000 / EMAC_DM646X_CMINTMAX_CNT) + 1)
296
297
298 /* EMAC EOI codes for C0 */
299 #define EMAC_DM646X_MAC_EOI_C0_RXEN (0x01)
300 #define EMAC_DM646X_MAC_EOI_C0_TXEN (0x02)
301
302 /* EMAC Stats Clear Mask */
303 #define EMAC_STATS_CLR_MASK (0xFFFFFFFF)
304
305 /* emac_priv: EMAC private data structure
306 *
307 * EMAC adapter private data structure
308 */
309 struct emac_priv {
310 u32 msg_enable;
311 struct net_device *ndev;
312 struct platform_device *pdev;
313 struct napi_struct napi;
314 char mac_addr[6];
315 void __iomem *remap_addr;
316 u32 emac_base_phys;
317 void __iomem *emac_base;
318 void __iomem *ctrl_base;
319 struct cpdma_ctlr *dma;
320 struct cpdma_chan *txchan;
321 struct cpdma_chan *rxchan;
322 u32 link; /* 1=link on, 0=link off */
323 u32 speed; /* 0=Auto Neg, 1=No PHY, 10,100, 1000 - mbps */
324 u32 duplex; /* Link duplex: 0=Half, 1=Full */
325 u32 rx_buf_size;
326 u32 isr_count;
327 u32 coal_intvl;
328 u32 bus_freq_mhz;
329 u8 rmii_en;
330 u8 version;
331 u32 mac_hash1;
332 u32 mac_hash2;
333 u32 multicast_hash_cnt[EMAC_NUM_MULTICAST_BITS];
334 u32 rx_addr_type;
335 const char *phy_id;
336 struct device_node *phy_node;
337 spinlock_t lock;
338 /*platform specific members*/
339 void (*int_enable) (void);
340 void (*int_disable) (void);
341 };
342
343 /* EMAC TX Host Error description strings */
344 static char *emac_txhost_errcodes[16] = {
345 "No error", "SOP error", "Ownership bit not set in SOP buffer",
346 "Zero Next Buffer Descriptor Pointer Without EOP",
347 "Zero Buffer Pointer", "Zero Buffer Length", "Packet Length Error",
348 "Reserved", "Reserved", "Reserved", "Reserved", "Reserved",
349 "Reserved", "Reserved", "Reserved", "Reserved"
350 };
351
352 /* EMAC RX Host Error description strings */
353 static char *emac_rxhost_errcodes[16] = {
354 "No error", "Reserved", "Ownership bit not set in input buffer",
355 "Reserved", "Zero Buffer Pointer", "Reserved", "Reserved",
356 "Reserved", "Reserved", "Reserved", "Reserved", "Reserved",
357 "Reserved", "Reserved", "Reserved", "Reserved"
358 };
359
360 /* Helper macros */
361 #define emac_read(reg) ioread32(priv->emac_base + (reg))
362 #define emac_write(reg, val) iowrite32(val, priv->emac_base + (reg))
363
364 #define emac_ctrl_read(reg) ioread32((priv->ctrl_base + (reg)))
365 #define emac_ctrl_write(reg, val) iowrite32(val, (priv->ctrl_base + (reg)))
366
367 /**
368 * emac_get_drvinfo - Get EMAC driver information
369 * @ndev: The DaVinci EMAC network adapter
370 * @info: ethtool info structure containing name and version
371 *
372 * Returns EMAC driver information (name and version)
373 *
374 */
375 static void emac_get_drvinfo(struct net_device *ndev,
376 struct ethtool_drvinfo *info)
377 {
378 strlcpy(info->driver, emac_version_string, sizeof(info->driver));
379 strlcpy(info->version, EMAC_MODULE_VERSION, sizeof(info->version));
380 }
381
382 /**
383 * emac_get_coalesce - Get interrupt coalesce settings for this device
384 * @ndev : The DaVinci EMAC network adapter
385 * @coal : ethtool coalesce settings structure
386 *
387 * Fetch the current interrupt coalesce settings
388 *
389 */
390 static int emac_get_coalesce(struct net_device *ndev,
391 struct ethtool_coalesce *coal)
392 {
393 struct emac_priv *priv = netdev_priv(ndev);
394
395 coal->rx_coalesce_usecs = priv->coal_intvl;
396 return 0;
397
398 }
399
400 /**
401 * emac_set_coalesce - Set interrupt coalesce settings for this device
402 * @ndev : The DaVinci EMAC network adapter
403 * @coal : ethtool coalesce settings structure
404 *
405 * Set interrupt coalesce parameters
406 *
407 */
408 static int emac_set_coalesce(struct net_device *ndev,
409 struct ethtool_coalesce *coal)
410 {
411 struct emac_priv *priv = netdev_priv(ndev);
412 u32 int_ctrl, num_interrupts = 0;
413 u32 prescale = 0, addnl_dvdr = 1, coal_intvl = 0;
414
415 if (!coal->rx_coalesce_usecs)
416 return -EINVAL;
417
418 coal_intvl = coal->rx_coalesce_usecs;
419
420 switch (priv->version) {
421 case EMAC_VERSION_2:
422 int_ctrl = emac_ctrl_read(EMAC_DM646X_CMINTCTRL);
423 prescale = priv->bus_freq_mhz * 4;
424
425 if (coal_intvl < EMAC_DM646X_CMINTMIN_INTVL)
426 coal_intvl = EMAC_DM646X_CMINTMIN_INTVL;
427
428 if (coal_intvl > EMAC_DM646X_CMINTMAX_INTVL) {
429 /*
430 * Interrupt pacer works with 4us Pulse, we can
431 * throttle further by dilating the 4us pulse.
432 */
433 addnl_dvdr = EMAC_DM646X_INTPRESCALE_MASK / prescale;
434
435 if (addnl_dvdr > 1) {
436 prescale *= addnl_dvdr;
437 if (coal_intvl > (EMAC_DM646X_CMINTMAX_INTVL
438 * addnl_dvdr))
439 coal_intvl = (EMAC_DM646X_CMINTMAX_INTVL
440 * addnl_dvdr);
441 } else {
442 addnl_dvdr = 1;
443 coal_intvl = EMAC_DM646X_CMINTMAX_INTVL;
444 }
445 }
446
447 num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
448
449 int_ctrl |= EMAC_DM646X_INTPACEEN;
450 int_ctrl &= (~EMAC_DM646X_INTPRESCALE_MASK);
451 int_ctrl |= (prescale & EMAC_DM646X_INTPRESCALE_MASK);
452 emac_ctrl_write(EMAC_DM646X_CMINTCTRL, int_ctrl);
453
454 emac_ctrl_write(EMAC_DM646X_CMRXINTMAX, num_interrupts);
455 emac_ctrl_write(EMAC_DM646X_CMTXINTMAX, num_interrupts);
456
457 break;
458 default:
459 int_ctrl = emac_ctrl_read(EMAC_CTRL_EWINTTCNT);
460 int_ctrl &= (~EMAC_DM644X_EWINTCNT_MASK);
461 prescale = coal_intvl * priv->bus_freq_mhz;
462 if (prescale > EMAC_DM644X_EWINTCNT_MASK) {
463 prescale = EMAC_DM644X_EWINTCNT_MASK;
464 coal_intvl = prescale / priv->bus_freq_mhz;
465 }
466 emac_ctrl_write(EMAC_CTRL_EWINTTCNT, (int_ctrl | prescale));
467
468 break;
469 }
470
471 printk(KERN_INFO"Set coalesce to %d usecs.\n", coal_intvl);
472 priv->coal_intvl = coal_intvl;
473
474 return 0;
475
476 }
477
478
479 /* ethtool_ops: DaVinci EMAC Ethtool structure
480 *
481 * Ethtool support for EMAC adapter
482 */
483 static const struct ethtool_ops ethtool_ops = {
484 .get_drvinfo = emac_get_drvinfo,
485 .get_link = ethtool_op_get_link,
486 .get_coalesce = emac_get_coalesce,
487 .set_coalesce = emac_set_coalesce,
488 .get_ts_info = ethtool_op_get_ts_info,
489 .get_link_ksettings = phy_ethtool_get_link_ksettings,
490 .set_link_ksettings = phy_ethtool_set_link_ksettings,
491 };
492
493 /**
494 * emac_update_phystatus - Update Phy status
495 * @priv: The DaVinci EMAC private adapter structure
496 *
497 * Updates phy status and takes action for network queue if required
498 * based upon link status
499 *
500 */
501 static void emac_update_phystatus(struct emac_priv *priv)
502 {
503 u32 mac_control;
504 u32 new_duplex;
505 u32 cur_duplex;
506 struct net_device *ndev = priv->ndev;
507
508 mac_control = emac_read(EMAC_MACCONTROL);
509 cur_duplex = (mac_control & EMAC_MACCONTROL_FULLDUPLEXEN) ?
510 DUPLEX_FULL : DUPLEX_HALF;
511 if (ndev->phydev)
512 new_duplex = ndev->phydev->duplex;
513 else
514 new_duplex = DUPLEX_FULL;
515
516 /* We get called only if link has changed (speed/duplex/status) */
517 if ((priv->link) && (new_duplex != cur_duplex)) {
518 priv->duplex = new_duplex;
519 if (DUPLEX_FULL == priv->duplex)
520 mac_control |= (EMAC_MACCONTROL_FULLDUPLEXEN);
521 else
522 mac_control &= ~(EMAC_MACCONTROL_FULLDUPLEXEN);
523 }
524
525 if (priv->speed == SPEED_1000 && (priv->version == EMAC_VERSION_2)) {
526 mac_control = emac_read(EMAC_MACCONTROL);
527 mac_control |= (EMAC_DM646X_MACCONTORL_GIG |
528 EMAC_DM646X_MACCONTORL_GIGFORCE);
529 } else {
530 /* Clear the GIG bit and GIGFORCE bit */
531 mac_control &= ~(EMAC_DM646X_MACCONTORL_GIGFORCE |
532 EMAC_DM646X_MACCONTORL_GIG);
533
534 if (priv->rmii_en && (priv->speed == SPEED_100))
535 mac_control |= EMAC_MACCONTROL_RMIISPEED_MASK;
536 else
537 mac_control &= ~EMAC_MACCONTROL_RMIISPEED_MASK;
538 }
539
540 /* Update mac_control if changed */
541 emac_write(EMAC_MACCONTROL, mac_control);
542
543 if (priv->link) {
544 /* link ON */
545 if (!netif_carrier_ok(ndev))
546 netif_carrier_on(ndev);
547 /* reactivate the transmit queue if it is stopped */
548 if (netif_running(ndev) && netif_queue_stopped(ndev))
549 netif_wake_queue(ndev);
550 } else {
551 /* link OFF */
552 if (netif_carrier_ok(ndev))
553 netif_carrier_off(ndev);
554 if (!netif_queue_stopped(ndev))
555 netif_stop_queue(ndev);
556 }
557 }
558
559 /**
560 * hash_get - Calculate hash value from mac address
561 * @addr: mac address to delete from hash table
562 *
563 * Calculates hash value from mac address
564 *
565 */
566 static u32 hash_get(u8 *addr)
567 {
568 u32 hash;
569 u8 tmpval;
570 int cnt;
571 hash = 0;
572
573 for (cnt = 0; cnt < 2; cnt++) {
574 tmpval = *addr++;
575 hash ^= (tmpval >> 2) ^ (tmpval << 4);
576 tmpval = *addr++;
577 hash ^= (tmpval >> 4) ^ (tmpval << 2);
578 tmpval = *addr++;
579 hash ^= (tmpval >> 6) ^ (tmpval);
580 }
581
582 return hash & 0x3F;
583 }
584
585 /**
586 * emac_hash_add - Hash function to add mac addr from hash table
587 * @priv: The DaVinci EMAC private adapter structure
588 * @mac_addr: mac address to delete from hash table
589 *
590 * Adds mac address to the internal hash table
591 *
592 */
593 static int emac_hash_add(struct emac_priv *priv, u8 *mac_addr)
594 {
595 struct device *emac_dev = &priv->ndev->dev;
596 u32 rc = 0;
597 u32 hash_bit;
598 u32 hash_value = hash_get(mac_addr);
599
600 if (hash_value >= EMAC_NUM_MULTICAST_BITS) {
601 if (netif_msg_drv(priv)) {
602 dev_err(emac_dev, "DaVinci EMAC: emac_hash_add(): Invalid "\
603 "Hash %08x, should not be greater than %08x",
604 hash_value, (EMAC_NUM_MULTICAST_BITS - 1));
605 }
606 return -1;
607 }
608
609 /* set the hash bit only if not previously set */
610 if (priv->multicast_hash_cnt[hash_value] == 0) {
611 rc = 1; /* hash value changed */
612 if (hash_value < 32) {
613 hash_bit = BIT(hash_value);
614 priv->mac_hash1 |= hash_bit;
615 } else {
616 hash_bit = BIT((hash_value - 32));
617 priv->mac_hash2 |= hash_bit;
618 }
619 }
620
621 /* incr counter for num of mcast addr's mapped to "this" hash bit */
622 ++priv->multicast_hash_cnt[hash_value];
623
624 return rc;
625 }
626
627 /**
628 * emac_hash_del - Hash function to delete mac addr from hash table
629 * @priv: The DaVinci EMAC private adapter structure
630 * @mac_addr: mac address to delete from hash table
631 *
632 * Removes mac address from the internal hash table
633 *
634 */
635 static int emac_hash_del(struct emac_priv *priv, u8 *mac_addr)
636 {
637 u32 hash_value;
638 u32 hash_bit;
639
640 hash_value = hash_get(mac_addr);
641 if (priv->multicast_hash_cnt[hash_value] > 0) {
642 /* dec cntr for num of mcast addr's mapped to this hash bit */
643 --priv->multicast_hash_cnt[hash_value];
644 }
645
646 /* if counter still > 0, at least one multicast address refers
647 * to this hash bit. so return 0 */
648 if (priv->multicast_hash_cnt[hash_value] > 0)
649 return 0;
650
651 if (hash_value < 32) {
652 hash_bit = BIT(hash_value);
653 priv->mac_hash1 &= ~hash_bit;
654 } else {
655 hash_bit = BIT((hash_value - 32));
656 priv->mac_hash2 &= ~hash_bit;
657 }
658
659 /* return 1 to indicate change in mac_hash registers reqd */
660 return 1;
661 }
662
663 /* EMAC multicast operation */
664 #define EMAC_MULTICAST_ADD 0
665 #define EMAC_MULTICAST_DEL 1
666 #define EMAC_ALL_MULTI_SET 2
667 #define EMAC_ALL_MULTI_CLR 3
668
669 /**
670 * emac_add_mcast - Set multicast address in the EMAC adapter (Internal)
671 * @priv: The DaVinci EMAC private adapter structure
672 * @action: multicast operation to perform
673 * mac_addr: mac address to set
674 *
675 * Set multicast addresses in EMAC adapter - internal function
676 *
677 */
678 static void emac_add_mcast(struct emac_priv *priv, u32 action, u8 *mac_addr)
679 {
680 struct device *emac_dev = &priv->ndev->dev;
681 int update = -1;
682
683 switch (action) {
684 case EMAC_MULTICAST_ADD:
685 update = emac_hash_add(priv, mac_addr);
686 break;
687 case EMAC_MULTICAST_DEL:
688 update = emac_hash_del(priv, mac_addr);
689 break;
690 case EMAC_ALL_MULTI_SET:
691 update = 1;
692 priv->mac_hash1 = EMAC_ALL_MULTI_REG_VALUE;
693 priv->mac_hash2 = EMAC_ALL_MULTI_REG_VALUE;
694 break;
695 case EMAC_ALL_MULTI_CLR:
696 update = 1;
697 priv->mac_hash1 = 0;
698 priv->mac_hash2 = 0;
699 memset(&(priv->multicast_hash_cnt[0]), 0,
700 sizeof(priv->multicast_hash_cnt[0]) *
701 EMAC_NUM_MULTICAST_BITS);
702 break;
703 default:
704 if (netif_msg_drv(priv))
705 dev_err(emac_dev, "DaVinci EMAC: add_mcast"\
706 ": bad operation %d", action);
707 break;
708 }
709
710 /* write to the hardware only if the register status chances */
711 if (update > 0) {
712 emac_write(EMAC_MACHASH1, priv->mac_hash1);
713 emac_write(EMAC_MACHASH2, priv->mac_hash2);
714 }
715 }
716
717 /**
718 * emac_dev_mcast_set - Set multicast address in the EMAC adapter
719 * @ndev: The DaVinci EMAC network adapter
720 *
721 * Set multicast addresses in EMAC adapter
722 *
723 */
724 static void emac_dev_mcast_set(struct net_device *ndev)
725 {
726 u32 mbp_enable;
727 struct emac_priv *priv = netdev_priv(ndev);
728
729 mbp_enable = emac_read(EMAC_RXMBPENABLE);
730 if (ndev->flags & IFF_PROMISC) {
731 mbp_enable &= (~EMAC_MBP_PROMISCCH(EMAC_DEF_PROM_CH));
732 mbp_enable |= (EMAC_MBP_RXPROMISC);
733 } else {
734 mbp_enable = (mbp_enable & ~EMAC_MBP_RXPROMISC);
735 if ((ndev->flags & IFF_ALLMULTI) ||
736 netdev_mc_count(ndev) > EMAC_DEF_MAX_MULTICAST_ADDRESSES) {
737 mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST);
738 emac_add_mcast(priv, EMAC_ALL_MULTI_SET, NULL);
739 } else if (!netdev_mc_empty(ndev)) {
740 struct netdev_hw_addr *ha;
741
742 mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST);
743 emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL);
744 /* program multicast address list into EMAC hardware */
745 netdev_for_each_mc_addr(ha, ndev) {
746 emac_add_mcast(priv, EMAC_MULTICAST_ADD,
747 (u8 *) ha->addr);
748 }
749 } else {
750 mbp_enable = (mbp_enable & ~EMAC_MBP_RXMCAST);
751 emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL);
752 }
753 }
754 /* Set mbp config register */
755 emac_write(EMAC_RXMBPENABLE, mbp_enable);
756 }
757
758 /*************************************************************************
759 * EMAC Hardware manipulation
760 *************************************************************************/
761
762 /**
763 * emac_int_disable - Disable EMAC module interrupt (from adapter)
764 * @priv: The DaVinci EMAC private adapter structure
765 *
766 * Disable EMAC interrupt on the adapter
767 *
768 */
769 static void emac_int_disable(struct emac_priv *priv)
770 {
771 if (priv->version == EMAC_VERSION_2) {
772 unsigned long flags;
773
774 local_irq_save(flags);
775
776 /* Program C0_Int_En to zero to turn off
777 * interrupts to the CPU */
778 emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0x0);
779 emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0x0);
780 /* NOTE: Rx Threshold and Misc interrupts are not disabled */
781 if (priv->int_disable)
782 priv->int_disable();
783
784 /* NOTE: Rx Threshold and Misc interrupts are not enabled */
785
786 /* ack rxen only then a new pulse will be generated */
787 emac_write(EMAC_DM646X_MACEOIVECTOR,
788 EMAC_DM646X_MAC_EOI_C0_RXEN);
789
790 /* ack txen- only then a new pulse will be generated */
791 emac_write(EMAC_DM646X_MACEOIVECTOR,
792 EMAC_DM646X_MAC_EOI_C0_TXEN);
793
794 local_irq_restore(flags);
795
796 } else {
797 /* Set DM644x control registers for interrupt control */
798 emac_ctrl_write(EMAC_CTRL_EWCTL, 0x0);
799 }
800 }
801
802 /**
803 * emac_int_enable - Enable EMAC module interrupt (from adapter)
804 * @priv: The DaVinci EMAC private adapter structure
805 *
806 * Enable EMAC interrupt on the adapter
807 *
808 */
809 static void emac_int_enable(struct emac_priv *priv)
810 {
811 if (priv->version == EMAC_VERSION_2) {
812 if (priv->int_enable)
813 priv->int_enable();
814
815 emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0xff);
816 emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0xff);
817
818 /* In addition to turning on interrupt Enable, we need
819 * ack by writing appropriate values to the EOI
820 * register */
821
822 /* NOTE: Rx Threshold and Misc interrupts are not enabled */
823 } else {
824 /* Set DM644x control registers for interrupt control */
825 emac_ctrl_write(EMAC_CTRL_EWCTL, 0x1);
826 }
827 }
828
829 /**
830 * emac_irq - EMAC interrupt handler
831 * @irq: interrupt number
832 * @dev_id: EMAC network adapter data structure ptr
833 *
834 * EMAC Interrupt handler - we only schedule NAPI and not process any packets
835 * here. EVen the interrupt status is checked (TX/RX/Err) in NAPI poll function
836 *
837 * Returns interrupt handled condition
838 */
839 static irqreturn_t emac_irq(int irq, void *dev_id)
840 {
841 struct net_device *ndev = (struct net_device *)dev_id;
842 struct emac_priv *priv = netdev_priv(ndev);
843
844 ++priv->isr_count;
845 if (likely(netif_running(priv->ndev))) {
846 emac_int_disable(priv);
847 napi_schedule(&priv->napi);
848 } else {
849 /* we are closing down, so dont process anything */
850 }
851 return IRQ_HANDLED;
852 }
853
854 static struct sk_buff *emac_rx_alloc(struct emac_priv *priv)
855 {
856 struct sk_buff *skb = netdev_alloc_skb(priv->ndev, priv->rx_buf_size);
857 if (WARN_ON(!skb))
858 return NULL;
859 skb_reserve(skb, NET_IP_ALIGN);
860 return skb;
861 }
862
863 static void emac_rx_handler(void *token, int len, int status)
864 {
865 struct sk_buff *skb = token;
866 struct net_device *ndev = skb->dev;
867 struct emac_priv *priv = netdev_priv(ndev);
868 struct device *emac_dev = &ndev->dev;
869 int ret;
870
871 /* free and bail if we are shutting down */
872 if (unlikely(!netif_running(ndev))) {
873 dev_kfree_skb_any(skb);
874 return;
875 }
876
877 /* recycle on receive error */
878 if (status < 0) {
879 ndev->stats.rx_errors++;
880 goto recycle;
881 }
882
883 /* feed received packet up the stack */
884 skb_put(skb, len);
885 skb->protocol = eth_type_trans(skb, ndev);
886 netif_receive_skb(skb);
887 ndev->stats.rx_bytes += len;
888 ndev->stats.rx_packets++;
889
890 /* alloc a new packet for receive */
891 skb = emac_rx_alloc(priv);
892 if (!skb) {
893 if (netif_msg_rx_err(priv) && net_ratelimit())
894 dev_err(emac_dev, "failed rx buffer alloc\n");
895 return;
896 }
897
898 recycle:
899 ret = cpdma_chan_submit(priv->rxchan, skb, skb->data,
900 skb_tailroom(skb), 0);
901
902 WARN_ON(ret == -ENOMEM);
903 if (unlikely(ret < 0))
904 dev_kfree_skb_any(skb);
905 }
906
907 static void emac_tx_handler(void *token, int len, int status)
908 {
909 struct sk_buff *skb = token;
910 struct net_device *ndev = skb->dev;
911
912 /* Check whether the queue is stopped due to stalled tx dma, if the
913 * queue is stopped then start the queue as we have free desc for tx
914 */
915 if (unlikely(netif_queue_stopped(ndev)))
916 netif_wake_queue(ndev);
917 ndev->stats.tx_packets++;
918 ndev->stats.tx_bytes += len;
919 dev_kfree_skb_any(skb);
920 }
921
922 /**
923 * emac_dev_xmit - EMAC Transmit function
924 * @skb: SKB pointer
925 * @ndev: The DaVinci EMAC network adapter
926 *
927 * Called by the system to transmit a packet - we queue the packet in
928 * EMAC hardware transmit queue
929 *
930 * Returns success(NETDEV_TX_OK) or error code (typically out of desc's)
931 */
932 static int emac_dev_xmit(struct sk_buff *skb, struct net_device *ndev)
933 {
934 struct device *emac_dev = &ndev->dev;
935 int ret_code;
936 struct emac_priv *priv = netdev_priv(ndev);
937
938 /* If no link, return */
939 if (unlikely(!priv->link)) {
940 if (netif_msg_tx_err(priv) && net_ratelimit())
941 dev_err(emac_dev, "DaVinci EMAC: No link to transmit");
942 goto fail_tx;
943 }
944
945 ret_code = skb_padto(skb, EMAC_DEF_MIN_ETHPKTSIZE);
946 if (unlikely(ret_code < 0)) {
947 if (netif_msg_tx_err(priv) && net_ratelimit())
948 dev_err(emac_dev, "DaVinci EMAC: packet pad failed");
949 goto fail_tx;
950 }
951
952 skb_tx_timestamp(skb);
953
954 ret_code = cpdma_chan_submit(priv->txchan, skb, skb->data, skb->len,
955 0);
956 if (unlikely(ret_code != 0)) {
957 if (netif_msg_tx_err(priv) && net_ratelimit())
958 dev_err(emac_dev, "DaVinci EMAC: desc submit failed");
959 goto fail_tx;
960 }
961
962 /* If there is no more tx desc left free then we need to
963 * tell the kernel to stop sending us tx frames.
964 */
965 if (unlikely(!cpdma_check_free_tx_desc(priv->txchan)))
966 netif_stop_queue(ndev);
967
968 return NETDEV_TX_OK;
969
970 fail_tx:
971 ndev->stats.tx_dropped++;
972 netif_stop_queue(ndev);
973 return NETDEV_TX_BUSY;
974 }
975
976 /**
977 * emac_dev_tx_timeout - EMAC Transmit timeout function
978 * @ndev: The DaVinci EMAC network adapter
979 *
980 * Called when system detects that a skb timeout period has expired
981 * potentially due to a fault in the adapter in not being able to send
982 * it out on the wire. We teardown the TX channel assuming a hardware
983 * error and re-initialize the TX channel for hardware operation
984 *
985 */
986 static void emac_dev_tx_timeout(struct net_device *ndev, unsigned int txqueue)
987 {
988 struct emac_priv *priv = netdev_priv(ndev);
989 struct device *emac_dev = &ndev->dev;
990
991 if (netif_msg_tx_err(priv))
992 dev_err(emac_dev, "DaVinci EMAC: xmit timeout, restarting TX");
993
994 ndev->stats.tx_errors++;
995 emac_int_disable(priv);
996 cpdma_chan_stop(priv->txchan);
997 cpdma_chan_start(priv->txchan);
998 emac_int_enable(priv);
999 }
1000
1001 /**
1002 * emac_set_type0addr - Set EMAC Type0 mac address
1003 * @priv: The DaVinci EMAC private adapter structure
1004 * @ch: RX channel number
1005 * @mac_addr: MAC address to set in device
1006 *
1007 * Called internally to set Type0 mac address of the adapter (Device)
1008 *
1009 * Returns success (0) or appropriate error code (none as of now)
1010 */
1011 static void emac_set_type0addr(struct emac_priv *priv, u32 ch, char *mac_addr)
1012 {
1013 u32 val;
1014 val = ((mac_addr[5] << 8) | (mac_addr[4]));
1015 emac_write(EMAC_MACSRCADDRLO, val);
1016
1017 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1018 (mac_addr[1] << 8) | (mac_addr[0]));
1019 emac_write(EMAC_MACSRCADDRHI, val);
1020 val = emac_read(EMAC_RXUNICASTSET);
1021 val |= BIT(ch);
1022 emac_write(EMAC_RXUNICASTSET, val);
1023 val = emac_read(EMAC_RXUNICASTCLEAR);
1024 val &= ~BIT(ch);
1025 emac_write(EMAC_RXUNICASTCLEAR, val);
1026 }
1027
1028 /**
1029 * emac_set_type1addr - Set EMAC Type1 mac address
1030 * @priv: The DaVinci EMAC private adapter structure
1031 * @ch: RX channel number
1032 * @mac_addr: MAC address to set in device
1033 *
1034 * Called internally to set Type1 mac address of the adapter (Device)
1035 *
1036 * Returns success (0) or appropriate error code (none as of now)
1037 */
1038 static void emac_set_type1addr(struct emac_priv *priv, u32 ch, char *mac_addr)
1039 {
1040 u32 val;
1041 emac_write(EMAC_MACINDEX, ch);
1042 val = ((mac_addr[5] << 8) | mac_addr[4]);
1043 emac_write(EMAC_MACADDRLO, val);
1044 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1045 (mac_addr[1] << 8) | (mac_addr[0]));
1046 emac_write(EMAC_MACADDRHI, val);
1047 emac_set_type0addr(priv, ch, mac_addr);
1048 }
1049
1050 /**
1051 * emac_set_type2addr - Set EMAC Type2 mac address
1052 * @priv: The DaVinci EMAC private adapter structure
1053 * @ch: RX channel number
1054 * @mac_addr: MAC address to set in device
1055 * @index: index into RX address entries
1056 * @match: match parameter for RX address matching logic
1057 *
1058 * Called internally to set Type2 mac address of the adapter (Device)
1059 *
1060 * Returns success (0) or appropriate error code (none as of now)
1061 */
1062 static void emac_set_type2addr(struct emac_priv *priv, u32 ch,
1063 char *mac_addr, int index, int match)
1064 {
1065 u32 val;
1066 emac_write(EMAC_MACINDEX, index);
1067 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1068 (mac_addr[1] << 8) | (mac_addr[0]));
1069 emac_write(EMAC_MACADDRHI, val);
1070 val = ((mac_addr[5] << 8) | mac_addr[4] | ((ch & 0x7) << 16) | \
1071 (match << 19) | BIT(20));
1072 emac_write(EMAC_MACADDRLO, val);
1073 emac_set_type0addr(priv, ch, mac_addr);
1074 }
1075
1076 /**
1077 * emac_setmac - Set mac address in the adapter (internal function)
1078 * @priv: The DaVinci EMAC private adapter structure
1079 * @ch: RX channel number
1080 * @mac_addr: MAC address to set in device
1081 *
1082 * Called internally to set the mac address of the adapter (Device)
1083 *
1084 * Returns success (0) or appropriate error code (none as of now)
1085 */
1086 static void emac_setmac(struct emac_priv *priv, u32 ch, char *mac_addr)
1087 {
1088 struct device *emac_dev = &priv->ndev->dev;
1089
1090 if (priv->rx_addr_type == 0) {
1091 emac_set_type0addr(priv, ch, mac_addr);
1092 } else if (priv->rx_addr_type == 1) {
1093 u32 cnt;
1094 for (cnt = 0; cnt < EMAC_MAX_TXRX_CHANNELS; cnt++)
1095 emac_set_type1addr(priv, ch, mac_addr);
1096 } else if (priv->rx_addr_type == 2) {
1097 emac_set_type2addr(priv, ch, mac_addr, ch, 1);
1098 emac_set_type0addr(priv, ch, mac_addr);
1099 } else {
1100 if (netif_msg_drv(priv))
1101 dev_err(emac_dev, "DaVinci EMAC: Wrong addressing\n");
1102 }
1103 }
1104
1105 /**
1106 * emac_dev_setmac_addr - Set mac address in the adapter
1107 * @ndev: The DaVinci EMAC network adapter
1108 * @addr: MAC address to set in device
1109 *
1110 * Called by the system to set the mac address of the adapter (Device)
1111 *
1112 * Returns success (0) or appropriate error code (none as of now)
1113 */
1114 static int emac_dev_setmac_addr(struct net_device *ndev, void *addr)
1115 {
1116 struct emac_priv *priv = netdev_priv(ndev);
1117 struct device *emac_dev = &priv->ndev->dev;
1118 struct sockaddr *sa = addr;
1119
1120 if (!is_valid_ether_addr(sa->sa_data))
1121 return -EADDRNOTAVAIL;
1122
1123 /* Store mac addr in priv and rx channel and set it in EMAC hw */
1124 memcpy(priv->mac_addr, sa->sa_data, ndev->addr_len);
1125 memcpy(ndev->dev_addr, sa->sa_data, ndev->addr_len);
1126
1127 /* MAC address is configured only after the interface is enabled. */
1128 if (netif_running(ndev)) {
1129 emac_setmac(priv, EMAC_DEF_RX_CH, priv->mac_addr);
1130 }
1131
1132 if (netif_msg_drv(priv))
1133 dev_notice(emac_dev, "DaVinci EMAC: emac_dev_setmac_addr %pM\n",
1134 priv->mac_addr);
1135
1136 return 0;
1137 }
1138
1139 /**
1140 * emac_hw_enable - Enable EMAC hardware for packet transmission/reception
1141 * @priv: The DaVinci EMAC private adapter structure
1142 *
1143 * Enables EMAC hardware for packet processing - enables PHY, enables RX
1144 * for packet reception and enables device interrupts and then NAPI
1145 *
1146 * Returns success (0) or appropriate error code (none right now)
1147 */
1148 static int emac_hw_enable(struct emac_priv *priv)
1149 {
1150 u32 val, mbp_enable, mac_control;
1151
1152 /* Soft reset */
1153 emac_write(EMAC_SOFTRESET, 1);
1154 while (emac_read(EMAC_SOFTRESET))
1155 cpu_relax();
1156
1157 /* Disable interrupt & Set pacing for more interrupts initially */
1158 emac_int_disable(priv);
1159
1160 /* Full duplex enable bit set when auto negotiation happens */
1161 mac_control =
1162 (((EMAC_DEF_TXPRIO_FIXED) ? (EMAC_MACCONTROL_TXPTYPE) : 0x0) |
1163 ((priv->speed == 1000) ? EMAC_MACCONTROL_GIGABITEN : 0x0) |
1164 ((EMAC_DEF_TXPACING_EN) ? (EMAC_MACCONTROL_TXPACEEN) : 0x0) |
1165 ((priv->duplex == DUPLEX_FULL) ? 0x1 : 0));
1166 emac_write(EMAC_MACCONTROL, mac_control);
1167
1168 mbp_enable =
1169 (((EMAC_DEF_PASS_CRC) ? (EMAC_RXMBP_PASSCRC_MASK) : 0x0) |
1170 ((EMAC_DEF_QOS_EN) ? (EMAC_RXMBP_QOSEN_MASK) : 0x0) |
1171 ((EMAC_DEF_NO_BUFF_CHAIN) ? (EMAC_RXMBP_NOCHAIN_MASK) : 0x0) |
1172 ((EMAC_DEF_MACCTRL_FRAME_EN) ? (EMAC_RXMBP_CMFEN_MASK) : 0x0) |
1173 ((EMAC_DEF_SHORT_FRAME_EN) ? (EMAC_RXMBP_CSFEN_MASK) : 0x0) |
1174 ((EMAC_DEF_ERROR_FRAME_EN) ? (EMAC_RXMBP_CEFEN_MASK) : 0x0) |
1175 ((EMAC_DEF_PROM_EN) ? (EMAC_RXMBP_CAFEN_MASK) : 0x0) |
1176 ((EMAC_DEF_PROM_CH & EMAC_RXMBP_CHMASK) << \
1177 EMAC_RXMBP_PROMCH_SHIFT) |
1178 ((EMAC_DEF_BCAST_EN) ? (EMAC_RXMBP_BROADEN_MASK) : 0x0) |
1179 ((EMAC_DEF_BCAST_CH & EMAC_RXMBP_CHMASK) << \
1180 EMAC_RXMBP_BROADCH_SHIFT) |
1181 ((EMAC_DEF_MCAST_EN) ? (EMAC_RXMBP_MULTIEN_MASK) : 0x0) |
1182 ((EMAC_DEF_MCAST_CH & EMAC_RXMBP_CHMASK) << \
1183 EMAC_RXMBP_MULTICH_SHIFT));
1184 emac_write(EMAC_RXMBPENABLE, mbp_enable);
1185 emac_write(EMAC_RXMAXLEN, (EMAC_DEF_MAX_FRAME_SIZE &
1186 EMAC_RX_MAX_LEN_MASK));
1187 emac_write(EMAC_RXBUFFEROFFSET, (EMAC_DEF_BUFFER_OFFSET &
1188 EMAC_RX_BUFFER_OFFSET_MASK));
1189 emac_write(EMAC_RXFILTERLOWTHRESH, 0);
1190 emac_write(EMAC_RXUNICASTCLEAR, EMAC_RX_UNICAST_CLEAR_ALL);
1191 priv->rx_addr_type = (emac_read(EMAC_MACCONFIG) >> 8) & 0xFF;
1192
1193 emac_write(EMAC_MACINTMASKSET, EMAC_MAC_HOST_ERR_INTMASK_VAL);
1194
1195 emac_setmac(priv, EMAC_DEF_RX_CH, priv->mac_addr);
1196
1197 /* Enable MII */
1198 val = emac_read(EMAC_MACCONTROL);
1199 val |= (EMAC_MACCONTROL_GMIIEN);
1200 emac_write(EMAC_MACCONTROL, val);
1201
1202 /* Enable NAPI and interrupts */
1203 napi_enable(&priv->napi);
1204 emac_int_enable(priv);
1205 return 0;
1206
1207 }
1208
1209 /**
1210 * emac_poll - EMAC NAPI Poll function
1211 * @ndev: The DaVinci EMAC network adapter
1212 * @budget: Number of receive packets to process (as told by NAPI layer)
1213 *
1214 * NAPI Poll function implemented to process packets as per budget. We check
1215 * the type of interrupt on the device and accordingly call the TX or RX
1216 * packet processing functions. We follow the budget for RX processing and
1217 * also put a cap on number of TX pkts processed through config param. The
1218 * NAPI schedule function is called if more packets pending.
1219 *
1220 * Returns number of packets received (in most cases; else TX pkts - rarely)
1221 */
1222 static int emac_poll(struct napi_struct *napi, int budget)
1223 {
1224 unsigned int mask;
1225 struct emac_priv *priv = container_of(napi, struct emac_priv, napi);
1226 struct net_device *ndev = priv->ndev;
1227 struct device *emac_dev = &ndev->dev;
1228 u32 status = 0;
1229 u32 num_tx_pkts = 0, num_rx_pkts = 0;
1230
1231 /* Check interrupt vectors and call packet processing */
1232 status = emac_read(EMAC_MACINVECTOR);
1233
1234 mask = EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC;
1235
1236 if (priv->version == EMAC_VERSION_2)
1237 mask = EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC;
1238
1239 if (status & mask) {
1240 num_tx_pkts = cpdma_chan_process(priv->txchan,
1241 EMAC_DEF_TX_MAX_SERVICE);
1242 } /* TX processing */
1243
1244 mask = EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC;
1245
1246 if (priv->version == EMAC_VERSION_2)
1247 mask = EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC;
1248
1249 if (status & mask) {
1250 num_rx_pkts = cpdma_chan_process(priv->rxchan, budget);
1251 } /* RX processing */
1252
1253 mask = EMAC_DM644X_MAC_IN_VECTOR_HOST_INT;
1254 if (priv->version == EMAC_VERSION_2)
1255 mask = EMAC_DM646X_MAC_IN_VECTOR_HOST_INT;
1256
1257 if (unlikely(status & mask)) {
1258 u32 ch, cause;
1259 dev_err(emac_dev, "DaVinci EMAC: Fatal Hardware Error\n");
1260 netif_stop_queue(ndev);
1261 napi_disable(&priv->napi);
1262
1263 status = emac_read(EMAC_MACSTATUS);
1264 cause = ((status & EMAC_MACSTATUS_TXERRCODE_MASK) >>
1265 EMAC_MACSTATUS_TXERRCODE_SHIFT);
1266 if (cause) {
1267 ch = ((status & EMAC_MACSTATUS_TXERRCH_MASK) >>
1268 EMAC_MACSTATUS_TXERRCH_SHIFT);
1269 if (net_ratelimit()) {
1270 dev_err(emac_dev, "TX Host error %s on ch=%d\n",
1271 &emac_txhost_errcodes[cause][0], ch);
1272 }
1273 }
1274 cause = ((status & EMAC_MACSTATUS_RXERRCODE_MASK) >>
1275 EMAC_MACSTATUS_RXERRCODE_SHIFT);
1276 if (cause) {
1277 ch = ((status & EMAC_MACSTATUS_RXERRCH_MASK) >>
1278 EMAC_MACSTATUS_RXERRCH_SHIFT);
1279 if (netif_msg_hw(priv) && net_ratelimit())
1280 dev_err(emac_dev, "RX Host error %s on ch=%d\n",
1281 &emac_rxhost_errcodes[cause][0], ch);
1282 }
1283 } else if (num_rx_pkts < budget) {
1284 napi_complete_done(napi, num_rx_pkts);
1285 emac_int_enable(priv);
1286 }
1287
1288 return num_rx_pkts;
1289 }
1290
1291 #ifdef CONFIG_NET_POLL_CONTROLLER
1292 /**
1293 * emac_poll_controller - EMAC Poll controller function
1294 * @ndev: The DaVinci EMAC network adapter
1295 *
1296 * Polled functionality used by netconsole and others in non interrupt mode
1297 *
1298 */
1299 static void emac_poll_controller(struct net_device *ndev)
1300 {
1301 struct emac_priv *priv = netdev_priv(ndev);
1302
1303 emac_int_disable(priv);
1304 emac_irq(ndev->irq, ndev);
1305 emac_int_enable(priv);
1306 }
1307 #endif
1308
1309 static void emac_adjust_link(struct net_device *ndev)
1310 {
1311 struct emac_priv *priv = netdev_priv(ndev);
1312 struct phy_device *phydev = ndev->phydev;
1313 unsigned long flags;
1314 int new_state = 0;
1315
1316 spin_lock_irqsave(&priv->lock, flags);
1317
1318 if (phydev->link) {
1319 /* check the mode of operation - full/half duplex */
1320 if (phydev->duplex != priv->duplex) {
1321 new_state = 1;
1322 priv->duplex = phydev->duplex;
1323 }
1324 if (phydev->speed != priv->speed) {
1325 new_state = 1;
1326 priv->speed = phydev->speed;
1327 }
1328 if (!priv->link) {
1329 new_state = 1;
1330 priv->link = 1;
1331 }
1332
1333 } else if (priv->link) {
1334 new_state = 1;
1335 priv->link = 0;
1336 priv->speed = 0;
1337 priv->duplex = ~0;
1338 }
1339 if (new_state) {
1340 emac_update_phystatus(priv);
1341 phy_print_status(ndev->phydev);
1342 }
1343
1344 spin_unlock_irqrestore(&priv->lock, flags);
1345 }
1346
1347 /*************************************************************************
1348 * Linux Driver Model
1349 *************************************************************************/
1350
1351 /**
1352 * emac_devioctl - EMAC adapter ioctl
1353 * @ndev: The DaVinci EMAC network adapter
1354 * @ifrq: request parameter
1355 * @cmd: command parameter
1356 *
1357 * EMAC driver ioctl function
1358 *
1359 * Returns success(0) or appropriate error code
1360 */
1361 static int emac_devioctl(struct net_device *ndev, struct ifreq *ifrq, int cmd)
1362 {
1363 if (!(netif_running(ndev)))
1364 return -EINVAL;
1365
1366 /* TODO: Add phy read and write and private statistics get feature */
1367
1368 if (ndev->phydev)
1369 return phy_mii_ioctl(ndev->phydev, ifrq, cmd);
1370 else
1371 return -EOPNOTSUPP;
1372 }
1373
1374 static int match_first_device(struct device *dev, const void *data)
1375 {
1376 if (dev->parent && dev->parent->of_node)
1377 return of_device_is_compatible(dev->parent->of_node,
1378 "ti,davinci_mdio");
1379
1380 return !strncmp(dev_name(dev), "davinci_mdio", 12);
1381 }
1382
1383 /**
1384 * emac_dev_open - EMAC device open
1385 * @ndev: The DaVinci EMAC network adapter
1386 *
1387 * Called when system wants to start the interface. We init TX/RX channels
1388 * and enable the hardware for packet reception/transmission and start the
1389 * network queue.
1390 *
1391 * Returns 0 for a successful open, or appropriate error code
1392 */
1393 static int emac_dev_open(struct net_device *ndev)
1394 {
1395 struct device *emac_dev = &ndev->dev;
1396 u32 cnt;
1397 struct resource *res;
1398 int q, m, ret;
1399 int res_num = 0, irq_num = 0;
1400 int i = 0;
1401 struct emac_priv *priv = netdev_priv(ndev);
1402 struct phy_device *phydev = NULL;
1403 struct device *phy = NULL;
1404
1405 ret = pm_runtime_get_sync(&priv->pdev->dev);
1406 if (ret < 0) {
1407 pm_runtime_put_noidle(&priv->pdev->dev);
1408 dev_err(&priv->pdev->dev, "%s: failed to get_sync(%d)\n",
1409 __func__, ret);
1410 return ret;
1411 }
1412
1413 netif_carrier_off(ndev);
1414 for (cnt = 0; cnt < ETH_ALEN; cnt++)
1415 ndev->dev_addr[cnt] = priv->mac_addr[cnt];
1416
1417 /* Configuration items */
1418 priv->rx_buf_size = EMAC_DEF_MAX_FRAME_SIZE + NET_IP_ALIGN;
1419
1420 priv->mac_hash1 = 0;
1421 priv->mac_hash2 = 0;
1422 emac_write(EMAC_MACHASH1, 0);
1423 emac_write(EMAC_MACHASH2, 0);
1424
1425 for (i = 0; i < EMAC_DEF_RX_NUM_DESC; i++) {
1426 struct sk_buff *skb = emac_rx_alloc(priv);
1427
1428 if (!skb)
1429 break;
1430
1431 ret = cpdma_chan_idle_submit(priv->rxchan, skb, skb->data,
1432 skb_tailroom(skb), 0);
1433 if (WARN_ON(ret < 0))
1434 break;
1435 }
1436
1437 /* Request IRQ */
1438 while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ,
1439 res_num))) {
1440 for (irq_num = res->start; irq_num <= res->end; irq_num++) {
1441 if (request_irq(irq_num, emac_irq, 0, ndev->name,
1442 ndev)) {
1443 dev_err(emac_dev,
1444 "DaVinci EMAC: request_irq() failed\n");
1445 ret = -EBUSY;
1446
1447 goto rollback;
1448 }
1449 }
1450 res_num++;
1451 }
1452 /* prepare counters for rollback in case of an error */
1453 res_num--;
1454 irq_num--;
1455
1456 /* Start/Enable EMAC hardware */
1457 emac_hw_enable(priv);
1458
1459 /* Enable Interrupt pacing if configured */
1460 if (priv->coal_intvl != 0) {
1461 struct ethtool_coalesce coal;
1462
1463 coal.rx_coalesce_usecs = (priv->coal_intvl << 4);
1464 emac_set_coalesce(ndev, &coal);
1465 }
1466
1467 cpdma_ctlr_start(priv->dma);
1468
1469 if (priv->phy_node) {
1470 phydev = of_phy_connect(ndev, priv->phy_node,
1471 &emac_adjust_link, 0, 0);
1472 if (!phydev) {
1473 dev_err(emac_dev, "could not connect to phy %pOF\n",
1474 priv->phy_node);
1475 ret = -ENODEV;
1476 goto err;
1477 }
1478 }
1479
1480 /* use the first phy on the bus if pdata did not give us a phy id */
1481 if (!phydev && !priv->phy_id) {
1482 /* NOTE: we can't use bus_find_device_by_name() here because
1483 * the device name is not guaranteed to be 'davinci_mdio'. On
1484 * some systems it can be 'davinci_mdio.0' so we need to use
1485 * strncmp() against the first part of the string to correctly
1486 * match it.
1487 */
1488 phy = bus_find_device(&mdio_bus_type, NULL, NULL,
1489 match_first_device);
1490 if (phy) {
1491 priv->phy_id = dev_name(phy);
1492 if (!priv->phy_id || !*priv->phy_id)
1493 put_device(phy);
1494 }
1495 }
1496
1497 if (!phydev && priv->phy_id && *priv->phy_id) {
1498 phydev = phy_connect(ndev, priv->phy_id,
1499 &emac_adjust_link,
1500 PHY_INTERFACE_MODE_MII);
1501 put_device(phy); /* reference taken by bus_find_device */
1502 if (IS_ERR(phydev)) {
1503 dev_err(emac_dev, "could not connect to phy %s\n",
1504 priv->phy_id);
1505 ret = PTR_ERR(phydev);
1506 goto err;
1507 }
1508
1509 priv->link = 0;
1510 priv->speed = 0;
1511 priv->duplex = ~0;
1512
1513 phy_attached_info(phydev);
1514 }
1515
1516 if (!phydev) {
1517 /* No PHY , fix the link, speed and duplex settings */
1518 dev_notice(emac_dev, "no phy, defaulting to 100/full\n");
1519 priv->link = 1;
1520 priv->speed = SPEED_100;
1521 priv->duplex = DUPLEX_FULL;
1522 emac_update_phystatus(priv);
1523 }
1524
1525 if (netif_msg_drv(priv))
1526 dev_notice(emac_dev, "DaVinci EMAC: Opened %s\n", ndev->name);
1527
1528 if (phydev)
1529 phy_start(phydev);
1530
1531 return 0;
1532
1533 err:
1534 emac_int_disable(priv);
1535 napi_disable(&priv->napi);
1536
1537 rollback:
1538 for (q = res_num; q >= 0; q--) {
1539 res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, q);
1540 /* at the first iteration, irq_num is already set to the
1541 * right value
1542 */
1543 if (q != res_num)
1544 irq_num = res->end;
1545
1546 for (m = irq_num; m >= res->start; m--)
1547 free_irq(m, ndev);
1548 }
1549 cpdma_ctlr_stop(priv->dma);
1550 pm_runtime_put(&priv->pdev->dev);
1551 return ret;
1552 }
1553
1554 /**
1555 * emac_dev_stop - EMAC device stop
1556 * @ndev: The DaVinci EMAC network adapter
1557 *
1558 * Called when system wants to stop or down the interface. We stop the network
1559 * queue, disable interrupts and cleanup TX/RX channels.
1560 *
1561 * We return the statistics in net_device_stats structure pulled from emac
1562 */
1563 static int emac_dev_stop(struct net_device *ndev)
1564 {
1565 struct resource *res;
1566 int i = 0;
1567 int irq_num;
1568 struct emac_priv *priv = netdev_priv(ndev);
1569 struct device *emac_dev = &ndev->dev;
1570
1571 /* inform the upper layers. */
1572 netif_stop_queue(ndev);
1573 napi_disable(&priv->napi);
1574
1575 netif_carrier_off(ndev);
1576 emac_int_disable(priv);
1577 cpdma_ctlr_stop(priv->dma);
1578 emac_write(EMAC_SOFTRESET, 1);
1579
1580 if (ndev->phydev)
1581 phy_disconnect(ndev->phydev);
1582
1583 /* Free IRQ */
1584 while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, i))) {
1585 for (irq_num = res->start; irq_num <= res->end; irq_num++)
1586 free_irq(irq_num, priv->ndev);
1587 i++;
1588 }
1589
1590 if (netif_msg_drv(priv))
1591 dev_notice(emac_dev, "DaVinci EMAC: %s stopped\n", ndev->name);
1592
1593 pm_runtime_put(&priv->pdev->dev);
1594 return 0;
1595 }
1596
1597 /**
1598 * emac_dev_getnetstats - EMAC get statistics function
1599 * @ndev: The DaVinci EMAC network adapter
1600 *
1601 * Called when system wants to get statistics from the device.
1602 *
1603 * We return the statistics in net_device_stats structure pulled from emac
1604 */
1605 static struct net_device_stats *emac_dev_getnetstats(struct net_device *ndev)
1606 {
1607 struct emac_priv *priv = netdev_priv(ndev);
1608 u32 mac_control;
1609 u32 stats_clear_mask;
1610 int err;
1611
1612 err = pm_runtime_get_sync(&priv->pdev->dev);
1613 if (err < 0) {
1614 pm_runtime_put_noidle(&priv->pdev->dev);
1615 dev_err(&priv->pdev->dev, "%s: failed to get_sync(%d)\n",
1616 __func__, err);
1617 return &ndev->stats;
1618 }
1619
1620 /* update emac hardware stats and reset the registers*/
1621
1622 mac_control = emac_read(EMAC_MACCONTROL);
1623
1624 if (mac_control & EMAC_MACCONTROL_GMIIEN)
1625 stats_clear_mask = EMAC_STATS_CLR_MASK;
1626 else
1627 stats_clear_mask = 0;
1628
1629 ndev->stats.multicast += emac_read(EMAC_RXMCASTFRAMES);
1630 emac_write(EMAC_RXMCASTFRAMES, stats_clear_mask);
1631
1632 ndev->stats.collisions += (emac_read(EMAC_TXCOLLISION) +
1633 emac_read(EMAC_TXSINGLECOLL) +
1634 emac_read(EMAC_TXMULTICOLL));
1635 emac_write(EMAC_TXCOLLISION, stats_clear_mask);
1636 emac_write(EMAC_TXSINGLECOLL, stats_clear_mask);
1637 emac_write(EMAC_TXMULTICOLL, stats_clear_mask);
1638
1639 ndev->stats.rx_length_errors += (emac_read(EMAC_RXOVERSIZED) +
1640 emac_read(EMAC_RXJABBER) +
1641 emac_read(EMAC_RXUNDERSIZED));
1642 emac_write(EMAC_RXOVERSIZED, stats_clear_mask);
1643 emac_write(EMAC_RXJABBER, stats_clear_mask);
1644 emac_write(EMAC_RXUNDERSIZED, stats_clear_mask);
1645
1646 ndev->stats.rx_over_errors += (emac_read(EMAC_RXSOFOVERRUNS) +
1647 emac_read(EMAC_RXMOFOVERRUNS));
1648 emac_write(EMAC_RXSOFOVERRUNS, stats_clear_mask);
1649 emac_write(EMAC_RXMOFOVERRUNS, stats_clear_mask);
1650
1651 ndev->stats.rx_fifo_errors += emac_read(EMAC_RXDMAOVERRUNS);
1652 emac_write(EMAC_RXDMAOVERRUNS, stats_clear_mask);
1653
1654 ndev->stats.tx_carrier_errors +=
1655 emac_read(EMAC_TXCARRIERSENSE);
1656 emac_write(EMAC_TXCARRIERSENSE, stats_clear_mask);
1657
1658 ndev->stats.tx_fifo_errors += emac_read(EMAC_TXUNDERRUN);
1659 emac_write(EMAC_TXUNDERRUN, stats_clear_mask);
1660
1661 pm_runtime_put(&priv->pdev->dev);
1662
1663 return &ndev->stats;
1664 }
1665
1666 static const struct net_device_ops emac_netdev_ops = {
1667 .ndo_open = emac_dev_open,
1668 .ndo_stop = emac_dev_stop,
1669 .ndo_start_xmit = emac_dev_xmit,
1670 .ndo_set_rx_mode = emac_dev_mcast_set,
1671 .ndo_set_mac_address = emac_dev_setmac_addr,
1672 .ndo_do_ioctl = emac_devioctl,
1673 .ndo_tx_timeout = emac_dev_tx_timeout,
1674 .ndo_get_stats = emac_dev_getnetstats,
1675 #ifdef CONFIG_NET_POLL_CONTROLLER
1676 .ndo_poll_controller = emac_poll_controller,
1677 #endif
1678 };
1679
1680 static const struct of_device_id davinci_emac_of_match[];
1681
1682 static struct emac_platform_data *
1683 davinci_emac_of_get_pdata(struct platform_device *pdev, struct emac_priv *priv)
1684 {
1685 struct device_node *np;
1686 const struct of_device_id *match;
1687 const struct emac_platform_data *auxdata;
1688 struct emac_platform_data *pdata = NULL;
1689 const u8 *mac_addr;
1690
1691 if (!IS_ENABLED(CONFIG_OF) || !pdev->dev.of_node)
1692 return dev_get_platdata(&pdev->dev);
1693
1694 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1695 if (!pdata)
1696 return NULL;
1697
1698 np = pdev->dev.of_node;
1699 pdata->version = EMAC_VERSION_2;
1700
1701 if (!is_valid_ether_addr(pdata->mac_addr)) {
1702 mac_addr = of_get_mac_address(np);
1703 if (!IS_ERR(mac_addr))
1704 ether_addr_copy(pdata->mac_addr, mac_addr);
1705 }
1706
1707 of_property_read_u32(np, "ti,davinci-ctrl-reg-offset",
1708 &pdata->ctrl_reg_offset);
1709
1710 of_property_read_u32(np, "ti,davinci-ctrl-mod-reg-offset",
1711 &pdata->ctrl_mod_reg_offset);
1712
1713 of_property_read_u32(np, "ti,davinci-ctrl-ram-offset",
1714 &pdata->ctrl_ram_offset);
1715
1716 of_property_read_u32(np, "ti,davinci-ctrl-ram-size",
1717 &pdata->ctrl_ram_size);
1718
1719 of_property_read_u8(np, "ti,davinci-rmii-en", &pdata->rmii_en);
1720
1721 pdata->no_bd_ram = of_property_read_bool(np, "ti,davinci-no-bd-ram");
1722
1723 priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
1724 if (!priv->phy_node) {
1725 if (!of_phy_is_fixed_link(np))
1726 pdata->phy_id = NULL;
1727 else if (of_phy_register_fixed_link(np) >= 0)
1728 priv->phy_node = of_node_get(np);
1729 }
1730
1731 auxdata = pdev->dev.platform_data;
1732 if (auxdata) {
1733 pdata->interrupt_enable = auxdata->interrupt_enable;
1734 pdata->interrupt_disable = auxdata->interrupt_disable;
1735 }
1736
1737 match = of_match_device(davinci_emac_of_match, &pdev->dev);
1738 if (match && match->data) {
1739 auxdata = match->data;
1740 pdata->version = auxdata->version;
1741 pdata->hw_ram_addr = auxdata->hw_ram_addr;
1742 }
1743
1744 return pdata;
1745 }
1746
1747 static int davinci_emac_try_get_mac(struct platform_device *pdev,
1748 int instance, u8 *mac_addr)
1749 {
1750 if (!pdev->dev.of_node)
1751 return -EINVAL;
1752
1753 return ti_cm_get_macid(&pdev->dev, instance, mac_addr);
1754 }
1755
1756 /**
1757 * davinci_emac_probe - EMAC device probe
1758 * @pdev: The DaVinci EMAC device that we are removing
1759 *
1760 * Called when probing for emac devicesr. We get details of instances and
1761 * resource information from platform init and register a network device
1762 * and allocate resources necessary for driver to perform
1763 */
1764 static int davinci_emac_probe(struct platform_device *pdev)
1765 {
1766 struct device_node *np = pdev->dev.of_node;
1767 int rc = 0;
1768 struct resource *res, *res_ctrl;
1769 struct net_device *ndev;
1770 struct emac_priv *priv;
1771 unsigned long hw_ram_addr;
1772 struct emac_platform_data *pdata;
1773 struct cpdma_params dma_params;
1774 struct clk *emac_clk;
1775 unsigned long emac_bus_frequency;
1776
1777
1778 /* obtain emac clock from kernel */
1779 emac_clk = devm_clk_get(&pdev->dev, NULL);
1780 if (IS_ERR(emac_clk)) {
1781 dev_err(&pdev->dev, "failed to get EMAC clock\n");
1782 return -EBUSY;
1783 }
1784 emac_bus_frequency = clk_get_rate(emac_clk);
1785 devm_clk_put(&pdev->dev, emac_clk);
1786
1787 /* TODO: Probe PHY here if possible */
1788
1789 ndev = alloc_etherdev(sizeof(struct emac_priv));
1790 if (!ndev)
1791 return -ENOMEM;
1792
1793 platform_set_drvdata(pdev, ndev);
1794 priv = netdev_priv(ndev);
1795 priv->pdev = pdev;
1796 priv->ndev = ndev;
1797 priv->msg_enable = netif_msg_init(debug_level, DAVINCI_EMAC_DEBUG);
1798
1799 spin_lock_init(&priv->lock);
1800
1801 pdata = davinci_emac_of_get_pdata(pdev, priv);
1802 if (!pdata) {
1803 dev_err(&pdev->dev, "no platform data\n");
1804 rc = -ENODEV;
1805 goto err_free_netdev;
1806 }
1807
1808 /* MAC addr and PHY mask , RMII enable info from platform_data */
1809 memcpy(priv->mac_addr, pdata->mac_addr, ETH_ALEN);
1810 priv->phy_id = pdata->phy_id;
1811 priv->rmii_en = pdata->rmii_en;
1812 priv->version = pdata->version;
1813 priv->int_enable = pdata->interrupt_enable;
1814 priv->int_disable = pdata->interrupt_disable;
1815
1816 priv->coal_intvl = 0;
1817 priv->bus_freq_mhz = (u32)(emac_bus_frequency / 1000000);
1818
1819 /* Get EMAC platform data */
1820 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1821 priv->emac_base_phys = res->start + pdata->ctrl_reg_offset;
1822 priv->remap_addr = devm_ioremap_resource(&pdev->dev, res);
1823 if (IS_ERR(priv->remap_addr)) {
1824 rc = PTR_ERR(priv->remap_addr);
1825 goto no_pdata;
1826 }
1827
1828 res_ctrl = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1829 if (res_ctrl) {
1830 priv->ctrl_base =
1831 devm_ioremap_resource(&pdev->dev, res_ctrl);
1832 if (IS_ERR(priv->ctrl_base)) {
1833 rc = PTR_ERR(priv->ctrl_base);
1834 goto no_pdata;
1835 }
1836 } else {
1837 priv->ctrl_base = priv->remap_addr + pdata->ctrl_mod_reg_offset;
1838 }
1839
1840 priv->emac_base = priv->remap_addr + pdata->ctrl_reg_offset;
1841 ndev->base_addr = (unsigned long)priv->remap_addr;
1842
1843 hw_ram_addr = pdata->hw_ram_addr;
1844 if (!hw_ram_addr)
1845 hw_ram_addr = (u32 __force)res->start + pdata->ctrl_ram_offset;
1846
1847 memset(&dma_params, 0, sizeof(dma_params));
1848 dma_params.dev = &pdev->dev;
1849 dma_params.dmaregs = priv->emac_base;
1850 dma_params.rxthresh = priv->emac_base + 0x120;
1851 dma_params.rxfree = priv->emac_base + 0x140;
1852 dma_params.txhdp = priv->emac_base + 0x600;
1853 dma_params.rxhdp = priv->emac_base + 0x620;
1854 dma_params.txcp = priv->emac_base + 0x640;
1855 dma_params.rxcp = priv->emac_base + 0x660;
1856 dma_params.num_chan = EMAC_MAX_TXRX_CHANNELS;
1857 dma_params.min_packet_size = EMAC_DEF_MIN_ETHPKTSIZE;
1858 dma_params.desc_hw_addr = hw_ram_addr;
1859 dma_params.desc_mem_size = pdata->ctrl_ram_size;
1860 dma_params.desc_align = 16;
1861
1862 dma_params.desc_mem_phys = pdata->no_bd_ram ? 0 :
1863 (u32 __force)res->start + pdata->ctrl_ram_offset;
1864
1865 priv->dma = cpdma_ctlr_create(&dma_params);
1866 if (!priv->dma) {
1867 dev_err(&pdev->dev, "error initializing DMA\n");
1868 rc = -ENOMEM;
1869 goto no_pdata;
1870 }
1871
1872 priv->txchan = cpdma_chan_create(priv->dma, EMAC_DEF_TX_CH,
1873 emac_tx_handler, 0);
1874 if (IS_ERR(priv->txchan)) {
1875 dev_err(&pdev->dev, "error initializing tx dma channel\n");
1876 rc = PTR_ERR(priv->txchan);
1877 goto err_free_dma;
1878 }
1879
1880 priv->rxchan = cpdma_chan_create(priv->dma, EMAC_DEF_RX_CH,
1881 emac_rx_handler, 1);
1882 if (IS_ERR(priv->rxchan)) {
1883 dev_err(&pdev->dev, "error initializing rx dma channel\n");
1884 rc = PTR_ERR(priv->rxchan);
1885 goto err_free_txchan;
1886 }
1887
1888 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1889 if (!res) {
1890 dev_err(&pdev->dev, "error getting irq res\n");
1891 rc = -ENOENT;
1892 goto err_free_rxchan;
1893 }
1894 ndev->irq = res->start;
1895
1896 rc = davinci_emac_try_get_mac(pdev, res_ctrl ? 0 : 1, priv->mac_addr);
1897 if (!rc)
1898 ether_addr_copy(ndev->dev_addr, priv->mac_addr);
1899
1900 if (!is_valid_ether_addr(priv->mac_addr)) {
1901 /* Use random MAC if still none obtained. */
1902 eth_hw_addr_random(ndev);
1903 memcpy(priv->mac_addr, ndev->dev_addr, ndev->addr_len);
1904 dev_warn(&pdev->dev, "using random MAC addr: %pM\n",
1905 priv->mac_addr);
1906 }
1907
1908 ndev->netdev_ops = &emac_netdev_ops;
1909 ndev->ethtool_ops = &ethtool_ops;
1910 netif_napi_add(ndev, &priv->napi, emac_poll, EMAC_POLL_WEIGHT);
1911
1912 pm_runtime_enable(&pdev->dev);
1913 rc = pm_runtime_get_sync(&pdev->dev);
1914 if (rc < 0) {
1915 pm_runtime_put_noidle(&pdev->dev);
1916 dev_err(&pdev->dev, "%s: failed to get_sync(%d)\n",
1917 __func__, rc);
1918 goto err_napi_del;
1919 }
1920
1921 /* register the network device */
1922 SET_NETDEV_DEV(ndev, &pdev->dev);
1923 rc = register_netdev(ndev);
1924 if (rc) {
1925 dev_err(&pdev->dev, "error in register_netdev\n");
1926 rc = -ENODEV;
1927 pm_runtime_put(&pdev->dev);
1928 goto err_napi_del;
1929 }
1930
1931
1932 if (netif_msg_probe(priv)) {
1933 dev_notice(&pdev->dev, "DaVinci EMAC Probe found device "
1934 "(regs: %pa, irq: %d)\n",
1935 &priv->emac_base_phys, ndev->irq);
1936 }
1937 pm_runtime_put(&pdev->dev);
1938
1939 return 0;
1940
1941 err_napi_del:
1942 netif_napi_del(&priv->napi);
1943 err_free_rxchan:
1944 cpdma_chan_destroy(priv->rxchan);
1945 err_free_txchan:
1946 cpdma_chan_destroy(priv->txchan);
1947 err_free_dma:
1948 cpdma_ctlr_destroy(priv->dma);
1949 no_pdata:
1950 if (of_phy_is_fixed_link(np))
1951 of_phy_deregister_fixed_link(np);
1952 of_node_put(priv->phy_node);
1953 err_free_netdev:
1954 free_netdev(ndev);
1955 return rc;
1956 }
1957
1958 /**
1959 * davinci_emac_remove - EMAC device remove
1960 * @pdev: The DaVinci EMAC device that we are removing
1961 *
1962 * Called when removing the device driver. We disable clock usage and release
1963 * the resources taken up by the driver and unregister network device
1964 */
1965 static int davinci_emac_remove(struct platform_device *pdev)
1966 {
1967 struct net_device *ndev = platform_get_drvdata(pdev);
1968 struct emac_priv *priv = netdev_priv(ndev);
1969 struct device_node *np = pdev->dev.of_node;
1970
1971 dev_notice(&ndev->dev, "DaVinci EMAC: davinci_emac_remove()\n");
1972
1973 if (priv->txchan)
1974 cpdma_chan_destroy(priv->txchan);
1975 if (priv->rxchan)
1976 cpdma_chan_destroy(priv->rxchan);
1977 cpdma_ctlr_destroy(priv->dma);
1978
1979 unregister_netdev(ndev);
1980 of_node_put(priv->phy_node);
1981 pm_runtime_disable(&pdev->dev);
1982 if (of_phy_is_fixed_link(np))
1983 of_phy_deregister_fixed_link(np);
1984 free_netdev(ndev);
1985
1986 return 0;
1987 }
1988
1989 static int davinci_emac_suspend(struct device *dev)
1990 {
1991 struct net_device *ndev = dev_get_drvdata(dev);
1992
1993 if (netif_running(ndev))
1994 emac_dev_stop(ndev);
1995
1996 return 0;
1997 }
1998
1999 static int davinci_emac_resume(struct device *dev)
2000 {
2001 struct net_device *ndev = dev_get_drvdata(dev);
2002
2003 if (netif_running(ndev))
2004 emac_dev_open(ndev);
2005
2006 return 0;
2007 }
2008
2009 static const struct dev_pm_ops davinci_emac_pm_ops = {
2010 .suspend = davinci_emac_suspend,
2011 .resume = davinci_emac_resume,
2012 };
2013
2014 static const struct emac_platform_data am3517_emac_data = {
2015 .version = EMAC_VERSION_2,
2016 .hw_ram_addr = 0x01e20000,
2017 };
2018
2019 static const struct emac_platform_data dm816_emac_data = {
2020 .version = EMAC_VERSION_2,
2021 };
2022
2023 static const struct of_device_id davinci_emac_of_match[] = {
2024 {.compatible = "ti,davinci-dm6467-emac", },
2025 {.compatible = "ti,am3517-emac", .data = &am3517_emac_data, },
2026 {.compatible = "ti,dm816-emac", .data = &dm816_emac_data, },
2027 {},
2028 };
2029 MODULE_DEVICE_TABLE(of, davinci_emac_of_match);
2030
2031 /* davinci_emac_driver: EMAC platform driver structure */
2032 static struct platform_driver davinci_emac_driver = {
2033 .driver = {
2034 .name = "davinci_emac",
2035 .pm = &davinci_emac_pm_ops,
2036 .of_match_table = davinci_emac_of_match,
2037 },
2038 .probe = davinci_emac_probe,
2039 .remove = davinci_emac_remove,
2040 };
2041
2042 /**
2043 * davinci_emac_init - EMAC driver module init
2044 *
2045 * Called when initializing the driver. We register the driver with
2046 * the platform.
2047 */
2048 static int __init davinci_emac_init(void)
2049 {
2050 return platform_driver_register(&davinci_emac_driver);
2051 }
2052 late_initcall(davinci_emac_init);
2053
2054 /**
2055 * davinci_emac_exit - EMAC driver module exit
2056 *
2057 * Called when exiting the driver completely. We unregister the driver with
2058 * the platform and exit
2059 */
2060 static void __exit davinci_emac_exit(void)
2061 {
2062 platform_driver_unregister(&davinci_emac_driver);
2063 }
2064 module_exit(davinci_emac_exit);
2065
2066 MODULE_LICENSE("GPL");
2067 MODULE_AUTHOR("DaVinci EMAC Maintainer: Anant Gole <anantgole@ti.com>");
2068 MODULE_AUTHOR("DaVinci EMAC Maintainer: Chaithrika U S <chaithrika@ti.com>");
2069 MODULE_DESCRIPTION("DaVinci EMAC Ethernet driver");
Linux with added FPC-III support