drivers/net/phy/dp83867.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Driver for the Texas Instruments DP83867 PHY
   4  *
   5  * Copyright (C) 2015 Texas Instruments Inc.
   6  */
   7
   8 #include <linux/ethtool.h>
   9 #include <linux/kernel.h>
  10 #include <linux/mii.h>
  11 #include <linux/module.h>
  12 #include <linux/of.h>
  13 #include <linux/phy.h>
  14 #include <linux/delay.h>
  15 #include <linux/netdevice.h>
  16 #include <linux/etherdevice.h>
  17
  18 #include <dt-bindings/net/ti-dp83867.h>
  19
  20 #define DP83867_PHY_ID          0x2000a231
  21 #define DP83867_DEVADDR         0x1f
  22
  23 #define MII_DP83867_PHYCTRL     0x10
  24 #define MII_DP83867_MICR        0x12
  25 #define MII_DP83867_ISR         0x13
  26 #define DP83867_CFG2            0x14
  27 #define DP83867_CFG3            0x1e
  28 #define DP83867_CTRL            0x1f
  29
  30 /* Extended Registers */
  31 #define DP83867_CFG4            0x0031
  32 #define DP83867_CFG4_SGMII_ANEG_MASK (BIT(5) | BIT(6))
  33 #define DP83867_CFG4_SGMII_ANEG_TIMER_11MS   (3 << 5)
  34 #define DP83867_CFG4_SGMII_ANEG_TIMER_800US  (2 << 5)
  35 #define DP83867_CFG4_SGMII_ANEG_TIMER_2US    (1 << 5)
  36 #define DP83867_CFG4_SGMII_ANEG_TIMER_16MS   (0 << 5)
  37
  38 #define DP83867_RGMIICTL        0x0032
  39 #define DP83867_STRAP_STS1      0x006E
  40 #define DP83867_STRAP_STS2      0x006f
  41 #define DP83867_RGMIIDCTL       0x0086
  42 #define DP83867_RXFCFG          0x0134
  43 #define DP83867_RXFPMD1 0x0136
  44 #define DP83867_RXFPMD2 0x0137
  45 #define DP83867_RXFPMD3 0x0138
  46 #define DP83867_RXFSOP1 0x0139
  47 #define DP83867_RXFSOP2 0x013A
  48 #define DP83867_RXFSOP3 0x013B
  49 #define DP83867_IO_MUX_CFG      0x0170
  50 #define DP83867_SGMIICTL        0x00D3
  51 #define DP83867_10M_SGMII_CFG   0x016F
  52 #define DP83867_10M_SGMII_RATE_ADAPT_MASK BIT(7)
  53
  54 #define DP83867_SW_RESET        BIT(15)
  55 #define DP83867_SW_RESTART      BIT(14)
  56
  57 /* MICR Interrupt bits */
  58 #define MII_DP83867_MICR_AN_ERR_INT_EN          BIT(15)
  59 #define MII_DP83867_MICR_SPEED_CHNG_INT_EN      BIT(14)
  60 #define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN   BIT(13)
  61 #define MII_DP83867_MICR_PAGE_RXD_INT_EN        BIT(12)
  62 #define MII_DP83867_MICR_AUTONEG_COMP_INT_EN    BIT(11)
  63 #define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN   BIT(10)
  64 #define MII_DP83867_MICR_FALSE_CARRIER_INT_EN   BIT(8)
  65 #define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4)
  66 #define MII_DP83867_MICR_WOL_INT_EN             BIT(3)
  67 #define MII_DP83867_MICR_XGMII_ERR_INT_EN       BIT(2)
  68 #define MII_DP83867_MICR_POL_CHNG_INT_EN        BIT(1)
  69 #define MII_DP83867_MICR_JABBER_INT_EN          BIT(0)
  70
  71 /* RGMIICTL bits */
  72 #define DP83867_RGMII_TX_CLK_DELAY_EN           BIT(1)
  73 #define DP83867_RGMII_RX_CLK_DELAY_EN           BIT(0)
  74
  75 /* SGMIICTL bits */
  76 #define DP83867_SGMII_TYPE              BIT(14)
  77
  78 /* RXFCFG bits*/
  79 #define DP83867_WOL_MAGIC_EN            BIT(0)
  80 #define DP83867_WOL_BCAST_EN            BIT(2)
  81 #define DP83867_WOL_UCAST_EN            BIT(4)
  82 #define DP83867_WOL_SEC_EN              BIT(5)
  83 #define DP83867_WOL_ENH_MAC             BIT(7)
  84
  85 /* STRAP_STS1 bits */
  86 #define DP83867_STRAP_STS1_RESERVED             BIT(11)
  87
  88 /* STRAP_STS2 bits */
  89 #define DP83867_STRAP_STS2_CLK_SKEW_TX_MASK     GENMASK(6, 4)
  90 #define DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT    4
  91 #define DP83867_STRAP_STS2_CLK_SKEW_RX_MASK     GENMASK(2, 0)
  92 #define DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT    0
  93 #define DP83867_STRAP_STS2_CLK_SKEW_NONE        BIT(2)
  94
  95 /* PHY CTRL bits */
  96 #define DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT       14
  97 #define DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT       12
  98 #define DP83867_PHYCR_FIFO_DEPTH_MAX            0x03
  99 #define DP83867_PHYCR_TX_FIFO_DEPTH_MASK        GENMASK(15, 14)
 100 #define DP83867_PHYCR_RX_FIFO_DEPTH_MASK        GENMASK(13, 12)
 101 #define DP83867_PHYCR_RESERVED_MASK             BIT(11)
 102 #define DP83867_PHYCR_FORCE_LINK_GOOD           BIT(10)
 103
 104 /* RGMIIDCTL bits */
 105 #define DP83867_RGMII_TX_CLK_DELAY_MAX          0xf
 106 #define DP83867_RGMII_TX_CLK_DELAY_SHIFT        4
 107 #define DP83867_RGMII_TX_CLK_DELAY_INV  (DP83867_RGMII_TX_CLK_DELAY_MAX + 1)
 108 #define DP83867_RGMII_RX_CLK_DELAY_MAX          0xf
 109 #define DP83867_RGMII_RX_CLK_DELAY_SHIFT        0
 110 #define DP83867_RGMII_RX_CLK_DELAY_INV  (DP83867_RGMII_RX_CLK_DELAY_MAX + 1)
 111
 112
 113 /* IO_MUX_CFG bits */
 114 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK    0x1f
 115 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX     0x0
 116 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN     0x1f
 117 #define DP83867_IO_MUX_CFG_CLK_O_DISABLE        BIT(6)
 118 #define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK       (0x1f << 8)
 119 #define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT      8
 120
 121 /* CFG3 bits */
 122 #define DP83867_CFG3_INT_OE                     BIT(7)
 123 #define DP83867_CFG3_ROBUST_AUTO_MDIX           BIT(9)
 124
 125 /* CFG4 bits */
 126 #define DP83867_CFG4_PORT_MIRROR_EN              BIT(0)
 127
 128 enum {
 129         DP83867_PORT_MIRROING_KEEP,
 130         DP83867_PORT_MIRROING_EN,
 131         DP83867_PORT_MIRROING_DIS,
 132 };
 133
 134 struct dp83867_private {
 135         u32 rx_id_delay;
 136         u32 tx_id_delay;
 137         u32 tx_fifo_depth;
 138         u32 rx_fifo_depth;
 139         int io_impedance;
 140         int port_mirroring;
 141         bool rxctrl_strap_quirk;
 142         bool set_clk_output;
 143         u32 clk_output_sel;
 144         bool sgmii_ref_clk_en;
 145 };
 146
 147 static int dp83867_ack_interrupt(struct phy_device *phydev)
 148 {
 149         int err = phy_read(phydev, MII_DP83867_ISR);
 150
 151         if (err < 0)
 152                 return err;
 153
 154         return 0;
 155 }
 156
 157 static int dp83867_set_wol(struct phy_device *phydev,
 158                            struct ethtool_wolinfo *wol)
 159 {
 160         struct net_device *ndev = phydev->attached_dev;
 161         u16 val_rxcfg, val_micr;
 162         u8 *mac;
 163
 164         val_rxcfg = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG);
 165         val_micr = phy_read(phydev, MII_DP83867_MICR);
 166
 167         if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_UCAST |
 168                             WAKE_BCAST)) {
 169                 val_rxcfg |= DP83867_WOL_ENH_MAC;
 170                 val_micr |= MII_DP83867_MICR_WOL_INT_EN;
 171
 172                 if (wol->wolopts & WAKE_MAGIC) {
 173                         mac = (u8 *)ndev->dev_addr;
 174
 175                         if (!is_valid_ether_addr(mac))
 176                                 return -EINVAL;
 177
 178                         phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD1,
 179                                       (mac[1] << 8 | mac[0]));
 180                         phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD2,
 181                                       (mac[3] << 8 | mac[2]));
 182                         phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD3,
 183                                       (mac[5] << 8 | mac[4]));
 184
 185                         val_rxcfg |= DP83867_WOL_MAGIC_EN;
 186                 } else {
 187                         val_rxcfg &= ~DP83867_WOL_MAGIC_EN;
 188                 }
 189
 190                 if (wol->wolopts & WAKE_MAGICSECURE) {
 191                         phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP1,
 192                                       (wol->sopass[1] << 8) | wol->sopass[0]);
 193                         phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP1,
 194                                       (wol->sopass[3] << 8) | wol->sopass[2]);
 195                         phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP1,
 196                                       (wol->sopass[5] << 8) | wol->sopass[4]);
 197
 198                         val_rxcfg |= DP83867_WOL_SEC_EN;
 199                 } else {
 200                         val_rxcfg &= ~DP83867_WOL_SEC_EN;
 201                 }
 202
 203                 if (wol->wolopts & WAKE_UCAST)
 204                         val_rxcfg |= DP83867_WOL_UCAST_EN;
 205                 else
 206                         val_rxcfg &= ~DP83867_WOL_UCAST_EN;
 207
 208                 if (wol->wolopts & WAKE_BCAST)
 209                         val_rxcfg |= DP83867_WOL_BCAST_EN;
 210                 else
 211                         val_rxcfg &= ~DP83867_WOL_BCAST_EN;
 212         } else {
 213                 val_rxcfg &= ~DP83867_WOL_ENH_MAC;
 214                 val_micr &= ~MII_DP83867_MICR_WOL_INT_EN;
 215         }
 216
 217         phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG, val_rxcfg);
 218         phy_write(phydev, MII_DP83867_MICR, val_micr);
 219
 220         return 0;
 221 }
 222
 223 static void dp83867_get_wol(struct phy_device *phydev,
 224                             struct ethtool_wolinfo *wol)
 225 {
 226         u16 value, sopass_val;
 227
 228         wol->supported = (WAKE_UCAST | WAKE_BCAST | WAKE_MAGIC |
 229                         WAKE_MAGICSECURE);
 230         wol->wolopts = 0;
 231
 232         value = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG);
 233
 234         if (value & DP83867_WOL_UCAST_EN)
 235                 wol->wolopts |= WAKE_UCAST;
 236
 237         if (value & DP83867_WOL_BCAST_EN)
 238                 wol->wolopts |= WAKE_BCAST;
 239
 240         if (value & DP83867_WOL_MAGIC_EN)
 241                 wol->wolopts |= WAKE_MAGIC;
 242
 243         if (value & DP83867_WOL_SEC_EN) {
 244                 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,
 245                                           DP83867_RXFSOP1);
 246                 wol->sopass[0] = (sopass_val & 0xff);
 247                 wol->sopass[1] = (sopass_val >> 8);
 248
 249                 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,
 250                                           DP83867_RXFSOP2);
 251                 wol->sopass[2] = (sopass_val & 0xff);
 252                 wol->sopass[3] = (sopass_val >> 8);
 253
 254                 sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,
 255                                           DP83867_RXFSOP3);
 256                 wol->sopass[4] = (sopass_val & 0xff);
 257                 wol->sopass[5] = (sopass_val >> 8);
 258
 259                 wol->wolopts |= WAKE_MAGICSECURE;
 260         }
 261
 262         if (!(value & DP83867_WOL_ENH_MAC))
 263                 wol->wolopts = 0;
 264 }
 265
 266 static int dp83867_config_intr(struct phy_device *phydev)
 267 {
 268         int micr_status;
 269
 270         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
 271                 micr_status = phy_read(phydev, MII_DP83867_MICR);
 272                 if (micr_status < 0)
 273                         return micr_status;
 274
 275                 micr_status |=
 276                         (MII_DP83867_MICR_AN_ERR_INT_EN |
 277                         MII_DP83867_MICR_SPEED_CHNG_INT_EN |
 278                         MII_DP83867_MICR_AUTONEG_COMP_INT_EN |
 279                         MII_DP83867_MICR_LINK_STS_CHNG_INT_EN |
 280                         MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN |
 281                         MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN);
 282
 283                 return phy_write(phydev, MII_DP83867_MICR, micr_status);
 284         }
 285
 286         micr_status = 0x0;
 287         return phy_write(phydev, MII_DP83867_MICR, micr_status);
 288 }
 289
 290 static int dp83867_config_port_mirroring(struct phy_device *phydev)
 291 {
 292         struct dp83867_private *dp83867 =
 293                 (struct dp83867_private *)phydev->priv;
 294
 295         if (dp83867->port_mirroring == DP83867_PORT_MIRROING_EN)
 296                 phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
 297                                  DP83867_CFG4_PORT_MIRROR_EN);
 298         else
 299                 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
 300                                    DP83867_CFG4_PORT_MIRROR_EN);
 301         return 0;
 302 }
 303
 304 static int dp83867_verify_rgmii_cfg(struct phy_device *phydev)
 305 {
 306         struct dp83867_private *dp83867 = phydev->priv;
 307
 308         /* Existing behavior was to use default pin strapping delay in rgmii
 309          * mode, but rgmii should have meant no delay.  Warn existing users.
 310          */
 311         if (phydev->interface == PHY_INTERFACE_MODE_RGMII) {
 312                 const u16 val = phy_read_mmd(phydev, DP83867_DEVADDR,
 313                                              DP83867_STRAP_STS2);
 314                 const u16 txskew = (val & DP83867_STRAP_STS2_CLK_SKEW_TX_MASK) >>
 315                                    DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT;
 316                 const u16 rxskew = (val & DP83867_STRAP_STS2_CLK_SKEW_RX_MASK) >>
 317                                    DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT;
 318
 319                 if (txskew != DP83867_STRAP_STS2_CLK_SKEW_NONE ||
 320                     rxskew != DP83867_STRAP_STS2_CLK_SKEW_NONE)
 321                         phydev_warn(phydev,
 322                                     "PHY has delays via pin strapping, but phy-mode = 'rgmii'\n"
 323                                     "Should be 'rgmii-id' to use internal delays txskew:%x rxskew:%x\n",
 324                                     txskew, rxskew);
 325         }
 326
 327         /* RX delay *must* be specified if internal delay of RX is used. */
 328         if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
 329              phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) &&
 330              dp83867->rx_id_delay == DP83867_RGMII_RX_CLK_DELAY_INV) {
 331                 phydev_err(phydev, "ti,rx-internal-delay must be specified\n");
 332                 return -EINVAL;
 333         }
 334
 335         /* TX delay *must* be specified if internal delay of TX is used. */
 336         if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
 337              phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) &&
 338              dp83867->tx_id_delay == DP83867_RGMII_TX_CLK_DELAY_INV) {
 339                 phydev_err(phydev, "ti,tx-internal-delay must be specified\n");
 340                 return -EINVAL;
 341         }
 342
 343         return 0;
 344 }
 345
 346 #ifdef CONFIG_OF_MDIO
 347 static int dp83867_of_init(struct phy_device *phydev)
 348 {
 349         struct dp83867_private *dp83867 = phydev->priv;
 350         struct device *dev = &phydev->mdio.dev;
 351         struct device_node *of_node = dev->of_node;
 352         int ret;
 353
 354         if (!of_node)
 355                 return -ENODEV;
 356
 357         /* Optional configuration */
 358         ret = of_property_read_u32(of_node, "ti,clk-output-sel",
 359                                    &dp83867->clk_output_sel);
 360         /* If not set, keep default */
 361         if (!ret) {
 362                 dp83867->set_clk_output = true;
 363                 /* Valid values are 0 to DP83867_CLK_O_SEL_REF_CLK or
 364                  * DP83867_CLK_O_SEL_OFF.
 365                  */
 366                 if (dp83867->clk_output_sel > DP83867_CLK_O_SEL_REF_CLK &&
 367                     dp83867->clk_output_sel != DP83867_CLK_O_SEL_OFF) {
 368                         phydev_err(phydev, "ti,clk-output-sel value %u out of range\n",
 369                                    dp83867->clk_output_sel);
 370                         return -EINVAL;
 371                 }
 372         }
 373
 374         if (of_property_read_bool(of_node, "ti,max-output-impedance"))
 375                 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
 376         else if (of_property_read_bool(of_node, "ti,min-output-impedance"))
 377                 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;
 378         else
 379                 dp83867->io_impedance = -1; /* leave at default */
 380
 381         dp83867->rxctrl_strap_quirk = of_property_read_bool(of_node,
 382                                         "ti,dp83867-rxctrl-strap-quirk");
 383
 384         dp83867->sgmii_ref_clk_en = of_property_read_bool(of_node,
 385                                         "ti,sgmii-ref-clock-output-enable");
 386
 387
 388         dp83867->rx_id_delay = DP83867_RGMII_RX_CLK_DELAY_INV;
 389         ret = of_property_read_u32(of_node, "ti,rx-internal-delay",
 390                                    &dp83867->rx_id_delay);
 391         if (!ret && dp83867->rx_id_delay > DP83867_RGMII_RX_CLK_DELAY_MAX) {
 392                 phydev_err(phydev,
 393                            "ti,rx-internal-delay value of %u out of range\n",
 394                            dp83867->rx_id_delay);
 395                 return -EINVAL;
 396         }
 397
 398         dp83867->tx_id_delay = DP83867_RGMII_TX_CLK_DELAY_INV;
 399         ret = of_property_read_u32(of_node, "ti,tx-internal-delay",
 400                                    &dp83867->tx_id_delay);
 401         if (!ret && dp83867->tx_id_delay > DP83867_RGMII_TX_CLK_DELAY_MAX) {
 402                 phydev_err(phydev,
 403                            "ti,tx-internal-delay value of %u out of range\n",
 404                            dp83867->tx_id_delay);
 405                 return -EINVAL;
 406         }
 407
 408         if (of_property_read_bool(of_node, "enet-phy-lane-swap"))
 409                 dp83867->port_mirroring = DP83867_PORT_MIRROING_EN;
 410
 411         if (of_property_read_bool(of_node, "enet-phy-lane-no-swap"))
 412                 dp83867->port_mirroring = DP83867_PORT_MIRROING_DIS;
 413
 414         ret = of_property_read_u32(of_node, "ti,fifo-depth",
 415                                    &dp83867->tx_fifo_depth);
 416         if (ret) {
 417                 ret = of_property_read_u32(of_node, "tx-fifo-depth",
 418                                            &dp83867->tx_fifo_depth);
 419                 if (ret)
 420                         dp83867->tx_fifo_depth =
 421                                         DP83867_PHYCR_FIFO_DEPTH_4_B_NIB;
 422         }
 423
 424         if (dp83867->tx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) {
 425                 phydev_err(phydev, "tx-fifo-depth value %u out of range\n",
 426                            dp83867->tx_fifo_depth);
 427                 return -EINVAL;
 428         }
 429
 430         ret = of_property_read_u32(of_node, "rx-fifo-depth",
 431                                    &dp83867->rx_fifo_depth);
 432         if (ret)
 433                 dp83867->rx_fifo_depth = DP83867_PHYCR_FIFO_DEPTH_4_B_NIB;
 434
 435         if (dp83867->rx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) {
 436                 phydev_err(phydev, "rx-fifo-depth value %u out of range\n",
 437                            dp83867->rx_fifo_depth);
 438                 return -EINVAL;
 439         }
 440
 441         return 0;
 442 }
 443 #else
 444 static int dp83867_of_init(struct phy_device *phydev)
 445 {
 446         return 0;
 447 }
 448 #endif /* CONFIG_OF_MDIO */
 449
 450 static int dp83867_probe(struct phy_device *phydev)
 451 {
 452         struct dp83867_private *dp83867;
 453
 454         dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867),
 455                                GFP_KERNEL);
 456         if (!dp83867)
 457                 return -ENOMEM;
 458
 459         phydev->priv = dp83867;
 460
 461         return dp83867_of_init(phydev);
 462 }
 463
 464 static int dp83867_config_init(struct phy_device *phydev)
 465 {
 466         struct dp83867_private *dp83867 = phydev->priv;
 467         int ret, val, bs;
 468         u16 delay;
 469
 470         ret = dp83867_verify_rgmii_cfg(phydev);
 471         if (ret)
 472                 return ret;
 473
 474         /* RX_DV/RX_CTRL strapped in mode 1 or mode 2 workaround */
 475         if (dp83867->rxctrl_strap_quirk)
 476                 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
 477                                    BIT(7));
 478
 479         if (phy_interface_is_rgmii(phydev) ||
 480             phydev->interface == PHY_INTERFACE_MODE_SGMII) {
 481                 val = phy_read(phydev, MII_DP83867_PHYCTRL);
 482                 if (val < 0)
 483                         return val;
 484
 485                 val &= ~DP83867_PHYCR_TX_FIFO_DEPTH_MASK;
 486                 val |= (dp83867->tx_fifo_depth <<
 487                         DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT);
 488
 489                 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
 490                         val &= ~DP83867_PHYCR_RX_FIFO_DEPTH_MASK;
 491                         val |= (dp83867->rx_fifo_depth <<
 492                                 DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT);
 493                 }
 494
 495                 ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
 496                 if (ret)
 497                         return ret;
 498         }
 499
 500         if (phy_interface_is_rgmii(phydev)) {
 501                 val = phy_read(phydev, MII_DP83867_PHYCTRL);
 502                 if (val < 0)
 503                         return val;
 504
 505                 /* The code below checks if "port mirroring" N/A MODE4 has been
 506                  * enabled during power on bootstrap.
 507                  *
 508                  * Such N/A mode enabled by mistake can put PHY IC in some
 509                  * internal testing mode and disable RGMII transmission.
 510                  *
 511                  * In this particular case one needs to check STRAP_STS1
 512                  * register's bit 11 (marked as RESERVED).
 513                  */
 514
 515                 bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS1);
 516                 if (bs & DP83867_STRAP_STS1_RESERVED)
 517                         val &= ~DP83867_PHYCR_RESERVED_MASK;
 518
 519                 ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
 520                 if (ret)
 521                         return ret;
 522
 523                 /* If rgmii mode with no internal delay is selected, we do NOT use
 524                  * aligned mode as one might expect.  Instead we use the PHY's default
 525                  * based on pin strapping.  And the "mode 0" default is to *use*
 526                  * internal delay with a value of 7 (2.00 ns).
 527                  *
 528                  * Set up RGMII delays
 529                  */
 530                 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL);
 531
 532                 val &= ~(DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
 533                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
 534                         val |= (DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
 535
 536                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
 537                         val |= DP83867_RGMII_TX_CLK_DELAY_EN;
 538
 539                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
 540                         val |= DP83867_RGMII_RX_CLK_DELAY_EN;
 541
 542                 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val);
 543
 544                 delay = 0;
 545                 if (dp83867->rx_id_delay != DP83867_RGMII_RX_CLK_DELAY_INV)
 546                         delay |= dp83867->rx_id_delay;
 547                 if (dp83867->tx_id_delay != DP83867_RGMII_TX_CLK_DELAY_INV)
 548                         delay |= dp83867->tx_id_delay <<
 549                                  DP83867_RGMII_TX_CLK_DELAY_SHIFT;
 550
 551                 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL,
 552                               delay);
 553         }
 554
 555         /* If specified, set io impedance */
 556         if (dp83867->io_impedance >= 0)
 557                 phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,
 558                                DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK,
 559                                dp83867->io_impedance);
 560
 561         if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
 562                 /* For support SPEED_10 in SGMII mode
 563                  * DP83867_10M_SGMII_RATE_ADAPT bit
 564                  * has to be cleared by software. That
 565                  * does not affect SPEED_100 and
 566                  * SPEED_1000.
 567                  */
 568                 ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
 569                                      DP83867_10M_SGMII_CFG,
 570                                      DP83867_10M_SGMII_RATE_ADAPT_MASK,
 571                                      0);
 572                 if (ret)
 573                         return ret;
 574
 575                 /* After reset SGMII Autoneg timer is set to 2us (bits 6 and 5
 576                  * are 01). That is not enough to finalize autoneg on some
 577                  * devices. Increase this timer duration to maximum 16ms.
 578                  */
 579                 ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
 580                                      DP83867_CFG4,
 581                                      DP83867_CFG4_SGMII_ANEG_MASK,
 582                                      DP83867_CFG4_SGMII_ANEG_TIMER_16MS);
 583
 584                 if (ret)
 585                         return ret;
 586
 587                 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL);
 588                 /* SGMII type is set to 4-wire mode by default.
 589                  * If we place appropriate property in dts (see above)
 590                  * switch on 6-wire mode.
 591                  */
 592                 if (dp83867->sgmii_ref_clk_en)
 593                         val |= DP83867_SGMII_TYPE;
 594                 else
 595                         val &= ~DP83867_SGMII_TYPE;
 596                 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL, val);
 597         }
 598
 599         val = phy_read(phydev, DP83867_CFG3);
 600         /* Enable Interrupt output INT_OE in CFG3 register */
 601         if (phy_interrupt_is_valid(phydev))
 602                 val |= DP83867_CFG3_INT_OE;
 603
 604         val |= DP83867_CFG3_ROBUST_AUTO_MDIX;
 605         phy_write(phydev, DP83867_CFG3, val);
 606
 607         if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP)
 608                 dp83867_config_port_mirroring(phydev);
 609
 610         /* Clock output selection if muxing property is set */
 611         if (dp83867->set_clk_output) {
 612                 u16 mask = DP83867_IO_MUX_CFG_CLK_O_DISABLE;
 613
 614                 if (dp83867->clk_output_sel == DP83867_CLK_O_SEL_OFF) {
 615                         val = DP83867_IO_MUX_CFG_CLK_O_DISABLE;
 616                 } else {
 617                         mask |= DP83867_IO_MUX_CFG_CLK_O_SEL_MASK;
 618                         val = dp83867->clk_output_sel <<
 619                               DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT;
 620                 }
 621
 622                 phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,
 623                                mask, val);
 624         }
 625
 626         return 0;
 627 }
 628
 629 static int dp83867_phy_reset(struct phy_device *phydev)
 630 {
 631         int err;
 632
 633         err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESET);
 634         if (err < 0)
 635                 return err;
 636
 637         usleep_range(10, 20);
 638
 639         /* After reset FORCE_LINK_GOOD bit is set. Although the
 640          * default value should be unset. Disable FORCE_LINK_GOOD
 641          * for the phy to work properly.
 642          */
 643         return phy_modify(phydev, MII_DP83867_PHYCTRL,
 644                          DP83867_PHYCR_FORCE_LINK_GOOD, 0);
 645 }
 646
 647 static struct phy_driver dp83867_driver[] = {
 648         {
 649                 .phy_id         = DP83867_PHY_ID,
 650                 .phy_id_mask    = 0xfffffff0,
 651                 .name           = "TI DP83867",
 652                 /* PHY_GBIT_FEATURES */
 653
 654                 .probe          = dp83867_probe,
 655                 .config_init    = dp83867_config_init,
 656                 .soft_reset     = dp83867_phy_reset,
 657
 658                 .get_wol        = dp83867_get_wol,
 659                 .set_wol        = dp83867_set_wol,
 660
 661                 /* IRQ related */
 662                 .ack_interrupt  = dp83867_ack_interrupt,
 663                 .config_intr    = dp83867_config_intr,
 664
 665                 .suspend        = genphy_suspend,
 666                 .resume         = genphy_resume,
 667         },
 668 };
 669 module_phy_driver(dp83867_driver);
 670
 671 static struct mdio_device_id __maybe_unused dp83867_tbl[] = {
 672         { DP83867_PHY_ID, 0xfffffff0 },
 673         { }
 674 };
 675
 676 MODULE_DEVICE_TABLE(mdio, dp83867_tbl);
 677
 678 MODULE_DESCRIPTION("Texas Instruments DP83867 PHY driver");
 679 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com");
 680 MODULE_LICENSE("GPL v2");