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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / net / wan / ixp4xx_hss.c
blob7c5cf77e9ef10e68d8be0c4b2acc7ffcfb83f804
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Intel IXP4xx HSS (synchronous serial port) driver for Linux
4 *
5 * Copyright (C) 2007-2008 Krzysztof Hałasa <khc@pm.waw.pl>
6 */
7
8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9
10 #include <linux/module.h>
11 #include <linux/bitops.h>
12 #include <linux/cdev.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/dmapool.h>
15 #include <linux/fs.h>
16 #include <linux/hdlc.h>
17 #include <linux/io.h>
18 #include <linux/kernel.h>
19 #include <linux/platform_device.h>
20 #include <linux/platform_data/wan_ixp4xx_hss.h>
21 #include <linux/poll.h>
22 #include <linux/slab.h>
23 #include <linux/soc/ixp4xx/npe.h>
24 #include <linux/soc/ixp4xx/qmgr.h>
25
26 #define DEBUG_DESC 0
27 #define DEBUG_RX 0
28 #define DEBUG_TX 0
29 #define DEBUG_PKT_BYTES 0
30 #define DEBUG_CLOSE 0
31
32 #define DRV_NAME "ixp4xx_hss"
33
34 #define PKT_EXTRA_FLAGS 0 /* orig 1 */
35 #define PKT_NUM_PIPES 1 /* 1, 2 or 4 */
36 #define PKT_PIPE_FIFO_SIZEW 4 /* total 4 dwords per HSS */
37
38 #define RX_DESCS 16 /* also length of all RX queues */
39 #define TX_DESCS 16 /* also length of all TX queues */
40
41 #define POOL_ALLOC_SIZE (sizeof(struct desc) * (RX_DESCS + TX_DESCS))
42 #define RX_SIZE (HDLC_MAX_MRU + 4) /* NPE needs more space */
43 #define MAX_CLOSE_WAIT 1000 /* microseconds */
44 #define HSS_COUNT 2
45 #define FRAME_SIZE 256 /* doesn't matter at this point */
46 #define FRAME_OFFSET 0
47 #define MAX_CHANNELS (FRAME_SIZE / 8)
48
49 #define NAPI_WEIGHT 16
50
51 /* Queue IDs */
52 #define HSS0_CHL_RXTRIG_QUEUE 12 /* orig size = 32 dwords */
53 #define HSS0_PKT_RX_QUEUE 13 /* orig size = 32 dwords */
54 #define HSS0_PKT_TX0_QUEUE 14 /* orig size = 16 dwords */
55 #define HSS0_PKT_TX1_QUEUE 15
56 #define HSS0_PKT_TX2_QUEUE 16
57 #define HSS0_PKT_TX3_QUEUE 17
58 #define HSS0_PKT_RXFREE0_QUEUE 18 /* orig size = 16 dwords */
59 #define HSS0_PKT_RXFREE1_QUEUE 19
60 #define HSS0_PKT_RXFREE2_QUEUE 20
61 #define HSS0_PKT_RXFREE3_QUEUE 21
62 #define HSS0_PKT_TXDONE_QUEUE 22 /* orig size = 64 dwords */
63
64 #define HSS1_CHL_RXTRIG_QUEUE 10
65 #define HSS1_PKT_RX_QUEUE 0
66 #define HSS1_PKT_TX0_QUEUE 5
67 #define HSS1_PKT_TX1_QUEUE 6
68 #define HSS1_PKT_TX2_QUEUE 7
69 #define HSS1_PKT_TX3_QUEUE 8
70 #define HSS1_PKT_RXFREE0_QUEUE 1
71 #define HSS1_PKT_RXFREE1_QUEUE 2
72 #define HSS1_PKT_RXFREE2_QUEUE 3
73 #define HSS1_PKT_RXFREE3_QUEUE 4
74 #define HSS1_PKT_TXDONE_QUEUE 9
75
76 #define NPE_PKT_MODE_HDLC 0
77 #define NPE_PKT_MODE_RAW 1
78 #define NPE_PKT_MODE_56KMODE 2
79 #define NPE_PKT_MODE_56KENDIAN_MSB 4
80
81 /* PKT_PIPE_HDLC_CFG_WRITE flags */
82 #define PKT_HDLC_IDLE_ONES 0x1 /* default = flags */
83 #define PKT_HDLC_CRC_32 0x2 /* default = CRC-16 */
84 #define PKT_HDLC_MSB_ENDIAN 0x4 /* default = LE */
85
86
87 /* hss_config, PCRs */
88 /* Frame sync sampling, default = active low */
89 #define PCR_FRM_SYNC_ACTIVE_HIGH 0x40000000
90 #define PCR_FRM_SYNC_FALLINGEDGE 0x80000000
91 #define PCR_FRM_SYNC_RISINGEDGE 0xC0000000
92
93 /* Frame sync pin: input (default) or output generated off a given clk edge */
94 #define PCR_FRM_SYNC_OUTPUT_FALLING 0x20000000
95 #define PCR_FRM_SYNC_OUTPUT_RISING 0x30000000
96
97 /* Frame and data clock sampling on edge, default = falling */
98 #define PCR_FCLK_EDGE_RISING 0x08000000
99 #define PCR_DCLK_EDGE_RISING 0x04000000
100
101 /* Clock direction, default = input */
102 #define PCR_SYNC_CLK_DIR_OUTPUT 0x02000000
103
104 /* Generate/Receive frame pulses, default = enabled */
105 #define PCR_FRM_PULSE_DISABLED 0x01000000
106
107 /* Data rate is full (default) or half the configured clk speed */
108 #define PCR_HALF_CLK_RATE 0x00200000
109
110 /* Invert data between NPE and HSS FIFOs? (default = no) */
111 #define PCR_DATA_POLARITY_INVERT 0x00100000
112
113 /* TX/RX endianness, default = LSB */
114 #define PCR_MSB_ENDIAN 0x00080000
115
116 /* Normal (default) / open drain mode (TX only) */
117 #define PCR_TX_PINS_OPEN_DRAIN 0x00040000
118
119 /* No framing bit transmitted and expected on RX? (default = framing bit) */
120 #define PCR_SOF_NO_FBIT 0x00020000
121
122 /* Drive data pins? */
123 #define PCR_TX_DATA_ENABLE 0x00010000
124
125 /* Voice 56k type: drive the data pins low (default), high, high Z */
126 #define PCR_TX_V56K_HIGH 0x00002000
127 #define PCR_TX_V56K_HIGH_IMP 0x00004000
128
129 /* Unassigned type: drive the data pins low (default), high, high Z */
130 #define PCR_TX_UNASS_HIGH 0x00000800
131 #define PCR_TX_UNASS_HIGH_IMP 0x00001000
132
133 /* T1 @ 1.544MHz only: Fbit dictated in FIFO (default) or high Z */
134 #define PCR_TX_FB_HIGH_IMP 0x00000400
135
136 /* 56k data endiannes - which bit unused: high (default) or low */
137 #define PCR_TX_56KE_BIT_0_UNUSED 0x00000200
138
139 /* 56k data transmission type: 32/8 bit data (default) or 56K data */
140 #define PCR_TX_56KS_56K_DATA 0x00000100
141
142 /* hss_config, cCR */
143 /* Number of packetized clients, default = 1 */
144 #define CCR_NPE_HFIFO_2_HDLC 0x04000000
145 #define CCR_NPE_HFIFO_3_OR_4HDLC 0x08000000
146
147 /* default = no loopback */
148 #define CCR_LOOPBACK 0x02000000
149
150 /* HSS number, default = 0 (first) */
151 #define CCR_SECOND_HSS 0x01000000
152
153
154 /* hss_config, clkCR: main:10, num:10, denom:12 */
155 #define CLK42X_SPEED_EXP ((0x3FF << 22) | ( 2 << 12) | 15) /*65 KHz*/
156
157 #define CLK42X_SPEED_512KHZ (( 130 << 22) | ( 2 << 12) | 15)
158 #define CLK42X_SPEED_1536KHZ (( 43 << 22) | ( 18 << 12) | 47)
159 #define CLK42X_SPEED_1544KHZ (( 43 << 22) | ( 33 << 12) | 192)
160 #define CLK42X_SPEED_2048KHZ (( 32 << 22) | ( 34 << 12) | 63)
161 #define CLK42X_SPEED_4096KHZ (( 16 << 22) | ( 34 << 12) | 127)
162 #define CLK42X_SPEED_8192KHZ (( 8 << 22) | ( 34 << 12) | 255)
163
164 #define CLK46X_SPEED_512KHZ (( 130 << 22) | ( 24 << 12) | 127)
165 #define CLK46X_SPEED_1536KHZ (( 43 << 22) | (152 << 12) | 383)
166 #define CLK46X_SPEED_1544KHZ (( 43 << 22) | ( 66 << 12) | 385)
167 #define CLK46X_SPEED_2048KHZ (( 32 << 22) | (280 << 12) | 511)
168 #define CLK46X_SPEED_4096KHZ (( 16 << 22) | (280 << 12) | 1023)
169 #define CLK46X_SPEED_8192KHZ (( 8 << 22) | (280 << 12) | 2047)
170
171 /*
172 * HSS_CONFIG_CLOCK_CR register consists of 3 parts:
173 * A (10 bits), B (10 bits) and C (12 bits).
174 * IXP42x HSS clock generator operation (verified with an oscilloscope):
175 * Each clock bit takes 7.5 ns (1 / 133.xx MHz).
176 * The clock sequence consists of (C - B) states of 0s and 1s, each state is
177 * A bits wide. It's followed by (B + 1) states of 0s and 1s, each state is
178 * (A + 1) bits wide.
179 *
180 * The resulting average clock frequency (assuming 33.333 MHz oscillator) is:
181 * freq = 66.666 MHz / (A + (B + 1) / (C + 1))
182 * minimum freq = 66.666 MHz / (A + 1)
183 * maximum freq = 66.666 MHz / A
184 *
185 * Example: A = 2, B = 2, C = 7, CLOCK_CR register = 2 << 22 | 2 << 12 | 7
186 * freq = 66.666 MHz / (2 + (2 + 1) / (7 + 1)) = 28.07 MHz (Mb/s).
187 * The clock sequence is: 1100110011 (5 doubles) 000111000 (3 triples).
188 * The sequence takes (C - B) * A + (B + 1) * (A + 1) = 5 * 2 + 3 * 3 bits
189 * = 19 bits (each 7.5 ns long) = 142.5 ns (then the sequence repeats).
190 * The sequence consists of 4 complete clock periods, thus the average
191 * frequency (= clock rate) is 4 / 142.5 ns = 28.07 MHz (Mb/s).
192 * (max specified clock rate for IXP42x HSS is 8.192 Mb/s).
193 */
194
195 /* hss_config, LUT entries */
196 #define TDMMAP_UNASSIGNED 0
197 #define TDMMAP_HDLC 1 /* HDLC - packetized */
198 #define TDMMAP_VOICE56K 2 /* Voice56K - 7-bit channelized */
199 #define TDMMAP_VOICE64K 3 /* Voice64K - 8-bit channelized */
200
201 /* offsets into HSS config */
202 #define HSS_CONFIG_TX_PCR 0x00 /* port configuration registers */
203 #define HSS_CONFIG_RX_PCR 0x04
204 #define HSS_CONFIG_CORE_CR 0x08 /* loopback control, HSS# */
205 #define HSS_CONFIG_CLOCK_CR 0x0C /* clock generator control */
206 #define HSS_CONFIG_TX_FCR 0x10 /* frame configuration registers */
207 #define HSS_CONFIG_RX_FCR 0x14
208 #define HSS_CONFIG_TX_LUT 0x18 /* channel look-up tables */
209 #define HSS_CONFIG_RX_LUT 0x38
210
211
212 /* NPE command codes */
213 /* writes the ConfigWord value to the location specified by offset */
214 #define PORT_CONFIG_WRITE 0x40
215
216 /* triggers the NPE to load the contents of the configuration table */
217 #define PORT_CONFIG_LOAD 0x41
218
219 /* triggers the NPE to return an HssErrorReadResponse message */
220 #define PORT_ERROR_READ 0x42
221
222 /* triggers the NPE to reset internal status and enable the HssPacketized
223 operation for the flow specified by pPipe */
224 #define PKT_PIPE_FLOW_ENABLE 0x50
225 #define PKT_PIPE_FLOW_DISABLE 0x51
226 #define PKT_NUM_PIPES_WRITE 0x52
227 #define PKT_PIPE_FIFO_SIZEW_WRITE 0x53
228 #define PKT_PIPE_HDLC_CFG_WRITE 0x54
229 #define PKT_PIPE_IDLE_PATTERN_WRITE 0x55
230 #define PKT_PIPE_RX_SIZE_WRITE 0x56
231 #define PKT_PIPE_MODE_WRITE 0x57
232
233 /* HDLC packet status values - desc->status */
234 #define ERR_SHUTDOWN 1 /* stop or shutdown occurrence */
235 #define ERR_HDLC_ALIGN 2 /* HDLC alignment error */
236 #define ERR_HDLC_FCS 3 /* HDLC Frame Check Sum error */
237 #define ERR_RXFREE_Q_EMPTY 4 /* RX-free queue became empty while receiving
238 this packet (if buf_len < pkt_len) */
239 #define ERR_HDLC_TOO_LONG 5 /* HDLC frame size too long */
240 #define ERR_HDLC_ABORT 6 /* abort sequence received */
241 #define ERR_DISCONNECTING 7 /* disconnect is in progress */
242
243
244 #ifdef __ARMEB__
245 typedef struct sk_buff buffer_t;
246 #define free_buffer dev_kfree_skb
247 #define free_buffer_irq dev_consume_skb_irq
248 #else
249 typedef void buffer_t;
250 #define free_buffer kfree
251 #define free_buffer_irq kfree
252 #endif
253
254 struct port {
255 struct device *dev;
256 struct npe *npe;
257 struct net_device *netdev;
258 struct napi_struct napi;
259 struct hss_plat_info *plat;
260 buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS];
261 struct desc *desc_tab; /* coherent */
262 dma_addr_t desc_tab_phys;
263 unsigned int id;
264 unsigned int clock_type, clock_rate, loopback;
265 unsigned int initialized, carrier;
266 u8 hdlc_cfg;
267 u32 clock_reg;
268 };
269
270 /* NPE message structure */
271 struct msg {
272 #ifdef __ARMEB__
273 u8 cmd, unused, hss_port, index;
274 union {
275 struct { u8 data8a, data8b, data8c, data8d; };
276 struct { u16 data16a, data16b; };
277 struct { u32 data32; };
278 };
279 #else
280 u8 index, hss_port, unused, cmd;
281 union {
282 struct { u8 data8d, data8c, data8b, data8a; };
283 struct { u16 data16b, data16a; };
284 struct { u32 data32; };
285 };
286 #endif
287 };
288
289 /* HDLC packet descriptor */
290 struct desc {
291 u32 next; /* pointer to next buffer, unused */
292
293 #ifdef __ARMEB__
294 u16 buf_len; /* buffer length */
295 u16 pkt_len; /* packet length */
296 u32 data; /* pointer to data buffer in RAM */
297 u8 status;
298 u8 error_count;
299 u16 __reserved;
300 #else
301 u16 pkt_len; /* packet length */
302 u16 buf_len; /* buffer length */
303 u32 data; /* pointer to data buffer in RAM */
304 u16 __reserved;
305 u8 error_count;
306 u8 status;
307 #endif
308 u32 __reserved1[4];
309 };
310
311
312 #define rx_desc_phys(port, n) ((port)->desc_tab_phys + \
313 (n) * sizeof(struct desc))
314 #define rx_desc_ptr(port, n) (&(port)->desc_tab[n])
315
316 #define tx_desc_phys(port, n) ((port)->desc_tab_phys + \
317 ((n) + RX_DESCS) * sizeof(struct desc))
318 #define tx_desc_ptr(port, n) (&(port)->desc_tab[(n) + RX_DESCS])
319
320 /*****************************************************************************
321 * global variables
322 ****************************************************************************/
323
324 static int ports_open;
325 static struct dma_pool *dma_pool;
326 static spinlock_t npe_lock;
327
328 static const struct {
329 int tx, txdone, rx, rxfree;
330 }queue_ids[2] = {{HSS0_PKT_TX0_QUEUE, HSS0_PKT_TXDONE_QUEUE, HSS0_PKT_RX_QUEUE,
331 HSS0_PKT_RXFREE0_QUEUE},
332 {HSS1_PKT_TX0_QUEUE, HSS1_PKT_TXDONE_QUEUE, HSS1_PKT_RX_QUEUE,
333 HSS1_PKT_RXFREE0_QUEUE},
334 };
335
336 /*****************************************************************************
337 * utility functions
338 ****************************************************************************/
339
340 static inline struct port* dev_to_port(struct net_device *dev)
341 {
342 return dev_to_hdlc(dev)->priv;
343 }
344
345 #ifndef __ARMEB__
346 static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt)
347 {
348 int i;
349 for (i = 0; i < cnt; i++)
350 dest[i] = swab32(src[i]);
351 }
352 #endif
353
354 /*****************************************************************************
355 * HSS access
356 ****************************************************************************/
357
358 static void hss_npe_send(struct port *port, struct msg *msg, const char* what)
359 {
360 u32 *val = (u32*)msg;
361 if (npe_send_message(port->npe, msg, what)) {
362 pr_crit("HSS-%i: unable to send command [%08X:%08X] to %s\n",
363 port->id, val[0], val[1], npe_name(port->npe));
364 BUG();
365 }
366 }
367
368 static void hss_config_set_lut(struct port *port)
369 {
370 struct msg msg;
371 int ch;
372
373 memset(&msg, 0, sizeof(msg));
374 msg.cmd = PORT_CONFIG_WRITE;
375 msg.hss_port = port->id;
376
377 for (ch = 0; ch < MAX_CHANNELS; ch++) {
378 msg.data32 >>= 2;
379 msg.data32 |= TDMMAP_HDLC << 30;
380
381 if (ch % 16 == 15) {
382 msg.index = HSS_CONFIG_TX_LUT + ((ch / 4) & ~3);
383 hss_npe_send(port, &msg, "HSS_SET_TX_LUT");
384
385 msg.index += HSS_CONFIG_RX_LUT - HSS_CONFIG_TX_LUT;
386 hss_npe_send(port, &msg, "HSS_SET_RX_LUT");
387 }
388 }
389 }
390
391 static void hss_config(struct port *port)
392 {
393 struct msg msg;
394
395 memset(&msg, 0, sizeof(msg));
396 msg.cmd = PORT_CONFIG_WRITE;
397 msg.hss_port = port->id;
398 msg.index = HSS_CONFIG_TX_PCR;
399 msg.data32 = PCR_FRM_PULSE_DISABLED | PCR_MSB_ENDIAN |
400 PCR_TX_DATA_ENABLE | PCR_SOF_NO_FBIT;
401 if (port->clock_type == CLOCK_INT)
402 msg.data32 |= PCR_SYNC_CLK_DIR_OUTPUT;
403 hss_npe_send(port, &msg, "HSS_SET_TX_PCR");
404
405 msg.index = HSS_CONFIG_RX_PCR;
406 msg.data32 ^= PCR_TX_DATA_ENABLE | PCR_DCLK_EDGE_RISING;
407 hss_npe_send(port, &msg, "HSS_SET_RX_PCR");
408
409 memset(&msg, 0, sizeof(msg));
410 msg.cmd = PORT_CONFIG_WRITE;
411 msg.hss_port = port->id;
412 msg.index = HSS_CONFIG_CORE_CR;
413 msg.data32 = (port->loopback ? CCR_LOOPBACK : 0) |
414 (port->id ? CCR_SECOND_HSS : 0);
415 hss_npe_send(port, &msg, "HSS_SET_CORE_CR");
416
417 memset(&msg, 0, sizeof(msg));
418 msg.cmd = PORT_CONFIG_WRITE;
419 msg.hss_port = port->id;
420 msg.index = HSS_CONFIG_CLOCK_CR;
421 msg.data32 = port->clock_reg;
422 hss_npe_send(port, &msg, "HSS_SET_CLOCK_CR");
423
424 memset(&msg, 0, sizeof(msg));
425 msg.cmd = PORT_CONFIG_WRITE;
426 msg.hss_port = port->id;
427 msg.index = HSS_CONFIG_TX_FCR;
428 msg.data16a = FRAME_OFFSET;
429 msg.data16b = FRAME_SIZE - 1;
430 hss_npe_send(port, &msg, "HSS_SET_TX_FCR");
431
432 memset(&msg, 0, sizeof(msg));
433 msg.cmd = PORT_CONFIG_WRITE;
434 msg.hss_port = port->id;
435 msg.index = HSS_CONFIG_RX_FCR;
436 msg.data16a = FRAME_OFFSET;
437 msg.data16b = FRAME_SIZE - 1;
438 hss_npe_send(port, &msg, "HSS_SET_RX_FCR");
439
440 hss_config_set_lut(port);
441
442 memset(&msg, 0, sizeof(msg));
443 msg.cmd = PORT_CONFIG_LOAD;
444 msg.hss_port = port->id;
445 hss_npe_send(port, &msg, "HSS_LOAD_CONFIG");
446
447 if (npe_recv_message(port->npe, &msg, "HSS_LOAD_CONFIG") ||
448 /* HSS_LOAD_CONFIG for port #1 returns port_id = #4 */
449 msg.cmd != PORT_CONFIG_LOAD || msg.data32) {
450 pr_crit("HSS-%i: HSS_LOAD_CONFIG failed\n", port->id);
451 BUG();
452 }
453
454 /* HDLC may stop working without this - check FIXME */
455 npe_recv_message(port->npe, &msg, "FLUSH_IT");
456 }
457
458 static void hss_set_hdlc_cfg(struct port *port)
459 {
460 struct msg msg;
461
462 memset(&msg, 0, sizeof(msg));
463 msg.cmd = PKT_PIPE_HDLC_CFG_WRITE;
464 msg.hss_port = port->id;
465 msg.data8a = port->hdlc_cfg; /* rx_cfg */
466 msg.data8b = port->hdlc_cfg | (PKT_EXTRA_FLAGS << 3); /* tx_cfg */
467 hss_npe_send(port, &msg, "HSS_SET_HDLC_CFG");
468 }
469
470 static u32 hss_get_status(struct port *port)
471 {
472 struct msg msg;
473
474 memset(&msg, 0, sizeof(msg));
475 msg.cmd = PORT_ERROR_READ;
476 msg.hss_port = port->id;
477 hss_npe_send(port, &msg, "PORT_ERROR_READ");
478 if (npe_recv_message(port->npe, &msg, "PORT_ERROR_READ")) {
479 pr_crit("HSS-%i: unable to read HSS status\n", port->id);
480 BUG();
481 }
482
483 return msg.data32;
484 }
485
486 static void hss_start_hdlc(struct port *port)
487 {
488 struct msg msg;
489
490 memset(&msg, 0, sizeof(msg));
491 msg.cmd = PKT_PIPE_FLOW_ENABLE;
492 msg.hss_port = port->id;
493 msg.data32 = 0;
494 hss_npe_send(port, &msg, "HSS_ENABLE_PKT_PIPE");
495 }
496
497 static void hss_stop_hdlc(struct port *port)
498 {
499 struct msg msg;
500
501 memset(&msg, 0, sizeof(msg));
502 msg.cmd = PKT_PIPE_FLOW_DISABLE;
503 msg.hss_port = port->id;
504 hss_npe_send(port, &msg, "HSS_DISABLE_PKT_PIPE");
505 hss_get_status(port); /* make sure it's halted */
506 }
507
508 static int hss_load_firmware(struct port *port)
509 {
510 struct msg msg;
511 int err;
512
513 if (port->initialized)
514 return 0;
515
516 if (!npe_running(port->npe) &&
517 (err = npe_load_firmware(port->npe, npe_name(port->npe),
518 port->dev)))
519 return err;
520
521 /* HDLC mode configuration */
522 memset(&msg, 0, sizeof(msg));
523 msg.cmd = PKT_NUM_PIPES_WRITE;
524 msg.hss_port = port->id;
525 msg.data8a = PKT_NUM_PIPES;
526 hss_npe_send(port, &msg, "HSS_SET_PKT_PIPES");
527
528 msg.cmd = PKT_PIPE_FIFO_SIZEW_WRITE;
529 msg.data8a = PKT_PIPE_FIFO_SIZEW;
530 hss_npe_send(port, &msg, "HSS_SET_PKT_FIFO");
531
532 msg.cmd = PKT_PIPE_MODE_WRITE;
533 msg.data8a = NPE_PKT_MODE_HDLC;
534 /* msg.data8b = inv_mask */
535 /* msg.data8c = or_mask */
536 hss_npe_send(port, &msg, "HSS_SET_PKT_MODE");
537
538 msg.cmd = PKT_PIPE_RX_SIZE_WRITE;
539 msg.data16a = HDLC_MAX_MRU; /* including CRC */
540 hss_npe_send(port, &msg, "HSS_SET_PKT_RX_SIZE");
541
542 msg.cmd = PKT_PIPE_IDLE_PATTERN_WRITE;
543 msg.data32 = 0x7F7F7F7F; /* ??? FIXME */
544 hss_npe_send(port, &msg, "HSS_SET_PKT_IDLE");
545
546 port->initialized = 1;
547 return 0;
548 }
549
550 /*****************************************************************************
551 * packetized (HDLC) operation
552 ****************************************************************************/
553
554 static inline void debug_pkt(struct net_device *dev, const char *func,
555 u8 *data, int len)
556 {
557 #if DEBUG_PKT_BYTES
558 int i;
559
560 printk(KERN_DEBUG "%s: %s(%i)", dev->name, func, len);
561 for (i = 0; i < len; i++) {
562 if (i >= DEBUG_PKT_BYTES)
563 break;
564 printk("%s%02X", !(i % 4) ? " " : "", data[i]);
565 }
566 printk("\n");
567 #endif
568 }
569
570
571 static inline void debug_desc(u32 phys, struct desc *desc)
572 {
573 #if DEBUG_DESC
574 printk(KERN_DEBUG "%X: %X %3X %3X %08X %X %X\n",
575 phys, desc->next, desc->buf_len, desc->pkt_len,
576 desc->data, desc->status, desc->error_count);
577 #endif
578 }
579
580 static inline int queue_get_desc(unsigned int queue, struct port *port,
581 int is_tx)
582 {
583 u32 phys, tab_phys, n_desc;
584 struct desc *tab;
585
586 if (!(phys = qmgr_get_entry(queue)))
587 return -1;
588
589 BUG_ON(phys & 0x1F);
590 tab_phys = is_tx ? tx_desc_phys(port, 0) : rx_desc_phys(port, 0);
591 tab = is_tx ? tx_desc_ptr(port, 0) : rx_desc_ptr(port, 0);
592 n_desc = (phys - tab_phys) / sizeof(struct desc);
593 BUG_ON(n_desc >= (is_tx ? TX_DESCS : RX_DESCS));
594 debug_desc(phys, &tab[n_desc]);
595 BUG_ON(tab[n_desc].next);
596 return n_desc;
597 }
598
599 static inline void queue_put_desc(unsigned int queue, u32 phys,
600 struct desc *desc)
601 {
602 debug_desc(phys, desc);
603 BUG_ON(phys & 0x1F);
604 qmgr_put_entry(queue, phys);
605 /* Don't check for queue overflow here, we've allocated sufficient
606 length and queues >= 32 don't support this check anyway. */
607 }
608
609
610 static inline void dma_unmap_tx(struct port *port, struct desc *desc)
611 {
612 #ifdef __ARMEB__
613 dma_unmap_single(&port->netdev->dev, desc->data,
614 desc->buf_len, DMA_TO_DEVICE);
615 #else
616 dma_unmap_single(&port->netdev->dev, desc->data & ~3,
617 ALIGN((desc->data & 3) + desc->buf_len, 4),
618 DMA_TO_DEVICE);
619 #endif
620 }
621
622
623 static void hss_hdlc_set_carrier(void *pdev, int carrier)
624 {
625 struct net_device *netdev = pdev;
626 struct port *port = dev_to_port(netdev);
627 unsigned long flags;
628
629 spin_lock_irqsave(&npe_lock, flags);
630 port->carrier = carrier;
631 if (!port->loopback) {
632 if (carrier)
633 netif_carrier_on(netdev);
634 else
635 netif_carrier_off(netdev);
636 }
637 spin_unlock_irqrestore(&npe_lock, flags);
638 }
639
640 static void hss_hdlc_rx_irq(void *pdev)
641 {
642 struct net_device *dev = pdev;
643 struct port *port = dev_to_port(dev);
644
645 #if DEBUG_RX
646 printk(KERN_DEBUG "%s: hss_hdlc_rx_irq\n", dev->name);
647 #endif
648 qmgr_disable_irq(queue_ids[port->id].rx);
649 napi_schedule(&port->napi);
650 }
651
652 static int hss_hdlc_poll(struct napi_struct *napi, int budget)
653 {
654 struct port *port = container_of(napi, struct port, napi);
655 struct net_device *dev = port->netdev;
656 unsigned int rxq = queue_ids[port->id].rx;
657 unsigned int rxfreeq = queue_ids[port->id].rxfree;
658 int received = 0;
659
660 #if DEBUG_RX
661 printk(KERN_DEBUG "%s: hss_hdlc_poll\n", dev->name);
662 #endif
663
664 while (received < budget) {
665 struct sk_buff *skb;
666 struct desc *desc;
667 int n;
668 #ifdef __ARMEB__
669 struct sk_buff *temp;
670 u32 phys;
671 #endif
672
673 if ((n = queue_get_desc(rxq, port, 0)) < 0) {
674 #if DEBUG_RX
675 printk(KERN_DEBUG "%s: hss_hdlc_poll"
676 " napi_complete\n", dev->name);
677 #endif
678 napi_complete(napi);
679 qmgr_enable_irq(rxq);
680 if (!qmgr_stat_empty(rxq) &&
681 napi_reschedule(napi)) {
682 #if DEBUG_RX
683 printk(KERN_DEBUG "%s: hss_hdlc_poll"
684 " napi_reschedule succeeded\n",
685 dev->name);
686 #endif
687 qmgr_disable_irq(rxq);
688 continue;
689 }
690 #if DEBUG_RX
691 printk(KERN_DEBUG "%s: hss_hdlc_poll all done\n",
692 dev->name);
693 #endif
694 return received; /* all work done */
695 }
696
697 desc = rx_desc_ptr(port, n);
698 #if 0 /* FIXME - error_count counts modulo 256, perhaps we should use it */
699 if (desc->error_count)
700 printk(KERN_DEBUG "%s: hss_hdlc_poll status 0x%02X"
701 " errors %u\n", dev->name, desc->status,
702 desc->error_count);
703 #endif
704 skb = NULL;
705 switch (desc->status) {
706 case 0:
707 #ifdef __ARMEB__
708 if ((skb = netdev_alloc_skb(dev, RX_SIZE)) != NULL) {
709 phys = dma_map_single(&dev->dev, skb->data,
710 RX_SIZE,
711 DMA_FROM_DEVICE);
712 if (dma_mapping_error(&dev->dev, phys)) {
713 dev_kfree_skb(skb);
714 skb = NULL;
715 }
716 }
717 #else
718 skb = netdev_alloc_skb(dev, desc->pkt_len);
719 #endif
720 if (!skb)
721 dev->stats.rx_dropped++;
722 break;
723 case ERR_HDLC_ALIGN:
724 case ERR_HDLC_ABORT:
725 dev->stats.rx_frame_errors++;
726 dev->stats.rx_errors++;
727 break;
728 case ERR_HDLC_FCS:
729 dev->stats.rx_crc_errors++;
730 dev->stats.rx_errors++;
731 break;
732 case ERR_HDLC_TOO_LONG:
733 dev->stats.rx_length_errors++;
734 dev->stats.rx_errors++;
735 break;
736 default: /* FIXME - remove printk */
737 netdev_err(dev, "hss_hdlc_poll: status 0x%02X errors %u\n",
738 desc->status, desc->error_count);
739 dev->stats.rx_errors++;
740 }
741
742 if (!skb) {
743 /* put the desc back on RX-ready queue */
744 desc->buf_len = RX_SIZE;
745 desc->pkt_len = desc->status = 0;
746 queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
747 continue;
748 }
749
750 /* process received frame */
751 #ifdef __ARMEB__
752 temp = skb;
753 skb = port->rx_buff_tab[n];
754 dma_unmap_single(&dev->dev, desc->data,
755 RX_SIZE, DMA_FROM_DEVICE);
756 #else
757 dma_sync_single_for_cpu(&dev->dev, desc->data,
758 RX_SIZE, DMA_FROM_DEVICE);
759 memcpy_swab32((u32 *)skb->data, (u32 *)port->rx_buff_tab[n],
760 ALIGN(desc->pkt_len, 4) / 4);
761 #endif
762 skb_put(skb, desc->pkt_len);
763
764 debug_pkt(dev, "hss_hdlc_poll", skb->data, skb->len);
765
766 skb->protocol = hdlc_type_trans(skb, dev);
767 dev->stats.rx_packets++;
768 dev->stats.rx_bytes += skb->len;
769 netif_receive_skb(skb);
770
771 /* put the new buffer on RX-free queue */
772 #ifdef __ARMEB__
773 port->rx_buff_tab[n] = temp;
774 desc->data = phys;
775 #endif
776 desc->buf_len = RX_SIZE;
777 desc->pkt_len = 0;
778 queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
779 received++;
780 }
781 #if DEBUG_RX
782 printk(KERN_DEBUG "hss_hdlc_poll: end, not all work done\n");
783 #endif
784 return received; /* not all work done */
785 }
786
787
788 static void hss_hdlc_txdone_irq(void *pdev)
789 {
790 struct net_device *dev = pdev;
791 struct port *port = dev_to_port(dev);
792 int n_desc;
793
794 #if DEBUG_TX
795 printk(KERN_DEBUG DRV_NAME ": hss_hdlc_txdone_irq\n");
796 #endif
797 while ((n_desc = queue_get_desc(queue_ids[port->id].txdone,
798 port, 1)) >= 0) {
799 struct desc *desc;
800 int start;
801
802 desc = tx_desc_ptr(port, n_desc);
803
804 dev->stats.tx_packets++;
805 dev->stats.tx_bytes += desc->pkt_len;
806
807 dma_unmap_tx(port, desc);
808 #if DEBUG_TX
809 printk(KERN_DEBUG "%s: hss_hdlc_txdone_irq free %p\n",
810 dev->name, port->tx_buff_tab[n_desc]);
811 #endif
812 free_buffer_irq(port->tx_buff_tab[n_desc]);
813 port->tx_buff_tab[n_desc] = NULL;
814
815 start = qmgr_stat_below_low_watermark(port->plat->txreadyq);
816 queue_put_desc(port->plat->txreadyq,
817 tx_desc_phys(port, n_desc), desc);
818 if (start) { /* TX-ready queue was empty */
819 #if DEBUG_TX
820 printk(KERN_DEBUG "%s: hss_hdlc_txdone_irq xmit"
821 " ready\n", dev->name);
822 #endif
823 netif_wake_queue(dev);
824 }
825 }
826 }
827
828 static int hss_hdlc_xmit(struct sk_buff *skb, struct net_device *dev)
829 {
830 struct port *port = dev_to_port(dev);
831 unsigned int txreadyq = port->plat->txreadyq;
832 int len, offset, bytes, n;
833 void *mem;
834 u32 phys;
835 struct desc *desc;
836
837 #if DEBUG_TX
838 printk(KERN_DEBUG "%s: hss_hdlc_xmit\n", dev->name);
839 #endif
840
841 if (unlikely(skb->len > HDLC_MAX_MRU)) {
842 dev_kfree_skb(skb);
843 dev->stats.tx_errors++;
844 return NETDEV_TX_OK;
845 }
846
847 debug_pkt(dev, "hss_hdlc_xmit", skb->data, skb->len);
848
849 len = skb->len;
850 #ifdef __ARMEB__
851 offset = 0; /* no need to keep alignment */
852 bytes = len;
853 mem = skb->data;
854 #else
855 offset = (int)skb->data & 3; /* keep 32-bit alignment */
856 bytes = ALIGN(offset + len, 4);
857 if (!(mem = kmalloc(bytes, GFP_ATOMIC))) {
858 dev_kfree_skb(skb);
859 dev->stats.tx_dropped++;
860 return NETDEV_TX_OK;
861 }
862 memcpy_swab32(mem, (u32 *)((uintptr_t)skb->data & ~3), bytes / 4);
863 dev_kfree_skb(skb);
864 #endif
865
866 phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE);
867 if (dma_mapping_error(&dev->dev, phys)) {
868 #ifdef __ARMEB__
869 dev_kfree_skb(skb);
870 #else
871 kfree(mem);
872 #endif
873 dev->stats.tx_dropped++;
874 return NETDEV_TX_OK;
875 }
876
877 n = queue_get_desc(txreadyq, port, 1);
878 BUG_ON(n < 0);
879 desc = tx_desc_ptr(port, n);
880
881 #ifdef __ARMEB__
882 port->tx_buff_tab[n] = skb;
883 #else
884 port->tx_buff_tab[n] = mem;
885 #endif
886 desc->data = phys + offset;
887 desc->buf_len = desc->pkt_len = len;
888
889 wmb();
890 queue_put_desc(queue_ids[port->id].tx, tx_desc_phys(port, n), desc);
891
892 if (qmgr_stat_below_low_watermark(txreadyq)) { /* empty */
893 #if DEBUG_TX
894 printk(KERN_DEBUG "%s: hss_hdlc_xmit queue full\n", dev->name);
895 #endif
896 netif_stop_queue(dev);
897 /* we could miss TX ready interrupt */
898 if (!qmgr_stat_below_low_watermark(txreadyq)) {
899 #if DEBUG_TX
900 printk(KERN_DEBUG "%s: hss_hdlc_xmit ready again\n",
901 dev->name);
902 #endif
903 netif_wake_queue(dev);
904 }
905 }
906
907 #if DEBUG_TX
908 printk(KERN_DEBUG "%s: hss_hdlc_xmit end\n", dev->name);
909 #endif
910 return NETDEV_TX_OK;
911 }
912
913
914 static int request_hdlc_queues(struct port *port)
915 {
916 int err;
917
918 err = qmgr_request_queue(queue_ids[port->id].rxfree, RX_DESCS, 0, 0,
919 "%s:RX-free", port->netdev->name);
920 if (err)
921 return err;
922
923 err = qmgr_request_queue(queue_ids[port->id].rx, RX_DESCS, 0, 0,
924 "%s:RX", port->netdev->name);
925 if (err)
926 goto rel_rxfree;
927
928 err = qmgr_request_queue(queue_ids[port->id].tx, TX_DESCS, 0, 0,
929 "%s:TX", port->netdev->name);
930 if (err)
931 goto rel_rx;
932
933 err = qmgr_request_queue(port->plat->txreadyq, TX_DESCS, 0, 0,
934 "%s:TX-ready", port->netdev->name);
935 if (err)
936 goto rel_tx;
937
938 err = qmgr_request_queue(queue_ids[port->id].txdone, TX_DESCS, 0, 0,
939 "%s:TX-done", port->netdev->name);
940 if (err)
941 goto rel_txready;
942 return 0;
943
944 rel_txready:
945 qmgr_release_queue(port->plat->txreadyq);
946 rel_tx:
947 qmgr_release_queue(queue_ids[port->id].tx);
948 rel_rx:
949 qmgr_release_queue(queue_ids[port->id].rx);
950 rel_rxfree:
951 qmgr_release_queue(queue_ids[port->id].rxfree);
952 printk(KERN_DEBUG "%s: unable to request hardware queues\n",
953 port->netdev->name);
954 return err;
955 }
956
957 static void release_hdlc_queues(struct port *port)
958 {
959 qmgr_release_queue(queue_ids[port->id].rxfree);
960 qmgr_release_queue(queue_ids[port->id].rx);
961 qmgr_release_queue(queue_ids[port->id].txdone);
962 qmgr_release_queue(queue_ids[port->id].tx);
963 qmgr_release_queue(port->plat->txreadyq);
964 }
965
966 static int init_hdlc_queues(struct port *port)
967 {
968 int i;
969
970 if (!ports_open) {
971 dma_pool = dma_pool_create(DRV_NAME, &port->netdev->dev,
972 POOL_ALLOC_SIZE, 32, 0);
973 if (!dma_pool)
974 return -ENOMEM;
975 }
976
977 if (!(port->desc_tab = dma_pool_alloc(dma_pool, GFP_KERNEL,
978 &port->desc_tab_phys)))
979 return -ENOMEM;
980 memset(port->desc_tab, 0, POOL_ALLOC_SIZE);
981 memset(port->rx_buff_tab, 0, sizeof(port->rx_buff_tab)); /* tables */
982 memset(port->tx_buff_tab, 0, sizeof(port->tx_buff_tab));
983
984 /* Setup RX buffers */
985 for (i = 0; i < RX_DESCS; i++) {
986 struct desc *desc = rx_desc_ptr(port, i);
987 buffer_t *buff;
988 void *data;
989 #ifdef __ARMEB__
990 if (!(buff = netdev_alloc_skb(port->netdev, RX_SIZE)))
991 return -ENOMEM;
992 data = buff->data;
993 #else
994 if (!(buff = kmalloc(RX_SIZE, GFP_KERNEL)))
995 return -ENOMEM;
996 data = buff;
997 #endif
998 desc->buf_len = RX_SIZE;
999 desc->data = dma_map_single(&port->netdev->dev, data,
1000 RX_SIZE, DMA_FROM_DEVICE);
1001 if (dma_mapping_error(&port->netdev->dev, desc->data)) {
1002 free_buffer(buff);
1003 return -EIO;
1004 }
1005 port->rx_buff_tab[i] = buff;
1006 }
1007
1008 return 0;
1009 }
1010
1011 static void destroy_hdlc_queues(struct port *port)
1012 {
1013 int i;
1014
1015 if (port->desc_tab) {
1016 for (i = 0; i < RX_DESCS; i++) {
1017 struct desc *desc = rx_desc_ptr(port, i);
1018 buffer_t *buff = port->rx_buff_tab[i];
1019 if (buff) {
1020 dma_unmap_single(&port->netdev->dev,
1021 desc->data, RX_SIZE,
1022 DMA_FROM_DEVICE);
1023 free_buffer(buff);
1024 }
1025 }
1026 for (i = 0; i < TX_DESCS; i++) {
1027 struct desc *desc = tx_desc_ptr(port, i);
1028 buffer_t *buff = port->tx_buff_tab[i];
1029 if (buff) {
1030 dma_unmap_tx(port, desc);
1031 free_buffer(buff);
1032 }
1033 }
1034 dma_pool_free(dma_pool, port->desc_tab, port->desc_tab_phys);
1035 port->desc_tab = NULL;
1036 }
1037
1038 if (!ports_open && dma_pool) {
1039 dma_pool_destroy(dma_pool);
1040 dma_pool = NULL;
1041 }
1042 }
1043
1044 static int hss_hdlc_open(struct net_device *dev)
1045 {
1046 struct port *port = dev_to_port(dev);
1047 unsigned long flags;
1048 int i, err = 0;
1049
1050 if ((err = hdlc_open(dev)))
1051 return err;
1052
1053 if ((err = hss_load_firmware(port)))
1054 goto err_hdlc_close;
1055
1056 if ((err = request_hdlc_queues(port)))
1057 goto err_hdlc_close;
1058
1059 if ((err = init_hdlc_queues(port)))
1060 goto err_destroy_queues;
1061
1062 spin_lock_irqsave(&npe_lock, flags);
1063 if (port->plat->open)
1064 if ((err = port->plat->open(port->id, dev,
1065 hss_hdlc_set_carrier)))
1066 goto err_unlock;
1067 spin_unlock_irqrestore(&npe_lock, flags);
1068
1069 /* Populate queues with buffers, no failure after this point */
1070 for (i = 0; i < TX_DESCS; i++)
1071 queue_put_desc(port->plat->txreadyq,
1072 tx_desc_phys(port, i), tx_desc_ptr(port, i));
1073
1074 for (i = 0; i < RX_DESCS; i++)
1075 queue_put_desc(queue_ids[port->id].rxfree,
1076 rx_desc_phys(port, i), rx_desc_ptr(port, i));
1077
1078 napi_enable(&port->napi);
1079 netif_start_queue(dev);
1080
1081 qmgr_set_irq(queue_ids[port->id].rx, QUEUE_IRQ_SRC_NOT_EMPTY,
1082 hss_hdlc_rx_irq, dev);
1083
1084 qmgr_set_irq(queue_ids[port->id].txdone, QUEUE_IRQ_SRC_NOT_EMPTY,
1085 hss_hdlc_txdone_irq, dev);
1086 qmgr_enable_irq(queue_ids[port->id].txdone);
1087
1088 ports_open++;
1089
1090 hss_set_hdlc_cfg(port);
1091 hss_config(port);
1092
1093 hss_start_hdlc(port);
1094
1095 /* we may already have RX data, enables IRQ */
1096 napi_schedule(&port->napi);
1097 return 0;
1098
1099 err_unlock:
1100 spin_unlock_irqrestore(&npe_lock, flags);
1101 err_destroy_queues:
1102 destroy_hdlc_queues(port);
1103 release_hdlc_queues(port);
1104 err_hdlc_close:
1105 hdlc_close(dev);
1106 return err;
1107 }
1108
1109 static int hss_hdlc_close(struct net_device *dev)
1110 {
1111 struct port *port = dev_to_port(dev);
1112 unsigned long flags;
1113 int i, buffs = RX_DESCS; /* allocated RX buffers */
1114
1115 spin_lock_irqsave(&npe_lock, flags);
1116 ports_open--;
1117 qmgr_disable_irq(queue_ids[port->id].rx);
1118 netif_stop_queue(dev);
1119 napi_disable(&port->napi);
1120
1121 hss_stop_hdlc(port);
1122
1123 while (queue_get_desc(queue_ids[port->id].rxfree, port, 0) >= 0)
1124 buffs--;
1125 while (queue_get_desc(queue_ids[port->id].rx, port, 0) >= 0)
1126 buffs--;
1127
1128 if (buffs)
1129 netdev_crit(dev, "unable to drain RX queue, %i buffer(s) left in NPE\n",
1130 buffs);
1131
1132 buffs = TX_DESCS;
1133 while (queue_get_desc(queue_ids[port->id].tx, port, 1) >= 0)
1134 buffs--; /* cancel TX */
1135
1136 i = 0;
1137 do {
1138 while (queue_get_desc(port->plat->txreadyq, port, 1) >= 0)
1139 buffs--;
1140 if (!buffs)
1141 break;
1142 } while (++i < MAX_CLOSE_WAIT);
1143
1144 if (buffs)
1145 netdev_crit(dev, "unable to drain TX queue, %i buffer(s) left in NPE\n",
1146 buffs);
1147 #if DEBUG_CLOSE
1148 if (!buffs)
1149 printk(KERN_DEBUG "Draining TX queues took %i cycles\n", i);
1150 #endif
1151 qmgr_disable_irq(queue_ids[port->id].txdone);
1152
1153 if (port->plat->close)
1154 port->plat->close(port->id, dev);
1155 spin_unlock_irqrestore(&npe_lock, flags);
1156
1157 destroy_hdlc_queues(port);
1158 release_hdlc_queues(port);
1159 hdlc_close(dev);
1160 return 0;
1161 }
1162
1163
1164 static int hss_hdlc_attach(struct net_device *dev, unsigned short encoding,
1165 unsigned short parity)
1166 {
1167 struct port *port = dev_to_port(dev);
1168
1169 if (encoding != ENCODING_NRZ)
1170 return -EINVAL;
1171
1172 switch(parity) {
1173 case PARITY_CRC16_PR1_CCITT:
1174 port->hdlc_cfg = 0;
1175 return 0;
1176
1177 case PARITY_CRC32_PR1_CCITT:
1178 port->hdlc_cfg = PKT_HDLC_CRC_32;
1179 return 0;
1180
1181 default:
1182 return -EINVAL;
1183 }
1184 }
1185
1186 static u32 check_clock(u32 timer_freq, u32 rate, u32 a, u32 b, u32 c,
1187 u32 *best, u32 *best_diff, u32 *reg)
1188 {
1189 /* a is 10-bit, b is 10-bit, c is 12-bit */
1190 u64 new_rate;
1191 u32 new_diff;
1192
1193 new_rate = timer_freq * (u64)(c + 1);
1194 do_div(new_rate, a * (c + 1) + b + 1);
1195 new_diff = abs((u32)new_rate - rate);
1196
1197 if (new_diff < *best_diff) {
1198 *best = new_rate;
1199 *best_diff = new_diff;
1200 *reg = (a << 22) | (b << 12) | c;
1201 }
1202 return new_diff;
1203 }
1204
1205 static void find_best_clock(u32 timer_freq, u32 rate, u32 *best, u32 *reg)
1206 {
1207 u32 a, b, diff = 0xFFFFFFFF;
1208
1209 a = timer_freq / rate;
1210
1211 if (a > 0x3FF) { /* 10-bit value - we can go as slow as ca. 65 kb/s */
1212 check_clock(timer_freq, rate, 0x3FF, 1, 1, best, &diff, reg);
1213 return;
1214 }
1215 if (a == 0) { /* > 66.666 MHz */
1216 a = 1; /* minimum divider is 1 (a = 0, b = 1, c = 1) */
1217 rate = timer_freq;
1218 }
1219
1220 if (rate * a == timer_freq) { /* don't divide by 0 later */
1221 check_clock(timer_freq, rate, a - 1, 1, 1, best, &diff, reg);
1222 return;
1223 }
1224
1225 for (b = 0; b < 0x400; b++) {
1226 u64 c = (b + 1) * (u64)rate;
1227 do_div(c, timer_freq - rate * a);
1228 c--;
1229 if (c >= 0xFFF) { /* 12-bit - no need to check more 'b's */
1230 if (b == 0 && /* also try a bit higher rate */
1231 !check_clock(timer_freq, rate, a - 1, 1, 1, best,
1232 &diff, reg))
1233 return;
1234 check_clock(timer_freq, rate, a, b, 0xFFF, best,
1235 &diff, reg);
1236 return;
1237 }
1238 if (!check_clock(timer_freq, rate, a, b, c, best, &diff, reg))
1239 return;
1240 if (!check_clock(timer_freq, rate, a, b, c + 1, best, &diff,
1241 reg))
1242 return;
1243 }
1244 }
1245
1246 static int hss_hdlc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1247 {
1248 const size_t size = sizeof(sync_serial_settings);
1249 sync_serial_settings new_line;
1250 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1251 struct port *port = dev_to_port(dev);
1252 unsigned long flags;
1253 int clk;
1254
1255 if (cmd != SIOCWANDEV)
1256 return hdlc_ioctl(dev, ifr, cmd);
1257
1258 switch(ifr->ifr_settings.type) {
1259 case IF_GET_IFACE:
1260 ifr->ifr_settings.type = IF_IFACE_V35;
1261 if (ifr->ifr_settings.size < size) {
1262 ifr->ifr_settings.size = size; /* data size wanted */
1263 return -ENOBUFS;
1264 }
1265 memset(&new_line, 0, sizeof(new_line));
1266 new_line.clock_type = port->clock_type;
1267 new_line.clock_rate = port->clock_rate;
1268 new_line.loopback = port->loopback;
1269 if (copy_to_user(line, &new_line, size))
1270 return -EFAULT;
1271 return 0;
1272
1273 case IF_IFACE_SYNC_SERIAL:
1274 case IF_IFACE_V35:
1275 if(!capable(CAP_NET_ADMIN))
1276 return -EPERM;
1277 if (copy_from_user(&new_line, line, size))
1278 return -EFAULT;
1279
1280 clk = new_line.clock_type;
1281 if (port->plat->set_clock)
1282 clk = port->plat->set_clock(port->id, clk);
1283
1284 if (clk != CLOCK_EXT && clk != CLOCK_INT)
1285 return -EINVAL; /* No such clock setting */
1286
1287 if (new_line.loopback != 0 && new_line.loopback != 1)
1288 return -EINVAL;
1289
1290 port->clock_type = clk; /* Update settings */
1291 if (clk == CLOCK_INT)
1292 find_best_clock(port->plat->timer_freq,
1293 new_line.clock_rate,
1294 &port->clock_rate, &port->clock_reg);
1295 else {
1296 port->clock_rate = 0;
1297 port->clock_reg = CLK42X_SPEED_2048KHZ;
1298 }
1299 port->loopback = new_line.loopback;
1300
1301 spin_lock_irqsave(&npe_lock, flags);
1302
1303 if (dev->flags & IFF_UP)
1304 hss_config(port);
1305
1306 if (port->loopback || port->carrier)
1307 netif_carrier_on(port->netdev);
1308 else
1309 netif_carrier_off(port->netdev);
1310 spin_unlock_irqrestore(&npe_lock, flags);
1311
1312 return 0;
1313
1314 default:
1315 return hdlc_ioctl(dev, ifr, cmd);
1316 }
1317 }
1318
1319 /*****************************************************************************
1320 * initialization
1321 ****************************************************************************/
1322
1323 static const struct net_device_ops hss_hdlc_ops = {
1324 .ndo_open = hss_hdlc_open,
1325 .ndo_stop = hss_hdlc_close,
1326 .ndo_start_xmit = hdlc_start_xmit,
1327 .ndo_do_ioctl = hss_hdlc_ioctl,
1328 };
1329
1330 static int hss_init_one(struct platform_device *pdev)
1331 {
1332 struct port *port;
1333 struct net_device *dev;
1334 hdlc_device *hdlc;
1335 int err;
1336
1337 if ((port = kzalloc(sizeof(*port), GFP_KERNEL)) == NULL)
1338 return -ENOMEM;
1339
1340 if ((port->npe = npe_request(0)) == NULL) {
1341 err = -ENODEV;
1342 goto err_free;
1343 }
1344
1345 if ((port->netdev = dev = alloc_hdlcdev(port)) == NULL) {
1346 err = -ENOMEM;
1347 goto err_plat;
1348 }
1349
1350 SET_NETDEV_DEV(dev, &pdev->dev);
1351 hdlc = dev_to_hdlc(dev);
1352 hdlc->attach = hss_hdlc_attach;
1353 hdlc->xmit = hss_hdlc_xmit;
1354 dev->netdev_ops = &hss_hdlc_ops;
1355 dev->tx_queue_len = 100;
1356 port->clock_type = CLOCK_EXT;
1357 port->clock_rate = 0;
1358 port->clock_reg = CLK42X_SPEED_2048KHZ;
1359 port->id = pdev->id;
1360 port->dev = &pdev->dev;
1361 port->plat = pdev->dev.platform_data;
1362 netif_napi_add(dev, &port->napi, hss_hdlc_poll, NAPI_WEIGHT);
1363
1364 if ((err = register_hdlc_device(dev)))
1365 goto err_free_netdev;
1366
1367 platform_set_drvdata(pdev, port);
1368
1369 netdev_info(dev, "initialized\n");
1370 return 0;
1371
1372 err_free_netdev:
1373 free_netdev(dev);
1374 err_plat:
1375 npe_release(port->npe);
1376 err_free:
1377 kfree(port);
1378 return err;
1379 }
1380
1381 static int hss_remove_one(struct platform_device *pdev)
1382 {
1383 struct port *port = platform_get_drvdata(pdev);
1384
1385 unregister_hdlc_device(port->netdev);
1386 free_netdev(port->netdev);
1387 npe_release(port->npe);
1388 kfree(port);
1389 return 0;
1390 }
1391
1392 static struct platform_driver ixp4xx_hss_driver = {
1393 .driver.name = DRV_NAME,
1394 .probe = hss_init_one,
1395 .remove = hss_remove_one,
1396 };
1397
1398 static int __init hss_init_module(void)
1399 {
1400 if ((ixp4xx_read_feature_bits() &
1401 (IXP4XX_FEATURE_HDLC | IXP4XX_FEATURE_HSS)) !=
1402 (IXP4XX_FEATURE_HDLC | IXP4XX_FEATURE_HSS))
1403 return -ENODEV;
1404
1405 spin_lock_init(&npe_lock);
1406
1407 return platform_driver_register(&ixp4xx_hss_driver);
1408 }
1409
1410 static void __exit hss_cleanup_module(void)
1411 {
1412 platform_driver_unregister(&ixp4xx_hss_driver);
1413 }
1414
1415 MODULE_AUTHOR("Krzysztof Halasa");
1416 MODULE_DESCRIPTION("Intel IXP4xx HSS driver");
1417 MODULE_LICENSE("GPL v2");
1418 MODULE_ALIAS("platform:ixp4xx_hss");
1419 module_init(hss_init_module);
1420 module_exit(hss_cleanup_module);
Linux with added FPC-III support