drivers/net/wireless/ath/ath11k/hal_tx.c

   1 // SPDX-License-Identifier: BSD-3-Clause-Clear
   2 /*
   3  * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include "ahb.h"
   7 #include "hal.h"
   8 #include "hal_tx.h"
   9
  10 #define DSCP_TID_MAP_TBL_ENTRY_SIZE 64
  11
  12 /* dscp_tid_map - Default DSCP-TID mapping
  13  *
  14  * DSCP        TID
  15  * 000000      0
  16  * 001000      1
  17  * 010000      2
  18  * 011000      3
  19  * 100000      4
  20  * 101000      5
  21  * 110000      6
  22  * 111000      7
  23  */
  24 static const u8 dscp_tid_map[DSCP_TID_MAP_TBL_ENTRY_SIZE] = {
  25         0, 0, 0, 0, 0, 0, 0, 0,
  26         1, 1, 1, 1, 1, 1, 1, 1,
  27         2, 2, 2, 2, 2, 2, 2, 2,
  28         3, 3, 3, 3, 3, 3, 3, 3,
  29         4, 4, 4, 4, 4, 4, 4, 4,
  30         5, 5, 5, 5, 5, 5, 5, 5,
  31         6, 6, 6, 6, 6, 6, 6, 6,
  32         7, 7, 7, 7, 7, 7, 7, 7,
  33 };
  34
  35 void ath11k_hal_tx_cmd_desc_setup(struct ath11k_base *ab, void *cmd,
  36                                   struct hal_tx_info *ti)
  37 {
  38         struct hal_tcl_data_cmd *tcl_cmd = (struct hal_tcl_data_cmd *)cmd;
  39
  40         tcl_cmd->buf_addr_info.info0 =
  41                 FIELD_PREP(BUFFER_ADDR_INFO0_ADDR, ti->paddr);
  42         tcl_cmd->buf_addr_info.info1 =
  43                 FIELD_PREP(BUFFER_ADDR_INFO1_ADDR,
  44                            ((uint64_t)ti->paddr >> HAL_ADDR_MSB_REG_SHIFT));
  45         tcl_cmd->buf_addr_info.info1 |=
  46                 FIELD_PREP(BUFFER_ADDR_INFO1_RET_BUF_MGR,
  47                            (ti->ring_id + HAL_RX_BUF_RBM_SW0_BM)) |
  48                 FIELD_PREP(BUFFER_ADDR_INFO1_SW_COOKIE, ti->desc_id);
  49
  50         tcl_cmd->info0 =
  51                 FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_DESC_TYPE, ti->type) |
  52                 FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_ENCAP_TYPE, ti->encap_type) |
  53                 FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_ENCRYPT_TYPE,
  54                            ti->encrypt_type) |
  55                 FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_SEARCH_TYPE,
  56                            ti->search_type) |
  57                 FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_ADDR_EN,
  58                            ti->addr_search_flags) |
  59                 FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_CMD_NUM,
  60                            ti->meta_data_flags);
  61
  62         tcl_cmd->info1 = ti->flags0 |
  63                 FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_DATA_LEN, ti->data_len) |
  64                 FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_PKT_OFFSET, ti->pkt_offset);
  65
  66         tcl_cmd->info2 = ti->flags1 |
  67                 FIELD_PREP(HAL_TCL_DATA_CMD_INFO2_TID, ti->tid) |
  68                 FIELD_PREP(HAL_TCL_DATA_CMD_INFO2_LMAC_ID, ti->lmac_id);
  69
  70         tcl_cmd->info3 = FIELD_PREP(HAL_TCL_DATA_CMD_INFO3_DSCP_TID_TABLE_IDX,
  71                                     ti->dscp_tid_tbl_idx) |
  72                          FIELD_PREP(HAL_TCL_DATA_CMD_INFO3_SEARCH_INDEX,
  73                                     ti->bss_ast_hash);
  74         tcl_cmd->info4 = 0;
  75 }
  76
  77 void ath11k_hal_tx_set_dscp_tid_map(struct ath11k_base *ab, int id)
  78 {
  79         u32 ctrl_reg_val;
  80         u32 addr;
  81         u8 hw_map_val[HAL_DSCP_TID_TBL_SIZE];
  82         int i;
  83         u32 value;
  84         int cnt = 0;
  85
  86         ctrl_reg_val = ath11k_ahb_read32(ab, HAL_SEQ_WCSS_UMAC_TCL_REG +
  87                                          HAL_TCL1_RING_CMN_CTRL_REG);
  88         /* Enable read/write access */
  89         ctrl_reg_val |= HAL_TCL1_RING_CMN_CTRL_DSCP_TID_MAP_PROG_EN;
  90         ath11k_ahb_write32(ab, HAL_SEQ_WCSS_UMAC_TCL_REG +
  91                            HAL_TCL1_RING_CMN_CTRL_REG, ctrl_reg_val);
  92
  93         addr = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL1_RING_DSCP_TID_MAP +
  94                (4 * id * (HAL_DSCP_TID_TBL_SIZE / 4));
  95
  96         /* Configure each DSCP-TID mapping in three bits there by configure
  97          * three bytes in an iteration.
  98          */
  99         for (i = 0; i < DSCP_TID_MAP_TBL_ENTRY_SIZE; i += 8) {
 100                 value = FIELD_PREP(HAL_TCL1_RING_FIELD_DSCP_TID_MAP0,
 101                                    dscp_tid_map[i]) |
 102                         FIELD_PREP(HAL_TCL1_RING_FIELD_DSCP_TID_MAP1,
 103                                    dscp_tid_map[i + 1]) |
 104                         FIELD_PREP(HAL_TCL1_RING_FIELD_DSCP_TID_MAP2,
 105                                    dscp_tid_map[i + 2]) |
 106                         FIELD_PREP(HAL_TCL1_RING_FIELD_DSCP_TID_MAP3,
 107                                    dscp_tid_map[i + 3]) |
 108                         FIELD_PREP(HAL_TCL1_RING_FIELD_DSCP_TID_MAP4,
 109                                    dscp_tid_map[i + 4]) |
 110                         FIELD_PREP(HAL_TCL1_RING_FIELD_DSCP_TID_MAP5,
 111                                    dscp_tid_map[i + 5]) |
 112                         FIELD_PREP(HAL_TCL1_RING_FIELD_DSCP_TID_MAP6,
 113                                    dscp_tid_map[i + 6]) |
 114                         FIELD_PREP(HAL_TCL1_RING_FIELD_DSCP_TID_MAP7,
 115                                    dscp_tid_map[i + 7]);
 116                 memcpy(&hw_map_val[cnt], (u8 *)&value, 3);
 117                 cnt += 3;
 118         }
 119
 120         for (i = 0; i < HAL_DSCP_TID_TBL_SIZE; i += 4) {
 121                 ath11k_ahb_write32(ab, addr, *(u32 *)&hw_map_val[i]);
 122                 addr += 4;
 123         }
 124
 125         /* Disable read/write access */
 126         ctrl_reg_val = ath11k_ahb_read32(ab, HAL_SEQ_WCSS_UMAC_TCL_REG +
 127                                          HAL_TCL1_RING_CMN_CTRL_REG);
 128         ctrl_reg_val &= ~HAL_TCL1_RING_CMN_CTRL_DSCP_TID_MAP_PROG_EN;
 129         ath11k_ahb_write32(ab, HAL_SEQ_WCSS_UMAC_TCL_REG +
 130                            HAL_TCL1_RING_CMN_CTRL_REG,
 131                            ctrl_reg_val);
 132 }
 133
 134 void ath11k_hal_tx_init_data_ring(struct ath11k_base *ab, struct hal_srng *srng)
 135 {
 136         struct hal_srng_params params;
 137         struct hal_tlv_hdr *tlv;
 138         int i, entry_size;
 139         u8 *desc;
 140
 141         memset(&params, 0, sizeof(params));
 142
 143         entry_size = ath11k_hal_srng_get_entrysize(HAL_TCL_DATA);
 144         ath11k_hal_srng_get_params(ab, srng, &params);
 145         desc = (u8 *)params.ring_base_vaddr;
 146
 147         for (i = 0; i < params.num_entries; i++) {
 148                 tlv = (struct hal_tlv_hdr *)desc;
 149                 tlv->tl = FIELD_PREP(HAL_TLV_HDR_TAG, HAL_TCL_DATA_CMD) |
 150                           FIELD_PREP(HAL_TLV_HDR_LEN,
 151                                      sizeof(struct hal_tcl_data_cmd));
 152                 desc += entry_size;
 153         }
 154 }