| blob | 42f00a2a8c8007d255d82dca96872bd7f4456c9d |
1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
34 /* General hardware code for the AR9003 hadware family */
36 /*
37 * The AR9003 family uses a new INI format (pre, core, post
38 * arrays per subsystem). This provides support for the
39 * AR9003 2.2 chipsets.
40 */
42 {
44 /* mac */
46 ar9331_1p1_mac_core);
48 ar9331_1p1_mac_postamble);
50 /* bb */
52 ar9331_1p1_baseband_core);
54 ar9331_1p1_baseband_postamble);
56 /* radio */
58 ar9331_1p1_radio_core);
60 /* soc */
62 ar9331_1p1_soc_preamble);
64 ar9331_1p1_soc_postamble);
66 /* rx/tx gain */
68 ar9331_common_rx_gain_1p1);
70 ar9331_modes_lowest_ob_db_tx_gain_1p1);
72 /* Japan 2484 Mhz CCK */
74 ar9331_1p1_baseband_core_txfir_coeff_japan_2484);
76 /* additional clock settings */
79 ar9331_1p1_xtal_25M);
80 else
82 ar9331_1p1_xtal_40M);
84 /* mac */
86 ar9331_1p2_mac_core);
88 ar9331_1p2_mac_postamble);
90 /* bb */
92 ar9331_1p2_baseband_core);
94 ar9331_1p2_baseband_postamble);
96 /* radio */
98 ar9331_1p2_radio_core);
100 /* soc */
102 ar9331_1p2_soc_preamble);
104 ar9331_1p2_soc_postamble);
106 /* rx/tx gain */
108 ar9331_common_rx_gain_1p2);
110 ar9331_modes_lowest_ob_db_tx_gain_1p2);
112 /* Japan 2484 Mhz CCK */
114 ar9331_1p2_baseband_core_txfir_coeff_japan_2484);
116 /* additional clock settings */
119 ar9331_1p2_xtal_25M);
120 else
122 ar9331_1p2_xtal_40M);
124 /* mac */
126 ar9340_1p0_mac_core);
128 ar9340_1p0_mac_postamble);
130 /* bb */
132 ar9340_1p0_baseband_core);
134 ar9340_1p0_baseband_postamble);
136 /* radio */
138 ar9340_1p0_radio_core);
140 ar9340_1p0_radio_postamble);
142 /* soc */
144 ar9340_1p0_soc_preamble);
146 ar9340_1p0_soc_postamble);
148 /* rx/tx gain */
150 ar9340Common_wo_xlna_rx_gain_table_1p0);
152 ar9340Modes_high_ob_db_tx_gain_table_1p0);
155 ar9340Modes_fast_clock_1p0);
157 ar9340_1p0_baseband_core_txfir_coeff_japan_2484);
159 ar9340_1p0_baseband_postamble_dfs_channel);
163 ar9340_1p0_radio_core_40M);
165 /* mac */
167 ar9485_1_1_mac_core);
169 ar9485_1_1_mac_postamble);
171 /* bb */
174 ar9485_1_1_baseband_core);
176 ar9485_1_1_baseband_postamble);
178 /* radio */
180 ar9485_1_1_radio_core);
182 ar9485_1_1_radio_postamble);
184 /* soc */
186 ar9485_1_1_soc_preamble);
188 /* rx/tx gain */
190 ar9485Common_wo_xlna_rx_gain_1_1);
192 ar9485_modes_lowest_ob_db_tx_gain_1_1);
194 /* Japan 2484 Mhz CCK */
196 ar9485_1_1_baseband_core_txfir_coeff_japan_2484);
200 ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1);
202 ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1);
205 ar9485_1_1_pcie_phy_clkreq_disable_L1);
207 ar9485_1_1_pcie_phy_clkreq_disable_L1);
208 }
211 ar9462_2p1_mac_core);
213 ar9462_2p1_mac_postamble);
215 ar9462_2p1_baseband_core);
217 ar9462_2p1_baseband_postamble);
219 ar9462_2p1_radio_core);
221 ar9462_2p1_radio_postamble);
223 ar9462_2p1_radio_postamble_sys2ant);
225 ar9462_2p1_soc_preamble);
227 ar9462_2p1_soc_postamble);
229 ar9462_2p1_common_rx_gain);
231 ar9462_2p1_modes_fast_clock);
233 ar9462_2p1_baseband_core_txfir_coeff_japan_2484);
235 /* Awake -> Sleep Setting */
239 ar9462_2p1_pciephy_clkreq_disable_L1);
240 }
242 /* Sleep -> Awake Setting */
246 ar9462_2p1_pciephy_clkreq_disable_L1);
247 }
252 ar9462_2p0_mac_postamble);
255 ar9462_2p0_baseband_core);
257 ar9462_2p0_baseband_postamble);
260 ar9462_2p0_radio_core);
262 ar9462_2p0_radio_postamble);
264 ar9462_2p0_radio_postamble_sys2ant);
267 ar9462_2p0_soc_preamble);
269 ar9462_2p0_soc_postamble);
272 ar9462_2p0_common_rx_gain);
274 /* Awake -> Sleep Setting */
278 ar9462_2p0_pciephy_clkreq_disable_L1);
279 }
281 /* Sleep -> Awake Setting */
285 ar9462_2p0_pciephy_clkreq_disable_L1);
286 }
288 /* Fast clock modal settings */
290 ar9462_2p0_modes_fast_clock);
293 ar9462_2p0_baseband_core_txfir_coeff_japan_2484);
295 /* mac */
297 ar955x_1p0_mac_core);
299 ar955x_1p0_mac_postamble);
301 /* bb */
303 ar955x_1p0_baseband_core);
305 ar955x_1p0_baseband_postamble);
307 /* radio */
309 ar955x_1p0_radio_core);
311 ar955x_1p0_radio_postamble);
313 /* soc */
315 ar955x_1p0_soc_preamble);
317 ar955x_1p0_soc_postamble);
319 /* rx/tx gain */
321 ar955x_1p0_common_wo_xlna_rx_gain_table);
323 ar955x_1p0_common_wo_xlna_rx_gain_bounds);
325 ar955x_1p0_modes_xpa_tx_gain_table);
327 /* Fast clock modal settings */
329 ar955x_1p0_modes_fast_clock);
332 qca953x_1p0_mac_core);
334 qca953x_1p0_mac_postamble);
337 qca953x_2p0_baseband_core);
339 qca953x_2p0_baseband_postamble);
342 qca953x_1p0_baseband_core);
344 qca953x_1p0_baseband_postamble);
345 }
347 qca953x_1p0_radio_core);
349 qca953x_1p0_radio_postamble);
351 qca953x_1p0_soc_preamble);
353 qca953x_1p0_soc_postamble);
357 qca953x_2p0_common_wo_xlna_rx_gain_table);
359 qca953x_2p0_common_wo_xlna_rx_gain_bounds);
362 qca953x_1p0_common_wo_xlna_rx_gain_table);
364 qca953x_1p0_common_wo_xlna_rx_gain_bounds);
365 }
369 qca953x_2p0_modes_no_xpa_tx_gain_table);
372 qca953x_1p1_modes_no_xpa_tx_gain_table);
373 else
375 qca953x_1p0_modes_no_xpa_tx_gain_table);
378 qca953x_1p0_modes_fast_clock);
381 qca956x_1p0_mac_core);
383 qca956x_1p0_mac_postamble);
386 qca956x_1p0_baseband_core);
388 qca956x_1p0_baseband_postamble);
391 qca956x_1p0_radio_core);
393 qca956x_1p0_radio_postamble);
396 qca956x_1p0_soc_preamble);
398 qca956x_1p0_soc_postamble);
401 qca956x_1p0_common_wo_xlna_rx_gain_table);
403 qca956x_1p0_common_wo_xlna_rx_gain_bounds);
405 qca956x_1p0_modes_no_xpa_tx_gain_table);
408 qca956x_1p0_baseband_postamble_dfs_channel);
410 qca956x_1p0_baseband_core_txfir_coeff_japan_2484);
412 qca956x_1p0_modes_fast_clock);
414 /* mac */
416 ar9580_1p0_mac_core);
418 ar9580_1p0_mac_postamble);
420 /* bb */
422 ar9580_1p0_baseband_core);
424 ar9580_1p0_baseband_postamble);
426 /* radio */
428 ar9580_1p0_radio_core);
430 ar9580_1p0_radio_postamble);
432 /* soc */
434 ar9580_1p0_soc_preamble);
436 ar9580_1p0_soc_postamble);
438 /* rx/tx gain */
440 ar9580_1p0_rx_gain_table);
442 ar9580_1p0_low_ob_db_tx_gain_table);
445 ar9580_1p0_modes_fast_clock);
447 ar9580_1p0_baseband_core_txfir_coeff_japan_2484);
449 ar9580_1p0_baseband_postamble_dfs_channel);
452 ar9565_1p1_mac_core);
454 ar9565_1p1_mac_postamble);
457 ar9565_1p1_baseband_core);
459 ar9565_1p1_baseband_postamble);
462 ar9565_1p1_radio_core);
464 ar9565_1p1_radio_postamble);
467 ar9565_1p1_soc_preamble);
469 ar9565_1p1_soc_postamble);
472 ar9565_1p1_Common_rx_gain_table);
474 ar9565_1p1_Modes_lowest_ob_db_tx_gain_table);
476 /* Awake -> Sleep Setting */
480 ar9565_1p1_pciephy_clkreq_disable_L1);
481 }
483 /* Sleep -> Awake Setting */
487 ar9565_1p1_pciephy_clkreq_disable_L1);
488 }
491 ar9565_1p1_modes_fast_clock);
493 ar9565_1p1_baseband_core_txfir_coeff_japan_2484);
496 ar9565_1p0_mac_core);
498 ar9565_1p0_mac_postamble);
501 ar9565_1p0_baseband_core);
503 ar9565_1p0_baseband_postamble);
506 ar9565_1p0_radio_core);
508 ar9565_1p0_radio_postamble);
511 ar9565_1p0_soc_preamble);
513 ar9565_1p0_soc_postamble);
516 ar9565_1p0_Common_rx_gain_table);
518 ar9565_1p0_Modes_lowest_ob_db_tx_gain_table);
520 /* Awake -> Sleep Setting */
524 ar9565_1p0_pciephy_clkreq_disable_L1);
525 }
527 /* Sleep -> Awake Setting */
531 ar9565_1p0_pciephy_clkreq_disable_L1);
532 }
535 ar9565_1p0_modes_fast_clock);
537 ar9565_1p0_baseband_core_txfir_coeff_japan_2484);
539 /* mac */
541 ar9300_2p2_mac_core);
543 ar9300_2p2_mac_postamble);
545 /* bb */
547 ar9300_2p2_baseband_core);
549 ar9300_2p2_baseband_postamble);
551 /* radio */
553 ar9300_2p2_radio_core);
555 ar9300_2p2_radio_postamble);
557 /* soc */
559 ar9300_2p2_soc_preamble);
561 ar9300_2p2_soc_postamble);
563 /* rx/tx gain */
565 ar9300Common_rx_gain_table_2p2);
567 ar9300Modes_lowest_ob_db_tx_gain_table_2p2);
569 /* Load PCIE SERDES settings from INI */
571 /* Awake Setting */
574 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2);
576 /* Sleep Setting */
579 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2);
581 /* Fast clock modal settings */
583 ar9300Modes_fast_clock_2p2);
585 ar9300_2p2_baseband_core_txfir_coeff_japan_2484);
587 ar9300_2p2_baseband_postamble_dfs_channel);
588 }
589 }
592 {
595 ar9331_modes_lowest_ob_db_tx_gain_1p2);
598 ar9331_modes_lowest_ob_db_tx_gain_1p1);
601 ar9340Modes_lowest_ob_db_tx_gain_table_1p0);
604 ar9485_modes_lowest_ob_db_tx_gain_1_1);
607 ar955x_1p0_modes_xpa_tx_gain_table);
610 qca953x_1p0_modes_xpa_tx_gain_table);
613 qca953x_1p1_modes_xpa_tx_gain_table);
616 qca953x_2p0_modes_xpa_tx_gain_table);
619 qca956x_1p0_modes_xpa_tx_gain_table);
622 ar9580_1p0_lowest_ob_db_tx_gain_table);
625 ar9462_2p1_modes_low_ob_db_tx_gain);
628 ar9462_2p0_modes_low_ob_db_tx_gain);
631 ar9565_1p1_modes_low_ob_db_tx_gain_table);
634 ar9565_1p0_modes_low_ob_db_tx_gain_table);
635 else
637 ar9300Modes_lowest_ob_db_tx_gain_table_2p2);
638 }
641 {
644 ar9331_modes_high_ob_db_tx_gain_1p2);
647 ar9331_modes_high_ob_db_tx_gain_1p1);
650 ar9340Modes_high_ob_db_tx_gain_table_1p0);
653 ar9485Modes_high_ob_db_tx_gain_1_1);
656 ar9580_1p0_high_ob_db_tx_gain_table);
659 ar955x_1p0_modes_no_xpa_tx_gain_table);
663 qca953x_2p0_modes_no_xpa_tx_gain_table);
666 qca953x_1p1_modes_no_xpa_tx_gain_table);
667 else
669 qca953x_1p0_modes_no_xpa_tx_gain_table);
672 qca956x_1p0_modes_no_xpa_tx_gain_table);
675 ar9462_2p1_modes_high_ob_db_tx_gain);
678 ar9462_2p0_modes_high_ob_db_tx_gain);
681 ar9565_1p1_modes_high_ob_db_tx_gain_table);
684 ar9565_1p0_modes_high_ob_db_tx_gain_table);
685 else
687 ar9300Modes_high_ob_db_tx_gain_table_2p2);
688 }
691 {
694 ar9331_modes_low_ob_db_tx_gain_1p2);
697 ar9331_modes_low_ob_db_tx_gain_1p1);
700 ar9340Modes_low_ob_db_tx_gain_table_1p0);
703 qca953x_1p1_modes_no_xpa_low_power_tx_gain_table);
706 ar9485Modes_low_ob_db_tx_gain_1_1);
709 ar9580_1p0_low_ob_db_tx_gain_table);
712 qca956x_1p0_modes_no_xpa_low_ob_db_tx_gain_table);
715 ar9565_1p1_modes_low_ob_db_tx_gain_table);
718 ar9565_1p0_modes_low_ob_db_tx_gain_table);
719 else
721 ar9300Modes_low_ob_db_tx_gain_table_2p2);
722 }
725 {
728 ar9331_modes_high_power_tx_gain_1p2);
731 ar9331_modes_high_power_tx_gain_1p1);
734 ar9340Modes_high_power_tx_gain_table_1p0);
737 ar9485Modes_high_power_tx_gain_1_1);
740 ar9580_1p0_high_power_tx_gain_table);
743 ar9565_1p1_modes_high_power_tx_gain_table);
746 ar9565_1p0_modes_high_power_tx_gain_table);
750 ar9300Modes_high_power_tx_gain_table_buffalo);
751 else
753 ar9300Modes_high_power_tx_gain_table_2p2);
754 }
755 }
758 {
761 ar9340Modes_mixed_ob_db_tx_gain_table_1p0);
764 ar9580_1p0_mixed_ob_db_tx_gain_table);
767 ar9462_2p1_modes_mix_ob_db_tx_gain);
770 ar9462_2p0_modes_mix_ob_db_tx_gain);
771 else
773 ar9300Modes_mixed_ob_db_tx_gain_table_2p2);
774 }
777 {
780 ar9485Modes_green_ob_db_tx_gain_1_1);
783 ar9580_1p0_type5_tx_gain_table);
786 qca956x_1p0_modes_no_xpa_green_tx_gain_table);
789 ar9300Modes_type5_tx_gain_table_2p2);
790 }
793 {
796 ar9340Modes_low_ob_db_and_spur_tx_gain_table_1p0);
799 ar9485Modes_green_spur_ob_db_tx_gain_1_1);
802 ar9580_1p0_type6_tx_gain_table);
803 }
806 {
809 ar9340_cus227_tx_gain_table_1p0);
810 }
815 {
817 ar9003_tx_gain_table_mode0,
818 ar9003_tx_gain_table_mode1,
819 ar9003_tx_gain_table_mode2,
820 ar9003_tx_gain_table_mode3,
821 ar9003_tx_gain_table_mode4,
822 ar9003_tx_gain_table_mode5,
823 ar9003_tx_gain_table_mode6,
824 ar9003_tx_gain_table_mode7,
825 };
832 }
835 {
838 ar9331_common_rx_gain_1p2);
841 ar9331_common_rx_gain_1p1);
844 ar9340Common_rx_gain_table_1p0);
847 ar9485_common_rx_gain_1_1);
850 ar955x_1p0_common_rx_gain_table);
852 ar955x_1p0_common_rx_gain_bounds);
855 qca953x_1p0_common_rx_gain_table);
857 qca953x_1p0_common_rx_gain_bounds);
860 qca956x_1p0_common_rx_gain_table);
862 qca956x_1p0_common_rx_gain_bounds);
864 qca956x_1p0_xlna_only);
867 ar9580_1p0_rx_gain_table);
870 ar9462_2p1_common_rx_gain);
873 ar9462_2p0_common_rx_gain);
876 ar9565_1p1_Common_rx_gain_table);
879 ar9565_1p0_Common_rx_gain_table);
880 else
882 ar9300Common_rx_gain_table_2p2);
883 }
886 {
889 ar9331_common_wo_xlna_rx_gain_1p2);
892 ar9331_common_wo_xlna_rx_gain_1p1);
895 ar9340Common_wo_xlna_rx_gain_table_1p0);
898 ar9485Common_wo_xlna_rx_gain_1_1);
901 ar9462_2p1_common_wo_xlna_rx_gain);
904 ar9462_2p0_common_wo_xlna_rx_gain);
907 ar955x_1p0_common_wo_xlna_rx_gain_table);
909 ar955x_1p0_common_wo_xlna_rx_gain_bounds);
912 qca953x_1p0_common_wo_xlna_rx_gain_table);
914 qca953x_1p0_common_wo_xlna_rx_gain_bounds);
917 qca953x_2p0_common_wo_xlna_rx_gain_table);
919 qca953x_2p0_common_wo_xlna_rx_gain_bounds);
922 qca956x_1p0_common_wo_xlna_rx_gain_table);
924 qca956x_1p0_common_wo_xlna_rx_gain_bounds);
927 ar9580_1p0_wo_xlna_rx_gain_table);
930 ar9565_1p1_common_wo_xlna_rx_gain_table);
933 ar9565_1p0_common_wo_xlna_rx_gain_table);
934 else
936 ar9300Common_wo_xlna_rx_gain_table_2p2);
937 }
940 {
943 ar9462_2p1_common_mixed_rx_gain);
945 ar9462_2p1_baseband_core_mix_rxgain);
947 ar9462_2p1_baseband_postamble_mix_rxgain);
949 ar9462_2p1_baseband_postamble_5g_xlna);
952 ar9462_2p0_common_mixed_rx_gain);
954 ar9462_2p0_baseband_core_mix_rxgain);
956 ar9462_2p0_baseband_postamble_mix_rxgain);
958 ar9462_2p0_baseband_postamble_5g_xlna);
959 }
960 }
963 {
966 ar9462_2p1_common_5g_xlna_only_rxgain);
968 ar9462_2p1_baseband_postamble_5g_xlna);
971 ar9462_2p0_common_5g_xlna_only_rxgain);
973 ar9462_2p0_baseband_postamble_5g_xlna);
974 }
975 }
978 {
993 }
994 }
996 /* set gain table pointers according to values read from the eeprom */
998 {
1001 }
1003 /*
1004 * Helper for ASPM support.
1005 *
1006 * Disable PLL when in L0s as well as receiver clock when in L1.
1007 * This power saving option must be enabled through the SerDes.
1008 *
1009 * Programming the SerDes must go through the same 288 bit serial shift
1010 * register as the other analog registers. Hence the 9 writes.
1011 */
1014 {
1018 /*
1019 * Increase L1 Entry Latency. Some WB222 boards don't have
1020 * this change in eeprom/OTP.
1021 *
1022 */
1029 }
1030 }
1032 /* Nothing to do on restore for 11N */
1034 /* set bit 19 to allow forcing of pcie core into L1 state */
1037 }
1039 /*
1040 * Configure PCIE after Ini init. SERDES values now come from ini file
1041 * This enables PCIe low power mode.
1042 */
1050 }
1051 }
1054 {
1055 /*
1056 * All chips support detection of BB/MAC hangs.
1057 */
1061 /*
1062 * This is not required for AR9580 1.0
1063 */
1069 else
1071 }
1073 /*
1074 * MAC HW hang check
1075 * =================
1076 *
1077 * Signature: dcu_chain_state is 0x6 and dcu_complete_state is 0x1.
1078 *
1079 * The state of each DCU chain (mapped to TX queues) is available from these
1080 * DMA debug registers:
1081 *
1082 * Chain 0 state : Bits 4:0 of AR_DMADBG_4
1083 * Chain 1 state : Bits 9:5 of AR_DMADBG_4
1084 * Chain 2 state : Bits 14:10 of AR_DMADBG_4
1085 * Chain 3 state : Bits 19:15 of AR_DMADBG_4
1086 * Chain 4 state : Bits 24:20 of AR_DMADBG_4
1087 * Chain 5 state : Bits 29:25 of AR_DMADBG_4
1088 * Chain 6 state : Bits 4:0 of AR_DMADBG_5
1089 * Chain 7 state : Bits 9:5 of AR_DMADBG_5
1090 * Chain 8 state : Bits 14:10 of AR_DMADBG_5
1091 * Chain 9 state : Bits 19:15 of AR_DMADBG_5
1092 *
1093 * The DCU chain state "0x6" means "WAIT_FRDONE" - wait for TX frame to be done.
1094 */
1096 #define NUM_STATUS_READS 50
1099 {
1107 else
1117 }
1123 }
1126 {
1144 else
1151 }
1152 }
1158 }
1159 }
1160 exit:
1162 }
1164 /* Sets up the AR9003 hardware familiy callbacks */
1166 {
1175 }
1187 }