2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/dma-mapping.h>
19 #include "ar9003_mac.h"
21 #define BITS_PER_BYTE 8
22 #define OFDM_PLCP_BITS 22
23 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
29 #define HT_LTF(_ns) (4 * (_ns))
30 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
31 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
32 #define TIME_SYMBOLS(t) ((t) >> 2)
33 #define TIME_SYMBOLS_HALFGI(t) (((t) * 5 - 4) / 18)
34 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
35 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
38 static u16 bits_per_symbol
[][2] = {
40 { 26, 54 }, /* 0: BPSK */
41 { 52, 108 }, /* 1: QPSK 1/2 */
42 { 78, 162 }, /* 2: QPSK 3/4 */
43 { 104, 216 }, /* 3: 16-QAM 1/2 */
44 { 156, 324 }, /* 4: 16-QAM 3/4 */
45 { 208, 432 }, /* 5: 64-QAM 2/3 */
46 { 234, 486 }, /* 6: 64-QAM 3/4 */
47 { 260, 540 }, /* 7: 64-QAM 5/6 */
50 static void ath_tx_send_normal(struct ath_softc
*sc
, struct ath_txq
*txq
,
51 struct ath_atx_tid
*tid
, struct sk_buff
*skb
);
52 static void ath_tx_complete(struct ath_softc
*sc
, struct sk_buff
*skb
,
53 int tx_flags
, struct ath_txq
*txq
,
54 struct ieee80211_sta
*sta
);
55 static void ath_tx_complete_buf(struct ath_softc
*sc
, struct ath_buf
*bf
,
56 struct ath_txq
*txq
, struct list_head
*bf_q
,
57 struct ieee80211_sta
*sta
,
58 struct ath_tx_status
*ts
, int txok
);
59 static void ath_tx_txqaddbuf(struct ath_softc
*sc
, struct ath_txq
*txq
,
60 struct list_head
*head
, bool internal
);
61 static void ath_tx_rc_status(struct ath_softc
*sc
, struct ath_buf
*bf
,
62 struct ath_tx_status
*ts
, int nframes
, int nbad
,
64 static void ath_tx_update_baw(struct ath_softc
*sc
, struct ath_atx_tid
*tid
,
66 static struct ath_buf
*ath_tx_setup_buffer(struct ath_softc
*sc
,
68 struct ath_atx_tid
*tid
,
70 static int ath_tx_prepare(struct ieee80211_hw
*hw
, struct sk_buff
*skb
,
71 struct ath_tx_control
*txctl
);
80 /*********************/
81 /* Aggregation logic */
82 /*********************/
84 static void ath_tx_status(struct ieee80211_hw
*hw
, struct sk_buff
*skb
)
86 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
87 struct ieee80211_sta
*sta
= info
->status
.status_driver_data
[0];
89 if (info
->flags
& (IEEE80211_TX_CTL_REQ_TX_STATUS
|
90 IEEE80211_TX_STATUS_EOSP
)) {
91 ieee80211_tx_status(hw
, skb
);
96 ieee80211_tx_status_noskb(hw
, sta
, info
);
101 void ath_txq_unlock_complete(struct ath_softc
*sc
, struct ath_txq
*txq
)
102 __releases(&txq
->axq_lock
)
104 struct ieee80211_hw
*hw
= sc
->hw
;
105 struct sk_buff_head q
;
108 __skb_queue_head_init(&q
);
109 skb_queue_splice_init(&txq
->complete_q
, &q
);
110 spin_unlock_bh(&txq
->axq_lock
);
112 while ((skb
= __skb_dequeue(&q
)))
113 ath_tx_status(hw
, skb
);
116 void ath_tx_queue_tid(struct ath_softc
*sc
, struct ath_atx_tid
*tid
)
118 struct ieee80211_txq
*queue
=
119 container_of((void *)tid
, struct ieee80211_txq
, drv_priv
);
121 ieee80211_schedule_txq(sc
->hw
, queue
);
124 void ath9k_wake_tx_queue(struct ieee80211_hw
*hw
, struct ieee80211_txq
*queue
)
126 struct ath_softc
*sc
= hw
->priv
;
127 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
128 struct ath_atx_tid
*tid
= (struct ath_atx_tid
*) queue
->drv_priv
;
129 struct ath_txq
*txq
= tid
->txq
;
131 ath_dbg(common
, QUEUE
, "Waking TX queue: %pM (%d)\n",
132 queue
->sta
? queue
->sta
->addr
: queue
->vif
->addr
,
135 ath_txq_lock(sc
, txq
);
136 ath_txq_schedule(sc
, txq
);
137 ath_txq_unlock(sc
, txq
);
140 static struct ath_frame_info
*get_frame_info(struct sk_buff
*skb
)
142 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
143 BUILD_BUG_ON(sizeof(struct ath_frame_info
) >
144 sizeof(tx_info
->rate_driver_data
));
145 return (struct ath_frame_info
*) &tx_info
->rate_driver_data
[0];
148 static void ath_send_bar(struct ath_atx_tid
*tid
, u16 seqno
)
153 ieee80211_send_bar(tid
->an
->vif
, tid
->an
->sta
->addr
, tid
->tidno
,
154 seqno
<< IEEE80211_SEQ_SEQ_SHIFT
);
157 static void ath_set_rates(struct ieee80211_vif
*vif
, struct ieee80211_sta
*sta
,
160 ieee80211_get_tx_rates(vif
, sta
, bf
->bf_mpdu
, bf
->rates
,
161 ARRAY_SIZE(bf
->rates
));
164 static void ath_txq_skb_done(struct ath_softc
*sc
, struct ath_txq
*txq
,
167 struct ath_frame_info
*fi
= get_frame_info(skb
);
173 txq
= sc
->tx
.txq_map
[q
];
174 if (WARN_ON(--txq
->pending_frames
< 0))
175 txq
->pending_frames
= 0;
179 static struct ath_atx_tid
*
180 ath_get_skb_tid(struct ath_softc
*sc
, struct ath_node
*an
, struct sk_buff
*skb
)
182 u8 tidno
= skb
->priority
& IEEE80211_QOS_CTL_TID_MASK
;
183 return ATH_AN_2_TID(an
, tidno
);
187 ath_tid_pull(struct ath_atx_tid
*tid
, struct sk_buff
**skbuf
)
189 struct ieee80211_txq
*txq
= container_of((void*)tid
, struct ieee80211_txq
, drv_priv
);
190 struct ath_softc
*sc
= tid
->an
->sc
;
191 struct ieee80211_hw
*hw
= sc
->hw
;
192 struct ath_tx_control txctl
= {
197 struct ath_frame_info
*fi
;
200 skb
= ieee80211_tx_dequeue(hw
, txq
);
204 ret
= ath_tx_prepare(hw
, skb
, &txctl
);
206 ieee80211_free_txskb(hw
, skb
);
210 q
= skb_get_queue_mapping(skb
);
211 if (tid
->txq
== sc
->tx
.txq_map
[q
]) {
212 fi
= get_frame_info(skb
);
214 ++tid
->txq
->pending_frames
;
221 static int ath_tid_dequeue(struct ath_atx_tid
*tid
,
222 struct sk_buff
**skb
)
225 *skb
= __skb_dequeue(&tid
->retry_q
);
227 ret
= ath_tid_pull(tid
, skb
);
232 static void ath_tx_flush_tid(struct ath_softc
*sc
, struct ath_atx_tid
*tid
)
234 struct ath_txq
*txq
= tid
->txq
;
237 struct list_head bf_head
;
238 struct ath_tx_status ts
;
239 struct ath_frame_info
*fi
;
240 bool sendbar
= false;
242 INIT_LIST_HEAD(&bf_head
);
244 memset(&ts
, 0, sizeof(ts
));
246 while ((skb
= __skb_dequeue(&tid
->retry_q
))) {
247 fi
= get_frame_info(skb
);
250 ath_txq_skb_done(sc
, txq
, skb
);
251 ieee80211_free_txskb(sc
->hw
, skb
);
255 if (fi
->baw_tracked
) {
256 ath_tx_update_baw(sc
, tid
, bf
);
260 list_add_tail(&bf
->list
, &bf_head
);
261 ath_tx_complete_buf(sc
, bf
, txq
, &bf_head
, NULL
, &ts
, 0);
265 ath_txq_unlock(sc
, txq
);
266 ath_send_bar(tid
, tid
->seq_start
);
267 ath_txq_lock(sc
, txq
);
271 static void ath_tx_update_baw(struct ath_softc
*sc
, struct ath_atx_tid
*tid
,
274 struct ath_frame_info
*fi
= get_frame_info(bf
->bf_mpdu
);
275 u16 seqno
= bf
->bf_state
.seqno
;
278 if (!fi
->baw_tracked
)
281 index
= ATH_BA_INDEX(tid
->seq_start
, seqno
);
282 cindex
= (tid
->baw_head
+ index
) & (ATH_TID_MAX_BUFS
- 1);
284 __clear_bit(cindex
, tid
->tx_buf
);
286 while (tid
->baw_head
!= tid
->baw_tail
&& !test_bit(tid
->baw_head
, tid
->tx_buf
)) {
287 INCR(tid
->seq_start
, IEEE80211_SEQ_MAX
);
288 INCR(tid
->baw_head
, ATH_TID_MAX_BUFS
);
289 if (tid
->bar_index
>= 0)
294 static void ath_tx_addto_baw(struct ath_softc
*sc
, struct ath_atx_tid
*tid
,
297 struct ath_frame_info
*fi
= get_frame_info(bf
->bf_mpdu
);
298 u16 seqno
= bf
->bf_state
.seqno
;
304 index
= ATH_BA_INDEX(tid
->seq_start
, seqno
);
305 cindex
= (tid
->baw_head
+ index
) & (ATH_TID_MAX_BUFS
- 1);
306 __set_bit(cindex
, tid
->tx_buf
);
309 if (index
>= ((tid
->baw_tail
- tid
->baw_head
) &
310 (ATH_TID_MAX_BUFS
- 1))) {
311 tid
->baw_tail
= cindex
;
312 INCR(tid
->baw_tail
, ATH_TID_MAX_BUFS
);
316 static void ath_tid_drain(struct ath_softc
*sc
, struct ath_txq
*txq
,
317 struct ath_atx_tid
*tid
)
322 struct list_head bf_head
;
323 struct ath_tx_status ts
;
324 struct ath_frame_info
*fi
;
327 memset(&ts
, 0, sizeof(ts
));
328 INIT_LIST_HEAD(&bf_head
);
330 while ((ret
= ath_tid_dequeue(tid
, &skb
)) == 0) {
331 fi
= get_frame_info(skb
);
335 ath_tx_complete(sc
, skb
, ATH_TX_ERROR
, txq
, NULL
);
339 list_add_tail(&bf
->list
, &bf_head
);
340 ath_tx_complete_buf(sc
, bf
, txq
, &bf_head
, NULL
, &ts
, 0);
344 static void ath_tx_set_retry(struct ath_softc
*sc
, struct ath_txq
*txq
,
345 struct sk_buff
*skb
, int count
)
347 struct ath_frame_info
*fi
= get_frame_info(skb
);
348 struct ath_buf
*bf
= fi
->bf
;
349 struct ieee80211_hdr
*hdr
;
350 int prev
= fi
->retries
;
352 TX_STAT_INC(sc
, txq
->axq_qnum
, a_retries
);
353 fi
->retries
+= count
;
358 hdr
= (struct ieee80211_hdr
*)skb
->data
;
359 hdr
->frame_control
|= cpu_to_le16(IEEE80211_FCTL_RETRY
);
360 dma_sync_single_for_device(sc
->dev
, bf
->bf_buf_addr
,
361 sizeof(*hdr
), DMA_TO_DEVICE
);
364 static struct ath_buf
*ath_tx_get_buffer(struct ath_softc
*sc
)
366 struct ath_buf
*bf
= NULL
;
368 spin_lock_bh(&sc
->tx
.txbuflock
);
370 if (unlikely(list_empty(&sc
->tx
.txbuf
))) {
371 spin_unlock_bh(&sc
->tx
.txbuflock
);
375 bf
= list_first_entry(&sc
->tx
.txbuf
, struct ath_buf
, list
);
378 spin_unlock_bh(&sc
->tx
.txbuflock
);
383 static void ath_tx_return_buffer(struct ath_softc
*sc
, struct ath_buf
*bf
)
385 spin_lock_bh(&sc
->tx
.txbuflock
);
386 list_add_tail(&bf
->list
, &sc
->tx
.txbuf
);
387 spin_unlock_bh(&sc
->tx
.txbuflock
);
390 static struct ath_buf
* ath_clone_txbuf(struct ath_softc
*sc
, struct ath_buf
*bf
)
394 tbf
= ath_tx_get_buffer(sc
);
398 ATH_TXBUF_RESET(tbf
);
400 tbf
->bf_mpdu
= bf
->bf_mpdu
;
401 tbf
->bf_buf_addr
= bf
->bf_buf_addr
;
402 memcpy(tbf
->bf_desc
, bf
->bf_desc
, sc
->sc_ah
->caps
.tx_desc_len
);
403 tbf
->bf_state
= bf
->bf_state
;
404 tbf
->bf_state
.stale
= false;
409 static void ath_tx_count_frames(struct ath_softc
*sc
, struct ath_buf
*bf
,
410 struct ath_tx_status
*ts
, int txok
,
411 int *nframes
, int *nbad
)
414 u32 ba
[WME_BA_BMP_SIZE
>> 5];
421 isaggr
= bf_isaggr(bf
);
423 seq_st
= ts
->ts_seqnum
;
424 memcpy(ba
, &ts
->ba_low
, WME_BA_BMP_SIZE
>> 3);
428 ba_index
= ATH_BA_INDEX(seq_st
, bf
->bf_state
.seqno
);
431 if (!txok
|| (isaggr
&& !ATH_BA_ISSET(ba
, ba_index
)))
439 static void ath_tx_complete_aggr(struct ath_softc
*sc
, struct ath_txq
*txq
,
440 struct ath_buf
*bf
, struct list_head
*bf_q
,
441 struct ieee80211_sta
*sta
,
442 struct ath_atx_tid
*tid
,
443 struct ath_tx_status
*ts
, int txok
)
445 struct ath_node
*an
= NULL
;
447 struct ieee80211_tx_info
*tx_info
;
448 struct ath_buf
*bf_next
, *bf_last
= bf
->bf_lastbf
;
449 struct list_head bf_head
;
450 struct sk_buff_head bf_pending
;
451 u16 seq_st
= 0, acked_cnt
= 0, txfail_cnt
= 0, seq_first
;
452 u32 ba
[WME_BA_BMP_SIZE
>> 5];
453 int isaggr
, txfail
, txpending
, sendbar
= 0, needreset
= 0, nbad
= 0;
454 bool rc_update
= true, isba
;
455 struct ieee80211_tx_rate rates
[4];
456 struct ath_frame_info
*fi
;
458 bool flush
= !!(ts
->ts_status
& ATH9K_TX_FLUSH
);
463 tx_info
= IEEE80211_SKB_CB(skb
);
465 memcpy(rates
, bf
->rates
, sizeof(rates
));
467 retries
= ts
->ts_longretry
+ 1;
468 for (i
= 0; i
< ts
->ts_rateindex
; i
++)
469 retries
+= rates
[i
].count
;
472 INIT_LIST_HEAD(&bf_head
);
474 bf_next
= bf
->bf_next
;
476 if (!bf
->bf_state
.stale
|| bf_next
!= NULL
)
477 list_move_tail(&bf
->list
, &bf_head
);
479 ath_tx_complete_buf(sc
, bf
, txq
, &bf_head
, NULL
, ts
, 0);
486 an
= (struct ath_node
*)sta
->drv_priv
;
487 seq_first
= tid
->seq_start
;
488 isba
= ts
->ts_flags
& ATH9K_TX_BA
;
491 * The hardware occasionally sends a tx status for the wrong TID.
492 * In this case, the BA status cannot be considered valid and all
493 * subframes need to be retransmitted
495 * Only BlockAcks have a TID and therefore normal Acks cannot be
498 if (isba
&& tid
->tidno
!= ts
->tid
)
501 isaggr
= bf_isaggr(bf
);
502 memset(ba
, 0, WME_BA_BMP_SIZE
>> 3);
504 if (isaggr
&& txok
) {
505 if (ts
->ts_flags
& ATH9K_TX_BA
) {
506 seq_st
= ts
->ts_seqnum
;
507 memcpy(ba
, &ts
->ba_low
, WME_BA_BMP_SIZE
>> 3);
510 * AR5416 can become deaf/mute when BA
511 * issue happens. Chip needs to be reset.
512 * But AP code may have sychronization issues
513 * when perform internal reset in this routine.
514 * Only enable reset in STA mode for now.
516 if (sc
->sc_ah
->opmode
== NL80211_IFTYPE_STATION
)
521 __skb_queue_head_init(&bf_pending
);
523 ath_tx_count_frames(sc
, bf
, ts
, txok
, &nframes
, &nbad
);
525 u16 seqno
= bf
->bf_state
.seqno
;
527 txfail
= txpending
= sendbar
= 0;
528 bf_next
= bf
->bf_next
;
531 tx_info
= IEEE80211_SKB_CB(skb
);
532 fi
= get_frame_info(skb
);
534 if (!BAW_WITHIN(tid
->seq_start
, tid
->baw_size
, seqno
) ||
537 * Outside of the current BlockAck window,
538 * maybe part of a previous session
541 } else if (ATH_BA_ISSET(ba
, ATH_BA_INDEX(seq_st
, seqno
))) {
542 /* transmit completion, subframe is
543 * acked by block ack */
545 } else if (!isaggr
&& txok
) {
546 /* transmit completion */
550 } else if (fi
->retries
< ATH_MAX_SW_RETRIES
) {
551 if (txok
|| !an
->sleeping
)
552 ath_tx_set_retry(sc
, txq
, bf
->bf_mpdu
,
559 bar_index
= max_t(int, bar_index
,
560 ATH_BA_INDEX(seq_first
, seqno
));
564 * Make sure the last desc is reclaimed if it
565 * not a holding desc.
567 INIT_LIST_HEAD(&bf_head
);
568 if (bf_next
!= NULL
|| !bf_last
->bf_state
.stale
)
569 list_move_tail(&bf
->list
, &bf_head
);
573 * complete the acked-ones/xretried ones; update
576 ath_tx_update_baw(sc
, tid
, bf
);
578 if (rc_update
&& (acked_cnt
== 1 || txfail_cnt
== 1)) {
579 memcpy(tx_info
->control
.rates
, rates
, sizeof(rates
));
580 ath_tx_rc_status(sc
, bf
, ts
, nframes
, nbad
, txok
);
582 if (bf
== bf
->bf_lastbf
)
583 ath_dynack_sample_tx_ts(sc
->sc_ah
,
588 ath_tx_complete_buf(sc
, bf
, txq
, &bf_head
, sta
, ts
,
591 if (tx_info
->flags
& IEEE80211_TX_STATUS_EOSP
) {
592 tx_info
->flags
&= ~IEEE80211_TX_STATUS_EOSP
;
593 ieee80211_sta_eosp(sta
);
595 /* retry the un-acked ones */
596 if (bf
->bf_next
== NULL
&& bf_last
->bf_state
.stale
) {
599 tbf
= ath_clone_txbuf(sc
, bf_last
);
601 * Update tx baw and complete the
602 * frame with failed status if we
606 ath_tx_update_baw(sc
, tid
, bf
);
608 ath_tx_complete_buf(sc
, bf
, txq
,
611 bar_index
= max_t(int, bar_index
,
612 ATH_BA_INDEX(seq_first
, seqno
));
620 * Put this buffer to the temporary pending
621 * queue to retain ordering
623 __skb_queue_tail(&bf_pending
, skb
);
629 /* prepend un-acked frames to the beginning of the pending frame queue */
630 if (!skb_queue_empty(&bf_pending
)) {
632 ieee80211_sta_set_buffered(sta
, tid
->tidno
, true);
634 skb_queue_splice_tail(&bf_pending
, &tid
->retry_q
);
636 ath_tx_queue_tid(sc
, tid
);
637 if (ts
->ts_status
& (ATH9K_TXERR_FILT
| ATH9K_TXERR_XRETRY
))
638 tid
->clear_ps_filter
= true;
642 if (bar_index
>= 0) {
643 u16 bar_seq
= ATH_BA_INDEX2SEQ(seq_first
, bar_index
);
645 if (BAW_WITHIN(tid
->seq_start
, tid
->baw_size
, bar_seq
))
646 tid
->bar_index
= ATH_BA_INDEX(tid
->seq_start
, bar_seq
);
648 ath_txq_unlock(sc
, txq
);
649 ath_send_bar(tid
, ATH_BA_INDEX2SEQ(seq_first
, bar_index
+ 1));
650 ath_txq_lock(sc
, txq
);
654 ath9k_queue_reset(sc
, RESET_TYPE_TX_ERROR
);
657 static bool bf_is_ampdu_not_probing(struct ath_buf
*bf
)
659 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(bf
->bf_mpdu
);
660 return bf_isampdu(bf
) && !(info
->flags
& IEEE80211_TX_CTL_RATE_CTRL_PROBE
);
663 static void ath_tx_count_airtime(struct ath_softc
*sc
,
664 struct ieee80211_sta
*sta
,
666 struct ath_tx_status
*ts
,
672 airtime
+= ts
->duration
* (ts
->ts_longretry
+ 1);
673 for(i
= 0; i
< ts
->ts_rateindex
; i
++) {
674 int rate_dur
= ath9k_hw_get_duration(sc
->sc_ah
, bf
->bf_desc
, i
);
675 airtime
+= rate_dur
* bf
->rates
[i
].count
;
678 ieee80211_sta_register_airtime(sta
, tid
, airtime
, 0);
681 static void ath_tx_process_buffer(struct ath_softc
*sc
, struct ath_txq
*txq
,
682 struct ath_tx_status
*ts
, struct ath_buf
*bf
,
683 struct list_head
*bf_head
)
685 struct ieee80211_hw
*hw
= sc
->hw
;
686 struct ieee80211_tx_info
*info
;
687 struct ieee80211_sta
*sta
;
688 struct ieee80211_hdr
*hdr
;
689 struct ath_atx_tid
*tid
= NULL
;
692 txok
= !(ts
->ts_status
& ATH9K_TXERR_MASK
);
693 flush
= !!(ts
->ts_status
& ATH9K_TX_FLUSH
);
694 txq
->axq_tx_inprogress
= false;
697 if (bf_is_ampdu_not_probing(bf
))
698 txq
->axq_ampdu_depth
--;
700 ts
->duration
= ath9k_hw_get_duration(sc
->sc_ah
, bf
->bf_desc
,
703 hdr
= (struct ieee80211_hdr
*) bf
->bf_mpdu
->data
;
704 sta
= ieee80211_find_sta_by_ifaddr(hw
, hdr
->addr1
, hdr
->addr2
);
706 struct ath_node
*an
= (struct ath_node
*)sta
->drv_priv
;
707 tid
= ath_get_skb_tid(sc
, an
, bf
->bf_mpdu
);
708 ath_tx_count_airtime(sc
, sta
, bf
, ts
, tid
->tidno
);
709 if (ts
->ts_status
& (ATH9K_TXERR_FILT
| ATH9K_TXERR_XRETRY
))
710 tid
->clear_ps_filter
= true;
713 if (!bf_isampdu(bf
)) {
715 info
= IEEE80211_SKB_CB(bf
->bf_mpdu
);
716 memcpy(info
->control
.rates
, bf
->rates
,
717 sizeof(info
->control
.rates
));
718 ath_tx_rc_status(sc
, bf
, ts
, 1, txok
? 0 : 1, txok
);
719 ath_dynack_sample_tx_ts(sc
->sc_ah
, bf
->bf_mpdu
, ts
,
722 ath_tx_complete_buf(sc
, bf
, txq
, bf_head
, sta
, ts
, txok
);
724 ath_tx_complete_aggr(sc
, txq
, bf
, bf_head
, sta
, tid
, ts
, txok
);
727 ath_txq_schedule(sc
, txq
);
730 static bool ath_lookup_legacy(struct ath_buf
*bf
)
733 struct ieee80211_tx_info
*tx_info
;
734 struct ieee80211_tx_rate
*rates
;
738 tx_info
= IEEE80211_SKB_CB(skb
);
739 rates
= tx_info
->control
.rates
;
741 for (i
= 0; i
< 4; i
++) {
742 if (!rates
[i
].count
|| rates
[i
].idx
< 0)
745 if (!(rates
[i
].flags
& IEEE80211_TX_RC_MCS
))
752 static u32
ath_lookup_rate(struct ath_softc
*sc
, struct ath_buf
*bf
,
753 struct ath_atx_tid
*tid
)
756 struct ieee80211_tx_info
*tx_info
;
757 struct ieee80211_tx_rate
*rates
;
758 u32 max_4ms_framelen
, frmlen
;
759 u16 aggr_limit
, bt_aggr_limit
, legacy
= 0;
760 int q
= tid
->txq
->mac80211_qnum
;
764 tx_info
= IEEE80211_SKB_CB(skb
);
768 * Find the lowest frame length among the rate series that will have a
769 * 4ms (or TXOP limited) transmit duration.
771 max_4ms_framelen
= ATH_AMPDU_LIMIT_MAX
;
773 for (i
= 0; i
< 4; i
++) {
779 if (!(rates
[i
].flags
& IEEE80211_TX_RC_MCS
)) {
784 if (rates
[i
].flags
& IEEE80211_TX_RC_40_MHZ_WIDTH
)
789 if (rates
[i
].flags
& IEEE80211_TX_RC_SHORT_GI
)
792 frmlen
= sc
->tx
.max_aggr_framelen
[q
][modeidx
][rates
[i
].idx
];
793 max_4ms_framelen
= min(max_4ms_framelen
, frmlen
);
797 * limit aggregate size by the minimum rate if rate selected is
798 * not a probe rate, if rate selected is a probe rate then
799 * avoid aggregation of this packet.
801 if (tx_info
->flags
& IEEE80211_TX_CTL_RATE_CTRL_PROBE
|| legacy
)
804 aggr_limit
= min(max_4ms_framelen
, (u32
)ATH_AMPDU_LIMIT_MAX
);
807 * Override the default aggregation limit for BTCOEX.
809 bt_aggr_limit
= ath9k_btcoex_aggr_limit(sc
, max_4ms_framelen
);
811 aggr_limit
= bt_aggr_limit
;
813 if (tid
->an
->maxampdu
)
814 aggr_limit
= min(aggr_limit
, tid
->an
->maxampdu
);
820 * Returns the number of delimiters to be added to
821 * meet the minimum required mpdudensity.
823 static int ath_compute_num_delims(struct ath_softc
*sc
, struct ath_atx_tid
*tid
,
824 struct ath_buf
*bf
, u16 frmlen
,
827 #define FIRST_DESC_NDELIMS 60
828 u32 nsymbits
, nsymbols
;
831 int width
, streams
, half_gi
, ndelim
, mindelim
;
832 struct ath_frame_info
*fi
= get_frame_info(bf
->bf_mpdu
);
834 /* Select standard number of delimiters based on frame length alone */
835 ndelim
= ATH_AGGR_GET_NDELIM(frmlen
);
838 * If encryption enabled, hardware requires some more padding between
840 * TODO - this could be improved to be dependent on the rate.
841 * The hardware can keep up at lower rates, but not higher rates
843 if ((fi
->keyix
!= ATH9K_TXKEYIX_INVALID
) &&
844 !(sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_EDMA
))
845 ndelim
+= ATH_AGGR_ENCRYPTDELIM
;
848 * Add delimiter when using RTS/CTS with aggregation
849 * and non enterprise AR9003 card
851 if (first_subfrm
&& !AR_SREV_9580_10_OR_LATER(sc
->sc_ah
) &&
852 (sc
->sc_ah
->ent_mode
& AR_ENT_OTP_MIN_PKT_SIZE_DISABLE
))
853 ndelim
= max(ndelim
, FIRST_DESC_NDELIMS
);
856 * Convert desired mpdu density from microeconds to bytes based
857 * on highest rate in rate series (i.e. first rate) to determine
858 * required minimum length for subframe. Take into account
859 * whether high rate is 20 or 40Mhz and half or full GI.
861 * If there is no mpdu density restriction, no further calculation
865 if (tid
->an
->mpdudensity
== 0)
868 rix
= bf
->rates
[0].idx
;
869 flags
= bf
->rates
[0].flags
;
870 width
= (flags
& IEEE80211_TX_RC_40_MHZ_WIDTH
) ? 1 : 0;
871 half_gi
= (flags
& IEEE80211_TX_RC_SHORT_GI
) ? 1 : 0;
874 nsymbols
= NUM_SYMBOLS_PER_USEC_HALFGI(tid
->an
->mpdudensity
);
876 nsymbols
= NUM_SYMBOLS_PER_USEC(tid
->an
->mpdudensity
);
881 streams
= HT_RC_2_STREAMS(rix
);
882 nsymbits
= bits_per_symbol
[rix
% 8][width
] * streams
;
883 minlen
= (nsymbols
* nsymbits
) / BITS_PER_BYTE
;
885 if (frmlen
< minlen
) {
886 mindelim
= (minlen
- frmlen
) / ATH_AGGR_DELIM_SZ
;
887 ndelim
= max(mindelim
, ndelim
);
894 ath_tx_get_tid_subframe(struct ath_softc
*sc
, struct ath_txq
*txq
,
895 struct ath_atx_tid
*tid
, struct ath_buf
**buf
)
897 struct ieee80211_tx_info
*tx_info
;
898 struct ath_frame_info
*fi
;
900 struct sk_buff
*skb
, *first_skb
= NULL
;
905 ret
= ath_tid_dequeue(tid
, &skb
);
909 fi
= get_frame_info(skb
);
912 bf
= ath_tx_setup_buffer(sc
, txq
, tid
, skb
);
914 bf
->bf_state
.stale
= false;
917 ath_txq_skb_done(sc
, txq
, skb
);
918 ieee80211_free_txskb(sc
->hw
, skb
);
925 tx_info
= IEEE80211_SKB_CB(skb
);
926 tx_info
->flags
&= ~(IEEE80211_TX_CTL_CLEAR_PS_FILT
|
927 IEEE80211_TX_STATUS_EOSP
);
930 * No aggregation session is running, but there may be frames
931 * from a previous session or a failed attempt in the queue.
932 * Send them out as normal data frames
935 tx_info
->flags
&= ~IEEE80211_TX_CTL_AMPDU
;
937 if (!(tx_info
->flags
& IEEE80211_TX_CTL_AMPDU
)) {
938 bf
->bf_state
.bf_type
= 0;
942 bf
->bf_state
.bf_type
= BUF_AMPDU
| BUF_AGGR
;
943 seqno
= bf
->bf_state
.seqno
;
945 /* do not step over block-ack window */
946 if (!BAW_WITHIN(tid
->seq_start
, tid
->baw_size
, seqno
)) {
947 __skb_queue_tail(&tid
->retry_q
, skb
);
949 /* If there are other skbs in the retry q, they are
950 * probably within the BAW, so loop immediately to get
951 * one of them. Otherwise the queue can get stuck. */
952 if (!skb_queue_is_first(&tid
->retry_q
, skb
) &&
953 !WARN_ON(skb
== first_skb
)) {
954 if(!first_skb
) /* infinite loop prevention */
961 if (tid
->bar_index
> ATH_BA_INDEX(tid
->seq_start
, seqno
)) {
962 struct ath_tx_status ts
= {};
963 struct list_head bf_head
;
965 INIT_LIST_HEAD(&bf_head
);
966 list_add(&bf
->list
, &bf_head
);
967 ath_tx_update_baw(sc
, tid
, bf
);
968 ath_tx_complete_buf(sc
, bf
, txq
, &bf_head
, NULL
, &ts
, 0);
973 ath_tx_addto_baw(sc
, tid
, bf
);
983 ath_tx_form_aggr(struct ath_softc
*sc
, struct ath_txq
*txq
,
984 struct ath_atx_tid
*tid
, struct list_head
*bf_q
,
985 struct ath_buf
*bf_first
)
987 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
988 struct ath_buf
*bf
= bf_first
, *bf_prev
= NULL
;
989 int nframes
= 0, ndelim
, ret
;
990 u16 aggr_limit
= 0, al
= 0, bpad
= 0,
991 al_delta
, h_baw
= tid
->baw_size
/ 2;
992 struct ieee80211_tx_info
*tx_info
;
993 struct ath_frame_info
*fi
;
998 aggr_limit
= ath_lookup_rate(sc
, bf
, tid
);
1003 fi
= get_frame_info(skb
);
1005 /* do not exceed aggregation limit */
1006 al_delta
= ATH_AGGR_DELIM_SZ
+ fi
->framelen
;
1008 if (aggr_limit
< al
+ bpad
+ al_delta
||
1009 ath_lookup_legacy(bf
) || nframes
>= h_baw
)
1012 tx_info
= IEEE80211_SKB_CB(bf
->bf_mpdu
);
1013 if ((tx_info
->flags
& IEEE80211_TX_CTL_RATE_CTRL_PROBE
) ||
1014 !(tx_info
->flags
& IEEE80211_TX_CTL_AMPDU
))
1018 /* add padding for previous frame to aggregation length */
1019 al
+= bpad
+ al_delta
;
1022 * Get the delimiters needed to meet the MPDU
1023 * density for this node.
1025 ndelim
= ath_compute_num_delims(sc
, tid
, bf_first
, fi
->framelen
,
1027 bpad
= PADBYTES(al_delta
) + (ndelim
<< 2);
1032 /* link buffers of this frame to the aggregate */
1033 bf
->bf_state
.ndelim
= ndelim
;
1035 list_add_tail(&bf
->list
, bf_q
);
1037 bf_prev
->bf_next
= bf
;
1041 ret
= ath_tx_get_tid_subframe(sc
, txq
, tid
, &bf
);
1047 __skb_queue_tail(&tid
->retry_q
, bf
->bf_mpdu
);
1050 bf
->bf_lastbf
= bf_prev
;
1052 if (bf
== bf_prev
) {
1053 al
= get_frame_info(bf
->bf_mpdu
)->framelen
;
1054 bf
->bf_state
.bf_type
= BUF_AMPDU
;
1056 TX_STAT_INC(sc
, txq
->axq_qnum
, a_aggr
);
1065 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
1066 * width - 0 for 20 MHz, 1 for 40 MHz
1067 * half_gi - to use 4us v/s 3.6 us for symbol time
1069 u32
ath_pkt_duration(struct ath_softc
*sc
, u8 rix
, int pktlen
,
1070 int width
, int half_gi
, bool shortPreamble
)
1072 u32 nbits
, nsymbits
, duration
, nsymbols
;
1075 /* find number of symbols: PLCP + data */
1076 streams
= HT_RC_2_STREAMS(rix
);
1077 nbits
= (pktlen
<< 3) + OFDM_PLCP_BITS
;
1078 nsymbits
= bits_per_symbol
[rix
% 8][width
] * streams
;
1079 nsymbols
= (nbits
+ nsymbits
- 1) / nsymbits
;
1082 duration
= SYMBOL_TIME(nsymbols
);
1084 duration
= SYMBOL_TIME_HALFGI(nsymbols
);
1086 /* addup duration for legacy/ht training and signal fields */
1087 duration
+= L_STF
+ L_LTF
+ L_SIG
+ HT_SIG
+ HT_STF
+ HT_LTF(streams
);
1092 static int ath_max_framelen(int usec
, int mcs
, bool ht40
, bool sgi
)
1094 int streams
= HT_RC_2_STREAMS(mcs
);
1098 usec
-= L_STF
+ L_LTF
+ L_SIG
+ HT_SIG
+ HT_STF
+ HT_LTF(streams
);
1099 symbols
= sgi
? TIME_SYMBOLS_HALFGI(usec
) : TIME_SYMBOLS(usec
);
1100 bits
= symbols
* bits_per_symbol
[mcs
% 8][ht40
] * streams
;
1101 bits
-= OFDM_PLCP_BITS
;
1109 void ath_update_max_aggr_framelen(struct ath_softc
*sc
, int queue
, int txop
)
1111 u16
*cur_ht20
, *cur_ht20_sgi
, *cur_ht40
, *cur_ht40_sgi
;
1114 /* 4ms is the default (and maximum) duration */
1115 if (!txop
|| txop
> 4096)
1118 cur_ht20
= sc
->tx
.max_aggr_framelen
[queue
][MCS_HT20
];
1119 cur_ht20_sgi
= sc
->tx
.max_aggr_framelen
[queue
][MCS_HT20_SGI
];
1120 cur_ht40
= sc
->tx
.max_aggr_framelen
[queue
][MCS_HT40
];
1121 cur_ht40_sgi
= sc
->tx
.max_aggr_framelen
[queue
][MCS_HT40_SGI
];
1122 for (mcs
= 0; mcs
< 32; mcs
++) {
1123 cur_ht20
[mcs
] = ath_max_framelen(txop
, mcs
, false, false);
1124 cur_ht20_sgi
[mcs
] = ath_max_framelen(txop
, mcs
, false, true);
1125 cur_ht40
[mcs
] = ath_max_framelen(txop
, mcs
, true, false);
1126 cur_ht40_sgi
[mcs
] = ath_max_framelen(txop
, mcs
, true, true);
1130 static u8
ath_get_rate_txpower(struct ath_softc
*sc
, struct ath_buf
*bf
,
1131 u8 rateidx
, bool is_40
, bool is_cck
)
1134 struct sk_buff
*skb
;
1135 struct ath_frame_info
*fi
;
1136 struct ieee80211_tx_info
*info
;
1137 struct ath_hw
*ah
= sc
->sc_ah
;
1139 if (sc
->tx99_state
|| !ah
->tpc_enabled
)
1140 return MAX_RATE_POWER
;
1143 fi
= get_frame_info(skb
);
1144 info
= IEEE80211_SKB_CB(skb
);
1146 if (!AR_SREV_9300_20_OR_LATER(ah
)) {
1147 int txpower
= fi
->tx_power
;
1151 struct ar5416_eeprom_def
*eep
= &ah
->eeprom
.def
;
1152 u16 eeprom_rev
= ah
->eep_ops
->get_eeprom_rev(ah
);
1154 if (eeprom_rev
>= AR5416_EEP_MINOR_VER_2
) {
1156 struct modal_eep_header
*pmodal
;
1158 is_2ghz
= info
->band
== NL80211_BAND_2GHZ
;
1159 pmodal
= &eep
->modalHeader
[is_2ghz
];
1160 power_ht40delta
= pmodal
->ht40PowerIncForPdadc
;
1162 power_ht40delta
= 2;
1164 txpower
+= power_ht40delta
;
1167 if (AR_SREV_9287(ah
) || AR_SREV_9285(ah
) ||
1169 txpower
-= 2 * AR9287_PWR_TABLE_OFFSET_DB
;
1170 } else if (AR_SREV_9280_20_OR_LATER(ah
)) {
1173 power_offset
= ah
->eep_ops
->get_eeprom(ah
,
1174 EEP_PWR_TABLE_OFFSET
);
1175 txpower
-= 2 * power_offset
;
1178 if (OLC_FOR_AR9280_20_LATER
&& is_cck
)
1181 txpower
= max(txpower
, 0);
1182 max_power
= min_t(u8
, ah
->tx_power
[rateidx
], txpower
);
1184 /* XXX: clamp minimum TX power at 1 for AR9160 since if
1185 * max_power is set to 0, frames are transmitted at max
1188 if (!max_power
&& !AR_SREV_9280_20_OR_LATER(ah
))
1190 } else if (!bf
->bf_state
.bfs_paprd
) {
1191 if (rateidx
< 8 && (info
->flags
& IEEE80211_TX_CTL_STBC
))
1192 max_power
= min_t(u8
, ah
->tx_power_stbc
[rateidx
],
1195 max_power
= min_t(u8
, ah
->tx_power
[rateidx
],
1198 max_power
= ah
->paprd_training_power
;
1204 static void ath_buf_set_rate(struct ath_softc
*sc
, struct ath_buf
*bf
,
1205 struct ath_tx_info
*info
, int len
, bool rts
)
1207 struct ath_hw
*ah
= sc
->sc_ah
;
1208 struct ath_common
*common
= ath9k_hw_common(ah
);
1209 struct sk_buff
*skb
;
1210 struct ieee80211_tx_info
*tx_info
;
1211 struct ieee80211_tx_rate
*rates
;
1212 const struct ieee80211_rate
*rate
;
1213 struct ieee80211_hdr
*hdr
;
1214 struct ath_frame_info
*fi
= get_frame_info(bf
->bf_mpdu
);
1215 u32 rts_thresh
= sc
->hw
->wiphy
->rts_threshold
;
1220 tx_info
= IEEE80211_SKB_CB(skb
);
1222 hdr
= (struct ieee80211_hdr
*)skb
->data
;
1224 /* set dur_update_en for l-sig computation except for PS-Poll frames */
1225 info
->dur_update
= !ieee80211_is_pspoll(hdr
->frame_control
);
1226 info
->rtscts_rate
= fi
->rtscts_rate
;
1228 for (i
= 0; i
< ARRAY_SIZE(bf
->rates
); i
++) {
1229 bool is_40
, is_sgi
, is_sp
, is_cck
;
1232 if (!rates
[i
].count
|| (rates
[i
].idx
< 0))
1236 info
->rates
[i
].Tries
= rates
[i
].count
;
1239 * Handle RTS threshold for unaggregated HT frames.
1241 if (bf_isampdu(bf
) && !bf_isaggr(bf
) &&
1242 (rates
[i
].flags
& IEEE80211_TX_RC_MCS
) &&
1243 unlikely(rts_thresh
!= (u32
) -1)) {
1244 if (!rts_thresh
|| (len
> rts_thresh
))
1248 if (rts
|| rates
[i
].flags
& IEEE80211_TX_RC_USE_RTS_CTS
) {
1249 info
->rates
[i
].RateFlags
|= ATH9K_RATESERIES_RTS_CTS
;
1250 info
->flags
|= ATH9K_TXDESC_RTSENA
;
1251 } else if (rates
[i
].flags
& IEEE80211_TX_RC_USE_CTS_PROTECT
) {
1252 info
->rates
[i
].RateFlags
|= ATH9K_RATESERIES_RTS_CTS
;
1253 info
->flags
|= ATH9K_TXDESC_CTSENA
;
1256 if (rates
[i
].flags
& IEEE80211_TX_RC_40_MHZ_WIDTH
)
1257 info
->rates
[i
].RateFlags
|= ATH9K_RATESERIES_2040
;
1258 if (rates
[i
].flags
& IEEE80211_TX_RC_SHORT_GI
)
1259 info
->rates
[i
].RateFlags
|= ATH9K_RATESERIES_HALFGI
;
1261 is_sgi
= !!(rates
[i
].flags
& IEEE80211_TX_RC_SHORT_GI
);
1262 is_40
= !!(rates
[i
].flags
& IEEE80211_TX_RC_40_MHZ_WIDTH
);
1263 is_sp
= !!(rates
[i
].flags
& IEEE80211_TX_RC_USE_SHORT_PREAMBLE
);
1265 if (rates
[i
].flags
& IEEE80211_TX_RC_MCS
) {
1267 info
->rates
[i
].Rate
= rix
| 0x80;
1268 info
->rates
[i
].ChSel
= ath_txchainmask_reduction(sc
,
1269 ah
->txchainmask
, info
->rates
[i
].Rate
);
1270 info
->rates
[i
].PktDuration
= ath_pkt_duration(sc
, rix
, len
,
1271 is_40
, is_sgi
, is_sp
);
1272 if (rix
< 8 && (tx_info
->flags
& IEEE80211_TX_CTL_STBC
))
1273 info
->rates
[i
].RateFlags
|= ATH9K_RATESERIES_STBC
;
1275 info
->txpower
[i
] = ath_get_rate_txpower(sc
, bf
, rix
,
1281 rate
= &common
->sbands
[tx_info
->band
].bitrates
[rates
[i
].idx
];
1282 if ((tx_info
->band
== NL80211_BAND_2GHZ
) &&
1283 !(rate
->flags
& IEEE80211_RATE_ERP_G
))
1284 phy
= WLAN_RC_PHY_CCK
;
1286 phy
= WLAN_RC_PHY_OFDM
;
1288 info
->rates
[i
].Rate
= rate
->hw_value
;
1289 if (rate
->hw_value_short
) {
1290 if (rates
[i
].flags
& IEEE80211_TX_RC_USE_SHORT_PREAMBLE
)
1291 info
->rates
[i
].Rate
|= rate
->hw_value_short
;
1296 if (bf
->bf_state
.bfs_paprd
)
1297 info
->rates
[i
].ChSel
= ah
->txchainmask
;
1299 info
->rates
[i
].ChSel
= ath_txchainmask_reduction(sc
,
1300 ah
->txchainmask
, info
->rates
[i
].Rate
);
1302 info
->rates
[i
].PktDuration
= ath9k_hw_computetxtime(sc
->sc_ah
,
1303 phy
, rate
->bitrate
* 100, len
, rix
, is_sp
);
1305 is_cck
= IS_CCK_RATE(info
->rates
[i
].Rate
);
1306 info
->txpower
[i
] = ath_get_rate_txpower(sc
, bf
, rix
, false,
1310 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1311 if (bf_isaggr(bf
) && (len
> sc
->sc_ah
->caps
.rts_aggr_limit
))
1312 info
->flags
&= ~ATH9K_TXDESC_RTSENA
;
1314 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
1315 if (info
->flags
& ATH9K_TXDESC_RTSENA
)
1316 info
->flags
&= ~ATH9K_TXDESC_CTSENA
;
1319 static enum ath9k_pkt_type
get_hw_packet_type(struct sk_buff
*skb
)
1321 struct ieee80211_hdr
*hdr
;
1322 enum ath9k_pkt_type htype
;
1325 hdr
= (struct ieee80211_hdr
*)skb
->data
;
1326 fc
= hdr
->frame_control
;
1328 if (ieee80211_is_beacon(fc
))
1329 htype
= ATH9K_PKT_TYPE_BEACON
;
1330 else if (ieee80211_is_probe_resp(fc
))
1331 htype
= ATH9K_PKT_TYPE_PROBE_RESP
;
1332 else if (ieee80211_is_atim(fc
))
1333 htype
= ATH9K_PKT_TYPE_ATIM
;
1334 else if (ieee80211_is_pspoll(fc
))
1335 htype
= ATH9K_PKT_TYPE_PSPOLL
;
1337 htype
= ATH9K_PKT_TYPE_NORMAL
;
1342 static void ath_tx_fill_desc(struct ath_softc
*sc
, struct ath_buf
*bf
,
1343 struct ath_txq
*txq
, int len
)
1345 struct ath_hw
*ah
= sc
->sc_ah
;
1346 struct ath_buf
*bf_first
= NULL
;
1347 struct ath_tx_info info
;
1348 u32 rts_thresh
= sc
->hw
->wiphy
->rts_threshold
;
1351 memset(&info
, 0, sizeof(info
));
1352 info
.is_first
= true;
1353 info
.is_last
= true;
1354 info
.qcu
= txq
->axq_qnum
;
1357 struct sk_buff
*skb
= bf
->bf_mpdu
;
1358 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
1359 struct ath_frame_info
*fi
= get_frame_info(skb
);
1360 bool aggr
= !!(bf
->bf_state
.bf_type
& BUF_AGGR
);
1362 info
.type
= get_hw_packet_type(skb
);
1364 info
.link
= bf
->bf_next
->bf_daddr
;
1366 info
.link
= (sc
->tx99_state
) ? bf
->bf_daddr
: 0;
1371 if (!sc
->tx99_state
)
1372 info
.flags
= ATH9K_TXDESC_INTREQ
;
1373 if ((tx_info
->flags
& IEEE80211_TX_CTL_CLEAR_PS_FILT
) ||
1374 txq
== sc
->tx
.uapsdq
)
1375 info
.flags
|= ATH9K_TXDESC_CLRDMASK
;
1377 if (tx_info
->flags
& IEEE80211_TX_CTL_NO_ACK
)
1378 info
.flags
|= ATH9K_TXDESC_NOACK
;
1379 if (tx_info
->flags
& IEEE80211_TX_CTL_LDPC
)
1380 info
.flags
|= ATH9K_TXDESC_LDPC
;
1382 if (bf
->bf_state
.bfs_paprd
)
1383 info
.flags
|= (u32
) bf
->bf_state
.bfs_paprd
<<
1384 ATH9K_TXDESC_PAPRD_S
;
1387 * mac80211 doesn't handle RTS threshold for HT because
1388 * the decision has to be taken based on AMPDU length
1389 * and aggregation is done entirely inside ath9k.
1390 * Set the RTS/CTS flag for the first subframe based
1393 if (aggr
&& (bf
== bf_first
) &&
1394 unlikely(rts_thresh
!= (u32
) -1)) {
1396 * "len" is the size of the entire AMPDU.
1398 if (!rts_thresh
|| (len
> rts_thresh
))
1405 ath_buf_set_rate(sc
, bf
, &info
, len
, rts
);
1408 info
.buf_addr
[0] = bf
->bf_buf_addr
;
1409 info
.buf_len
[0] = skb
->len
;
1410 info
.pkt_len
= fi
->framelen
;
1411 info
.keyix
= fi
->keyix
;
1412 info
.keytype
= fi
->keytype
;
1416 info
.aggr
= AGGR_BUF_FIRST
;
1417 else if (bf
== bf_first
->bf_lastbf
)
1418 info
.aggr
= AGGR_BUF_LAST
;
1420 info
.aggr
= AGGR_BUF_MIDDLE
;
1422 info
.ndelim
= bf
->bf_state
.ndelim
;
1423 info
.aggr_len
= len
;
1426 if (bf
== bf_first
->bf_lastbf
)
1429 ath9k_hw_set_txdesc(ah
, bf
->bf_desc
, &info
);
1435 ath_tx_form_burst(struct ath_softc
*sc
, struct ath_txq
*txq
,
1436 struct ath_atx_tid
*tid
, struct list_head
*bf_q
,
1437 struct ath_buf
*bf_first
)
1439 struct ath_buf
*bf
= bf_first
, *bf_prev
= NULL
;
1440 int nframes
= 0, ret
;
1443 struct ieee80211_tx_info
*tx_info
;
1446 list_add_tail(&bf
->list
, bf_q
);
1448 bf_prev
->bf_next
= bf
;
1454 ret
= ath_tx_get_tid_subframe(sc
, txq
, tid
, &bf
);
1458 tx_info
= IEEE80211_SKB_CB(bf
->bf_mpdu
);
1459 if (tx_info
->flags
& IEEE80211_TX_CTL_AMPDU
) {
1460 __skb_queue_tail(&tid
->retry_q
, bf
->bf_mpdu
);
1464 ath_set_rates(tid
->an
->vif
, tid
->an
->sta
, bf
);
1468 static int ath_tx_sched_aggr(struct ath_softc
*sc
, struct ath_txq
*txq
,
1469 struct ath_atx_tid
*tid
)
1471 struct ath_buf
*bf
= NULL
;
1472 struct ieee80211_tx_info
*tx_info
;
1473 struct list_head bf_q
;
1474 int aggr_len
= 0, ret
;
1477 INIT_LIST_HEAD(&bf_q
);
1479 ret
= ath_tx_get_tid_subframe(sc
, txq
, tid
, &bf
);
1483 tx_info
= IEEE80211_SKB_CB(bf
->bf_mpdu
);
1484 aggr
= !!(tx_info
->flags
& IEEE80211_TX_CTL_AMPDU
);
1485 if ((aggr
&& txq
->axq_ampdu_depth
>= ATH_AGGR_MIN_QDEPTH
) ||
1486 (!aggr
&& txq
->axq_depth
>= ATH_NON_AGGR_MIN_QDEPTH
)) {
1487 __skb_queue_tail(&tid
->retry_q
, bf
->bf_mpdu
);
1491 ath_set_rates(tid
->an
->vif
, tid
->an
->sta
, bf
);
1493 aggr_len
= ath_tx_form_aggr(sc
, txq
, tid
, &bf_q
, bf
);
1495 ath_tx_form_burst(sc
, txq
, tid
, &bf_q
, bf
);
1497 if (list_empty(&bf_q
))
1500 if (tid
->clear_ps_filter
|| tid
->an
->no_ps_filter
) {
1501 tid
->clear_ps_filter
= false;
1502 tx_info
->flags
|= IEEE80211_TX_CTL_CLEAR_PS_FILT
;
1505 ath_tx_fill_desc(sc
, bf
, txq
, aggr_len
);
1506 ath_tx_txqaddbuf(sc
, txq
, &bf_q
, false);
1510 int ath_tx_aggr_start(struct ath_softc
*sc
, struct ieee80211_sta
*sta
,
1513 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
1514 struct ath_atx_tid
*txtid
;
1515 struct ath_txq
*txq
;
1516 struct ath_node
*an
;
1519 ath_dbg(common
, XMIT
, "%s called\n", __func__
);
1521 an
= (struct ath_node
*)sta
->drv_priv
;
1522 txtid
= ATH_AN_2_TID(an
, tid
);
1525 ath_txq_lock(sc
, txq
);
1527 /* update ampdu factor/density, they may have changed. This may happen
1528 * in HT IBSS when a beacon with HT-info is received after the station
1529 * has already been added.
1531 if (sta
->ht_cap
.ht_supported
) {
1532 an
->maxampdu
= (1 << (IEEE80211_HT_MAX_AMPDU_FACTOR
+
1533 sta
->ht_cap
.ampdu_factor
)) - 1;
1534 density
= ath9k_parse_mpdudensity(sta
->ht_cap
.ampdu_density
);
1535 an
->mpdudensity
= density
;
1538 txtid
->active
= true;
1539 *ssn
= txtid
->seq_start
= txtid
->seq_next
;
1540 txtid
->bar_index
= -1;
1542 memset(txtid
->tx_buf
, 0, sizeof(txtid
->tx_buf
));
1543 txtid
->baw_head
= txtid
->baw_tail
= 0;
1545 ath_txq_unlock_complete(sc
, txq
);
1550 void ath_tx_aggr_stop(struct ath_softc
*sc
, struct ieee80211_sta
*sta
, u16 tid
)
1552 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
1553 struct ath_node
*an
= (struct ath_node
*)sta
->drv_priv
;
1554 struct ath_atx_tid
*txtid
= ATH_AN_2_TID(an
, tid
);
1555 struct ath_txq
*txq
= txtid
->txq
;
1557 ath_dbg(common
, XMIT
, "%s called\n", __func__
);
1559 ath_txq_lock(sc
, txq
);
1560 txtid
->active
= false;
1561 ath_tx_flush_tid(sc
, txtid
);
1562 ath_txq_unlock_complete(sc
, txq
);
1565 void ath_tx_aggr_sleep(struct ieee80211_sta
*sta
, struct ath_softc
*sc
,
1566 struct ath_node
*an
)
1568 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
1569 struct ath_atx_tid
*tid
;
1572 ath_dbg(common
, XMIT
, "%s called\n", __func__
);
1574 for (tidno
= 0; tidno
< IEEE80211_NUM_TIDS
; tidno
++) {
1575 tid
= ath_node_to_tid(an
, tidno
);
1577 if (!skb_queue_empty(&tid
->retry_q
))
1578 ieee80211_sta_set_buffered(sta
, tid
->tidno
, true);
1583 void ath_tx_aggr_wakeup(struct ath_softc
*sc
, struct ath_node
*an
)
1585 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
1586 struct ath_atx_tid
*tid
;
1587 struct ath_txq
*txq
;
1590 ath_dbg(common
, XMIT
, "%s called\n", __func__
);
1592 for (tidno
= 0; tidno
< IEEE80211_NUM_TIDS
; tidno
++) {
1593 tid
= ath_node_to_tid(an
, tidno
);
1596 ath_txq_lock(sc
, txq
);
1597 tid
->clear_ps_filter
= true;
1598 if (!skb_queue_empty(&tid
->retry_q
)) {
1599 ath_tx_queue_tid(sc
, tid
);
1600 ath_txq_schedule(sc
, txq
);
1602 ath_txq_unlock_complete(sc
, txq
);
1609 ath9k_set_moredata(struct ath_softc
*sc
, struct ath_buf
*bf
, bool val
)
1611 struct ieee80211_hdr
*hdr
;
1612 u16 mask
= cpu_to_le16(IEEE80211_FCTL_MOREDATA
);
1613 u16 mask_val
= mask
* val
;
1615 hdr
= (struct ieee80211_hdr
*) bf
->bf_mpdu
->data
;
1616 if ((hdr
->frame_control
& mask
) != mask_val
) {
1617 hdr
->frame_control
= (hdr
->frame_control
& ~mask
) | mask_val
;
1618 dma_sync_single_for_device(sc
->dev
, bf
->bf_buf_addr
,
1619 sizeof(*hdr
), DMA_TO_DEVICE
);
1623 void ath9k_release_buffered_frames(struct ieee80211_hw
*hw
,
1624 struct ieee80211_sta
*sta
,
1625 u16 tids
, int nframes
,
1626 enum ieee80211_frame_release_type reason
,
1629 struct ath_softc
*sc
= hw
->priv
;
1630 struct ath_node
*an
= (struct ath_node
*)sta
->drv_priv
;
1631 struct ath_txq
*txq
= sc
->tx
.uapsdq
;
1632 struct ieee80211_tx_info
*info
;
1633 struct list_head bf_q
;
1634 struct ath_buf
*bf_tail
= NULL
, *bf
= NULL
;
1638 INIT_LIST_HEAD(&bf_q
);
1639 for (i
= 0; tids
&& nframes
; i
++, tids
>>= 1) {
1640 struct ath_atx_tid
*tid
;
1645 tid
= ATH_AN_2_TID(an
, i
);
1647 ath_txq_lock(sc
, tid
->txq
);
1648 while (nframes
> 0) {
1649 ret
= ath_tx_get_tid_subframe(sc
, sc
->tx
.uapsdq
,
1654 ath9k_set_moredata(sc
, bf
, true);
1655 list_add_tail(&bf
->list
, &bf_q
);
1656 ath_set_rates(tid
->an
->vif
, tid
->an
->sta
, bf
);
1658 bf
->bf_state
.bf_type
&= ~BUF_AGGR
;
1660 bf_tail
->bf_next
= bf
;
1665 TX_STAT_INC(sc
, txq
->axq_qnum
, a_queued_hw
);
1667 if (an
->sta
&& skb_queue_empty(&tid
->retry_q
))
1668 ieee80211_sta_set_buffered(an
->sta
, i
, false);
1670 ath_txq_unlock_complete(sc
, tid
->txq
);
1673 if (list_empty(&bf_q
))
1677 ath9k_set_moredata(sc
, bf_tail
, false);
1679 info
= IEEE80211_SKB_CB(bf_tail
->bf_mpdu
);
1680 info
->flags
|= IEEE80211_TX_STATUS_EOSP
;
1682 bf
= list_first_entry(&bf_q
, struct ath_buf
, list
);
1683 ath_txq_lock(sc
, txq
);
1684 ath_tx_fill_desc(sc
, bf
, txq
, 0);
1685 ath_tx_txqaddbuf(sc
, txq
, &bf_q
, false);
1686 ath_txq_unlock(sc
, txq
);
1689 /********************/
1690 /* Queue Management */
1691 /********************/
1693 struct ath_txq
*ath_txq_setup(struct ath_softc
*sc
, int qtype
, int subtype
)
1695 struct ath_hw
*ah
= sc
->sc_ah
;
1696 struct ath9k_tx_queue_info qi
;
1697 static const int subtype_txq_to_hwq
[] = {
1698 [IEEE80211_AC_BE
] = ATH_TXQ_AC_BE
,
1699 [IEEE80211_AC_BK
] = ATH_TXQ_AC_BK
,
1700 [IEEE80211_AC_VI
] = ATH_TXQ_AC_VI
,
1701 [IEEE80211_AC_VO
] = ATH_TXQ_AC_VO
,
1705 memset(&qi
, 0, sizeof(qi
));
1706 qi
.tqi_subtype
= subtype_txq_to_hwq
[subtype
];
1707 qi
.tqi_aifs
= ATH9K_TXQ_USEDEFAULT
;
1708 qi
.tqi_cwmin
= ATH9K_TXQ_USEDEFAULT
;
1709 qi
.tqi_cwmax
= ATH9K_TXQ_USEDEFAULT
;
1710 qi
.tqi_physCompBuf
= 0;
1713 * Enable interrupts only for EOL and DESC conditions.
1714 * We mark tx descriptors to receive a DESC interrupt
1715 * when a tx queue gets deep; otherwise waiting for the
1716 * EOL to reap descriptors. Note that this is done to
1717 * reduce interrupt load and this only defers reaping
1718 * descriptors, never transmitting frames. Aside from
1719 * reducing interrupts this also permits more concurrency.
1720 * The only potential downside is if the tx queue backs
1721 * up in which case the top half of the kernel may backup
1722 * due to a lack of tx descriptors.
1724 * The UAPSD queue is an exception, since we take a desc-
1725 * based intr on the EOSP frames.
1727 if (ah
->caps
.hw_caps
& ATH9K_HW_CAP_EDMA
) {
1728 qi
.tqi_qflags
= TXQ_FLAG_TXINT_ENABLE
;
1730 if (qtype
== ATH9K_TX_QUEUE_UAPSD
)
1731 qi
.tqi_qflags
= TXQ_FLAG_TXDESCINT_ENABLE
;
1733 qi
.tqi_qflags
= TXQ_FLAG_TXEOLINT_ENABLE
|
1734 TXQ_FLAG_TXDESCINT_ENABLE
;
1736 axq_qnum
= ath9k_hw_setuptxqueue(ah
, qtype
, &qi
);
1737 if (axq_qnum
== -1) {
1739 * NB: don't print a message, this happens
1740 * normally on parts with too few tx queues
1744 if (!ATH_TXQ_SETUP(sc
, axq_qnum
)) {
1745 struct ath_txq
*txq
= &sc
->tx
.txq
[axq_qnum
];
1747 txq
->axq_qnum
= axq_qnum
;
1748 txq
->mac80211_qnum
= -1;
1749 txq
->axq_link
= NULL
;
1750 __skb_queue_head_init(&txq
->complete_q
);
1751 INIT_LIST_HEAD(&txq
->axq_q
);
1752 spin_lock_init(&txq
->axq_lock
);
1754 txq
->axq_ampdu_depth
= 0;
1755 txq
->axq_tx_inprogress
= false;
1756 sc
->tx
.txqsetup
|= 1<<axq_qnum
;
1758 txq
->txq_headidx
= txq
->txq_tailidx
= 0;
1759 for (i
= 0; i
< ATH_TXFIFO_DEPTH
; i
++)
1760 INIT_LIST_HEAD(&txq
->txq_fifo
[i
]);
1762 return &sc
->tx
.txq
[axq_qnum
];
1765 int ath_txq_update(struct ath_softc
*sc
, int qnum
,
1766 struct ath9k_tx_queue_info
*qinfo
)
1768 struct ath_hw
*ah
= sc
->sc_ah
;
1770 struct ath9k_tx_queue_info qi
;
1772 BUG_ON(sc
->tx
.txq
[qnum
].axq_qnum
!= qnum
);
1774 ath9k_hw_get_txq_props(ah
, qnum
, &qi
);
1775 qi
.tqi_aifs
= qinfo
->tqi_aifs
;
1776 qi
.tqi_cwmin
= qinfo
->tqi_cwmin
;
1777 qi
.tqi_cwmax
= qinfo
->tqi_cwmax
;
1778 qi
.tqi_burstTime
= qinfo
->tqi_burstTime
;
1779 qi
.tqi_readyTime
= qinfo
->tqi_readyTime
;
1781 if (!ath9k_hw_set_txq_props(ah
, qnum
, &qi
)) {
1782 ath_err(ath9k_hw_common(sc
->sc_ah
),
1783 "Unable to update hardware queue %u!\n", qnum
);
1786 ath9k_hw_resettxqueue(ah
, qnum
);
1792 int ath_cabq_update(struct ath_softc
*sc
)
1794 struct ath9k_tx_queue_info qi
;
1795 struct ath_beacon_config
*cur_conf
= &sc
->cur_chan
->beacon
;
1796 int qnum
= sc
->beacon
.cabq
->axq_qnum
;
1798 ath9k_hw_get_txq_props(sc
->sc_ah
, qnum
, &qi
);
1800 qi
.tqi_readyTime
= (TU_TO_USEC(cur_conf
->beacon_interval
) *
1801 ATH_CABQ_READY_TIME
) / 100;
1802 ath_txq_update(sc
, qnum
, &qi
);
1807 static void ath_drain_txq_list(struct ath_softc
*sc
, struct ath_txq
*txq
,
1808 struct list_head
*list
)
1810 struct ath_buf
*bf
, *lastbf
;
1811 struct list_head bf_head
;
1812 struct ath_tx_status ts
;
1814 memset(&ts
, 0, sizeof(ts
));
1815 ts
.ts_status
= ATH9K_TX_FLUSH
;
1816 INIT_LIST_HEAD(&bf_head
);
1818 while (!list_empty(list
)) {
1819 bf
= list_first_entry(list
, struct ath_buf
, list
);
1821 if (bf
->bf_state
.stale
) {
1822 list_del(&bf
->list
);
1824 ath_tx_return_buffer(sc
, bf
);
1828 lastbf
= bf
->bf_lastbf
;
1829 list_cut_position(&bf_head
, list
, &lastbf
->list
);
1830 ath_tx_process_buffer(sc
, txq
, &ts
, bf
, &bf_head
);
1835 * Drain a given TX queue (could be Beacon or Data)
1837 * This assumes output has been stopped and
1838 * we do not need to block ath_tx_tasklet.
1840 void ath_draintxq(struct ath_softc
*sc
, struct ath_txq
*txq
)
1843 ath_txq_lock(sc
, txq
);
1845 if (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_EDMA
) {
1846 int idx
= txq
->txq_tailidx
;
1848 while (!list_empty(&txq
->txq_fifo
[idx
])) {
1849 ath_drain_txq_list(sc
, txq
, &txq
->txq_fifo
[idx
]);
1851 INCR(idx
, ATH_TXFIFO_DEPTH
);
1853 txq
->txq_tailidx
= idx
;
1856 txq
->axq_link
= NULL
;
1857 txq
->axq_tx_inprogress
= false;
1858 ath_drain_txq_list(sc
, txq
, &txq
->axq_q
);
1860 ath_txq_unlock_complete(sc
, txq
);
1864 bool ath_drain_all_txq(struct ath_softc
*sc
)
1866 struct ath_hw
*ah
= sc
->sc_ah
;
1867 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
1868 struct ath_txq
*txq
;
1872 if (test_bit(ATH_OP_INVALID
, &common
->op_flags
))
1875 ath9k_hw_abort_tx_dma(ah
);
1877 /* Check if any queue remains active */
1878 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++) {
1879 if (!ATH_TXQ_SETUP(sc
, i
))
1882 if (!sc
->tx
.txq
[i
].axq_depth
)
1885 if (ath9k_hw_numtxpending(ah
, sc
->tx
.txq
[i
].axq_qnum
))
1890 RESET_STAT_INC(sc
, RESET_TX_DMA_ERROR
);
1891 ath_dbg(common
, RESET
,
1892 "Failed to stop TX DMA, queues=0x%03x!\n", npend
);
1895 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++) {
1896 if (!ATH_TXQ_SETUP(sc
, i
))
1899 txq
= &sc
->tx
.txq
[i
];
1900 ath_draintxq(sc
, txq
);
1906 void ath_tx_cleanupq(struct ath_softc
*sc
, struct ath_txq
*txq
)
1908 ath9k_hw_releasetxqueue(sc
->sc_ah
, txq
->axq_qnum
);
1909 sc
->tx
.txqsetup
&= ~(1<<txq
->axq_qnum
);
1912 /* For each acq entry, for each tid, try to schedule packets
1913 * for transmit until ampdu_depth has reached min Q depth.
1915 void ath_txq_schedule(struct ath_softc
*sc
, struct ath_txq
*txq
)
1917 struct ieee80211_hw
*hw
= sc
->hw
;
1918 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
1919 struct ieee80211_txq
*queue
;
1920 struct ath_atx_tid
*tid
;
1923 if (txq
->mac80211_qnum
< 0)
1926 if (test_bit(ATH_OP_HW_RESET
, &common
->op_flags
))
1929 ieee80211_txq_schedule_start(hw
, txq
->mac80211_qnum
);
1930 spin_lock_bh(&sc
->chan_lock
);
1933 if (sc
->cur_chan
->stopped
)
1936 while ((queue
= ieee80211_next_txq(hw
, txq
->mac80211_qnum
))) {
1939 tid
= (struct ath_atx_tid
*)queue
->drv_priv
;
1941 ret
= ath_tx_sched_aggr(sc
, txq
, tid
);
1942 ath_dbg(common
, QUEUE
, "ath_tx_sched_aggr returned %d\n", ret
);
1944 force
= !skb_queue_empty(&tid
->retry_q
);
1945 ieee80211_return_txq(hw
, queue
, force
);
1950 spin_unlock_bh(&sc
->chan_lock
);
1951 ieee80211_txq_schedule_end(hw
, txq
->mac80211_qnum
);
1954 void ath_txq_schedule_all(struct ath_softc
*sc
)
1956 struct ath_txq
*txq
;
1959 for (i
= 0; i
< IEEE80211_NUM_ACS
; i
++) {
1960 txq
= sc
->tx
.txq_map
[i
];
1962 spin_lock_bh(&txq
->axq_lock
);
1963 ath_txq_schedule(sc
, txq
);
1964 spin_unlock_bh(&txq
->axq_lock
);
1973 * Insert a chain of ath_buf (descriptors) on a txq and
1974 * assume the descriptors are already chained together by caller.
1976 static void ath_tx_txqaddbuf(struct ath_softc
*sc
, struct ath_txq
*txq
,
1977 struct list_head
*head
, bool internal
)
1979 struct ath_hw
*ah
= sc
->sc_ah
;
1980 struct ath_common
*common
= ath9k_hw_common(ah
);
1981 struct ath_buf
*bf
, *bf_last
;
1982 bool puttxbuf
= false;
1986 * Insert the frame on the outbound list and
1987 * pass it on to the hardware.
1990 if (list_empty(head
))
1993 edma
= !!(ah
->caps
.hw_caps
& ATH9K_HW_CAP_EDMA
);
1994 bf
= list_first_entry(head
, struct ath_buf
, list
);
1995 bf_last
= list_entry(head
->prev
, struct ath_buf
, list
);
1997 ath_dbg(common
, QUEUE
, "qnum: %d, txq depth: %d\n",
1998 txq
->axq_qnum
, txq
->axq_depth
);
2000 if (edma
&& list_empty(&txq
->txq_fifo
[txq
->txq_headidx
])) {
2001 list_splice_tail_init(head
, &txq
->txq_fifo
[txq
->txq_headidx
]);
2002 INCR(txq
->txq_headidx
, ATH_TXFIFO_DEPTH
);
2005 list_splice_tail_init(head
, &txq
->axq_q
);
2007 if (txq
->axq_link
) {
2008 ath9k_hw_set_desc_link(ah
, txq
->axq_link
, bf
->bf_daddr
);
2009 ath_dbg(common
, XMIT
, "link[%u] (%p)=%llx (%p)\n",
2010 txq
->axq_qnum
, txq
->axq_link
,
2011 ito64(bf
->bf_daddr
), bf
->bf_desc
);
2015 txq
->axq_link
= bf_last
->bf_desc
;
2019 TX_STAT_INC(sc
, txq
->axq_qnum
, puttxbuf
);
2020 ath9k_hw_puttxbuf(ah
, txq
->axq_qnum
, bf
->bf_daddr
);
2021 ath_dbg(common
, XMIT
, "TXDP[%u] = %llx (%p)\n",
2022 txq
->axq_qnum
, ito64(bf
->bf_daddr
), bf
->bf_desc
);
2025 if (!edma
|| sc
->tx99_state
) {
2026 TX_STAT_INC(sc
, txq
->axq_qnum
, txstart
);
2027 ath9k_hw_txstart(ah
, txq
->axq_qnum
);
2033 if (bf_is_ampdu_not_probing(bf
))
2034 txq
->axq_ampdu_depth
++;
2036 bf_last
= bf
->bf_lastbf
;
2037 bf
= bf_last
->bf_next
;
2038 bf_last
->bf_next
= NULL
;
2043 static void ath_tx_send_normal(struct ath_softc
*sc
, struct ath_txq
*txq
,
2044 struct ath_atx_tid
*tid
, struct sk_buff
*skb
)
2046 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
2047 struct ath_frame_info
*fi
= get_frame_info(skb
);
2048 struct list_head bf_head
;
2049 struct ath_buf
*bf
= fi
->bf
;
2051 INIT_LIST_HEAD(&bf_head
);
2052 list_add_tail(&bf
->list
, &bf_head
);
2053 bf
->bf_state
.bf_type
= 0;
2054 if (tid
&& (tx_info
->flags
& IEEE80211_TX_CTL_AMPDU
)) {
2055 bf
->bf_state
.bf_type
= BUF_AMPDU
;
2056 ath_tx_addto_baw(sc
, tid
, bf
);
2061 ath_tx_fill_desc(sc
, bf
, txq
, fi
->framelen
);
2062 ath_tx_txqaddbuf(sc
, txq
, &bf_head
, false);
2063 TX_STAT_INC(sc
, txq
->axq_qnum
, queued
);
2066 static void setup_frame_info(struct ieee80211_hw
*hw
,
2067 struct ieee80211_sta
*sta
,
2068 struct sk_buff
*skb
,
2071 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
2072 struct ieee80211_key_conf
*hw_key
= tx_info
->control
.hw_key
;
2073 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
2074 const struct ieee80211_rate
*rate
;
2075 struct ath_frame_info
*fi
= get_frame_info(skb
);
2076 struct ath_node
*an
= NULL
;
2077 enum ath9k_key_type keytype
;
2078 bool short_preamble
= false;
2082 * We check if Short Preamble is needed for the CTS rate by
2083 * checking the BSS's global flag.
2084 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
2086 if (tx_info
->control
.vif
&&
2087 tx_info
->control
.vif
->bss_conf
.use_short_preamble
)
2088 short_preamble
= true;
2090 rate
= ieee80211_get_rts_cts_rate(hw
, tx_info
);
2091 keytype
= ath9k_cmn_get_hw_crypto_keytype(skb
);
2094 an
= (struct ath_node
*) sta
->drv_priv
;
2096 if (tx_info
->control
.vif
) {
2097 struct ieee80211_vif
*vif
= tx_info
->control
.vif
;
2099 txpower
= 2 * vif
->bss_conf
.txpower
;
2101 struct ath_softc
*sc
= hw
->priv
;
2103 txpower
= sc
->cur_chan
->cur_txpower
;
2106 memset(fi
, 0, sizeof(*fi
));
2109 fi
->keyix
= hw_key
->hw_key_idx
;
2110 else if (an
&& ieee80211_is_data(hdr
->frame_control
) && an
->ps_key
> 0)
2111 fi
->keyix
= an
->ps_key
;
2113 fi
->keyix
= ATH9K_TXKEYIX_INVALID
;
2114 fi
->keytype
= keytype
;
2115 fi
->framelen
= framelen
;
2116 fi
->tx_power
= txpower
;
2120 fi
->rtscts_rate
= rate
->hw_value
;
2122 fi
->rtscts_rate
|= rate
->hw_value_short
;
2125 u8
ath_txchainmask_reduction(struct ath_softc
*sc
, u8 chainmask
, u32 rate
)
2127 struct ath_hw
*ah
= sc
->sc_ah
;
2128 struct ath9k_channel
*curchan
= ah
->curchan
;
2130 if ((ah
->caps
.hw_caps
& ATH9K_HW_CAP_APM
) && IS_CHAN_5GHZ(curchan
) &&
2131 (chainmask
== 0x7) && (rate
< 0x90))
2133 else if (AR_SREV_9462(ah
) && ath9k_hw_btcoex_is_enabled(ah
) &&
2141 * Assign a descriptor (and sequence number if necessary,
2142 * and map buffer for DMA. Frees skb on error
2144 static struct ath_buf
*ath_tx_setup_buffer(struct ath_softc
*sc
,
2145 struct ath_txq
*txq
,
2146 struct ath_atx_tid
*tid
,
2147 struct sk_buff
*skb
)
2149 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
2150 struct ath_frame_info
*fi
= get_frame_info(skb
);
2151 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
2156 bf
= ath_tx_get_buffer(sc
);
2158 ath_dbg(common
, XMIT
, "TX buffers are full\n");
2162 ATH_TXBUF_RESET(bf
);
2164 if (tid
&& ieee80211_is_data_present(hdr
->frame_control
)) {
2165 fragno
= le16_to_cpu(hdr
->seq_ctrl
) & IEEE80211_SCTL_FRAG
;
2166 seqno
= tid
->seq_next
;
2167 hdr
->seq_ctrl
= cpu_to_le16(tid
->seq_next
<< IEEE80211_SEQ_SEQ_SHIFT
);
2170 hdr
->seq_ctrl
|= cpu_to_le16(fragno
);
2172 if (!ieee80211_has_morefrags(hdr
->frame_control
))
2173 INCR(tid
->seq_next
, IEEE80211_SEQ_MAX
);
2175 bf
->bf_state
.seqno
= seqno
;
2180 bf
->bf_buf_addr
= dma_map_single(sc
->dev
, skb
->data
,
2181 skb
->len
, DMA_TO_DEVICE
);
2182 if (unlikely(dma_mapping_error(sc
->dev
, bf
->bf_buf_addr
))) {
2184 bf
->bf_buf_addr
= 0;
2185 ath_err(ath9k_hw_common(sc
->sc_ah
),
2186 "dma_mapping_error() on TX\n");
2187 ath_tx_return_buffer(sc
, bf
);
2196 void ath_assign_seq(struct ath_common
*common
, struct sk_buff
*skb
)
2198 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*) skb
->data
;
2199 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
2200 struct ieee80211_vif
*vif
= info
->control
.vif
;
2201 struct ath_vif
*avp
;
2203 if (!(info
->flags
& IEEE80211_TX_CTL_ASSIGN_SEQ
))
2209 avp
= (struct ath_vif
*)vif
->drv_priv
;
2211 if (info
->flags
& IEEE80211_TX_CTL_FIRST_FRAGMENT
)
2212 avp
->seq_no
+= 0x10;
2214 hdr
->seq_ctrl
&= cpu_to_le16(IEEE80211_SCTL_FRAG
);
2215 hdr
->seq_ctrl
|= cpu_to_le16(avp
->seq_no
);
2218 static int ath_tx_prepare(struct ieee80211_hw
*hw
, struct sk_buff
*skb
,
2219 struct ath_tx_control
*txctl
)
2221 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*) skb
->data
;
2222 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
2223 struct ieee80211_sta
*sta
= txctl
->sta
;
2224 struct ieee80211_vif
*vif
= info
->control
.vif
;
2225 struct ath_vif
*avp
;
2226 struct ath_softc
*sc
= hw
->priv
;
2227 int frmlen
= skb
->len
+ FCS_LEN
;
2228 int padpos
, padsize
;
2230 /* NOTE: sta can be NULL according to net/mac80211.h */
2232 txctl
->an
= (struct ath_node
*)sta
->drv_priv
;
2233 else if (vif
&& ieee80211_is_data(hdr
->frame_control
)) {
2234 avp
= (void *)vif
->drv_priv
;
2235 txctl
->an
= &avp
->mcast_node
;
2238 if (info
->control
.hw_key
)
2239 frmlen
+= info
->control
.hw_key
->icv_len
;
2241 ath_assign_seq(ath9k_hw_common(sc
->sc_ah
), skb
);
2243 if ((vif
&& vif
->type
!= NL80211_IFTYPE_AP
&&
2244 vif
->type
!= NL80211_IFTYPE_AP_VLAN
) ||
2245 !ieee80211_is_data(hdr
->frame_control
))
2246 info
->flags
|= IEEE80211_TX_CTL_CLEAR_PS_FILT
;
2248 /* Add the padding after the header if this is not already done */
2249 padpos
= ieee80211_hdrlen(hdr
->frame_control
);
2250 padsize
= padpos
& 3;
2251 if (padsize
&& skb
->len
> padpos
) {
2252 if (skb_headroom(skb
) < padsize
)
2255 skb_push(skb
, padsize
);
2256 memmove(skb
->data
, skb
->data
+ padsize
, padpos
);
2259 setup_frame_info(hw
, sta
, skb
, frmlen
);
2264 /* Upon failure caller should free skb */
2265 int ath_tx_start(struct ieee80211_hw
*hw
, struct sk_buff
*skb
,
2266 struct ath_tx_control
*txctl
)
2268 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
2269 struct ieee80211_sta
*sta
= txctl
->sta
;
2270 struct ieee80211_vif
*vif
= info
->control
.vif
;
2271 struct ath_frame_info
*fi
= get_frame_info(skb
);
2272 struct ath_softc
*sc
= hw
->priv
;
2273 struct ath_txq
*txq
= txctl
->txq
;
2274 struct ath_atx_tid
*tid
= NULL
;
2275 struct ath_node
*an
= NULL
;
2280 ps_resp
= !!(info
->control
.flags
& IEEE80211_TX_CTRL_PS_RESPONSE
);
2282 ret
= ath_tx_prepare(hw
, skb
, txctl
);
2287 * At this point, the vif, hw_key and sta pointers in the tx control
2288 * info are no longer valid (overwritten by the ath_frame_info data.
2291 q
= skb_get_queue_mapping(skb
);
2294 txq
= sc
->tx
.uapsdq
;
2297 an
= (struct ath_node
*) sta
->drv_priv
;
2298 tid
= ath_get_skb_tid(sc
, an
, skb
);
2301 ath_txq_lock(sc
, txq
);
2302 if (txq
== sc
->tx
.txq_map
[q
]) {
2304 ++txq
->pending_frames
;
2307 bf
= ath_tx_setup_buffer(sc
, txq
, tid
, skb
);
2309 ath_txq_skb_done(sc
, txq
, skb
);
2311 dev_kfree_skb_any(skb
);
2313 ieee80211_free_txskb(sc
->hw
, skb
);
2317 bf
->bf_state
.bfs_paprd
= txctl
->paprd
;
2320 bf
->bf_state
.bfs_paprd_timestamp
= jiffies
;
2322 ath_set_rates(vif
, sta
, bf
);
2323 ath_tx_send_normal(sc
, txq
, tid
, skb
);
2326 ath_txq_unlock(sc
, txq
);
2331 void ath_tx_cabq(struct ieee80211_hw
*hw
, struct ieee80211_vif
*vif
,
2332 struct sk_buff
*skb
)
2334 struct ath_softc
*sc
= hw
->priv
;
2335 struct ath_tx_control txctl
= {
2336 .txq
= sc
->beacon
.cabq
2338 struct ath_tx_info info
= {};
2339 struct ath_buf
*bf_tail
= NULL
;
2346 sc
->cur_chan
->beacon
.beacon_interval
* 1000 *
2347 sc
->cur_chan
->beacon
.dtim_period
/ ATH_BCBUF
;
2350 struct ath_frame_info
*fi
= get_frame_info(skb
);
2352 if (ath_tx_prepare(hw
, skb
, &txctl
))
2355 bf
= ath_tx_setup_buffer(sc
, txctl
.txq
, NULL
, skb
);
2360 ath_set_rates(vif
, NULL
, bf
);
2361 ath_buf_set_rate(sc
, bf
, &info
, fi
->framelen
, false);
2362 duration
+= info
.rates
[0].PktDuration
;
2364 bf_tail
->bf_next
= bf
;
2366 list_add_tail(&bf
->list
, &bf_q
);
2370 if (duration
> max_duration
)
2373 skb
= ieee80211_get_buffered_bc(hw
, vif
);
2377 ieee80211_free_txskb(hw
, skb
);
2379 if (list_empty(&bf_q
))
2382 bf
= list_last_entry(&bf_q
, struct ath_buf
, list
);
2383 ath9k_set_moredata(sc
, bf
, false);
2385 bf
= list_first_entry(&bf_q
, struct ath_buf
, list
);
2386 ath_txq_lock(sc
, txctl
.txq
);
2387 ath_tx_fill_desc(sc
, bf
, txctl
.txq
, 0);
2388 ath_tx_txqaddbuf(sc
, txctl
.txq
, &bf_q
, false);
2389 TX_STAT_INC(sc
, txctl
.txq
->axq_qnum
, queued
);
2390 ath_txq_unlock(sc
, txctl
.txq
);
2397 static void ath_tx_complete(struct ath_softc
*sc
, struct sk_buff
*skb
,
2398 int tx_flags
, struct ath_txq
*txq
,
2399 struct ieee80211_sta
*sta
)
2401 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
2402 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
2403 struct ieee80211_hdr
* hdr
= (struct ieee80211_hdr
*)skb
->data
;
2404 int padpos
, padsize
;
2405 unsigned long flags
;
2407 ath_dbg(common
, XMIT
, "TX complete: skb: %p\n", skb
);
2409 if (sc
->sc_ah
->caldata
)
2410 set_bit(PAPRD_PACKET_SENT
, &sc
->sc_ah
->caldata
->cal_flags
);
2412 if (!(tx_flags
& ATH_TX_ERROR
)) {
2413 if (tx_info
->flags
& IEEE80211_TX_CTL_NO_ACK
)
2414 tx_info
->flags
|= IEEE80211_TX_STAT_NOACK_TRANSMITTED
;
2416 tx_info
->flags
|= IEEE80211_TX_STAT_ACK
;
2419 if (tx_info
->flags
& IEEE80211_TX_CTL_REQ_TX_STATUS
) {
2420 padpos
= ieee80211_hdrlen(hdr
->frame_control
);
2421 padsize
= padpos
& 3;
2422 if (padsize
&& skb
->len
>padpos
+padsize
) {
2424 * Remove MAC header padding before giving the frame back to
2427 memmove(skb
->data
+ padsize
, skb
->data
, padpos
);
2428 skb_pull(skb
, padsize
);
2432 spin_lock_irqsave(&sc
->sc_pm_lock
, flags
);
2433 if ((sc
->ps_flags
& PS_WAIT_FOR_TX_ACK
) && !txq
->axq_depth
) {
2434 sc
->ps_flags
&= ~PS_WAIT_FOR_TX_ACK
;
2436 "Going back to sleep after having received TX status (0x%lx)\n",
2437 sc
->ps_flags
& (PS_WAIT_FOR_BEACON
|
2439 PS_WAIT_FOR_PSPOLL_DATA
|
2440 PS_WAIT_FOR_TX_ACK
));
2442 spin_unlock_irqrestore(&sc
->sc_pm_lock
, flags
);
2444 ath_txq_skb_done(sc
, txq
, skb
);
2445 tx_info
->status
.status_driver_data
[0] = sta
;
2446 __skb_queue_tail(&txq
->complete_q
, skb
);
2449 static void ath_tx_complete_buf(struct ath_softc
*sc
, struct ath_buf
*bf
,
2450 struct ath_txq
*txq
, struct list_head
*bf_q
,
2451 struct ieee80211_sta
*sta
,
2452 struct ath_tx_status
*ts
, int txok
)
2454 struct sk_buff
*skb
= bf
->bf_mpdu
;
2455 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
2456 unsigned long flags
;
2460 tx_flags
|= ATH_TX_ERROR
;
2462 if (ts
->ts_status
& ATH9K_TXERR_FILT
)
2463 tx_info
->flags
|= IEEE80211_TX_STAT_TX_FILTERED
;
2465 dma_unmap_single(sc
->dev
, bf
->bf_buf_addr
, skb
->len
, DMA_TO_DEVICE
);
2466 bf
->bf_buf_addr
= 0;
2468 goto skip_tx_complete
;
2470 if (bf
->bf_state
.bfs_paprd
) {
2471 if (time_after(jiffies
,
2472 bf
->bf_state
.bfs_paprd_timestamp
+
2473 msecs_to_jiffies(ATH_PAPRD_TIMEOUT
)))
2474 dev_kfree_skb_any(skb
);
2476 complete(&sc
->paprd_complete
);
2478 ath_debug_stat_tx(sc
, bf
, ts
, txq
, tx_flags
);
2479 ath_tx_complete(sc
, skb
, tx_flags
, txq
, sta
);
2482 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
2483 * accidentally reference it later.
2488 * Return the list of ath_buf of this mpdu to free queue
2490 spin_lock_irqsave(&sc
->tx
.txbuflock
, flags
);
2491 list_splice_tail_init(bf_q
, &sc
->tx
.txbuf
);
2492 spin_unlock_irqrestore(&sc
->tx
.txbuflock
, flags
);
2495 static void ath_tx_rc_status(struct ath_softc
*sc
, struct ath_buf
*bf
,
2496 struct ath_tx_status
*ts
, int nframes
, int nbad
,
2499 struct sk_buff
*skb
= bf
->bf_mpdu
;
2500 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
2501 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
2502 struct ieee80211_hw
*hw
= sc
->hw
;
2503 struct ath_hw
*ah
= sc
->sc_ah
;
2507 tx_info
->status
.ack_signal
= ts
->ts_rssi
;
2509 tx_rateindex
= ts
->ts_rateindex
;
2510 WARN_ON(tx_rateindex
>= hw
->max_rates
);
2512 if (tx_info
->flags
& IEEE80211_TX_CTL_AMPDU
) {
2513 tx_info
->flags
|= IEEE80211_TX_STAT_AMPDU
;
2515 BUG_ON(nbad
> nframes
);
2517 tx_info
->status
.ampdu_len
= nframes
;
2518 tx_info
->status
.ampdu_ack_len
= nframes
- nbad
;
2520 if ((ts
->ts_status
& ATH9K_TXERR_FILT
) == 0 &&
2521 (tx_info
->flags
& IEEE80211_TX_CTL_NO_ACK
) == 0) {
2523 * If an underrun error is seen assume it as an excessive
2524 * retry only if max frame trigger level has been reached
2525 * (2 KB for single stream, and 4 KB for dual stream).
2526 * Adjust the long retry as if the frame was tried
2527 * hw->max_rate_tries times to affect how rate control updates
2528 * PER for the failed rate.
2529 * In case of congestion on the bus penalizing this type of
2530 * underruns should help hardware actually transmit new frames
2531 * successfully by eventually preferring slower rates.
2532 * This itself should also alleviate congestion on the bus.
2534 if (unlikely(ts
->ts_flags
& (ATH9K_TX_DATA_UNDERRUN
|
2535 ATH9K_TX_DELIM_UNDERRUN
)) &&
2536 ieee80211_is_data(hdr
->frame_control
) &&
2537 ah
->tx_trig_level
>= sc
->sc_ah
->config
.max_txtrig_level
)
2538 tx_info
->status
.rates
[tx_rateindex
].count
=
2542 for (i
= tx_rateindex
+ 1; i
< hw
->max_rates
; i
++) {
2543 tx_info
->status
.rates
[i
].count
= 0;
2544 tx_info
->status
.rates
[i
].idx
= -1;
2547 tx_info
->status
.rates
[tx_rateindex
].count
= ts
->ts_longretry
+ 1;
2549 /* we report airtime in ath_tx_count_airtime(), don't report twice */
2550 tx_info
->status
.tx_time
= 0;
2553 static void ath_tx_processq(struct ath_softc
*sc
, struct ath_txq
*txq
)
2555 struct ath_hw
*ah
= sc
->sc_ah
;
2556 struct ath_common
*common
= ath9k_hw_common(ah
);
2557 struct ath_buf
*bf
, *lastbf
, *bf_held
= NULL
;
2558 struct list_head bf_head
;
2559 struct ath_desc
*ds
;
2560 struct ath_tx_status ts
;
2563 ath_dbg(common
, QUEUE
, "tx queue %d (%x), link %p\n",
2564 txq
->axq_qnum
, ath9k_hw_gettxbuf(sc
->sc_ah
, txq
->axq_qnum
),
2567 ath_txq_lock(sc
, txq
);
2569 if (test_bit(ATH_OP_HW_RESET
, &common
->op_flags
))
2572 if (list_empty(&txq
->axq_q
)) {
2573 txq
->axq_link
= NULL
;
2574 ath_txq_schedule(sc
, txq
);
2577 bf
= list_first_entry(&txq
->axq_q
, struct ath_buf
, list
);
2580 * There is a race condition that a BH gets scheduled
2581 * after sw writes TxE and before hw re-load the last
2582 * descriptor to get the newly chained one.
2583 * Software must keep the last DONE descriptor as a
2584 * holding descriptor - software does so by marking
2585 * it with the STALE flag.
2588 if (bf
->bf_state
.stale
) {
2590 if (list_is_last(&bf_held
->list
, &txq
->axq_q
))
2593 bf
= list_entry(bf_held
->list
.next
, struct ath_buf
,
2597 lastbf
= bf
->bf_lastbf
;
2598 ds
= lastbf
->bf_desc
;
2600 memset(&ts
, 0, sizeof(ts
));
2601 status
= ath9k_hw_txprocdesc(ah
, ds
, &ts
);
2602 if (status
== -EINPROGRESS
)
2605 TX_STAT_INC(sc
, txq
->axq_qnum
, txprocdesc
);
2608 * Remove ath_buf's of the same transmit unit from txq,
2609 * however leave the last descriptor back as the holding
2610 * descriptor for hw.
2612 lastbf
->bf_state
.stale
= true;
2613 INIT_LIST_HEAD(&bf_head
);
2614 if (!list_is_singular(&lastbf
->list
))
2615 list_cut_position(&bf_head
,
2616 &txq
->axq_q
, lastbf
->list
.prev
);
2619 list_del(&bf_held
->list
);
2620 ath_tx_return_buffer(sc
, bf_held
);
2623 ath_tx_process_buffer(sc
, txq
, &ts
, bf
, &bf_head
);
2625 ath_txq_unlock_complete(sc
, txq
);
2628 void ath_tx_tasklet(struct ath_softc
*sc
)
2630 struct ath_hw
*ah
= sc
->sc_ah
;
2631 u32 qcumask
= ((1 << ATH9K_NUM_TX_QUEUES
) - 1) & ah
->intr_txqs
;
2635 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++) {
2636 if (ATH_TXQ_SETUP(sc
, i
) && (qcumask
& (1 << i
)))
2637 ath_tx_processq(sc
, &sc
->tx
.txq
[i
]);
2642 void ath_tx_edma_tasklet(struct ath_softc
*sc
)
2644 struct ath_tx_status ts
;
2645 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
2646 struct ath_hw
*ah
= sc
->sc_ah
;
2647 struct ath_txq
*txq
;
2648 struct ath_buf
*bf
, *lastbf
;
2649 struct list_head bf_head
;
2650 struct list_head
*fifo_list
;
2655 if (test_bit(ATH_OP_HW_RESET
, &common
->op_flags
))
2658 status
= ath9k_hw_txprocdesc(ah
, NULL
, (void *)&ts
);
2659 if (status
== -EINPROGRESS
)
2661 if (status
== -EIO
) {
2662 ath_dbg(common
, XMIT
, "Error processing tx status\n");
2666 /* Process beacon completions separately */
2667 if (ts
.qid
== sc
->beacon
.beaconq
) {
2668 sc
->beacon
.tx_processed
= true;
2669 sc
->beacon
.tx_last
= !(ts
.ts_status
& ATH9K_TXERR_MASK
);
2671 if (ath9k_is_chanctx_enabled()) {
2672 ath_chanctx_event(sc
, NULL
,
2673 ATH_CHANCTX_EVENT_BEACON_SENT
);
2676 ath9k_csa_update(sc
);
2680 txq
= &sc
->tx
.txq
[ts
.qid
];
2682 ath_txq_lock(sc
, txq
);
2684 TX_STAT_INC(sc
, txq
->axq_qnum
, txprocdesc
);
2686 fifo_list
= &txq
->txq_fifo
[txq
->txq_tailidx
];
2687 if (list_empty(fifo_list
)) {
2688 ath_txq_unlock(sc
, txq
);
2692 bf
= list_first_entry(fifo_list
, struct ath_buf
, list
);
2693 if (bf
->bf_state
.stale
) {
2694 list_del(&bf
->list
);
2695 ath_tx_return_buffer(sc
, bf
);
2696 bf
= list_first_entry(fifo_list
, struct ath_buf
, list
);
2699 lastbf
= bf
->bf_lastbf
;
2701 INIT_LIST_HEAD(&bf_head
);
2702 if (list_is_last(&lastbf
->list
, fifo_list
)) {
2703 list_splice_tail_init(fifo_list
, &bf_head
);
2704 INCR(txq
->txq_tailidx
, ATH_TXFIFO_DEPTH
);
2706 if (!list_empty(&txq
->axq_q
)) {
2707 struct list_head bf_q
;
2709 INIT_LIST_HEAD(&bf_q
);
2710 txq
->axq_link
= NULL
;
2711 list_splice_tail_init(&txq
->axq_q
, &bf_q
);
2712 ath_tx_txqaddbuf(sc
, txq
, &bf_q
, true);
2715 lastbf
->bf_state
.stale
= true;
2717 list_cut_position(&bf_head
, fifo_list
,
2721 ath_tx_process_buffer(sc
, txq
, &ts
, bf
, &bf_head
);
2722 ath_txq_unlock_complete(sc
, txq
);
2731 static int ath_txstatus_setup(struct ath_softc
*sc
, int size
)
2733 struct ath_descdma
*dd
= &sc
->txsdma
;
2734 u8 txs_len
= sc
->sc_ah
->caps
.txs_len
;
2736 dd
->dd_desc_len
= size
* txs_len
;
2737 dd
->dd_desc
= dmam_alloc_coherent(sc
->dev
, dd
->dd_desc_len
,
2738 &dd
->dd_desc_paddr
, GFP_KERNEL
);
2745 static int ath_tx_edma_init(struct ath_softc
*sc
)
2749 err
= ath_txstatus_setup(sc
, ATH_TXSTATUS_RING_SIZE
);
2751 ath9k_hw_setup_statusring(sc
->sc_ah
, sc
->txsdma
.dd_desc
,
2752 sc
->txsdma
.dd_desc_paddr
,
2753 ATH_TXSTATUS_RING_SIZE
);
2758 int ath_tx_init(struct ath_softc
*sc
, int nbufs
)
2760 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
2763 spin_lock_init(&sc
->tx
.txbuflock
);
2765 error
= ath_descdma_setup(sc
, &sc
->tx
.txdma
, &sc
->tx
.txbuf
,
2769 "Failed to allocate tx descriptors: %d\n", error
);
2773 error
= ath_descdma_setup(sc
, &sc
->beacon
.bdma
, &sc
->beacon
.bbuf
,
2774 "beacon", ATH_BCBUF
, 1, 1);
2777 "Failed to allocate beacon descriptors: %d\n", error
);
2781 if (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_EDMA
)
2782 error
= ath_tx_edma_init(sc
);
2787 void ath_tx_node_init(struct ath_softc
*sc
, struct ath_node
*an
)
2789 struct ath_atx_tid
*tid
;
2792 for (tidno
= 0; tidno
< IEEE80211_NUM_TIDS
; tidno
++) {
2793 tid
= ath_node_to_tid(an
, tidno
);
2796 tid
->seq_start
= tid
->seq_next
= 0;
2797 tid
->baw_size
= WME_MAX_BA
;
2798 tid
->baw_head
= tid
->baw_tail
= 0;
2799 tid
->active
= false;
2800 tid
->clear_ps_filter
= true;
2801 __skb_queue_head_init(&tid
->retry_q
);
2802 INIT_LIST_HEAD(&tid
->list
);
2803 acno
= TID_TO_WME_AC(tidno
);
2804 tid
->txq
= sc
->tx
.txq_map
[acno
];
2807 break; /* just one multicast ath_atx_tid */
2811 void ath_tx_node_cleanup(struct ath_softc
*sc
, struct ath_node
*an
)
2813 struct ath_atx_tid
*tid
;
2814 struct ath_txq
*txq
;
2819 for (tidno
= 0; tidno
< IEEE80211_NUM_TIDS
; tidno
++) {
2820 tid
= ath_node_to_tid(an
, tidno
);
2823 ath_txq_lock(sc
, txq
);
2825 if (!list_empty(&tid
->list
))
2826 list_del_init(&tid
->list
);
2828 ath_tid_drain(sc
, txq
, tid
);
2829 tid
->active
= false;
2831 ath_txq_unlock(sc
, txq
);
2834 break; /* just one multicast ath_atx_tid */
2840 #ifdef CONFIG_ATH9K_TX99
2842 int ath9k_tx99_send(struct ath_softc
*sc
, struct sk_buff
*skb
,
2843 struct ath_tx_control
*txctl
)
2845 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*) skb
->data
;
2846 struct ath_frame_info
*fi
= get_frame_info(skb
);
2847 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
2849 int padpos
, padsize
;
2851 padpos
= ieee80211_hdrlen(hdr
->frame_control
);
2852 padsize
= padpos
& 3;
2854 if (padsize
&& skb
->len
> padpos
) {
2855 if (skb_headroom(skb
) < padsize
) {
2856 ath_dbg(common
, XMIT
,
2857 "tx99 padding failed\n");
2861 skb_push(skb
, padsize
);
2862 memmove(skb
->data
, skb
->data
+ padsize
, padpos
);
2865 fi
->keyix
= ATH9K_TXKEYIX_INVALID
;
2866 fi
->framelen
= skb
->len
+ FCS_LEN
;
2867 fi
->keytype
= ATH9K_KEY_TYPE_CLEAR
;
2869 bf
= ath_tx_setup_buffer(sc
, txctl
->txq
, NULL
, skb
);
2871 ath_dbg(common
, XMIT
, "tx99 buffer setup failed\n");
2875 ath_set_rates(sc
->tx99_vif
, NULL
, bf
);
2877 ath9k_hw_set_desc_link(sc
->sc_ah
, bf
->bf_desc
, bf
->bf_daddr
);
2878 ath9k_hw_tx99_start(sc
->sc_ah
, txctl
->txq
->axq_qnum
);
2880 ath_tx_send_normal(sc
, txctl
->txq
, NULL
, skb
);
2885 #endif /* CONFIG_ATH9K_TX99 */