drivers/net/wireless/intel/iwlwifi/pcie/ctxt-info.c

   1 /******************************************************************************
   2  *
   3  * This file is provided under a dual BSD/GPLv2 license.  When using or
   4  * redistributing this file, you may do so under either license.
   5  *
   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2017 Intel Deutschland GmbH
   9  * Copyright(c) 2018 - 2019 Intel Corporation
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of version 2 of the GNU General Public License as
  13  * published by the Free Software Foundation.
  14  *
  15  * This program is distributed in the hope that it will be useful, but
  16  * WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  18  * General Public License for more details.
  19  *
  20  * BSD LICENSE
  21  *
  22  * Copyright(c) 2017 Intel Deutschland GmbH
  23  * Copyright(c) 2018 - 2019 Intel Corporation
  24  * All rights reserved.
  25  *
  26  * Redistribution and use in source and binary forms, with or without
  27  * modification, are permitted provided that the following conditions
  28  * are met:
  29  *
  30  *  * Redistributions of source code must retain the above copyright
  31  *    notice, this list of conditions and the following disclaimer.
  32  *  * Redistributions in binary form must reproduce the above copyright
  33  *    notice, this list of conditions and the following disclaimer in
  34  *    the documentation and/or other materials provided with the
  35  *    distribution.
  36  *  * Neither the name Intel Corporation nor the names of its
  37  *    contributors may be used to endorse or promote products derived
  38  *    from this software without specific prior written permission.
  39  *
  40  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  41  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  42  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  43  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  44  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  45  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  46  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  47  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  48  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  49  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  50  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  51  *
  52  *****************************************************************************/
  53
  54 #include "iwl-trans.h"
  55 #include "iwl-fh.h"
  56 #include "iwl-context-info.h"
  57 #include "internal.h"
  58 #include "iwl-prph.h"
  59
  60 static void *_iwl_pcie_ctxt_info_dma_alloc_coherent(struct iwl_trans *trans,
  61                                                     size_t size,
  62                                                     dma_addr_t *phys,
  63                                                     int depth)
  64 {
  65         void *result;
  66
  67         if (WARN(depth > 2,
  68                  "failed to allocate DMA memory not crossing 2^32 boundary"))
  69                 return NULL;
  70
  71         result = dma_alloc_coherent(trans->dev, size, phys, GFP_KERNEL);
  72
  73         if (!result)
  74                 return NULL;
  75
  76         if (unlikely(iwl_pcie_crosses_4g_boundary(*phys, size))) {
  77                 void *old = result;
  78                 dma_addr_t oldphys = *phys;
  79
  80                 result = _iwl_pcie_ctxt_info_dma_alloc_coherent(trans, size,
  81                                                                 phys,
  82                                                                 depth + 1);
  83                 dma_free_coherent(trans->dev, size, old, oldphys);
  84         }
  85
  86         return result;
  87 }
  88
  89 static void *iwl_pcie_ctxt_info_dma_alloc_coherent(struct iwl_trans *trans,
  90                                                    size_t size,
  91                                                    dma_addr_t *phys)
  92 {
  93         return _iwl_pcie_ctxt_info_dma_alloc_coherent(trans, size, phys, 0);
  94 }
  95
  96 void iwl_pcie_ctxt_info_free_paging(struct iwl_trans *trans)
  97 {
  98         struct iwl_self_init_dram *dram = &trans->init_dram;
  99         int i;
 100
 101         if (!dram->paging) {
 102                 WARN_ON(dram->paging_cnt);
 103                 return;
 104         }
 105
 106         /* free paging*/
 107         for (i = 0; i < dram->paging_cnt; i++)
 108                 dma_free_coherent(trans->dev, dram->paging[i].size,
 109                                   dram->paging[i].block,
 110                                   dram->paging[i].physical);
 111
 112         kfree(dram->paging);
 113         dram->paging_cnt = 0;
 114         dram->paging = NULL;
 115 }
 116
 117 int iwl_pcie_init_fw_sec(struct iwl_trans *trans,
 118                          const struct fw_img *fw,
 119                          struct iwl_context_info_dram *ctxt_dram)
 120 {
 121         struct iwl_self_init_dram *dram = &trans->init_dram;
 122         int i, ret, lmac_cnt, umac_cnt, paging_cnt;
 123
 124         if (WARN(dram->paging,
 125                  "paging shouldn't already be initialized (%d pages)\n",
 126                  dram->paging_cnt))
 127                 iwl_pcie_ctxt_info_free_paging(trans);
 128
 129         lmac_cnt = iwl_pcie_get_num_sections(fw, 0);
 130         /* add 1 due to separator */
 131         umac_cnt = iwl_pcie_get_num_sections(fw, lmac_cnt + 1);
 132         /* add 2 due to separators */
 133         paging_cnt = iwl_pcie_get_num_sections(fw, lmac_cnt + umac_cnt + 2);
 134
 135         dram->fw = kcalloc(umac_cnt + lmac_cnt, sizeof(*dram->fw), GFP_KERNEL);
 136         if (!dram->fw)
 137                 return -ENOMEM;
 138         dram->paging = kcalloc(paging_cnt, sizeof(*dram->paging), GFP_KERNEL);
 139         if (!dram->paging)
 140                 return -ENOMEM;
 141
 142         /* initialize lmac sections */
 143         for (i = 0; i < lmac_cnt; i++) {
 144                 ret = iwl_pcie_ctxt_info_alloc_dma(trans, &fw->sec[i],
 145                                                    &dram->fw[dram->fw_cnt]);
 146                 if (ret)
 147                         return ret;
 148                 ctxt_dram->lmac_img[i] =
 149                         cpu_to_le64(dram->fw[dram->fw_cnt].physical);
 150                 dram->fw_cnt++;
 151         }
 152
 153         /* initialize umac sections */
 154         for (i = 0; i < umac_cnt; i++) {
 155                 /* access FW with +1 to make up for lmac separator */
 156                 ret = iwl_pcie_ctxt_info_alloc_dma(trans,
 157                                                    &fw->sec[dram->fw_cnt + 1],
 158                                                    &dram->fw[dram->fw_cnt]);
 159                 if (ret)
 160                         return ret;
 161                 ctxt_dram->umac_img[i] =
 162                         cpu_to_le64(dram->fw[dram->fw_cnt].physical);
 163                 dram->fw_cnt++;
 164         }
 165
 166         /*
 167          * Initialize paging.
 168          * Paging memory isn't stored in dram->fw as the umac and lmac - it is
 169          * stored separately.
 170          * This is since the timing of its release is different -
 171          * while fw memory can be released on alive, the paging memory can be
 172          * freed only when the device goes down.
 173          * Given that, the logic here in accessing the fw image is a bit
 174          * different - fw_cnt isn't changing so loop counter is added to it.
 175          */
 176         for (i = 0; i < paging_cnt; i++) {
 177                 /* access FW with +2 to make up for lmac & umac separators */
 178                 int fw_idx = dram->fw_cnt + i + 2;
 179
 180                 ret = iwl_pcie_ctxt_info_alloc_dma(trans, &fw->sec[fw_idx],
 181                                                    &dram->paging[i]);
 182                 if (ret)
 183                         return ret;
 184
 185                 ctxt_dram->virtual_img[i] =
 186                         cpu_to_le64(dram->paging[i].physical);
 187                 dram->paging_cnt++;
 188         }
 189
 190         return 0;
 191 }
 192
 193 int iwl_pcie_ctxt_info_init(struct iwl_trans *trans,
 194                             const struct fw_img *fw)
 195 {
 196         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 197         struct iwl_context_info *ctxt_info;
 198         struct iwl_context_info_rbd_cfg *rx_cfg;
 199         u32 control_flags = 0, rb_size;
 200         dma_addr_t phys;
 201         int ret;
 202
 203         ctxt_info = iwl_pcie_ctxt_info_dma_alloc_coherent(trans,
 204                                                           sizeof(*ctxt_info),
 205                                                           &phys);
 206         if (!ctxt_info)
 207                 return -ENOMEM;
 208
 209         trans_pcie->ctxt_info_dma_addr = phys;
 210
 211         ctxt_info->version.version = 0;
 212         ctxt_info->version.mac_id =
 213                 cpu_to_le16((u16)iwl_read32(trans, CSR_HW_REV));
 214         /* size is in DWs */
 215         ctxt_info->version.size = cpu_to_le16(sizeof(*ctxt_info) / 4);
 216
 217         switch (trans_pcie->rx_buf_size) {
 218         case IWL_AMSDU_2K:
 219                 rb_size = IWL_CTXT_INFO_RB_SIZE_2K;
 220                 break;
 221         case IWL_AMSDU_4K:
 222                 rb_size = IWL_CTXT_INFO_RB_SIZE_4K;
 223                 break;
 224         case IWL_AMSDU_8K:
 225                 rb_size = IWL_CTXT_INFO_RB_SIZE_8K;
 226                 break;
 227         case IWL_AMSDU_12K:
 228                 rb_size = IWL_CTXT_INFO_RB_SIZE_12K;
 229                 break;
 230         default:
 231                 WARN_ON(1);
 232                 rb_size = IWL_CTXT_INFO_RB_SIZE_4K;
 233         }
 234
 235         WARN_ON(RX_QUEUE_CB_SIZE(trans->cfg->num_rbds) > 12);
 236         control_flags = IWL_CTXT_INFO_TFD_FORMAT_LONG;
 237         control_flags |=
 238                 u32_encode_bits(RX_QUEUE_CB_SIZE(trans->cfg->num_rbds),
 239                                 IWL_CTXT_INFO_RB_CB_SIZE);
 240         control_flags |= u32_encode_bits(rb_size, IWL_CTXT_INFO_RB_SIZE);
 241         ctxt_info->control.control_flags = cpu_to_le32(control_flags);
 242
 243         /* initialize RX default queue */
 244         rx_cfg = &ctxt_info->rbd_cfg;
 245         rx_cfg->free_rbd_addr = cpu_to_le64(trans_pcie->rxq->bd_dma);
 246         rx_cfg->used_rbd_addr = cpu_to_le64(trans_pcie->rxq->used_bd_dma);
 247         rx_cfg->status_wr_ptr = cpu_to_le64(trans_pcie->rxq->rb_stts_dma);
 248
 249         /* initialize TX command queue */
 250         ctxt_info->hcmd_cfg.cmd_queue_addr =
 251                 cpu_to_le64(trans_pcie->txq[trans_pcie->cmd_queue]->dma_addr);
 252         ctxt_info->hcmd_cfg.cmd_queue_size =
 253                 TFD_QUEUE_CB_SIZE(IWL_CMD_QUEUE_SIZE);
 254
 255         /* allocate ucode sections in dram and set addresses */
 256         ret = iwl_pcie_init_fw_sec(trans, fw, &ctxt_info->dram);
 257         if (ret) {
 258                 dma_free_coherent(trans->dev, sizeof(*trans_pcie->ctxt_info),
 259                                   ctxt_info, trans_pcie->ctxt_info_dma_addr);
 260                 return ret;
 261         }
 262
 263         trans_pcie->ctxt_info = ctxt_info;
 264
 265         iwl_enable_fw_load_int_ctx_info(trans);
 266
 267         /* Configure debug, if exists */
 268         if (iwl_pcie_dbg_on(trans))
 269                 iwl_pcie_apply_destination(trans);
 270
 271         /* kick FW self load */
 272         iwl_write64(trans, CSR_CTXT_INFO_BA, trans_pcie->ctxt_info_dma_addr);
 273         iwl_write_prph(trans, UREG_CPU_INIT_RUN, 1);
 274
 275         /* Context info will be released upon alive or failure to get one */
 276
 277         return 0;
 278 }
 279
 280 void iwl_pcie_ctxt_info_free(struct iwl_trans *trans)
 281 {
 282         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 283
 284         if (!trans_pcie->ctxt_info)
 285                 return;
 286
 287         dma_free_coherent(trans->dev, sizeof(*trans_pcie->ctxt_info),
 288                           trans_pcie->ctxt_info,
 289                           trans_pcie->ctxt_info_dma_addr);
 290         trans_pcie->ctxt_info_dma_addr = 0;
 291         trans_pcie->ctxt_info = NULL;
 292
 293         iwl_pcie_ctxt_info_free_fw_img(trans);
 294 }