drivers/net/wireless/mediatek/mt76/mt76x02_mmio.c

   1 // SPDX-License-Identifier: ISC
   2 /*
   3  * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
   4  * Copyright (C) 2018 Lorenzo Bianconi <lorenzo.bianconi83@gmail.com>
   5  */
   6
   7 #include <linux/kernel.h>
   8 #include <linux/irq.h>
   9
  10 #include "mt76x02.h"
  11 #include "mt76x02_mcu.h"
  12 #include "mt76x02_trace.h"
  13
  14 static void mt76x02_pre_tbtt_tasklet(unsigned long arg)
  15 {
  16         struct mt76x02_dev *dev = (struct mt76x02_dev *)arg;
  17         struct mt76_queue *q = dev->mt76.q_tx[MT_TXQ_PSD].q;
  18         struct beacon_bc_data data = {};
  19         struct sk_buff *skb;
  20         int i;
  21
  22         if (mt76_hw(dev)->conf.flags & IEEE80211_CONF_OFFCHANNEL)
  23                 return;
  24
  25         mt76x02_resync_beacon_timer(dev);
  26
  27         ieee80211_iterate_active_interfaces_atomic(mt76_hw(dev),
  28                 IEEE80211_IFACE_ITER_RESUME_ALL,
  29                 mt76x02_update_beacon_iter, dev);
  30
  31         mt76_csa_check(&dev->mt76);
  32
  33         if (dev->mt76.csa_complete)
  34                 return;
  35
  36         mt76x02_enqueue_buffered_bc(dev, &data, 8);
  37
  38         if (!skb_queue_len(&data.q))
  39                 return;
  40
  41         for (i = 0; i < ARRAY_SIZE(data.tail); i++) {
  42                 if (!data.tail[i])
  43                         continue;
  44
  45                 mt76_skb_set_moredata(data.tail[i], false);
  46         }
  47
  48         spin_lock_bh(&q->lock);
  49         while ((skb = __skb_dequeue(&data.q)) != NULL) {
  50                 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  51                 struct ieee80211_vif *vif = info->control.vif;
  52                 struct mt76x02_vif *mvif = (struct mt76x02_vif *)vif->drv_priv;
  53
  54                 mt76_tx_queue_skb(dev, MT_TXQ_PSD, skb, &mvif->group_wcid,
  55                                   NULL);
  56         }
  57         spin_unlock_bh(&q->lock);
  58 }
  59
  60 static void mt76x02e_pre_tbtt_enable(struct mt76x02_dev *dev, bool en)
  61 {
  62         if (en)
  63                 tasklet_enable(&dev->mt76.pre_tbtt_tasklet);
  64         else
  65                 tasklet_disable(&dev->mt76.pre_tbtt_tasklet);
  66 }
  67
  68 static void mt76x02e_beacon_enable(struct mt76x02_dev *dev, bool en)
  69 {
  70         mt76_rmw_field(dev, MT_INT_TIMER_EN, MT_INT_TIMER_EN_PRE_TBTT_EN, en);
  71         if (en)
  72                 mt76x02_irq_enable(dev, MT_INT_PRE_TBTT | MT_INT_TBTT);
  73         else
  74                 mt76x02_irq_disable(dev, MT_INT_PRE_TBTT | MT_INT_TBTT);
  75 }
  76
  77 void mt76x02e_init_beacon_config(struct mt76x02_dev *dev)
  78 {
  79         static const struct mt76x02_beacon_ops beacon_ops = {
  80                 .nslots = 8,
  81                 .slot_size = 1024,
  82                 .pre_tbtt_enable = mt76x02e_pre_tbtt_enable,
  83                 .beacon_enable = mt76x02e_beacon_enable,
  84         };
  85
  86         dev->beacon_ops = &beacon_ops;
  87
  88         /* Fire a pre-TBTT interrupt 8 ms before TBTT */
  89         mt76_rmw_field(dev, MT_INT_TIMER_CFG, MT_INT_TIMER_CFG_PRE_TBTT,
  90                        8 << 4);
  91         mt76_rmw_field(dev, MT_INT_TIMER_CFG, MT_INT_TIMER_CFG_GP_TIMER,
  92                        MT_DFS_GP_INTERVAL);
  93         mt76_wr(dev, MT_INT_TIMER_EN, 0);
  94
  95         mt76x02_init_beacon_config(dev);
  96 }
  97 EXPORT_SYMBOL_GPL(mt76x02e_init_beacon_config);
  98
  99 static int
 100 mt76x02_init_tx_queue(struct mt76x02_dev *dev, struct mt76_sw_queue *q,
 101                       int idx, int n_desc)
 102 {
 103         struct mt76_queue *hwq;
 104         int err;
 105
 106         hwq = devm_kzalloc(dev->mt76.dev, sizeof(*hwq), GFP_KERNEL);
 107         if (!hwq)
 108                 return -ENOMEM;
 109
 110         err = mt76_queue_alloc(dev, hwq, idx, n_desc, 0, MT_TX_RING_BASE);
 111         if (err < 0)
 112                 return err;
 113
 114         INIT_LIST_HEAD(&q->swq);
 115         q->q = hwq;
 116
 117         mt76x02_irq_enable(dev, MT_INT_TX_DONE(idx));
 118
 119         return 0;
 120 }
 121
 122 static int
 123 mt76x02_init_rx_queue(struct mt76x02_dev *dev, struct mt76_queue *q,
 124                       int idx, int n_desc, int bufsize)
 125 {
 126         int err;
 127
 128         err = mt76_queue_alloc(dev, q, idx, n_desc, bufsize,
 129                                MT_RX_RING_BASE);
 130         if (err < 0)
 131                 return err;
 132
 133         mt76x02_irq_enable(dev, MT_INT_RX_DONE(idx));
 134
 135         return 0;
 136 }
 137
 138 static void mt76x02_process_tx_status_fifo(struct mt76x02_dev *dev)
 139 {
 140         struct mt76x02_tx_status stat;
 141         u8 update = 1;
 142
 143         while (kfifo_get(&dev->txstatus_fifo, &stat))
 144                 mt76x02_send_tx_status(dev, &stat, &update);
 145 }
 146
 147 static void mt76x02_tx_tasklet(unsigned long data)
 148 {
 149         struct mt76x02_dev *dev = (struct mt76x02_dev *)data;
 150
 151         mt76x02_mac_poll_tx_status(dev, false);
 152         mt76x02_process_tx_status_fifo(dev);
 153
 154         mt76_txq_schedule_all(&dev->mt76);
 155 }
 156
 157 static int mt76x02_poll_tx(struct napi_struct *napi, int budget)
 158 {
 159         struct mt76x02_dev *dev = container_of(napi, struct mt76x02_dev,
 160                                                mt76.tx_napi);
 161         int i;
 162
 163         mt76x02_mac_poll_tx_status(dev, false);
 164
 165         for (i = MT_TXQ_MCU; i >= 0; i--)
 166                 mt76_queue_tx_cleanup(dev, i, false);
 167
 168         if (napi_complete_done(napi, 0))
 169                 mt76x02_irq_enable(dev, MT_INT_TX_DONE_ALL);
 170
 171         for (i = MT_TXQ_MCU; i >= 0; i--)
 172                 mt76_queue_tx_cleanup(dev, i, false);
 173
 174         tasklet_schedule(&dev->mt76.tx_tasklet);
 175
 176         return 0;
 177 }
 178
 179 int mt76x02_dma_init(struct mt76x02_dev *dev)
 180 {
 181         struct mt76_txwi_cache __maybe_unused *t;
 182         int i, ret, fifo_size;
 183         struct mt76_queue *q;
 184         void *status_fifo;
 185
 186         BUILD_BUG_ON(sizeof(struct mt76x02_rxwi) > MT_RX_HEADROOM);
 187
 188         fifo_size = roundup_pow_of_two(32 * sizeof(struct mt76x02_tx_status));
 189         status_fifo = devm_kzalloc(dev->mt76.dev, fifo_size, GFP_KERNEL);
 190         if (!status_fifo)
 191                 return -ENOMEM;
 192
 193         tasklet_init(&dev->mt76.tx_tasklet, mt76x02_tx_tasklet,
 194                      (unsigned long)dev);
 195         tasklet_init(&dev->mt76.pre_tbtt_tasklet, mt76x02_pre_tbtt_tasklet,
 196                      (unsigned long)dev);
 197
 198         spin_lock_init(&dev->txstatus_fifo_lock);
 199         kfifo_init(&dev->txstatus_fifo, status_fifo, fifo_size);
 200
 201         mt76_dma_attach(&dev->mt76);
 202
 203         mt76_wr(dev, MT_WPDMA_RST_IDX, ~0);
 204
 205         for (i = 0; i < IEEE80211_NUM_ACS; i++) {
 206                 ret = mt76x02_init_tx_queue(dev, &dev->mt76.q_tx[i],
 207                                             mt76_ac_to_hwq(i),
 208                                             MT_TX_RING_SIZE);
 209                 if (ret)
 210                         return ret;
 211         }
 212
 213         ret = mt76x02_init_tx_queue(dev, &dev->mt76.q_tx[MT_TXQ_PSD],
 214                                     MT_TX_HW_QUEUE_MGMT, MT_TX_RING_SIZE);
 215         if (ret)
 216                 return ret;
 217
 218         ret = mt76x02_init_tx_queue(dev, &dev->mt76.q_tx[MT_TXQ_MCU],
 219                                     MT_TX_HW_QUEUE_MCU, MT_MCU_RING_SIZE);
 220         if (ret)
 221                 return ret;
 222
 223         ret = mt76x02_init_rx_queue(dev, &dev->mt76.q_rx[MT_RXQ_MCU], 1,
 224                                     MT_MCU_RING_SIZE, MT_RX_BUF_SIZE);
 225         if (ret)
 226                 return ret;
 227
 228         q = &dev->mt76.q_rx[MT_RXQ_MAIN];
 229         q->buf_offset = MT_RX_HEADROOM - sizeof(struct mt76x02_rxwi);
 230         ret = mt76x02_init_rx_queue(dev, q, 0, MT76X02_RX_RING_SIZE,
 231                                     MT_RX_BUF_SIZE);
 232         if (ret)
 233                 return ret;
 234
 235         ret = mt76_init_queues(dev);
 236         if (ret)
 237                 return ret;
 238
 239         netif_tx_napi_add(&dev->mt76.napi_dev, &dev->mt76.tx_napi,
 240                           mt76x02_poll_tx, NAPI_POLL_WEIGHT);
 241         napi_enable(&dev->mt76.tx_napi);
 242
 243         return 0;
 244 }
 245 EXPORT_SYMBOL_GPL(mt76x02_dma_init);
 246
 247 void mt76x02_rx_poll_complete(struct mt76_dev *mdev, enum mt76_rxq_id q)
 248 {
 249         struct mt76x02_dev *dev;
 250
 251         dev = container_of(mdev, struct mt76x02_dev, mt76);
 252         mt76x02_irq_enable(dev, MT_INT_RX_DONE(q));
 253 }
 254 EXPORT_SYMBOL_GPL(mt76x02_rx_poll_complete);
 255
 256 irqreturn_t mt76x02_irq_handler(int irq, void *dev_instance)
 257 {
 258         struct mt76x02_dev *dev = dev_instance;
 259         u32 intr;
 260
 261         intr = mt76_rr(dev, MT_INT_SOURCE_CSR);
 262         mt76_wr(dev, MT_INT_SOURCE_CSR, intr);
 263
 264         if (!test_bit(MT76_STATE_INITIALIZED, &dev->mt76.state))
 265                 return IRQ_NONE;
 266
 267         trace_dev_irq(dev, intr, dev->mt76.mmio.irqmask);
 268
 269         intr &= dev->mt76.mmio.irqmask;
 270
 271         if (intr & MT_INT_RX_DONE(0)) {
 272                 mt76x02_irq_disable(dev, MT_INT_RX_DONE(0));
 273                 napi_schedule(&dev->mt76.napi[0]);
 274         }
 275
 276         if (intr & MT_INT_RX_DONE(1)) {
 277                 mt76x02_irq_disable(dev, MT_INT_RX_DONE(1));
 278                 napi_schedule(&dev->mt76.napi[1]);
 279         }
 280
 281         if (intr & MT_INT_PRE_TBTT)
 282                 tasklet_schedule(&dev->mt76.pre_tbtt_tasklet);
 283
 284         /* send buffered multicast frames now */
 285         if (intr & MT_INT_TBTT) {
 286                 if (dev->mt76.csa_complete)
 287                         mt76_csa_finish(&dev->mt76);
 288                 else
 289                         mt76_queue_kick(dev, dev->mt76.q_tx[MT_TXQ_PSD].q);
 290         }
 291
 292         if (intr & MT_INT_TX_STAT)
 293                 mt76x02_mac_poll_tx_status(dev, true);
 294
 295         if (intr & (MT_INT_TX_STAT | MT_INT_TX_DONE_ALL)) {
 296                 mt76x02_irq_disable(dev, MT_INT_TX_DONE_ALL);
 297                 napi_schedule(&dev->mt76.tx_napi);
 298         }
 299
 300         if (intr & MT_INT_GPTIMER) {
 301                 mt76x02_irq_disable(dev, MT_INT_GPTIMER);
 302                 tasklet_schedule(&dev->dfs_pd.dfs_tasklet);
 303         }
 304
 305         return IRQ_HANDLED;
 306 }
 307 EXPORT_SYMBOL_GPL(mt76x02_irq_handler);
 308
 309 static void mt76x02_dma_enable(struct mt76x02_dev *dev)
 310 {
 311         u32 val;
 312
 313         mt76_wr(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_TX);
 314         mt76x02_wait_for_wpdma(&dev->mt76, 1000);
 315         usleep_range(50, 100);
 316
 317         val = FIELD_PREP(MT_WPDMA_GLO_CFG_DMA_BURST_SIZE, 3) |
 318               MT_WPDMA_GLO_CFG_TX_DMA_EN |
 319               MT_WPDMA_GLO_CFG_RX_DMA_EN;
 320         mt76_set(dev, MT_WPDMA_GLO_CFG, val);
 321         mt76_clear(dev, MT_WPDMA_GLO_CFG,
 322                    MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE);
 323 }
 324
 325 void mt76x02_dma_cleanup(struct mt76x02_dev *dev)
 326 {
 327         tasklet_kill(&dev->mt76.tx_tasklet);
 328         mt76_dma_cleanup(&dev->mt76);
 329 }
 330 EXPORT_SYMBOL_GPL(mt76x02_dma_cleanup);
 331
 332 void mt76x02_dma_disable(struct mt76x02_dev *dev)
 333 {
 334         u32 val = mt76_rr(dev, MT_WPDMA_GLO_CFG);
 335
 336         val &= MT_WPDMA_GLO_CFG_DMA_BURST_SIZE |
 337                MT_WPDMA_GLO_CFG_BIG_ENDIAN |
 338                MT_WPDMA_GLO_CFG_HDR_SEG_LEN;
 339         val |= MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE;
 340         mt76_wr(dev, MT_WPDMA_GLO_CFG, val);
 341 }
 342 EXPORT_SYMBOL_GPL(mt76x02_dma_disable);
 343
 344 void mt76x02_mac_start(struct mt76x02_dev *dev)
 345 {
 346         mt76x02_mac_reset_counters(dev);
 347         mt76x02_dma_enable(dev);
 348         mt76_wr(dev, MT_RX_FILTR_CFG, dev->mt76.rxfilter);
 349         mt76_wr(dev, MT_MAC_SYS_CTRL,
 350                 MT_MAC_SYS_CTRL_ENABLE_TX |
 351                 MT_MAC_SYS_CTRL_ENABLE_RX);
 352         mt76x02_irq_enable(dev,
 353                            MT_INT_RX_DONE_ALL | MT_INT_TX_DONE_ALL |
 354                            MT_INT_TX_STAT);
 355 }
 356 EXPORT_SYMBOL_GPL(mt76x02_mac_start);
 357
 358 static bool mt76x02_tx_hang(struct mt76x02_dev *dev)
 359 {
 360         u32 dma_idx, prev_dma_idx;
 361         struct mt76_queue *q;
 362         int i;
 363
 364         for (i = 0; i < 4; i++) {
 365                 q = dev->mt76.q_tx[i].q;
 366
 367                 if (!q->queued)
 368                         continue;
 369
 370                 prev_dma_idx = dev->mt76.tx_dma_idx[i];
 371                 dma_idx = readl(&q->regs->dma_idx);
 372                 dev->mt76.tx_dma_idx[i] = dma_idx;
 373
 374                 if (prev_dma_idx == dma_idx)
 375                         break;
 376         }
 377
 378         return i < 4;
 379 }
 380
 381 static void mt76x02_key_sync(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
 382                              struct ieee80211_sta *sta,
 383                              struct ieee80211_key_conf *key, void *data)
 384 {
 385         struct mt76x02_dev *dev = hw->priv;
 386         struct mt76_wcid *wcid;
 387
 388         if (!sta)
 389                 return;
 390
 391         wcid = (struct mt76_wcid *)sta->drv_priv;
 392
 393         if (wcid->hw_key_idx != key->keyidx || wcid->sw_iv)
 394                 return;
 395
 396         mt76x02_mac_wcid_sync_pn(dev, wcid->idx, key);
 397 }
 398
 399 static void mt76x02_reset_state(struct mt76x02_dev *dev)
 400 {
 401         int i;
 402
 403         lockdep_assert_held(&dev->mt76.mutex);
 404
 405         clear_bit(MT76_STATE_RUNNING, &dev->mt76.state);
 406
 407         rcu_read_lock();
 408         ieee80211_iter_keys_rcu(dev->mt76.hw, NULL, mt76x02_key_sync, NULL);
 409         rcu_read_unlock();
 410
 411         for (i = 0; i < ARRAY_SIZE(dev->mt76.wcid); i++) {
 412                 struct ieee80211_sta *sta;
 413                 struct ieee80211_vif *vif;
 414                 struct mt76x02_sta *msta;
 415                 struct mt76_wcid *wcid;
 416                 void *priv;
 417
 418                 wcid = rcu_dereference_protected(dev->mt76.wcid[i],
 419                                         lockdep_is_held(&dev->mt76.mutex));
 420                 if (!wcid)
 421                         continue;
 422
 423                 priv = msta = container_of(wcid, struct mt76x02_sta, wcid);
 424                 sta = container_of(priv, struct ieee80211_sta, drv_priv);
 425
 426                 priv = msta->vif;
 427                 vif = container_of(priv, struct ieee80211_vif, drv_priv);
 428
 429                 __mt76_sta_remove(&dev->mt76, vif, sta);
 430                 memset(msta, 0, sizeof(*msta));
 431         }
 432
 433         dev->vif_mask = 0;
 434         dev->mt76.beacon_mask = 0;
 435 }
 436
 437 static void mt76x02_watchdog_reset(struct mt76x02_dev *dev)
 438 {
 439         u32 mask = dev->mt76.mmio.irqmask;
 440         bool restart = dev->mt76.mcu_ops->mcu_restart;
 441         int i;
 442
 443         ieee80211_stop_queues(dev->mt76.hw);
 444         set_bit(MT76_RESET, &dev->mt76.state);
 445
 446         tasklet_disable(&dev->mt76.pre_tbtt_tasklet);
 447         tasklet_disable(&dev->mt76.tx_tasklet);
 448         napi_disable(&dev->mt76.tx_napi);
 449
 450         for (i = 0; i < ARRAY_SIZE(dev->mt76.napi); i++)
 451                 napi_disable(&dev->mt76.napi[i]);
 452
 453         mutex_lock(&dev->mt76.mutex);
 454
 455         if (restart)
 456                 mt76x02_reset_state(dev);
 457
 458         if (dev->mt76.beacon_mask)
 459                 mt76_clear(dev, MT_BEACON_TIME_CFG,
 460                            MT_BEACON_TIME_CFG_BEACON_TX |
 461                            MT_BEACON_TIME_CFG_TBTT_EN);
 462
 463         mt76x02_irq_disable(dev, mask);
 464
 465         /* perform device reset */
 466         mt76_clear(dev, MT_TXOP_CTRL_CFG, MT_TXOP_ED_CCA_EN);
 467         mt76_wr(dev, MT_MAC_SYS_CTRL, 0);
 468         mt76_clear(dev, MT_WPDMA_GLO_CFG,
 469                    MT_WPDMA_GLO_CFG_TX_DMA_EN | MT_WPDMA_GLO_CFG_RX_DMA_EN);
 470         usleep_range(5000, 10000);
 471         mt76_wr(dev, MT_INT_SOURCE_CSR, 0xffffffff);
 472
 473         /* let fw reset DMA */
 474         mt76_set(dev, 0x734, 0x3);
 475
 476         if (restart)
 477                 mt76_mcu_restart(dev);
 478
 479         for (i = 0; i < ARRAY_SIZE(dev->mt76.q_tx); i++)
 480                 mt76_queue_tx_cleanup(dev, i, true);
 481
 482         for (i = 0; i < ARRAY_SIZE(dev->mt76.q_rx); i++)
 483                 mt76_queue_rx_reset(dev, i);
 484
 485         mt76x02_mac_start(dev);
 486
 487         if (dev->ed_monitor)
 488                 mt76_set(dev, MT_TXOP_CTRL_CFG, MT_TXOP_ED_CCA_EN);
 489
 490         if (dev->mt76.beacon_mask && !restart)
 491                 mt76_set(dev, MT_BEACON_TIME_CFG,
 492                          MT_BEACON_TIME_CFG_BEACON_TX |
 493                          MT_BEACON_TIME_CFG_TBTT_EN);
 494
 495         mt76x02_irq_enable(dev, mask);
 496
 497         mutex_unlock(&dev->mt76.mutex);
 498
 499         clear_bit(MT76_RESET, &dev->mt76.state);
 500
 501         tasklet_enable(&dev->mt76.tx_tasklet);
 502         napi_enable(&dev->mt76.tx_napi);
 503         napi_schedule(&dev->mt76.tx_napi);
 504
 505         tasklet_enable(&dev->mt76.pre_tbtt_tasklet);
 506
 507         for (i = 0; i < ARRAY_SIZE(dev->mt76.napi); i++) {
 508                 napi_enable(&dev->mt76.napi[i]);
 509                 napi_schedule(&dev->mt76.napi[i]);
 510         }
 511
 512         if (restart) {
 513                 mt76x02_mcu_function_select(dev, Q_SELECT, 1);
 514                 ieee80211_restart_hw(dev->mt76.hw);
 515         } else {
 516                 ieee80211_wake_queues(dev->mt76.hw);
 517                 mt76_txq_schedule_all(&dev->mt76);
 518         }
 519 }
 520
 521 static void mt76x02_check_tx_hang(struct mt76x02_dev *dev)
 522 {
 523         if (mt76x02_tx_hang(dev)) {
 524                 if (++dev->tx_hang_check >= MT_TX_HANG_TH)
 525                         goto restart;
 526         } else {
 527                 dev->tx_hang_check = 0;
 528         }
 529
 530         if (dev->mcu_timeout)
 531                 goto restart;
 532
 533         return;
 534
 535 restart:
 536         mt76x02_watchdog_reset(dev);
 537
 538         mutex_lock(&dev->mt76.mmio.mcu.mutex);
 539         dev->mcu_timeout = 0;
 540         mutex_unlock(&dev->mt76.mmio.mcu.mutex);
 541
 542         dev->tx_hang_reset++;
 543         dev->tx_hang_check = 0;
 544         memset(dev->mt76.tx_dma_idx, 0xff,
 545                sizeof(dev->mt76.tx_dma_idx));
 546 }
 547
 548 void mt76x02_wdt_work(struct work_struct *work)
 549 {
 550         struct mt76x02_dev *dev = container_of(work, struct mt76x02_dev,
 551                                                wdt_work.work);
 552
 553         mt76x02_check_tx_hang(dev);
 554
 555         ieee80211_queue_delayed_work(mt76_hw(dev), &dev->wdt_work,
 556                                      MT_WATCHDOG_TIME);
 557 }