| blob | 7e64aee2a172e237243f9df774a2490b6678f30a |
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
4 <http://rt2x00.serialmonkey.com>
6 */
8 /*
9 Module: rt2500pci
10 Abstract: Data structures and registers for the rt2500pci module.
11 Supported chipsets: RT2560.
12 */
14 #ifndef RT2500PCI_H
15 #define RT2500PCI_H
17 /*
18 * RF chip defines.
19 */
20 #define RF2522 0x0000
21 #define RF2523 0x0001
22 #define RF2524 0x0002
23 #define RF2525 0x0003
24 #define RF2525E 0x0004
25 #define RF5222 0x0010
27 /*
28 * RT2560 version
29 */
30 #define RT2560_VERSION_B 2
31 #define RT2560_VERSION_C 3
32 #define RT2560_VERSION_D 4
34 /*
35 * Signal information.
36 * Default offset is required for RSSI <-> dBm conversion.
37 */
38 #define DEFAULT_RSSI_OFFSET 121
40 /*
41 * Register layout information.
42 */
43 #define CSR_REG_BASE 0x0000
44 #define CSR_REG_SIZE 0x0174
45 #define EEPROM_BASE 0x0000
46 #define EEPROM_SIZE 0x0200
47 #define BBP_BASE 0x0000
48 #define BBP_SIZE 0x0040
49 #define RF_BASE 0x0004
50 #define RF_SIZE 0x0010
52 /*
53 * Number of TX queues.
54 */
55 #define NUM_TX_QUEUES 2
57 /*
58 * Control/Status Registers(CSR).
59 * Some values are set in TU, whereas 1 TU == 1024 us.
60 */
62 /*
63 * CSR0: ASIC revision number.
64 */
65 #define CSR0 0x0000
66 #define CSR0_REVISION FIELD32(0x0000ffff)
68 /*
69 * CSR1: System control register.
70 * SOFT_RESET: Software reset, 1: reset, 0: normal.
71 * BBP_RESET: Hardware reset, 1: reset, 0, release.
72 * HOST_READY: Host ready after initialization.
73 */
74 #define CSR1 0x0004
75 #define CSR1_SOFT_RESET FIELD32(0x00000001)
76 #define CSR1_BBP_RESET FIELD32(0x00000002)
77 #define CSR1_HOST_READY FIELD32(0x00000004)
79 /*
80 * CSR2: System admin status register (invalid).
81 */
82 #define CSR2 0x0008
84 /*
85 * CSR3: STA MAC address register 0.
86 */
87 #define CSR3 0x000c
88 #define CSR3_BYTE0 FIELD32(0x000000ff)
89 #define CSR3_BYTE1 FIELD32(0x0000ff00)
90 #define CSR3_BYTE2 FIELD32(0x00ff0000)
91 #define CSR3_BYTE3 FIELD32(0xff000000)
93 /*
94 * CSR4: STA MAC address register 1.
95 */
96 #define CSR4 0x0010
97 #define CSR4_BYTE4 FIELD32(0x000000ff)
98 #define CSR4_BYTE5 FIELD32(0x0000ff00)
100 /*
101 * CSR5: BSSID register 0.
102 */
103 #define CSR5 0x0014
104 #define CSR5_BYTE0 FIELD32(0x000000ff)
105 #define CSR5_BYTE1 FIELD32(0x0000ff00)
106 #define CSR5_BYTE2 FIELD32(0x00ff0000)
107 #define CSR5_BYTE3 FIELD32(0xff000000)
109 /*
110 * CSR6: BSSID register 1.
111 */
112 #define CSR6 0x0018
113 #define CSR6_BYTE4 FIELD32(0x000000ff)
114 #define CSR6_BYTE5 FIELD32(0x0000ff00)
116 /*
117 * CSR7: Interrupt source register.
118 * Write 1 to clear.
119 * TBCN_EXPIRE: Beacon timer expired interrupt.
120 * TWAKE_EXPIRE: Wakeup timer expired interrupt.
121 * TATIMW_EXPIRE: Timer of atim window expired interrupt.
122 * TXDONE_TXRING: Tx ring transmit done interrupt.
123 * TXDONE_ATIMRING: Atim ring transmit done interrupt.
124 * TXDONE_PRIORING: Priority ring transmit done interrupt.
125 * RXDONE: Receive done interrupt.
126 * DECRYPTION_DONE: Decryption done interrupt.
127 * ENCRYPTION_DONE: Encryption done interrupt.
128 * UART1_TX_TRESHOLD: UART1 TX reaches threshold.
129 * UART1_RX_TRESHOLD: UART1 RX reaches threshold.
130 * UART1_IDLE_TRESHOLD: UART1 IDLE over threshold.
131 * UART1_TX_BUFF_ERROR: UART1 TX buffer error.
132 * UART1_RX_BUFF_ERROR: UART1 RX buffer error.
133 * UART2_TX_TRESHOLD: UART2 TX reaches threshold.
134 * UART2_RX_TRESHOLD: UART2 RX reaches threshold.
135 * UART2_IDLE_TRESHOLD: UART2 IDLE over threshold.
136 * UART2_TX_BUFF_ERROR: UART2 TX buffer error.
137 * UART2_RX_BUFF_ERROR: UART2 RX buffer error.
138 * TIMER_CSR3_EXPIRE: TIMECSR3 timer expired (802.1H quiet period).
140 */
141 #define CSR7 0x001c
142 #define CSR7_TBCN_EXPIRE FIELD32(0x00000001)
143 #define CSR7_TWAKE_EXPIRE FIELD32(0x00000002)
144 #define CSR7_TATIMW_EXPIRE FIELD32(0x00000004)
145 #define CSR7_TXDONE_TXRING FIELD32(0x00000008)
146 #define CSR7_TXDONE_ATIMRING FIELD32(0x00000010)
147 #define CSR7_TXDONE_PRIORING FIELD32(0x00000020)
148 #define CSR7_RXDONE FIELD32(0x00000040)
149 #define CSR7_DECRYPTION_DONE FIELD32(0x00000080)
150 #define CSR7_ENCRYPTION_DONE FIELD32(0x00000100)
151 #define CSR7_UART1_TX_TRESHOLD FIELD32(0x00000200)
152 #define CSR7_UART1_RX_TRESHOLD FIELD32(0x00000400)
153 #define CSR7_UART1_IDLE_TRESHOLD FIELD32(0x00000800)
154 #define CSR7_UART1_TX_BUFF_ERROR FIELD32(0x00001000)
155 #define CSR7_UART1_RX_BUFF_ERROR FIELD32(0x00002000)
156 #define CSR7_UART2_TX_TRESHOLD FIELD32(0x00004000)
157 #define CSR7_UART2_RX_TRESHOLD FIELD32(0x00008000)
158 #define CSR7_UART2_IDLE_TRESHOLD FIELD32(0x00010000)
159 #define CSR7_UART2_TX_BUFF_ERROR FIELD32(0x00020000)
160 #define CSR7_UART2_RX_BUFF_ERROR FIELD32(0x00040000)
161 #define CSR7_TIMER_CSR3_EXPIRE FIELD32(0x00080000)
163 /*
164 * CSR8: Interrupt mask register.
165 * Write 1 to mask interrupt.
166 * TBCN_EXPIRE: Beacon timer expired interrupt.
167 * TWAKE_EXPIRE: Wakeup timer expired interrupt.
168 * TATIMW_EXPIRE: Timer of atim window expired interrupt.
169 * TXDONE_TXRING: Tx ring transmit done interrupt.
170 * TXDONE_ATIMRING: Atim ring transmit done interrupt.
171 * TXDONE_PRIORING: Priority ring transmit done interrupt.
172 * RXDONE: Receive done interrupt.
173 * DECRYPTION_DONE: Decryption done interrupt.
174 * ENCRYPTION_DONE: Encryption done interrupt.
175 * UART1_TX_TRESHOLD: UART1 TX reaches threshold.
176 * UART1_RX_TRESHOLD: UART1 RX reaches threshold.
177 * UART1_IDLE_TRESHOLD: UART1 IDLE over threshold.
178 * UART1_TX_BUFF_ERROR: UART1 TX buffer error.
179 * UART1_RX_BUFF_ERROR: UART1 RX buffer error.
180 * UART2_TX_TRESHOLD: UART2 TX reaches threshold.
181 * UART2_RX_TRESHOLD: UART2 RX reaches threshold.
182 * UART2_IDLE_TRESHOLD: UART2 IDLE over threshold.
183 * UART2_TX_BUFF_ERROR: UART2 TX buffer error.
184 * UART2_RX_BUFF_ERROR: UART2 RX buffer error.
185 * TIMER_CSR3_EXPIRE: TIMECSR3 timer expired (802.1H quiet period).
186 */
187 #define CSR8 0x0020
188 #define CSR8_TBCN_EXPIRE FIELD32(0x00000001)
189 #define CSR8_TWAKE_EXPIRE FIELD32(0x00000002)
190 #define CSR8_TATIMW_EXPIRE FIELD32(0x00000004)
191 #define CSR8_TXDONE_TXRING FIELD32(0x00000008)
192 #define CSR8_TXDONE_ATIMRING FIELD32(0x00000010)
193 #define CSR8_TXDONE_PRIORING FIELD32(0x00000020)
194 #define CSR8_RXDONE FIELD32(0x00000040)
195 #define CSR8_DECRYPTION_DONE FIELD32(0x00000080)
196 #define CSR8_ENCRYPTION_DONE FIELD32(0x00000100)
197 #define CSR8_UART1_TX_TRESHOLD FIELD32(0x00000200)
198 #define CSR8_UART1_RX_TRESHOLD FIELD32(0x00000400)
199 #define CSR8_UART1_IDLE_TRESHOLD FIELD32(0x00000800)
200 #define CSR8_UART1_TX_BUFF_ERROR FIELD32(0x00001000)
201 #define CSR8_UART1_RX_BUFF_ERROR FIELD32(0x00002000)
202 #define CSR8_UART2_TX_TRESHOLD FIELD32(0x00004000)
203 #define CSR8_UART2_RX_TRESHOLD FIELD32(0x00008000)
204 #define CSR8_UART2_IDLE_TRESHOLD FIELD32(0x00010000)
205 #define CSR8_UART2_TX_BUFF_ERROR FIELD32(0x00020000)
206 #define CSR8_UART2_RX_BUFF_ERROR FIELD32(0x00040000)
207 #define CSR8_TIMER_CSR3_EXPIRE FIELD32(0x00080000)
209 /*
210 * CSR9: Maximum frame length register.
211 * MAX_FRAME_UNIT: Maximum frame length in 128b unit, default: 12.
212 */
213 #define CSR9 0x0024
214 #define CSR9_MAX_FRAME_UNIT FIELD32(0x00000f80)
216 /*
217 * SECCSR0: WEP control register.
218 * KICK_DECRYPT: Kick decryption engine, self-clear.
219 * ONE_SHOT: 0: ring mode, 1: One shot only mode.
220 * DESC_ADDRESS: Descriptor physical address of frame.
221 */
222 #define SECCSR0 0x0028
223 #define SECCSR0_KICK_DECRYPT FIELD32(0x00000001)
224 #define SECCSR0_ONE_SHOT FIELD32(0x00000002)
225 #define SECCSR0_DESC_ADDRESS FIELD32(0xfffffffc)
227 /*
228 * CSR11: Back-off control register.
229 * CWMIN: CWmin. Default cwmin is 31 (2^5 - 1).
230 * CWMAX: CWmax. Default cwmax is 1023 (2^10 - 1).
231 * SLOT_TIME: Slot time, default is 20us for 802.11b
232 * CW_SELECT: CWmin/CWmax selection, 1: Register, 0: TXD.
233 * LONG_RETRY: Long retry count.
234 * SHORT_RETRY: Short retry count.
235 */
236 #define CSR11 0x002c
237 #define CSR11_CWMIN FIELD32(0x0000000f)
238 #define CSR11_CWMAX FIELD32(0x000000f0)
239 #define CSR11_SLOT_TIME FIELD32(0x00001f00)
240 #define CSR11_CW_SELECT FIELD32(0x00002000)
241 #define CSR11_LONG_RETRY FIELD32(0x00ff0000)
242 #define CSR11_SHORT_RETRY FIELD32(0xff000000)
244 /*
245 * CSR12: Synchronization configuration register 0.
246 * All units in 1/16 TU.
247 * BEACON_INTERVAL: Beacon interval, default is 100 TU.
248 * CFP_MAX_DURATION: Cfp maximum duration, default is 100 TU.
249 */
250 #define CSR12 0x0030
251 #define CSR12_BEACON_INTERVAL FIELD32(0x0000ffff)
252 #define CSR12_CFP_MAX_DURATION FIELD32(0xffff0000)
254 /*
255 * CSR13: Synchronization configuration register 1.
256 * All units in 1/16 TU.
257 * ATIMW_DURATION: Atim window duration.
258 * CFP_PERIOD: Cfp period, default is 0 TU.
259 */
260 #define CSR13 0x0034
261 #define CSR13_ATIMW_DURATION FIELD32(0x0000ffff)
262 #define CSR13_CFP_PERIOD FIELD32(0x00ff0000)
264 /*
265 * CSR14: Synchronization control register.
266 * TSF_COUNT: Enable tsf auto counting.
267 * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode.
268 * TBCN: Enable tbcn with reload value.
269 * TCFP: Enable tcfp & cfp / cp switching.
270 * TATIMW: Enable tatimw & atim window switching.
271 * BEACON_GEN: Enable beacon generator.
272 * CFP_COUNT_PRELOAD: Cfp count preload value.
273 * TBCM_PRELOAD: Tbcn preload value in units of 64us.
274 */
275 #define CSR14 0x0038
276 #define CSR14_TSF_COUNT FIELD32(0x00000001)
277 #define CSR14_TSF_SYNC FIELD32(0x00000006)
278 #define CSR14_TBCN FIELD32(0x00000008)
279 #define CSR14_TCFP FIELD32(0x00000010)
280 #define CSR14_TATIMW FIELD32(0x00000020)
281 #define CSR14_BEACON_GEN FIELD32(0x00000040)
282 #define CSR14_CFP_COUNT_PRELOAD FIELD32(0x0000ff00)
283 #define CSR14_TBCM_PRELOAD FIELD32(0xffff0000)
285 /*
286 * CSR15: Synchronization status register.
287 * CFP: ASIC is in contention-free period.
288 * ATIMW: ASIC is in ATIM window.
289 * BEACON_SENT: Beacon is send.
290 */
291 #define CSR15 0x003c
292 #define CSR15_CFP FIELD32(0x00000001)
293 #define CSR15_ATIMW FIELD32(0x00000002)
294 #define CSR15_BEACON_SENT FIELD32(0x00000004)
296 /*
297 * CSR16: TSF timer register 0.
298 */
299 #define CSR16 0x0040
300 #define CSR16_LOW_TSFTIMER FIELD32(0xffffffff)
302 /*
303 * CSR17: TSF timer register 1.
304 */
305 #define CSR17 0x0044
306 #define CSR17_HIGH_TSFTIMER FIELD32(0xffffffff)
308 /*
309 * CSR18: IFS timer register 0.
310 * SIFS: Sifs, default is 10 us.
311 * PIFS: Pifs, default is 30 us.
312 */
313 #define CSR18 0x0048
314 #define CSR18_SIFS FIELD32(0x000001ff)
315 #define CSR18_PIFS FIELD32(0x001f0000)
317 /*
318 * CSR19: IFS timer register 1.
319 * DIFS: Difs, default is 50 us.
320 * EIFS: Eifs, default is 364 us.
321 */
322 #define CSR19 0x004c
323 #define CSR19_DIFS FIELD32(0x0000ffff)
324 #define CSR19_EIFS FIELD32(0xffff0000)
326 /*
327 * CSR20: Wakeup timer register.
328 * DELAY_AFTER_TBCN: Delay after tbcn expired in units of 1/16 TU.
329 * TBCN_BEFORE_WAKEUP: Number of beacon before wakeup.
330 * AUTOWAKE: Enable auto wakeup / sleep mechanism.
331 */
332 #define CSR20 0x0050
333 #define CSR20_DELAY_AFTER_TBCN FIELD32(0x0000ffff)
334 #define CSR20_TBCN_BEFORE_WAKEUP FIELD32(0x00ff0000)
335 #define CSR20_AUTOWAKE FIELD32(0x01000000)
337 /*
338 * CSR21: EEPROM control register.
339 * RELOAD: Write 1 to reload eeprom content.
340 * TYPE_93C46: 1: 93c46, 0:93c66.
341 */
342 #define CSR21 0x0054
343 #define CSR21_RELOAD FIELD32(0x00000001)
344 #define CSR21_EEPROM_DATA_CLOCK FIELD32(0x00000002)
345 #define CSR21_EEPROM_CHIP_SELECT FIELD32(0x00000004)
346 #define CSR21_EEPROM_DATA_IN FIELD32(0x00000008)
347 #define CSR21_EEPROM_DATA_OUT FIELD32(0x00000010)
348 #define CSR21_TYPE_93C46 FIELD32(0x00000020)
350 /*
351 * CSR22: CFP control register.
352 * CFP_DURATION_REMAIN: Cfp duration remain, in units of TU.
353 * RELOAD_CFP_DURATION: Write 1 to reload cfp duration remain.
354 */
355 #define CSR22 0x0058
356 #define CSR22_CFP_DURATION_REMAIN FIELD32(0x0000ffff)
357 #define CSR22_RELOAD_CFP_DURATION FIELD32(0x00010000)
359 /*
360 * Transmit related CSRs.
361 * Some values are set in TU, whereas 1 TU == 1024 us.
362 */
364 /*
365 * TXCSR0: TX Control Register.
366 * KICK_TX: Kick tx ring.
367 * KICK_ATIM: Kick atim ring.
368 * KICK_PRIO: Kick priority ring.
369 * ABORT: Abort all transmit related ring operation.
370 */
371 #define TXCSR0 0x0060
372 #define TXCSR0_KICK_TX FIELD32(0x00000001)
373 #define TXCSR0_KICK_ATIM FIELD32(0x00000002)
374 #define TXCSR0_KICK_PRIO FIELD32(0x00000004)
375 #define TXCSR0_ABORT FIELD32(0x00000008)
377 /*
378 * TXCSR1: TX Configuration Register.
379 * ACK_TIMEOUT: Ack timeout, default = sifs + 2*slottime + acktime @ 1mbps.
380 * ACK_CONSUME_TIME: Ack consume time, default = sifs + acktime @ 1mbps.
381 * TSF_OFFSET: Insert tsf offset.
382 * AUTORESPONDER: Enable auto responder which include ack & cts.
383 */
384 #define TXCSR1 0x0064
385 #define TXCSR1_ACK_TIMEOUT FIELD32(0x000001ff)
386 #define TXCSR1_ACK_CONSUME_TIME FIELD32(0x0003fe00)
387 #define TXCSR1_TSF_OFFSET FIELD32(0x00fc0000)
388 #define TXCSR1_AUTORESPONDER FIELD32(0x01000000)
390 /*
391 * TXCSR2: Tx descriptor configuration register.
392 * TXD_SIZE: Tx descriptor size, default is 48.
393 * NUM_TXD: Number of tx entries in ring.
394 * NUM_ATIM: Number of atim entries in ring.
395 * NUM_PRIO: Number of priority entries in ring.
396 */
397 #define TXCSR2 0x0068
398 #define TXCSR2_TXD_SIZE FIELD32(0x000000ff)
399 #define TXCSR2_NUM_TXD FIELD32(0x0000ff00)
400 #define TXCSR2_NUM_ATIM FIELD32(0x00ff0000)
401 #define TXCSR2_NUM_PRIO FIELD32(0xff000000)
403 /*
404 * TXCSR3: TX Ring Base address register.
405 */
406 #define TXCSR3 0x006c
407 #define TXCSR3_TX_RING_REGISTER FIELD32(0xffffffff)
409 /*
410 * TXCSR4: TX Atim Ring Base address register.
411 */
412 #define TXCSR4 0x0070
413 #define TXCSR4_ATIM_RING_REGISTER FIELD32(0xffffffff)
415 /*
416 * TXCSR5: TX Prio Ring Base address register.
417 */
418 #define TXCSR5 0x0074
419 #define TXCSR5_PRIO_RING_REGISTER FIELD32(0xffffffff)
421 /*
422 * TXCSR6: Beacon Base address register.
423 */
424 #define TXCSR6 0x0078
425 #define TXCSR6_BEACON_RING_REGISTER FIELD32(0xffffffff)
427 /*
428 * TXCSR7: Auto responder control register.
429 * AR_POWERMANAGEMENT: Auto responder power management bit.
430 */
431 #define TXCSR7 0x007c
432 #define TXCSR7_AR_POWERMANAGEMENT FIELD32(0x00000001)
434 /*
435 * TXCSR8: CCK Tx BBP register.
436 */
437 #define TXCSR8 0x0098
438 #define TXCSR8_BBP_ID0 FIELD32(0x0000007f)
439 #define TXCSR8_BBP_ID0_VALID FIELD32(0x00000080)
440 #define TXCSR8_BBP_ID1 FIELD32(0x00007f00)
441 #define TXCSR8_BBP_ID1_VALID FIELD32(0x00008000)
442 #define TXCSR8_BBP_ID2 FIELD32(0x007f0000)
443 #define TXCSR8_BBP_ID2_VALID FIELD32(0x00800000)
444 #define TXCSR8_BBP_ID3 FIELD32(0x7f000000)
445 #define TXCSR8_BBP_ID3_VALID FIELD32(0x80000000)
447 /*
448 * TXCSR9: OFDM TX BBP registers
449 * OFDM_SIGNAL: BBP rate field address for OFDM.
450 * OFDM_SERVICE: BBP service field address for OFDM.
451 * OFDM_LENGTH_LOW: BBP length low byte address for OFDM.
452 * OFDM_LENGTH_HIGH: BBP length high byte address for OFDM.
453 */
454 #define TXCSR9 0x0094
455 #define TXCSR9_OFDM_RATE FIELD32(0x000000ff)
456 #define TXCSR9_OFDM_SERVICE FIELD32(0x0000ff00)
457 #define TXCSR9_OFDM_LENGTH_LOW FIELD32(0x00ff0000)
458 #define TXCSR9_OFDM_LENGTH_HIGH FIELD32(0xff000000)
460 /*
461 * Receive related CSRs.
462 * Some values are set in TU, whereas 1 TU == 1024 us.
463 */
465 /*
466 * RXCSR0: RX Control Register.
467 * DISABLE_RX: Disable rx engine.
468 * DROP_CRC: Drop crc error.
469 * DROP_PHYSICAL: Drop physical error.
470 * DROP_CONTROL: Drop control frame.
471 * DROP_NOT_TO_ME: Drop not to me unicast frame.
472 * DROP_TODS: Drop frame tods bit is true.
473 * DROP_VERSION_ERROR: Drop version error frame.
474 * PASS_CRC: Pass all packets with crc attached.
475 * PASS_CRC: Pass all packets with crc attached.
476 * PASS_PLCP: Pass all packets with 4 bytes PLCP attached.
477 * DROP_MCAST: Drop multicast frames.
478 * DROP_BCAST: Drop broadcast frames.
479 * ENABLE_QOS: Accept QOS data frame and parse QOS field.
480 */
481 #define RXCSR0 0x0080
482 #define RXCSR0_DISABLE_RX FIELD32(0x00000001)
483 #define RXCSR0_DROP_CRC FIELD32(0x00000002)
484 #define RXCSR0_DROP_PHYSICAL FIELD32(0x00000004)
485 #define RXCSR0_DROP_CONTROL FIELD32(0x00000008)
486 #define RXCSR0_DROP_NOT_TO_ME FIELD32(0x00000010)
487 #define RXCSR0_DROP_TODS FIELD32(0x00000020)
488 #define RXCSR0_DROP_VERSION_ERROR FIELD32(0x00000040)
489 #define RXCSR0_PASS_CRC FIELD32(0x00000080)
490 #define RXCSR0_PASS_PLCP FIELD32(0x00000100)
491 #define RXCSR0_DROP_MCAST FIELD32(0x00000200)
492 #define RXCSR0_DROP_BCAST FIELD32(0x00000400)
493 #define RXCSR0_ENABLE_QOS FIELD32(0x00000800)
495 /*
496 * RXCSR1: RX descriptor configuration register.
497 * RXD_SIZE: Rx descriptor size, default is 32b.
498 * NUM_RXD: Number of rx entries in ring.
499 */
500 #define RXCSR1 0x0084
501 #define RXCSR1_RXD_SIZE FIELD32(0x000000ff)
502 #define RXCSR1_NUM_RXD FIELD32(0x0000ff00)
504 /*
505 * RXCSR2: RX Ring base address register.
506 */
507 #define RXCSR2 0x0088
508 #define RXCSR2_RX_RING_REGISTER FIELD32(0xffffffff)
510 /*
511 * RXCSR3: BBP ID register for Rx operation.
512 * BBP_ID#: BBP register # id.
513 * BBP_ID#_VALID: BBP register # id is valid or not.
514 */
515 #define RXCSR3 0x0090
516 #define RXCSR3_BBP_ID0 FIELD32(0x0000007f)
517 #define RXCSR3_BBP_ID0_VALID FIELD32(0x00000080)
518 #define RXCSR3_BBP_ID1 FIELD32(0x00007f00)
519 #define RXCSR3_BBP_ID1_VALID FIELD32(0x00008000)
520 #define RXCSR3_BBP_ID2 FIELD32(0x007f0000)
521 #define RXCSR3_BBP_ID2_VALID FIELD32(0x00800000)
522 #define RXCSR3_BBP_ID3 FIELD32(0x7f000000)
523 #define RXCSR3_BBP_ID3_VALID FIELD32(0x80000000)
525 /*
526 * ARCSR1: Auto Responder PLCP config register 1.
527 * AR_BBP_DATA#: Auto responder BBP register # data.
528 * AR_BBP_ID#: Auto responder BBP register # Id.
529 */
530 #define ARCSR1 0x009c
531 #define ARCSR1_AR_BBP_DATA2 FIELD32(0x000000ff)
532 #define ARCSR1_AR_BBP_ID2 FIELD32(0x0000ff00)
533 #define ARCSR1_AR_BBP_DATA3 FIELD32(0x00ff0000)
534 #define ARCSR1_AR_BBP_ID3 FIELD32(0xff000000)
536 /*
537 * Miscellaneous Registers.
538 * Some values are set in TU, whereas 1 TU == 1024 us.
540 */
542 /*
543 * PCICSR: PCI control register.
544 * BIG_ENDIAN: 1: big endian, 0: little endian.
545 * RX_TRESHOLD: Rx threshold in dw to start pci access
546 * 0: 16dw (default), 1: 8dw, 2: 4dw, 3: 32dw.
547 * TX_TRESHOLD: Tx threshold in dw to start pci access
548 * 0: 0dw (default), 1: 1dw, 2: 4dw, 3: forward.
549 * BURST_LENTH: Pci burst length 0: 4dw (default, 1: 8dw, 2: 16dw, 3:32dw.
550 * ENABLE_CLK: Enable clk_run, pci clock can't going down to non-operational.
551 * READ_MULTIPLE: Enable memory read multiple.
552 * WRITE_INVALID: Enable memory write & invalid.
553 */
554 #define PCICSR 0x008c
555 #define PCICSR_BIG_ENDIAN FIELD32(0x00000001)
556 #define PCICSR_RX_TRESHOLD FIELD32(0x00000006)
557 #define PCICSR_TX_TRESHOLD FIELD32(0x00000018)
558 #define PCICSR_BURST_LENTH FIELD32(0x00000060)
559 #define PCICSR_ENABLE_CLK FIELD32(0x00000080)
560 #define PCICSR_READ_MULTIPLE FIELD32(0x00000100)
561 #define PCICSR_WRITE_INVALID FIELD32(0x00000200)
563 /*
564 * CNT0: FCS error count.
565 * FCS_ERROR: FCS error count, cleared when read.
566 */
567 #define CNT0 0x00a0
568 #define CNT0_FCS_ERROR FIELD32(0x0000ffff)
570 /*
571 * Statistic Register.
572 * CNT1: PLCP error count.
573 * CNT2: Long error count.
574 */
575 #define TIMECSR2 0x00a8
576 #define CNT1 0x00ac
577 #define CNT2 0x00b0
578 #define TIMECSR3 0x00b4
580 /*
581 * CNT3: CCA false alarm count.
582 */
583 #define CNT3 0x00b8
584 #define CNT3_FALSE_CCA FIELD32(0x0000ffff)
586 /*
587 * Statistic Register.
588 * CNT4: Rx FIFO overflow count.
589 * CNT5: Tx FIFO underrun count.
590 */
591 #define CNT4 0x00bc
592 #define CNT5 0x00c0
594 /*
595 * Baseband Control Register.
596 */
598 /*
599 * PWRCSR0: Power mode configuration register.
600 */
601 #define PWRCSR0 0x00c4
603 /*
604 * Power state transition time registers.
605 */
606 #define PSCSR0 0x00c8
607 #define PSCSR1 0x00cc
608 #define PSCSR2 0x00d0
609 #define PSCSR3 0x00d4
611 /*
612 * PWRCSR1: Manual power control / status register.
613 * Allowed state: 0 deep_sleep, 1: sleep, 2: standby, 3: awake.
614 * SET_STATE: Set state. Write 1 to trigger, self cleared.
615 * BBP_DESIRE_STATE: BBP desired state.
616 * RF_DESIRE_STATE: RF desired state.
617 * BBP_CURR_STATE: BBP current state.
618 * RF_CURR_STATE: RF current state.
619 * PUT_TO_SLEEP: Put to sleep. Write 1 to trigger, self cleared.
620 */
621 #define PWRCSR1 0x00d8
622 #define PWRCSR1_SET_STATE FIELD32(0x00000001)
623 #define PWRCSR1_BBP_DESIRE_STATE FIELD32(0x00000006)
624 #define PWRCSR1_RF_DESIRE_STATE FIELD32(0x00000018)
625 #define PWRCSR1_BBP_CURR_STATE FIELD32(0x00000060)
626 #define PWRCSR1_RF_CURR_STATE FIELD32(0x00000180)
627 #define PWRCSR1_PUT_TO_SLEEP FIELD32(0x00000200)
629 /*
630 * TIMECSR: Timer control register.
631 * US_COUNT: 1 us timer count in units of clock cycles.
632 * US_64_COUNT: 64 us timer count in units of 1 us timer.
633 * BEACON_EXPECT: Beacon expect window.
634 */
635 #define TIMECSR 0x00dc
636 #define TIMECSR_US_COUNT FIELD32(0x000000ff)
637 #define TIMECSR_US_64_COUNT FIELD32(0x0000ff00)
638 #define TIMECSR_BEACON_EXPECT FIELD32(0x00070000)
640 /*
641 * MACCSR0: MAC configuration register 0.
642 */
643 #define MACCSR0 0x00e0
645 /*
646 * MACCSR1: MAC configuration register 1.
647 * KICK_RX: Kick one-shot rx in one-shot rx mode.
648 * ONESHOT_RXMODE: Enable one-shot rx mode for debugging.
649 * BBPRX_RESET_MODE: Ralink bbp rx reset mode.
650 * AUTO_TXBBP: Auto tx logic access bbp control register.
651 * AUTO_RXBBP: Auto rx logic access bbp control register.
652 * LOOPBACK: Loopback mode. 0: normal, 1: internal, 2: external, 3:rsvd.
653 * INTERSIL_IF: Intersil if calibration pin.
654 */
655 #define MACCSR1 0x00e4
656 #define MACCSR1_KICK_RX FIELD32(0x00000001)
657 #define MACCSR1_ONESHOT_RXMODE FIELD32(0x00000002)
658 #define MACCSR1_BBPRX_RESET_MODE FIELD32(0x00000004)
659 #define MACCSR1_AUTO_TXBBP FIELD32(0x00000008)
660 #define MACCSR1_AUTO_RXBBP FIELD32(0x00000010)
661 #define MACCSR1_LOOPBACK FIELD32(0x00000060)
662 #define MACCSR1_INTERSIL_IF FIELD32(0x00000080)
664 /*
665 * RALINKCSR: Ralink Rx auto-reset BBCR.
666 * AR_BBP_DATA#: Auto reset BBP register # data.
667 * AR_BBP_ID#: Auto reset BBP register # id.
668 */
669 #define RALINKCSR 0x00e8
670 #define RALINKCSR_AR_BBP_DATA0 FIELD32(0x000000ff)
671 #define RALINKCSR_AR_BBP_ID0 FIELD32(0x00007f00)
672 #define RALINKCSR_AR_BBP_VALID0 FIELD32(0x00008000)
673 #define RALINKCSR_AR_BBP_DATA1 FIELD32(0x00ff0000)
674 #define RALINKCSR_AR_BBP_ID1 FIELD32(0x7f000000)
675 #define RALINKCSR_AR_BBP_VALID1 FIELD32(0x80000000)
677 /*
678 * BCNCSR: Beacon interval control register.
679 * CHANGE: Write one to change beacon interval.
680 * DELTATIME: The delta time value.
681 * NUM_BEACON: Number of beacon according to mode.
682 * MODE: Please refer to asic specs.
683 * PLUS: Plus or minus delta time value.
684 */
685 #define BCNCSR 0x00ec
686 #define BCNCSR_CHANGE FIELD32(0x00000001)
687 #define BCNCSR_DELTATIME FIELD32(0x0000001e)
688 #define BCNCSR_NUM_BEACON FIELD32(0x00001fe0)
689 #define BCNCSR_MODE FIELD32(0x00006000)
690 #define BCNCSR_PLUS FIELD32(0x00008000)
692 /*
693 * BBP / RF / IF Control Register.
694 */
696 /*
697 * BBPCSR: BBP serial control register.
698 * VALUE: Register value to program into BBP.
699 * REGNUM: Selected BBP register.
700 * BUSY: 1: asic is busy execute BBP programming.
701 * WRITE_CONTROL: 1: write BBP, 0: read BBP.
702 */
703 #define BBPCSR 0x00f0
704 #define BBPCSR_VALUE FIELD32(0x000000ff)
705 #define BBPCSR_REGNUM FIELD32(0x00007f00)
706 #define BBPCSR_BUSY FIELD32(0x00008000)
707 #define BBPCSR_WRITE_CONTROL FIELD32(0x00010000)
709 /*
710 * RFCSR: RF serial control register.
711 * VALUE: Register value + id to program into rf/if.
712 * NUMBER_OF_BITS: Number of bits used in value (i:20, rfmd:22).
713 * IF_SELECT: Chip to program: 0: rf, 1: if.
714 * PLL_LD: Rf pll_ld status.
715 * BUSY: 1: asic is busy execute rf programming.
716 */
717 #define RFCSR 0x00f4
718 #define RFCSR_VALUE FIELD32(0x00ffffff)
719 #define RFCSR_NUMBER_OF_BITS FIELD32(0x1f000000)
720 #define RFCSR_IF_SELECT FIELD32(0x20000000)
721 #define RFCSR_PLL_LD FIELD32(0x40000000)
722 #define RFCSR_BUSY FIELD32(0x80000000)
724 /*
725 * LEDCSR: LED control register.
726 * ON_PERIOD: On period, default 70ms.
727 * OFF_PERIOD: Off period, default 30ms.
728 * LINK: 0: linkoff, 1: linkup.
729 * ACTIVITY: 0: idle, 1: active.
730 * LINK_POLARITY: 0: active low, 1: active high.
731 * ACTIVITY_POLARITY: 0: active low, 1: active high.
732 * LED_DEFAULT: LED state for "enable" 0: ON, 1: OFF.
733 */
734 #define LEDCSR 0x00f8
735 #define LEDCSR_ON_PERIOD FIELD32(0x000000ff)
736 #define LEDCSR_OFF_PERIOD FIELD32(0x0000ff00)
737 #define LEDCSR_LINK FIELD32(0x00010000)
738 #define LEDCSR_ACTIVITY FIELD32(0x00020000)
739 #define LEDCSR_LINK_POLARITY FIELD32(0x00040000)
740 #define LEDCSR_ACTIVITY_POLARITY FIELD32(0x00080000)
741 #define LEDCSR_LED_DEFAULT FIELD32(0x00100000)
743 /*
744 * SECCSR3: AES control register.
745 */
746 #define SECCSR3 0x00fc
748 /*
749 * ASIC pointer information.
750 * RXPTR: Current RX ring address.
751 * TXPTR: Current Tx ring address.
752 * PRIPTR: Current Priority ring address.
753 * ATIMPTR: Current ATIM ring address.
754 */
755 #define RXPTR 0x0100
756 #define TXPTR 0x0104
757 #define PRIPTR 0x0108
758 #define ATIMPTR 0x010c
760 /*
761 * TXACKCSR0: TX ACK timeout.
762 */
763 #define TXACKCSR0 0x0110
765 /*
766 * ACK timeout count registers.
767 * ACKCNT0: TX ACK timeout count.
768 * ACKCNT1: RX ACK timeout count.
769 */
770 #define ACKCNT0 0x0114
771 #define ACKCNT1 0x0118
773 /*
774 * GPIO and others.
775 */
777 /*
778 * GPIOCSR: GPIO control register.
779 * GPIOCSR_VALx: GPIO value
780 * GPIOCSR_DIRx: GPIO direction: 0 = output; 1 = input
781 */
782 #define GPIOCSR 0x0120
783 #define GPIOCSR_VAL0 FIELD32(0x00000001)
784 #define GPIOCSR_VAL1 FIELD32(0x00000002)
785 #define GPIOCSR_VAL2 FIELD32(0x00000004)
786 #define GPIOCSR_VAL3 FIELD32(0x00000008)
787 #define GPIOCSR_VAL4 FIELD32(0x00000010)
788 #define GPIOCSR_VAL5 FIELD32(0x00000020)
789 #define GPIOCSR_VAL6 FIELD32(0x00000040)
790 #define GPIOCSR_VAL7 FIELD32(0x00000080)
791 #define GPIOCSR_DIR0 FIELD32(0x00000100)
792 #define GPIOCSR_DIR1 FIELD32(0x00000200)
793 #define GPIOCSR_DIR2 FIELD32(0x00000400)
794 #define GPIOCSR_DIR3 FIELD32(0x00000800)
795 #define GPIOCSR_DIR4 FIELD32(0x00001000)
796 #define GPIOCSR_DIR5 FIELD32(0x00002000)
797 #define GPIOCSR_DIR6 FIELD32(0x00004000)
798 #define GPIOCSR_DIR7 FIELD32(0x00008000)
800 /*
801 * FIFO pointer registers.
802 * FIFOCSR0: TX FIFO pointer.
803 * FIFOCSR1: RX FIFO pointer.
804 */
805 #define FIFOCSR0 0x0128
806 #define FIFOCSR1 0x012c
808 /*
809 * BCNCSR1: Tx BEACON offset time control register.
810 * PRELOAD: Beacon timer offset in units of usec.
811 * BEACON_CWMIN: 2^CwMin.
812 */
813 #define BCNCSR1 0x0130
814 #define BCNCSR1_PRELOAD FIELD32(0x0000ffff)
815 #define BCNCSR1_BEACON_CWMIN FIELD32(0x000f0000)
817 /*
818 * MACCSR2: TX_PE to RX_PE turn-around time control register
819 * DELAY: RX_PE low width, in units of pci clock cycle.
820 */
821 #define MACCSR2 0x0134
822 #define MACCSR2_DELAY FIELD32(0x000000ff)
824 /*
825 * TESTCSR: TEST mode selection register.
826 */
827 #define TESTCSR 0x0138
829 /*
830 * ARCSR2: 1 Mbps ACK/CTS PLCP.
831 */
832 #define ARCSR2 0x013c
833 #define ARCSR2_SIGNAL FIELD32(0x000000ff)
834 #define ARCSR2_SERVICE FIELD32(0x0000ff00)
835 #define ARCSR2_LENGTH FIELD32(0xffff0000)
837 /*
838 * ARCSR3: 2 Mbps ACK/CTS PLCP.
839 */
840 #define ARCSR3 0x0140
841 #define ARCSR3_SIGNAL FIELD32(0x000000ff)
842 #define ARCSR3_SERVICE FIELD32(0x0000ff00)
843 #define ARCSR3_LENGTH FIELD32(0xffff0000)
845 /*
846 * ARCSR4: 5.5 Mbps ACK/CTS PLCP.
847 */
848 #define ARCSR4 0x0144
849 #define ARCSR4_SIGNAL FIELD32(0x000000ff)
850 #define ARCSR4_SERVICE FIELD32(0x0000ff00)
851 #define ARCSR4_LENGTH FIELD32(0xffff0000)
853 /*
854 * ARCSR5: 11 Mbps ACK/CTS PLCP.
855 */
856 #define ARCSR5 0x0148
857 #define ARCSR5_SIGNAL FIELD32(0x000000ff)
858 #define ARCSR5_SERVICE FIELD32(0x0000ff00)
859 #define ARCSR5_LENGTH FIELD32(0xffff0000)
861 /*
862 * ARTCSR0: CCK ACK/CTS payload consumed time for 1/2/5.5/11 mbps.
863 */
864 #define ARTCSR0 0x014c
865 #define ARTCSR0_ACK_CTS_11MBS FIELD32(0x000000ff)
866 #define ARTCSR0_ACK_CTS_5_5MBS FIELD32(0x0000ff00)
867 #define ARTCSR0_ACK_CTS_2MBS FIELD32(0x00ff0000)
868 #define ARTCSR0_ACK_CTS_1MBS FIELD32(0xff000000)
871 /*
872 * ARTCSR1: OFDM ACK/CTS payload consumed time for 6/9/12/18 mbps.
873 */
874 #define ARTCSR1 0x0150
875 #define ARTCSR1_ACK_CTS_6MBS FIELD32(0x000000ff)
876 #define ARTCSR1_ACK_CTS_9MBS FIELD32(0x0000ff00)
877 #define ARTCSR1_ACK_CTS_12MBS FIELD32(0x00ff0000)
878 #define ARTCSR1_ACK_CTS_18MBS FIELD32(0xff000000)
880 /*
881 * ARTCSR2: OFDM ACK/CTS payload consumed time for 24/36/48/54 mbps.
882 */
883 #define ARTCSR2 0x0154
884 #define ARTCSR2_ACK_CTS_24MBS FIELD32(0x000000ff)
885 #define ARTCSR2_ACK_CTS_36MBS FIELD32(0x0000ff00)
886 #define ARTCSR2_ACK_CTS_48MBS FIELD32(0x00ff0000)
887 #define ARTCSR2_ACK_CTS_54MBS FIELD32(0xff000000)
889 /*
890 * SECCSR1: WEP control register.
891 * KICK_ENCRYPT: Kick encryption engine, self-clear.
892 * ONE_SHOT: 0: ring mode, 1: One shot only mode.
893 * DESC_ADDRESS: Descriptor physical address of frame.
894 */
895 #define SECCSR1 0x0158
896 #define SECCSR1_KICK_ENCRYPT FIELD32(0x00000001)
897 #define SECCSR1_ONE_SHOT FIELD32(0x00000002)
898 #define SECCSR1_DESC_ADDRESS FIELD32(0xfffffffc)
900 /*
901 * BBPCSR1: BBP TX configuration.
902 */
903 #define BBPCSR1 0x015c
904 #define BBPCSR1_CCK FIELD32(0x00000003)
905 #define BBPCSR1_CCK_FLIP FIELD32(0x00000004)
906 #define BBPCSR1_OFDM FIELD32(0x00030000)
907 #define BBPCSR1_OFDM_FLIP FIELD32(0x00040000)
909 /*
910 * Dual band configuration registers.
911 * DBANDCSR0: Dual band configuration register 0.
912 * DBANDCSR1: Dual band configuration register 1.
913 */
914 #define DBANDCSR0 0x0160
915 #define DBANDCSR1 0x0164
917 /*
918 * BBPPCSR: BBP Pin control register.
919 */
920 #define BBPPCSR 0x0168
922 /*
923 * MAC special debug mode selection registers.
924 * DBGSEL0: MAC special debug mode selection register 0.
925 * DBGSEL1: MAC special debug mode selection register 1.
926 */
927 #define DBGSEL0 0x016c
928 #define DBGSEL1 0x0170
930 /*
931 * BISTCSR: BBP BIST register.
932 */
933 #define BISTCSR 0x0174
935 /*
936 * Multicast filter registers.
937 * MCAST0: Multicast filter register 0.
938 * MCAST1: Multicast filter register 1.
939 */
940 #define MCAST0 0x0178
941 #define MCAST1 0x017c
943 /*
944 * UART registers.
945 * UARTCSR0: UART1 TX register.
946 * UARTCSR1: UART1 RX register.
947 * UARTCSR3: UART1 frame control register.
948 * UARTCSR4: UART1 buffer control register.
949 * UART2CSR0: UART2 TX register.
950 * UART2CSR1: UART2 RX register.
951 * UART2CSR3: UART2 frame control register.
952 * UART2CSR4: UART2 buffer control register.
953 */
954 #define UARTCSR0 0x0180
955 #define UARTCSR1 0x0184
956 #define UARTCSR3 0x0188
957 #define UARTCSR4 0x018c
958 #define UART2CSR0 0x0190
959 #define UART2CSR1 0x0194
960 #define UART2CSR3 0x0198
961 #define UART2CSR4 0x019c
963 /*
964 * BBP registers.
965 * The wordsize of the BBP is 8 bits.
966 */
968 /*
969 * R2: TX antenna control
970 */
971 #define BBP_R2_TX_ANTENNA FIELD8(0x03)
972 #define BBP_R2_TX_IQ_FLIP FIELD8(0x04)
974 /*
975 * R14: RX antenna control
976 */
977 #define BBP_R14_RX_ANTENNA FIELD8(0x03)
978 #define BBP_R14_RX_IQ_FLIP FIELD8(0x04)
980 /*
981 * BBP_R70
982 */
983 #define BBP_R70_JAPAN_FILTER FIELD8(0x08)
985 /*
986 * RF registers
987 */
989 /*
990 * RF 1
991 */
992 #define RF1_TUNER FIELD32(0x00020000)
994 /*
995 * RF 3
996 */
997 #define RF3_TUNER FIELD32(0x00000100)
998 #define RF3_TXPOWER FIELD32(0x00003e00)
1000 /*
1001 * EEPROM content.
1002 * The wordsize of the EEPROM is 16 bits.
1003 */
1005 /*
1006 * HW MAC address.
1007 */
1008 #define EEPROM_MAC_ADDR_0 0x0002
1009 #define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
1010 #define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
1011 #define EEPROM_MAC_ADDR1 0x0003
1012 #define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
1013 #define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
1014 #define EEPROM_MAC_ADDR_2 0x0004
1015 #define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
1016 #define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
1018 /*
1019 * EEPROM antenna.
1020 * ANTENNA_NUM: Number of antenna's.
1021 * TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
1022 * RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
1023 * LED_MODE: 0: default, 1: TX/RX activity,2: Single (ignore link), 3: rsvd.
1024 * DYN_TXAGC: Dynamic TX AGC control.
1025 * HARDWARE_RADIO: 1: Hardware controlled radio. Read GPIO0.
1026 * RF_TYPE: Rf_type of this adapter.
1027 */
1028 #define EEPROM_ANTENNA 0x10
1029 #define EEPROM_ANTENNA_NUM FIELD16(0x0003)
1030 #define EEPROM_ANTENNA_TX_DEFAULT FIELD16(0x000c)
1031 #define EEPROM_ANTENNA_RX_DEFAULT FIELD16(0x0030)
1032 #define EEPROM_ANTENNA_LED_MODE FIELD16(0x01c0)
1033 #define EEPROM_ANTENNA_DYN_TXAGC FIELD16(0x0200)
1034 #define EEPROM_ANTENNA_HARDWARE_RADIO FIELD16(0x0400)
1035 #define EEPROM_ANTENNA_RF_TYPE FIELD16(0xf800)
1037 /*
1038 * EEPROM NIC config.
1039 * CARDBUS_ACCEL: 0: enable, 1: disable.
1040 * DYN_BBP_TUNE: 0: enable, 1: disable.
1041 * CCK_TX_POWER: CCK TX power compensation.
1042 */
1043 #define EEPROM_NIC 0x11
1044 #define EEPROM_NIC_CARDBUS_ACCEL FIELD16(0x0001)
1045 #define EEPROM_NIC_DYN_BBP_TUNE FIELD16(0x0002)
1046 #define EEPROM_NIC_CCK_TX_POWER FIELD16(0x000c)
1048 /*
1049 * EEPROM geography.
1050 * GEO: Default geography setting for device.
1051 */
1052 #define EEPROM_GEOGRAPHY 0x12
1053 #define EEPROM_GEOGRAPHY_GEO FIELD16(0x0f00)
1055 /*
1056 * EEPROM BBP.
1057 */
1058 #define EEPROM_BBP_START 0x13
1059 #define EEPROM_BBP_SIZE 16
1060 #define EEPROM_BBP_VALUE FIELD16(0x00ff)
1061 #define EEPROM_BBP_REG_ID FIELD16(0xff00)
1063 /*
1064 * EEPROM TXPOWER
1065 */
1066 #define EEPROM_TXPOWER_START 0x23
1067 #define EEPROM_TXPOWER_SIZE 7
1068 #define EEPROM_TXPOWER_1 FIELD16(0x00ff)
1069 #define EEPROM_TXPOWER_2 FIELD16(0xff00)
1071 /*
1072 * RSSI <-> dBm offset calibration
1073 */
1074 #define EEPROM_CALIBRATE_OFFSET 0x3e
1075 #define EEPROM_CALIBRATE_OFFSET_RSSI FIELD16(0x00ff)
1077 /*
1078 * DMA descriptor defines.
1079 */
1080 #define TXD_DESC_SIZE (11 * sizeof(__le32))
1081 #define RXD_DESC_SIZE (11 * sizeof(__le32))
1083 /*
1084 * TX descriptor format for TX, PRIO, ATIM and Beacon Ring.
1085 */
1087 /*
1088 * Word0
1089 */
1090 #define TXD_W0_OWNER_NIC FIELD32(0x00000001)
1091 #define TXD_W0_VALID FIELD32(0x00000002)
1092 #define TXD_W0_RESULT FIELD32(0x0000001c)
1093 #define TXD_W0_RETRY_COUNT FIELD32(0x000000e0)
1094 #define TXD_W0_MORE_FRAG FIELD32(0x00000100)
1095 #define TXD_W0_ACK FIELD32(0x00000200)
1096 #define TXD_W0_TIMESTAMP FIELD32(0x00000400)
1097 #define TXD_W0_OFDM FIELD32(0x00000800)
1098 #define TXD_W0_CIPHER_OWNER FIELD32(0x00001000)
1099 #define TXD_W0_IFS FIELD32(0x00006000)
1100 #define TXD_W0_RETRY_MODE FIELD32(0x00008000)
1101 #define TXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
1102 #define TXD_W0_CIPHER_ALG FIELD32(0xe0000000)
1104 /*
1105 * Word1
1106 */
1107 #define TXD_W1_BUFFER_ADDRESS FIELD32(0xffffffff)
1109 /*
1110 * Word2
1111 */
1112 #define TXD_W2_IV_OFFSET FIELD32(0x0000003f)
1113 #define TXD_W2_AIFS FIELD32(0x000000c0)
1114 #define TXD_W2_CWMIN FIELD32(0x00000f00)
1115 #define TXD_W2_CWMAX FIELD32(0x0000f000)
1117 /*
1118 * Word3: PLCP information
1119 */
1120 #define TXD_W3_PLCP_SIGNAL FIELD32(0x000000ff)
1121 #define TXD_W3_PLCP_SERVICE FIELD32(0x0000ff00)
1122 #define TXD_W3_PLCP_LENGTH_LOW FIELD32(0x00ff0000)
1123 #define TXD_W3_PLCP_LENGTH_HIGH FIELD32(0xff000000)
1125 /*
1126 * Word4
1127 */
1128 #define TXD_W4_IV FIELD32(0xffffffff)
1130 /*
1131 * Word5
1132 */
1133 #define TXD_W5_EIV FIELD32(0xffffffff)
1135 /*
1136 * Word6-9: Key
1137 */
1138 #define TXD_W6_KEY FIELD32(0xffffffff)
1139 #define TXD_W7_KEY FIELD32(0xffffffff)
1140 #define TXD_W8_KEY FIELD32(0xffffffff)
1141 #define TXD_W9_KEY FIELD32(0xffffffff)
1143 /*
1144 * Word10
1145 */
1146 #define TXD_W10_RTS FIELD32(0x00000001)
1147 #define TXD_W10_TX_RATE FIELD32(0x000000fe)
1149 /*
1150 * RX descriptor format for RX Ring.
1151 */
1153 /*
1154 * Word0
1155 */
1156 #define RXD_W0_OWNER_NIC FIELD32(0x00000001)
1157 #define RXD_W0_UNICAST_TO_ME FIELD32(0x00000002)
1158 #define RXD_W0_MULTICAST FIELD32(0x00000004)
1159 #define RXD_W0_BROADCAST FIELD32(0x00000008)
1160 #define RXD_W0_MY_BSS FIELD32(0x00000010)
1161 #define RXD_W0_CRC_ERROR FIELD32(0x00000020)
1162 #define RXD_W0_OFDM FIELD32(0x00000040)
1163 #define RXD_W0_PHYSICAL_ERROR FIELD32(0x00000080)
1164 #define RXD_W0_CIPHER_OWNER FIELD32(0x00000100)
1165 #define RXD_W0_ICV_ERROR FIELD32(0x00000200)
1166 #define RXD_W0_IV_OFFSET FIELD32(0x0000fc00)
1167 #define RXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
1168 #define RXD_W0_CIPHER_ALG FIELD32(0xe0000000)
1170 /*
1171 * Word1
1172 */
1173 #define RXD_W1_BUFFER_ADDRESS FIELD32(0xffffffff)
1175 /*
1176 * Word2
1177 */
1178 #define RXD_W2_SIGNAL FIELD32(0x000000ff)
1179 #define RXD_W2_RSSI FIELD32(0x0000ff00)
1180 #define RXD_W2_TA FIELD32(0xffff0000)
1182 /*
1183 * Word3
1184 */
1185 #define RXD_W3_TA FIELD32(0xffffffff)
1187 /*
1188 * Word4
1189 */
1190 #define RXD_W4_IV FIELD32(0xffffffff)
1192 /*
1193 * Word5
1194 */
1195 #define RXD_W5_EIV FIELD32(0xffffffff)
1197 /*
1198 * Word6-9: Key
1199 */
1200 #define RXD_W6_KEY FIELD32(0xffffffff)
1201 #define RXD_W7_KEY FIELD32(0xffffffff)
1202 #define RXD_W8_KEY FIELD32(0xffffffff)
1203 #define RXD_W9_KEY FIELD32(0xffffffff)
1205 /*
1206 * Word10
1207 */
1208 #define RXD_W10_DROP FIELD32(0x00000001)
1210 /*
1211 * Macros for converting txpower from EEPROM to mac80211 value
1212 * and from mac80211 value to register value.
1213 */
1214 #define MIN_TXPOWER 0
1215 #define MAX_TXPOWER 31
1216 #define DEFAULT_TXPOWER 24
1218 #define TXPOWER_FROM_DEV(__txpower) \
1219 (((u8)(__txpower)) > MAX_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
1221 #define TXPOWER_TO_DEV(__txpower) \
1222 clamp_t(char, __txpower, MIN_TXPOWER, MAX_TXPOWER)