drivers/net/wireless/realtek/rtlwifi/rtl8188ee/def.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /* Copyright(c) 2009-2013  Realtek Corporation.*/
   3
   4 #ifndef __RTL92C_DEF_H__
   5 #define __RTL92C_DEF_H__
   6
   7 #define HAL_PRIME_CHNL_OFFSET_DONT_CARE                 0
   8 #define HAL_PRIME_CHNL_OFFSET_LOWER                     1
   9 #define HAL_PRIME_CHNL_OFFSET_UPPER                     2
  10
  11 #define RX_MPDU_QUEUE                                   0
  12 #define RX_CMD_QUEUE                                    1
  13
  14 #define C2H_RX_CMD_HDR_LEN                              8
  15
  16 #define CHIP_BONDING_IDENTIFIER(_value) (((_value)>>22)&0x3)
  17
  18 /* [15:12] IC version(CUT): A-cut=0, B-cut=1, C-cut=2, D-cut=3
  19  * [7] Manufacturer: TSMC=0, UMC=1
  20  * [6:4] RF type: 1T1R=0, 1T2R=1, 2T2R=2
  21  * [3] Chip type: TEST=0, NORMAL=1
  22  * [2:0] IC type: 81xxC=0, 8723=1, 92D=2
  23  */
  24 #define CHIP_8723                       BIT(0)
  25 #define CHIP_92D                        BIT(1)
  26 #define NORMAL_CHIP                     BIT(3)
  27 #define RF_TYPE_1T1R                    (~(BIT(4)|BIT(5)|BIT(6)))
  28 #define RF_TYPE_1T2R                    BIT(4)
  29 #define RF_TYPE_2T2R                    BIT(5)
  30 #define CHIP_VENDOR_UMC                 BIT(7)
  31 #define B_CUT_VERSION                   BIT(12)
  32 #define C_CUT_VERSION                   BIT(13)
  33 #define D_CUT_VERSION                   ((BIT(12)|BIT(13)))
  34 #define E_CUT_VERSION                   BIT(14)
  35
  36 /* MASK */
  37 #define IC_TYPE_MASK                    (BIT(0)|BIT(1)|BIT(2))
  38 #define CHIP_TYPE_MASK                  BIT(3)
  39 #define RF_TYPE_MASK                    (BIT(4)|BIT(5)|BIT(6))
  40 #define MANUFACTUER_MASK                BIT(7)
  41 #define ROM_VERSION_MASK                (BIT(11)|BIT(10)|BIT(9)|BIT(8))
  42 #define CUT_VERSION_MASK                (BIT(15)|BIT(14)|BIT(13)|BIT(12))
  43
  44 /* Get element */
  45 #define GET_CVID_IC_TYPE(version)       ((version) & IC_TYPE_MASK)
  46 #define GET_CVID_CHIP_TYPE(version)     ((version) & CHIP_TYPE_MASK)
  47 #define GET_CVID_RF_TYPE(version)       ((version) & RF_TYPE_MASK)
  48 #define GET_CVID_MANUFACTUER(version)   ((version) & MANUFACTUER_MASK)
  49 #define GET_CVID_ROM_VERSION(version)   ((version) & ROM_VERSION_MASK)
  50 #define GET_CVID_CUT_VERSION(version)   ((version) & CUT_VERSION_MASK)
  51
  52 #define IS_81XXC(version)                                               \
  53         ((GET_CVID_IC_TYPE(version) == 0) ? true : false)
  54 #define IS_8723_SERIES(version)                                         \
  55         ((GET_CVID_IC_TYPE(version) == CHIP_8723) ? true : false)
  56 #define IS_92D(version)                                                 \
  57         ((GET_CVID_IC_TYPE(version) == CHIP_92D) ? true : false)
  58
  59 #define IS_NORMAL_CHIP(version)                                         \
  60         ((GET_CVID_CHIP_TYPE(version)) ? true : false)
  61 #define IS_NORMAL_CHIP92D(version)                                      \
  62         ((GET_CVID_CHIP_TYPE(version)) ? true : false)
  63
  64 #define IS_1T1R(version)                                                \
  65         ((GET_CVID_RF_TYPE(version)) ? false : true)
  66 #define IS_1T2R(version)                                                \
  67         ((GET_CVID_RF_TYPE(version) == RF_TYPE_1T2R) ? true : false)
  68 #define IS_2T2R(version)                                                \
  69         ((GET_CVID_RF_TYPE(version) == RF_TYPE_2T2R) ? true : false)
  70 #define IS_CHIP_VENDOR_UMC(version)                                     \
  71         ((GET_CVID_MANUFACTUER(version)) ? true : false)
  72
  73 #define IS_92C_SERIAL(version)                                          \
  74         ((IS_81XXC(version) && IS_2T2R(version)) ? true : false)
  75 #define IS_81XXC_VENDOR_UMC_B_CUT(version)                              \
  76         (IS_81XXC(version) ? (IS_CHIP_VENDOR_UMC(version) ?             \
  77         ((GET_CVID_CUT_VERSION(version) == B_CUT_VERSION) ? true        \
  78         : false) : false) : false)
  79
  80 enum version_8188e {
  81         VERSION_TEST_CHIP_88E = 0x00,
  82         VERSION_NORMAL_CHIP_88E = 0x01,
  83         VERSION_UNKNOWN = 0xFF,
  84 };
  85
  86 enum rtl819x_loopback_e {
  87         RTL819X_NO_LOOPBACK = 0,
  88         RTL819X_MAC_LOOPBACK = 1,
  89         RTL819X_DMA_LOOPBACK = 2,
  90         RTL819X_CCK_LOOPBACK = 3,
  91 };
  92
  93 enum rf_optype {
  94         RF_OP_BY_SW_3WIRE = 0,
  95         RF_OP_BY_FW,
  96         RF_OP_MAX
  97 };
  98
  99 enum rf_power_state {
 100         RF_ON,
 101         RF_OFF,
 102         RF_SLEEP,
 103         RF_SHUT_DOWN,
 104 };
 105
 106 enum power_save_mode {
 107         POWER_SAVE_MODE_ACTIVE,
 108         POWER_SAVE_MODE_SAVE,
 109 };
 110
 111 enum power_polocy_config {
 112         POWERCFG_MAX_POWER_SAVINGS,
 113         POWERCFG_GLOBAL_POWER_SAVINGS,
 114         POWERCFG_LOCAL_POWER_SAVINGS,
 115         POWERCFG_LENOVO,
 116 };
 117
 118 enum interface_select_pci {
 119         INTF_SEL1_MINICARD = 0,
 120         INTF_SEL0_PCIE = 1,
 121         INTF_SEL2_RSV = 2,
 122         INTF_SEL3_RSV = 3,
 123 };
 124
 125 enum rtl_desc_qsel {
 126         QSLT_BK = 0x2,
 127         QSLT_BE = 0x0,
 128         QSLT_VI = 0x5,
 129         QSLT_VO = 0x7,
 130         QSLT_BEACON = 0x10,
 131         QSLT_HIGH = 0x11,
 132         QSLT_MGNT = 0x12,
 133         QSLT_CMD = 0x13,
 134 };
 135
 136 enum rtl_desc92c_rate {
 137         DESC92C_RATE1M = 0x00,
 138         DESC92C_RATE2M = 0x01,
 139         DESC92C_RATE5_5M = 0x02,
 140         DESC92C_RATE11M = 0x03,
 141
 142         DESC92C_RATE6M = 0x04,
 143         DESC92C_RATE9M = 0x05,
 144         DESC92C_RATE12M = 0x06,
 145         DESC92C_RATE18M = 0x07,
 146         DESC92C_RATE24M = 0x08,
 147         DESC92C_RATE36M = 0x09,
 148         DESC92C_RATE48M = 0x0a,
 149         DESC92C_RATE54M = 0x0b,
 150
 151         DESC92C_RATEMCS0 = 0x0c,
 152         DESC92C_RATEMCS1 = 0x0d,
 153         DESC92C_RATEMCS2 = 0x0e,
 154         DESC92C_RATEMCS3 = 0x0f,
 155         DESC92C_RATEMCS4 = 0x10,
 156         DESC92C_RATEMCS5 = 0x11,
 157         DESC92C_RATEMCS6 = 0x12,
 158         DESC92C_RATEMCS7 = 0x13,
 159         DESC92C_RATEMCS8 = 0x14,
 160         DESC92C_RATEMCS9 = 0x15,
 161         DESC92C_RATEMCS10 = 0x16,
 162         DESC92C_RATEMCS11 = 0x17,
 163         DESC92C_RATEMCS12 = 0x18,
 164         DESC92C_RATEMCS13 = 0x19,
 165         DESC92C_RATEMCS14 = 0x1a,
 166         DESC92C_RATEMCS15 = 0x1b,
 167         DESC92C_RATEMCS15_SG = 0x1c,
 168         DESC92C_RATEMCS32 = 0x20,
 169 };
 170
 171 struct phy_sts_cck_8192s_t {
 172         u8 adc_pwdb_X[4];
 173         u8 sq_rpt;
 174         u8 cck_agc_rpt;
 175 };
 176
 177 struct h2c_cmd_8192c {
 178         u8 element_id;
 179         u32 cmd_len;
 180         u8 *p_cmdbuffer;
 181 };
 182
 183 #endif