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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / net / wireless / realtek / rtlwifi / rtl8188ee / phy.c
blobd13983ec09ad9488fc5796a3e4514b20fff7fced
1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2013 Realtek Corporation.*/
3
4 #include "../wifi.h"
5 #include "../pci.h"
6 #include "../ps.h"
7 #include "reg.h"
8 #include "def.h"
9 #include "phy.h"
10 #include "rf.h"
11 #include "dm.h"
12 #include "table.h"
13
14 static u32 _rtl88e_phy_rf_serial_read(struct ieee80211_hw *hw,
15 enum radio_path rfpath, u32 offset);
16 static void _rtl88e_phy_rf_serial_write(struct ieee80211_hw *hw,
17 enum radio_path rfpath, u32 offset,
18 u32 data);
19 static u32 _rtl88e_phy_calculate_bit_shift(u32 bitmask);
20 static bool _rtl88e_phy_bb8188e_config_parafile(struct ieee80211_hw *hw);
21 static bool _rtl88e_phy_config_mac_with_headerfile(struct ieee80211_hw *hw);
22 static bool phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
23 u8 configtype);
24 static bool phy_config_bb_with_pghdr(struct ieee80211_hw *hw,
25 u8 configtype);
26 static void _rtl88e_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw);
27 static bool _rtl88e_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
28 u32 cmdtableidx, u32 cmdtablesz,
29 enum swchnlcmd_id cmdid, u32 para1,
30 u32 para2, u32 msdelay);
31 static bool _rtl88e_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
32 u8 channel, u8 *stage, u8 *step,
33 u32 *delay);
34
35 static long _rtl88e_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw,
36 enum wireless_mode wirelessmode,
37 u8 txpwridx);
38 static void rtl88ee_phy_set_rf_on(struct ieee80211_hw *hw);
39 static void rtl88e_phy_set_io(struct ieee80211_hw *hw);
40
41 u32 rtl88e_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask)
42 {
43 struct rtl_priv *rtlpriv = rtl_priv(hw);
44 u32 returnvalue, originalvalue, bitshift;
45
46 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
47 "regaddr(%#x), bitmask(%#x)\n", regaddr, bitmask);
48 originalvalue = rtl_read_dword(rtlpriv, regaddr);
49 bitshift = _rtl88e_phy_calculate_bit_shift(bitmask);
50 returnvalue = (originalvalue & bitmask) >> bitshift;
51
52 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
53 "BBR MASK=0x%x Addr[0x%x]=0x%x\n", bitmask,
54 regaddr, originalvalue);
55
56 return returnvalue;
57
58 }
59
60 void rtl88e_phy_set_bb_reg(struct ieee80211_hw *hw,
61 u32 regaddr, u32 bitmask, u32 data)
62 {
63 struct rtl_priv *rtlpriv = rtl_priv(hw);
64 u32 originalvalue, bitshift;
65
66 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
67 "regaddr(%#x), bitmask(%#x), data(%#x)\n",
68 regaddr, bitmask, data);
69
70 if (bitmask != MASKDWORD) {
71 originalvalue = rtl_read_dword(rtlpriv, regaddr);
72 bitshift = _rtl88e_phy_calculate_bit_shift(bitmask);
73 data = ((originalvalue & (~bitmask)) | (data << bitshift));
74 }
75
76 rtl_write_dword(rtlpriv, regaddr, data);
77
78 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
79 "regaddr(%#x), bitmask(%#x), data(%#x)\n",
80 regaddr, bitmask, data);
81 }
82
83 u32 rtl88e_phy_query_rf_reg(struct ieee80211_hw *hw,
84 enum radio_path rfpath, u32 regaddr, u32 bitmask)
85 {
86 struct rtl_priv *rtlpriv = rtl_priv(hw);
87 u32 original_value, readback_value, bitshift;
88
89 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
90 "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n",
91 regaddr, rfpath, bitmask);
92
93 spin_lock(&rtlpriv->locks.rf_lock);
94
95
96 original_value = _rtl88e_phy_rf_serial_read(hw, rfpath, regaddr);
97 bitshift = _rtl88e_phy_calculate_bit_shift(bitmask);
98 readback_value = (original_value & bitmask) >> bitshift;
99
100 spin_unlock(&rtlpriv->locks.rf_lock);
101
102 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
103 "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n",
104 regaddr, rfpath, bitmask, original_value);
105 return readback_value;
106 }
107
108 void rtl88e_phy_set_rf_reg(struct ieee80211_hw *hw,
109 enum radio_path rfpath,
110 u32 regaddr, u32 bitmask, u32 data)
111 {
112 struct rtl_priv *rtlpriv = rtl_priv(hw);
113 u32 original_value, bitshift;
114
115 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
116 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
117 regaddr, bitmask, data, rfpath);
118
119 spin_lock(&rtlpriv->locks.rf_lock);
120
121 if (bitmask != RFREG_OFFSET_MASK) {
122 original_value = _rtl88e_phy_rf_serial_read(hw,
123 rfpath,
124 regaddr);
125 bitshift = _rtl88e_phy_calculate_bit_shift(bitmask);
126 data =
127 ((original_value & (~bitmask)) |
128 (data << bitshift));
129 }
130
131 _rtl88e_phy_rf_serial_write(hw, rfpath, regaddr, data);
132
133
134 spin_unlock(&rtlpriv->locks.rf_lock);
135
136 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
137 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
138 regaddr, bitmask, data, rfpath);
139 }
140
141 static u32 _rtl88e_phy_rf_serial_read(struct ieee80211_hw *hw,
142 enum radio_path rfpath, u32 offset)
143 {
144 struct rtl_priv *rtlpriv = rtl_priv(hw);
145 struct rtl_phy *rtlphy = &rtlpriv->phy;
146 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
147 u32 newoffset;
148 u32 tmplong, tmplong2;
149 u8 rfpi_enable = 0;
150 u32 retvalue;
151
152 offset &= 0xff;
153 newoffset = offset;
154 if (RT_CANNOT_IO(hw)) {
155 pr_err("return all one\n");
156 return 0xFFFFFFFF;
157 }
158 tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD);
159 if (rfpath == RF90_PATH_A)
160 tmplong2 = tmplong;
161 else
162 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD);
163 tmplong2 = (tmplong2 & (~BLSSIREADADDRESS)) |
164 (newoffset << 23) | BLSSIREADEDGE;
165 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
166 tmplong & (~BLSSIREADEDGE));
167 udelay(10);
168 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2);
169 udelay(120);
170 if (rfpath == RF90_PATH_A)
171 rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,
172 BIT(8));
173 else if (rfpath == RF90_PATH_B)
174 rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1,
175 BIT(8));
176 if (rfpi_enable)
177 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rbpi,
178 BLSSIREADBACKDATA);
179 else
180 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb,
181 BLSSIREADBACKDATA);
182 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
183 "RFR-%d Addr[0x%x]=0x%x\n",
184 rfpath, pphyreg->rf_rb, retvalue);
185 return retvalue;
186 }
187
188 static void _rtl88e_phy_rf_serial_write(struct ieee80211_hw *hw,
189 enum radio_path rfpath, u32 offset,
190 u32 data)
191 {
192 u32 data_and_addr;
193 u32 newoffset;
194 struct rtl_priv *rtlpriv = rtl_priv(hw);
195 struct rtl_phy *rtlphy = &rtlpriv->phy;
196 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
197
198 if (RT_CANNOT_IO(hw)) {
199 pr_err("stop\n");
200 return;
201 }
202 offset &= 0xff;
203 newoffset = offset;
204 data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff;
205 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);
206 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
207 "RFW-%d Addr[0x%x]=0x%x\n",
208 rfpath, pphyreg->rf3wire_offset, data_and_addr);
209 }
210
211 static u32 _rtl88e_phy_calculate_bit_shift(u32 bitmask)
212 {
213 u32 i;
214
215 for (i = 0; i <= 31; i++) {
216 if (((bitmask >> i) & 0x1) == 1)
217 break;
218 }
219 return i;
220 }
221
222 bool rtl88e_phy_mac_config(struct ieee80211_hw *hw)
223 {
224 struct rtl_priv *rtlpriv = rtl_priv(hw);
225 bool rtstatus = _rtl88e_phy_config_mac_with_headerfile(hw);
226
227 rtl_write_byte(rtlpriv, 0x04CA, 0x0B);
228 return rtstatus;
229 }
230
231 bool rtl88e_phy_bb_config(struct ieee80211_hw *hw)
232 {
233 bool rtstatus = true;
234 struct rtl_priv *rtlpriv = rtl_priv(hw);
235 u16 regval;
236 u8 b_reg_hwparafile = 1;
237 u32 tmp;
238 _rtl88e_phy_init_bb_rf_register_definition(hw);
239 regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
240 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN,
241 regval | BIT(13) | BIT(0) | BIT(1));
242
243 rtl_write_byte(rtlpriv, REG_RF_CTRL, RF_EN | RF_RSTB | RF_SDMRSTB);
244 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN,
245 FEN_PPLL | FEN_PCIEA | FEN_DIO_PCIE |
246 FEN_BB_GLB_RSTN | FEN_BBRSTB);
247 tmp = rtl_read_dword(rtlpriv, 0x4c);
248 rtl_write_dword(rtlpriv, 0x4c, tmp | BIT(23));
249 if (b_reg_hwparafile == 1)
250 rtstatus = _rtl88e_phy_bb8188e_config_parafile(hw);
251 return rtstatus;
252 }
253
254 bool rtl88e_phy_rf_config(struct ieee80211_hw *hw)
255 {
256 return rtl88e_phy_rf6052_config(hw);
257 }
258
259 static bool _rtl88e_check_condition(struct ieee80211_hw *hw,
260 const u32 condition)
261 {
262 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
263 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
264 u32 _board = rtlefuse->board_type; /*need efuse define*/
265 u32 _interface = rtlhal->interface;
266 u32 _platform = 0x08;/*SupportPlatform */
267 u32 cond;
268
269 if (condition == 0xCDCDCDCD)
270 return true;
271
272 cond = condition & 0xFF;
273 if ((_board & cond) == 0 && cond != 0x1F)
274 return false;
275
276 cond = condition & 0xFF00;
277 cond = cond >> 8;
278 if ((_interface & cond) == 0 && cond != 0x07)
279 return false;
280
281 cond = condition & 0xFF0000;
282 cond = cond >> 16;
283 if ((_platform & cond) == 0 && cond != 0x0F)
284 return false;
285 return true;
286 }
287
288 static void _rtl8188e_config_rf_reg(struct ieee80211_hw *hw, u32 addr,
289 u32 data, enum radio_path rfpath,
290 u32 regaddr)
291 {
292 if (addr == 0xffe) {
293 mdelay(50);
294 } else if (addr == 0xfd) {
295 mdelay(5);
296 } else if (addr == 0xfc) {
297 mdelay(1);
298 } else if (addr == 0xfb) {
299 udelay(50);
300 } else if (addr == 0xfa) {
301 udelay(5);
302 } else if (addr == 0xf9) {
303 udelay(1);
304 } else {
305 rtl_set_rfreg(hw, rfpath, regaddr,
306 RFREG_OFFSET_MASK,
307 data);
308 udelay(1);
309 }
310 }
311
312 static void _rtl8188e_config_rf_radio_a(struct ieee80211_hw *hw,
313 u32 addr, u32 data)
314 {
315 u32 content = 0x1000; /*RF Content: radio_a_txt*/
316 u32 maskforphyset = (u32)(content & 0xE000);
317
318 _rtl8188e_config_rf_reg(hw, addr, data, RF90_PATH_A,
319 addr | maskforphyset);
320 }
321
322 static void _rtl8188e_config_bb_reg(struct ieee80211_hw *hw,
323 u32 addr, u32 data)
324 {
325 if (addr == 0xfe) {
326 mdelay(50);
327 } else if (addr == 0xfd) {
328 mdelay(5);
329 } else if (addr == 0xfc) {
330 mdelay(1);
331 } else if (addr == 0xfb) {
332 udelay(50);
333 } else if (addr == 0xfa) {
334 udelay(5);
335 } else if (addr == 0xf9) {
336 udelay(1);
337 } else {
338 rtl_set_bbreg(hw, addr, MASKDWORD, data);
339 udelay(1);
340 }
341 }
342
343 static bool _rtl88e_phy_bb8188e_config_parafile(struct ieee80211_hw *hw)
344 {
345 struct rtl_priv *rtlpriv = rtl_priv(hw);
346 struct rtl_phy *rtlphy = &rtlpriv->phy;
347 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
348 bool rtstatus;
349
350 rtstatus = phy_config_bb_with_headerfile(hw, BASEBAND_CONFIG_PHY_REG);
351 if (!rtstatus) {
352 pr_err("Write BB Reg Fail!!\n");
353 return false;
354 }
355
356 if (!rtlefuse->autoload_failflag) {
357 rtlphy->pwrgroup_cnt = 0;
358 rtstatus =
359 phy_config_bb_with_pghdr(hw, BASEBAND_CONFIG_PHY_REG);
360 }
361 if (!rtstatus) {
362 pr_err("BB_PG Reg Fail!!\n");
363 return false;
364 }
365 rtstatus =
366 phy_config_bb_with_headerfile(hw, BASEBAND_CONFIG_AGC_TAB);
367 if (!rtstatus) {
368 pr_err("AGC Table Fail\n");
369 return false;
370 }
371 rtlphy->cck_high_power =
372 (bool)(rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, 0x200));
373
374 return true;
375 }
376
377 static bool _rtl88e_phy_config_mac_with_headerfile(struct ieee80211_hw *hw)
378 {
379 struct rtl_priv *rtlpriv = rtl_priv(hw);
380 u32 i;
381 u32 arraylength;
382 u32 *ptrarray;
383
384 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Read Rtl8188EMACPHY_Array\n");
385 arraylength = RTL8188EEMAC_1T_ARRAYLEN;
386 ptrarray = RTL8188EEMAC_1T_ARRAY;
387 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
388 "Img:RTL8188EEMAC_1T_ARRAY LEN %d\n", arraylength);
389 for (i = 0; i < arraylength; i = i + 2)
390 rtl_write_byte(rtlpriv, ptrarray[i], (u8)ptrarray[i + 1]);
391 return true;
392 }
393
394 #define READ_NEXT_PAIR(v1, v2, i) \
395 do { \
396 i += 2; v1 = array_table[i]; \
397 v2 = array_table[i+1]; \
398 } while (0)
399
400 static void handle_branch1(struct ieee80211_hw *hw, u16 arraylen,
401 u32 *array_table)
402 {
403 u32 v1;
404 u32 v2;
405 int i;
406
407 for (i = 0; i < arraylen; i = i + 2) {
408 v1 = array_table[i];
409 v2 = array_table[i+1];
410 if (v1 < 0xcdcdcdcd) {
411 _rtl8188e_config_bb_reg(hw, v1, v2);
412 } else { /*This line is the start line of branch.*/
413 /* to protect READ_NEXT_PAIR not overrun */
414 if (i >= arraylen - 2)
415 break;
416
417 if (!_rtl88e_check_condition(hw, array_table[i])) {
418 /*Discard the following (offset, data) pairs*/
419 READ_NEXT_PAIR(v1, v2, i);
420 while (v2 != 0xDEAD &&
421 v2 != 0xCDEF &&
422 v2 != 0xCDCD && i < arraylen - 2)
423 READ_NEXT_PAIR(v1, v2, i);
424 i -= 2; /* prevent from for-loop += 2*/
425 } else { /* Configure matched pairs and skip
426 * to end of if-else.
427 */
428 READ_NEXT_PAIR(v1, v2, i);
429 while (v2 != 0xDEAD &&
430 v2 != 0xCDEF &&
431 v2 != 0xCDCD && i < arraylen - 2) {
432 _rtl8188e_config_bb_reg(hw, v1, v2);
433 READ_NEXT_PAIR(v1, v2, i);
434 }
435
436 while (v2 != 0xDEAD && i < arraylen - 2)
437 READ_NEXT_PAIR(v1, v2, i);
438 }
439 }
440 }
441 }
442
443 static void handle_branch2(struct ieee80211_hw *hw, u16 arraylen,
444 u32 *array_table)
445 {
446 struct rtl_priv *rtlpriv = rtl_priv(hw);
447 u32 v1;
448 u32 v2;
449 int i;
450
451 for (i = 0; i < arraylen; i = i + 2) {
452 v1 = array_table[i];
453 v2 = array_table[i+1];
454 if (v1 < 0xCDCDCDCD) {
455 rtl_set_bbreg(hw, array_table[i], MASKDWORD,
456 array_table[i + 1]);
457 udelay(1);
458 continue;
459 } else { /*This line is the start line of branch.*/
460 /* to protect READ_NEXT_PAIR not overrun */
461 if (i >= arraylen - 2)
462 break;
463
464 if (!_rtl88e_check_condition(hw, array_table[i])) {
465 /*Discard the following (offset, data) pairs*/
466 READ_NEXT_PAIR(v1, v2, i);
467 while (v2 != 0xDEAD &&
468 v2 != 0xCDEF &&
469 v2 != 0xCDCD && i < arraylen - 2)
470 READ_NEXT_PAIR(v1, v2, i);
471 i -= 2; /* prevent from for-loop += 2*/
472 } else { /* Configure matched pairs and skip
473 * to end of if-else.
474 */
475 READ_NEXT_PAIR(v1, v2, i);
476 while (v2 != 0xDEAD &&
477 v2 != 0xCDEF &&
478 v2 != 0xCDCD && i < arraylen - 2) {
479 rtl_set_bbreg(hw, array_table[i],
480 MASKDWORD,
481 array_table[i + 1]);
482 udelay(1);
483 READ_NEXT_PAIR(v1, v2, i);
484 }
485
486 while (v2 != 0xDEAD && i < arraylen - 2)
487 READ_NEXT_PAIR(v1, v2, i);
488 }
489 }
490 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
491 "The agctab_array_table[0] is %x Rtl818EEPHY_REGArray[1] is %x\n",
492 array_table[i], array_table[i + 1]);
493 }
494 }
495
496 static bool phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
497 u8 configtype)
498 {
499 u32 *array_table;
500 u16 arraylen;
501
502 if (configtype == BASEBAND_CONFIG_PHY_REG) {
503 arraylen = RTL8188EEPHY_REG_1TARRAYLEN;
504 array_table = RTL8188EEPHY_REG_1TARRAY;
505 handle_branch1(hw, arraylen, array_table);
506 } else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
507 arraylen = RTL8188EEAGCTAB_1TARRAYLEN;
508 array_table = RTL8188EEAGCTAB_1TARRAY;
509 handle_branch2(hw, arraylen, array_table);
510 }
511 return true;
512 }
513
514 static void store_pwrindex_rate_offset(struct ieee80211_hw *hw,
515 u32 regaddr, u32 bitmask,
516 u32 data)
517 {
518 struct rtl_priv *rtlpriv = rtl_priv(hw);
519 struct rtl_phy *rtlphy = &rtlpriv->phy;
520 int count = rtlphy->pwrgroup_cnt;
521
522 if (regaddr == RTXAGC_A_RATE18_06) {
523 rtlphy->mcs_txpwrlevel_origoffset[count][0] = data;
524 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
525 "MCSTxPowerLevelOriginalOffset[%d][0] = 0x%x\n",
526 count,
527 rtlphy->mcs_txpwrlevel_origoffset[count][0]);
528 }
529 if (regaddr == RTXAGC_A_RATE54_24) {
530 rtlphy->mcs_txpwrlevel_origoffset[count][1] = data;
531 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
532 "MCSTxPowerLevelOriginalOffset[%d][1] = 0x%x\n",
533 count,
534 rtlphy->mcs_txpwrlevel_origoffset[count][1]);
535 }
536 if (regaddr == RTXAGC_A_CCK1_MCS32) {
537 rtlphy->mcs_txpwrlevel_origoffset[count][6] = data;
538 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
539 "MCSTxPowerLevelOriginalOffset[%d][6] = 0x%x\n",
540 count,
541 rtlphy->mcs_txpwrlevel_origoffset[count][6]);
542 }
543 if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00) {
544 rtlphy->mcs_txpwrlevel_origoffset[count][7] = data;
545 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
546 "MCSTxPowerLevelOriginalOffset[%d][7] = 0x%x\n",
547 count,
548 rtlphy->mcs_txpwrlevel_origoffset[count][7]);
549 }
550 if (regaddr == RTXAGC_A_MCS03_MCS00) {
551 rtlphy->mcs_txpwrlevel_origoffset[count][2] = data;
552 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
553 "MCSTxPowerLevelOriginalOffset[%d][2] = 0x%x\n",
554 count,
555 rtlphy->mcs_txpwrlevel_origoffset[count][2]);
556 }
557 if (regaddr == RTXAGC_A_MCS07_MCS04) {
558 rtlphy->mcs_txpwrlevel_origoffset[count][3] = data;
559 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
560 "MCSTxPowerLevelOriginalOffset[%d][3] = 0x%x\n",
561 count,
562 rtlphy->mcs_txpwrlevel_origoffset[count][3]);
563 }
564 if (regaddr == RTXAGC_A_MCS11_MCS08) {
565 rtlphy->mcs_txpwrlevel_origoffset[count][4] = data;
566 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
567 "MCSTxPowerLevelOriginalOffset[%d][4] = 0x%x\n",
568 count,
569 rtlphy->mcs_txpwrlevel_origoffset[count][4]);
570 }
571 if (regaddr == RTXAGC_A_MCS15_MCS12) {
572 rtlphy->mcs_txpwrlevel_origoffset[count][5] = data;
573 if (get_rf_type(rtlphy) == RF_1T1R) {
574 count++;
575 rtlphy->pwrgroup_cnt = count;
576 }
577 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
578 "MCSTxPowerLevelOriginalOffset[%d][5] = 0x%x\n",
579 count,
580 rtlphy->mcs_txpwrlevel_origoffset[count][5]);
581 }
582 if (regaddr == RTXAGC_B_RATE18_06) {
583 rtlphy->mcs_txpwrlevel_origoffset[count][8] = data;
584 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
585 "MCSTxPowerLevelOriginalOffset[%d][8] = 0x%x\n",
586 count,
587 rtlphy->mcs_txpwrlevel_origoffset[count][8]);
588 }
589 if (regaddr == RTXAGC_B_RATE54_24) {
590 rtlphy->mcs_txpwrlevel_origoffset[count][9] = data;
591 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
592 "MCSTxPowerLevelOriginalOffset[%d][9] = 0x%x\n",
593 count,
594 rtlphy->mcs_txpwrlevel_origoffset[count][9]);
595 }
596 if (regaddr == RTXAGC_B_CCK1_55_MCS32) {
597 rtlphy->mcs_txpwrlevel_origoffset[count][14] = data;
598 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
599 "MCSTxPowerLevelOriginalOffset[%d][14] = 0x%x\n",
600 count,
601 rtlphy->mcs_txpwrlevel_origoffset[count][14]);
602 }
603 if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff) {
604 rtlphy->mcs_txpwrlevel_origoffset[count][15] = data;
605 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
606 "MCSTxPowerLevelOriginalOffset[%d][15] = 0x%x\n",
607 count,
608 rtlphy->mcs_txpwrlevel_origoffset[count][15]);
609 }
610 if (regaddr == RTXAGC_B_MCS03_MCS00) {
611 rtlphy->mcs_txpwrlevel_origoffset[count][10] = data;
612 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
613 "MCSTxPowerLevelOriginalOffset[%d][10] = 0x%x\n",
614 count,
615 rtlphy->mcs_txpwrlevel_origoffset[count][10]);
616 }
617 if (regaddr == RTXAGC_B_MCS07_MCS04) {
618 rtlphy->mcs_txpwrlevel_origoffset[count][11] = data;
619 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
620 "MCSTxPowerLevelOriginalOffset[%d][11] = 0x%x\n",
621 count,
622 rtlphy->mcs_txpwrlevel_origoffset[count][11]);
623 }
624 if (regaddr == RTXAGC_B_MCS11_MCS08) {
625 rtlphy->mcs_txpwrlevel_origoffset[count][12] = data;
626 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
627 "MCSTxPowerLevelOriginalOffset[%d][12] = 0x%x\n",
628 count,
629 rtlphy->mcs_txpwrlevel_origoffset[count][12]);
630 }
631 if (regaddr == RTXAGC_B_MCS15_MCS12) {
632 rtlphy->mcs_txpwrlevel_origoffset[count][13] = data;
633 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
634 "MCSTxPowerLevelOriginalOffset[%d][13] = 0x%x\n",
635 count,
636 rtlphy->mcs_txpwrlevel_origoffset[count][13]);
637 if (get_rf_type(rtlphy) != RF_1T1R) {
638 count++;
639 rtlphy->pwrgroup_cnt = count;
640 }
641 }
642 }
643
644 static bool phy_config_bb_with_pghdr(struct ieee80211_hw *hw, u8 configtype)
645 {
646 struct rtl_priv *rtlpriv = rtl_priv(hw);
647 int i;
648 u32 *phy_reg_page;
649 u16 phy_reg_page_len;
650 u32 v1 = 0, v2 = 0;
651
652 phy_reg_page_len = RTL8188EEPHY_REG_ARRAY_PGLEN;
653 phy_reg_page = RTL8188EEPHY_REG_ARRAY_PG;
654
655 if (configtype == BASEBAND_CONFIG_PHY_REG) {
656 for (i = 0; i < phy_reg_page_len; i = i + 3) {
657 v1 = phy_reg_page[i];
658 v2 = phy_reg_page[i+1];
659
660 if (v1 < 0xcdcdcdcd) {
661 if (phy_reg_page[i] == 0xfe)
662 mdelay(50);
663 else if (phy_reg_page[i] == 0xfd)
664 mdelay(5);
665 else if (phy_reg_page[i] == 0xfc)
666 mdelay(1);
667 else if (phy_reg_page[i] == 0xfb)
668 udelay(50);
669 else if (phy_reg_page[i] == 0xfa)
670 udelay(5);
671 else if (phy_reg_page[i] == 0xf9)
672 udelay(1);
673
674 store_pwrindex_rate_offset(hw, phy_reg_page[i],
675 phy_reg_page[i + 1],
676 phy_reg_page[i + 2]);
677 continue;
678 } else {
679 if (!_rtl88e_check_condition(hw,
680 phy_reg_page[i])) {
681 /*don't need the hw_body*/
682 i += 2; /* skip the pair of expression*/
683 /* to protect 'i+1' 'i+2' not overrun */
684 if (i >= phy_reg_page_len - 2)
685 break;
686
687 v1 = phy_reg_page[i];
688 v2 = phy_reg_page[i+1];
689 while (v2 != 0xDEAD &&
690 i < phy_reg_page_len - 5) {
691 i += 3;
692 v1 = phy_reg_page[i];
693 v2 = phy_reg_page[i+1];
694 }
695 }
696 }
697 }
698 } else {
699 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
700 "configtype != BaseBand_Config_PHY_REG\n");
701 }
702 return true;
703 }
704
705 #define READ_NEXT_RF_PAIR(v1, v2, i) \
706 do { \
707 i += 2; \
708 v1 = radioa_array_table[i]; \
709 v2 = radioa_array_table[i+1]; \
710 } while (0)
711
712 static void process_path_a(struct ieee80211_hw *hw,
713 u16 radioa_arraylen,
714 u32 *radioa_array_table)
715 {
716 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
717 u32 v1, v2;
718 int i;
719
720 for (i = 0; i < radioa_arraylen; i = i + 2) {
721 v1 = radioa_array_table[i];
722 v2 = radioa_array_table[i+1];
723 if (v1 < 0xcdcdcdcd) {
724 _rtl8188e_config_rf_radio_a(hw, v1, v2);
725 } else { /*This line is the start line of branch.*/
726 /* to protect READ_NEXT_PAIR not overrun */
727 if (i >= radioa_arraylen - 2)
728 break;
729
730 if (!_rtl88e_check_condition(hw, radioa_array_table[i])) {
731 /*Discard the following (offset, data) pairs*/
732 READ_NEXT_RF_PAIR(v1, v2, i);
733 while (v2 != 0xDEAD &&
734 v2 != 0xCDEF &&
735 v2 != 0xCDCD &&
736 i < radioa_arraylen - 2) {
737 READ_NEXT_RF_PAIR(v1, v2, i);
738 }
739 i -= 2; /* prevent from for-loop += 2*/
740 } else { /* Configure matched pairs and
741 * skip to end of if-else.
742 */
743 READ_NEXT_RF_PAIR(v1, v2, i);
744 while (v2 != 0xDEAD &&
745 v2 != 0xCDEF &&
746 v2 != 0xCDCD &&
747 i < radioa_arraylen - 2) {
748 _rtl8188e_config_rf_radio_a(hw, v1, v2);
749 READ_NEXT_RF_PAIR(v1, v2, i);
750 }
751
752 while (v2 != 0xDEAD &&
753 i < radioa_arraylen - 2)
754 READ_NEXT_RF_PAIR(v1, v2, i);
755 }
756 }
757 }
758
759 if (rtlhal->oem_id == RT_CID_819X_HP)
760 _rtl8188e_config_rf_radio_a(hw, 0x52, 0x7E4BD);
761 }
762
763 bool rtl88e_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
764 enum radio_path rfpath)
765 {
766 struct rtl_priv *rtlpriv = rtl_priv(hw);
767 u32 *radioa_array_table;
768 u16 radioa_arraylen;
769
770 radioa_arraylen = RTL8188EE_RADIOA_1TARRAYLEN;
771 radioa_array_table = RTL8188EE_RADIOA_1TARRAY;
772 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
773 "Radio_A:RTL8188EE_RADIOA_1TARRAY %d\n", radioa_arraylen);
774 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Radio No %x\n", rfpath);
775 switch (rfpath) {
776 case RF90_PATH_A:
777 process_path_a(hw, radioa_arraylen, radioa_array_table);
778 break;
779 case RF90_PATH_B:
780 case RF90_PATH_C:
781 case RF90_PATH_D:
782 break;
783 }
784 return true;
785 }
786
787 void rtl88e_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
788 {
789 struct rtl_priv *rtlpriv = rtl_priv(hw);
790 struct rtl_phy *rtlphy = &rtlpriv->phy;
791
792 rtlphy->default_initialgain[0] =
793 (u8)rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0);
794 rtlphy->default_initialgain[1] =
795 (u8)rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0);
796 rtlphy->default_initialgain[2] =
797 (u8)rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0);
798 rtlphy->default_initialgain[3] =
799 (u8)rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0);
800
801 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
802 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n",
803 rtlphy->default_initialgain[0],
804 rtlphy->default_initialgain[1],
805 rtlphy->default_initialgain[2],
806 rtlphy->default_initialgain[3]);
807
808 rtlphy->framesync = (u8)rtl_get_bbreg(hw, ROFDM0_RXDETECTOR3,
809 MASKBYTE0);
810 rtlphy->framesync_c34 = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR2,
811 MASKDWORD);
812
813 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
814 "Default framesync (0x%x) = 0x%x\n",
815 ROFDM0_RXDETECTOR3, rtlphy->framesync);
816 }
817
818 static void _rtl88e_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw)
819 {
820 struct rtl_priv *rtlpriv = rtl_priv(hw);
821 struct rtl_phy *rtlphy = &rtlpriv->phy;
822
823 rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;
824 rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;
825 rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW;
826 rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW;
827
828 rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB;
829 rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB;
830 rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB;
831 rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB;
832
833 rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE;
834 rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;
835
836 rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE;
837 rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;
838
839 rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset =
840 RFPGA0_XA_LSSIPARAMETER;
841 rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset =
842 RFPGA0_XB_LSSIPARAMETER;
843
844 rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = RFPGA0_XAB_RFPARAMETER;
845 rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = RFPGA0_XAB_RFPARAMETER;
846 rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = RFPGA0_XCD_RFPARAMETER;
847 rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = RFPGA0_XCD_RFPARAMETER;
848
849 rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE;
850 rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE;
851 rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE;
852 rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE;
853
854 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1;
855 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1;
856
857 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2;
858 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2;
859
860 rtlphy->phyreg_def[RF90_PATH_A].rfsw_ctrl =
861 RFPGA0_XAB_SWITCHCONTROL;
862 rtlphy->phyreg_def[RF90_PATH_B].rfsw_ctrl =
863 RFPGA0_XAB_SWITCHCONTROL;
864 rtlphy->phyreg_def[RF90_PATH_C].rfsw_ctrl =
865 RFPGA0_XCD_SWITCHCONTROL;
866 rtlphy->phyreg_def[RF90_PATH_D].rfsw_ctrl =
867 RFPGA0_XCD_SWITCHCONTROL;
868
869 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1;
870 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1;
871 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1;
872 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1;
873
874 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2;
875 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2;
876 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2;
877 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2;
878
879 rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbal = ROFDM0_XARXIQIMBALANCE;
880 rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbal = ROFDM0_XBRXIQIMBALANCE;
881 rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbal = ROFDM0_XCRXIQIMBANLANCE;
882 rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbal = ROFDM0_XDRXIQIMBALANCE;
883
884 rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE;
885 rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE;
886 rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE;
887 rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE;
888
889 rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbal = ROFDM0_XATXIQIMBALANCE;
890 rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbal = ROFDM0_XBTXIQIMBALANCE;
891 rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbal = ROFDM0_XCTXIQIMBALANCE;
892 rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbal = ROFDM0_XDTXIQIMBALANCE;
893
894 rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATXAFE;
895 rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTXAFE;
896
897 rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RFPGA0_XA_LSSIREADBACK;
898 rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK;
899
900 rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = TRANSCEIVEA_HSPI_READBACK;
901 rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVEB_HSPI_READBACK;
902 }
903
904 void rtl88e_phy_get_txpower_level(struct ieee80211_hw *hw, long *powerlevel)
905 {
906 struct rtl_priv *rtlpriv = rtl_priv(hw);
907 struct rtl_phy *rtlphy = &rtlpriv->phy;
908 u8 txpwr_level;
909 long txpwr_dbm;
910
911 txpwr_level = rtlphy->cur_cck_txpwridx;
912 txpwr_dbm = _rtl88e_phy_txpwr_idx_to_dbm(hw,
913 WIRELESS_MODE_B, txpwr_level);
914 txpwr_level = rtlphy->cur_ofdm24g_txpwridx;
915 if (_rtl88e_phy_txpwr_idx_to_dbm(hw,
916 WIRELESS_MODE_G,
917 txpwr_level) > txpwr_dbm)
918 txpwr_dbm =
919 _rtl88e_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_G,
920 txpwr_level);
921 txpwr_level = rtlphy->cur_ofdm24g_txpwridx;
922 if (_rtl88e_phy_txpwr_idx_to_dbm(hw,
923 WIRELESS_MODE_N_24G,
924 txpwr_level) > txpwr_dbm)
925 txpwr_dbm =
926 _rtl88e_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_N_24G,
927 txpwr_level);
928 *powerlevel = txpwr_dbm;
929 }
930
931 static void handle_path_a(struct rtl_efuse *rtlefuse, u8 index,
932 u8 *cckpowerlevel, u8 *ofdmpowerlevel,
933 u8 *bw20powerlevel, u8 *bw40powerlevel)
934 {
935 cckpowerlevel[RF90_PATH_A] =
936 rtlefuse->txpwrlevel_cck[RF90_PATH_A][index];
937 /*-8~7 */
938 if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][index] > 0x0f)
939 bw20powerlevel[RF90_PATH_A] =
940 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_A][index] -
941 (~(rtlefuse->txpwr_ht20diff[RF90_PATH_A][index]) + 1);
942 else
943 bw20powerlevel[RF90_PATH_A] =
944 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_A][index] +
945 rtlefuse->txpwr_ht20diff[RF90_PATH_A][index];
946 if (rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][index] > 0xf)
947 ofdmpowerlevel[RF90_PATH_A] =
948 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_A][index] -
949 (~(rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][index])+1);
950 else
951 ofdmpowerlevel[RF90_PATH_A] =
952 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_A][index] +
953 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][index];
954 bw40powerlevel[RF90_PATH_A] =
955 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_A][index];
956 }
957
958 static void _rtl88e_get_txpower_index(struct ieee80211_hw *hw, u8 channel,
959 u8 *cckpowerlevel, u8 *ofdmpowerlevel,
960 u8 *bw20powerlevel, u8 *bw40powerlevel)
961 {
962 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
963 u8 index = (channel - 1);
964 u8 rf_path = 0;
965
966 for (rf_path = 0; rf_path < 2; rf_path++) {
967 if (rf_path == RF90_PATH_A) {
968 handle_path_a(rtlefuse, index, cckpowerlevel,
969 ofdmpowerlevel, bw20powerlevel,
970 bw40powerlevel);
971 } else if (rf_path == RF90_PATH_B) {
972 cckpowerlevel[RF90_PATH_B] =
973 rtlefuse->txpwrlevel_cck[RF90_PATH_B][index];
974 bw20powerlevel[RF90_PATH_B] =
975 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_B][index] +
976 rtlefuse->txpwr_ht20diff[RF90_PATH_B][index];
977 ofdmpowerlevel[RF90_PATH_B] =
978 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_B][index] +
979 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][index];
980 bw40powerlevel[RF90_PATH_B] =
981 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_B][index];
982 }
983 }
984
985 }
986
987 static void _rtl88e_ccxpower_index_check(struct ieee80211_hw *hw,
988 u8 channel, u8 *cckpowerlevel,
989 u8 *ofdmpowerlevel, u8 *bw20powerlevel,
990 u8 *bw40powerlevel)
991 {
992 struct rtl_priv *rtlpriv = rtl_priv(hw);
993 struct rtl_phy *rtlphy = &rtlpriv->phy;
994
995 rtlphy->cur_cck_txpwridx = cckpowerlevel[0];
996 rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0];
997 rtlphy->cur_bw20_txpwridx = bw20powerlevel[0];
998 rtlphy->cur_bw40_txpwridx = bw40powerlevel[0];
999
1000 }
1001
1002 void rtl88e_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel)
1003 {
1004 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1005 u8 cckpowerlevel[MAX_TX_COUNT] = {0};
1006 u8 ofdmpowerlevel[MAX_TX_COUNT] = {0};
1007 u8 bw20powerlevel[MAX_TX_COUNT] = {0};
1008 u8 bw40powerlevel[MAX_TX_COUNT] = {0};
1009
1010 if (!rtlefuse->txpwr_fromeprom)
1011 return;
1012 _rtl88e_get_txpower_index(hw, channel,
1013 &cckpowerlevel[0], &ofdmpowerlevel[0],
1014 &bw20powerlevel[0], &bw40powerlevel[0]);
1015 _rtl88e_ccxpower_index_check(hw, channel,
1016 &cckpowerlevel[0], &ofdmpowerlevel[0],
1017 &bw20powerlevel[0], &bw40powerlevel[0]);
1018 rtl88e_phy_rf6052_set_cck_txpower(hw, &cckpowerlevel[0]);
1019 rtl88e_phy_rf6052_set_ofdm_txpower(hw, &ofdmpowerlevel[0],
1020 &bw20powerlevel[0],
1021 &bw40powerlevel[0], channel);
1022 }
1023
1024 static long _rtl88e_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw,
1025 enum wireless_mode wirelessmode,
1026 u8 txpwridx)
1027 {
1028 long offset;
1029 long pwrout_dbm;
1030
1031 switch (wirelessmode) {
1032 case WIRELESS_MODE_B:
1033 offset = -7;
1034 break;
1035 case WIRELESS_MODE_G:
1036 case WIRELESS_MODE_N_24G:
1037 offset = -8;
1038 break;
1039 default:
1040 offset = -8;
1041 break;
1042 }
1043 pwrout_dbm = txpwridx / 2 + offset;
1044 return pwrout_dbm;
1045 }
1046
1047 void rtl88e_phy_scan_operation_backup(struct ieee80211_hw *hw, u8 operation)
1048 {
1049 struct rtl_priv *rtlpriv = rtl_priv(hw);
1050 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1051 enum io_type iotype;
1052
1053 if (!is_hal_stop(rtlhal)) {
1054 switch (operation) {
1055 case SCAN_OPT_BACKUP_BAND0:
1056 iotype = IO_CMD_PAUSE_BAND0_DM_BY_SCAN;
1057 rtlpriv->cfg->ops->set_hw_reg(hw,
1058 HW_VAR_IO_CMD,
1059 (u8 *)&iotype);
1060
1061 break;
1062 case SCAN_OPT_RESTORE:
1063 iotype = IO_CMD_RESUME_DM_BY_SCAN;
1064 rtlpriv->cfg->ops->set_hw_reg(hw,
1065 HW_VAR_IO_CMD,
1066 (u8 *)&iotype);
1067 break;
1068 default:
1069 pr_err("Unknown Scan Backup operation.\n");
1070 break;
1071 }
1072 }
1073 }
1074
1075 void rtl88e_phy_set_bw_mode_callback(struct ieee80211_hw *hw)
1076 {
1077 struct rtl_priv *rtlpriv = rtl_priv(hw);
1078 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1079 struct rtl_phy *rtlphy = &rtlpriv->phy;
1080 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1081 u8 reg_bw_opmode;
1082 u8 reg_prsr_rsc;
1083
1084 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
1085 "Switch to %s bandwidth\n",
1086 rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
1087 "20MHz" : "40MHz");
1088
1089 if (is_hal_stop(rtlhal)) {
1090 rtlphy->set_bwmode_inprogress = false;
1091 return;
1092 }
1093
1094 reg_bw_opmode = rtl_read_byte(rtlpriv, REG_BWOPMODE);
1095 reg_prsr_rsc = rtl_read_byte(rtlpriv, REG_RRSR + 2);
1096
1097 switch (rtlphy->current_chan_bw) {
1098 case HT_CHANNEL_WIDTH_20:
1099 reg_bw_opmode |= BW_OPMODE_20MHZ;
1100 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
1101 break;
1102 case HT_CHANNEL_WIDTH_20_40:
1103 reg_bw_opmode &= ~BW_OPMODE_20MHZ;
1104 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
1105 reg_prsr_rsc =
1106 (reg_prsr_rsc & 0x90) | (mac->cur_40_prime_sc << 5);
1107 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_prsr_rsc);
1108 break;
1109 default:
1110 pr_err("unknown bandwidth: %#X\n",
1111 rtlphy->current_chan_bw);
1112 break;
1113 }
1114
1115 switch (rtlphy->current_chan_bw) {
1116 case HT_CHANNEL_WIDTH_20:
1117 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0);
1118 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0);
1119 /* rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);*/
1120 break;
1121 case HT_CHANNEL_WIDTH_20_40:
1122 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1);
1123 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1);
1124
1125 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND,
1126 (mac->cur_40_prime_sc >> 1));
1127 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc);
1128 /*rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 0);*/
1129
1130 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)),
1131 (mac->cur_40_prime_sc ==
1132 HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
1133 break;
1134 default:
1135 pr_err("unknown bandwidth: %#X\n",
1136 rtlphy->current_chan_bw);
1137 break;
1138 }
1139 rtl88e_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
1140 rtlphy->set_bwmode_inprogress = false;
1141 RT_TRACE(rtlpriv, COMP_SCAN, DBG_LOUD, "\n");
1142 }
1143
1144 void rtl88e_phy_set_bw_mode(struct ieee80211_hw *hw,
1145 enum nl80211_channel_type ch_type)
1146 {
1147 struct rtl_priv *rtlpriv = rtl_priv(hw);
1148 struct rtl_phy *rtlphy = &rtlpriv->phy;
1149 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1150 u8 tmp_bw = rtlphy->current_chan_bw;
1151
1152 if (rtlphy->set_bwmode_inprogress)
1153 return;
1154 rtlphy->set_bwmode_inprogress = true;
1155 if ((!is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) {
1156 rtl88e_phy_set_bw_mode_callback(hw);
1157 } else {
1158 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1159 "false driver sleep or unload\n");
1160 rtlphy->set_bwmode_inprogress = false;
1161 rtlphy->current_chan_bw = tmp_bw;
1162 }
1163 }
1164
1165 void rtl88e_phy_sw_chnl_callback(struct ieee80211_hw *hw)
1166 {
1167 struct rtl_priv *rtlpriv = rtl_priv(hw);
1168 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1169 struct rtl_phy *rtlphy = &rtlpriv->phy;
1170 u32 delay;
1171
1172 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
1173 "switch to channel%d\n", rtlphy->current_channel);
1174 if (is_hal_stop(rtlhal))
1175 return;
1176 do {
1177 if (!rtlphy->sw_chnl_inprogress)
1178 break;
1179 if (!_rtl88e_phy_sw_chnl_step_by_step
1180 (hw, rtlphy->current_channel, &rtlphy->sw_chnl_stage,
1181 &rtlphy->sw_chnl_step, &delay)) {
1182 if (delay > 0)
1183 mdelay(delay);
1184 else
1185 continue;
1186 } else {
1187 rtlphy->sw_chnl_inprogress = false;
1188 }
1189 break;
1190 } while (true);
1191 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "\n");
1192 }
1193
1194 u8 rtl88e_phy_sw_chnl(struct ieee80211_hw *hw)
1195 {
1196 struct rtl_priv *rtlpriv = rtl_priv(hw);
1197 struct rtl_phy *rtlphy = &rtlpriv->phy;
1198 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1199
1200 if (rtlphy->sw_chnl_inprogress)
1201 return 0;
1202 if (rtlphy->set_bwmode_inprogress)
1203 return 0;
1204 WARN_ONCE((rtlphy->current_channel > 14),
1205 "rtl8188ee: WIRELESS_MODE_G but channel>14");
1206 rtlphy->sw_chnl_inprogress = true;
1207 rtlphy->sw_chnl_stage = 0;
1208 rtlphy->sw_chnl_step = 0;
1209 if (!(is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) {
1210 rtl88e_phy_sw_chnl_callback(hw);
1211 RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD,
1212 "sw_chnl_inprogress false schedule workitem current channel %d\n",
1213 rtlphy->current_channel);
1214 rtlphy->sw_chnl_inprogress = false;
1215 } else {
1216 RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD,
1217 "sw_chnl_inprogress false driver sleep or unload\n");
1218 rtlphy->sw_chnl_inprogress = false;
1219 }
1220 return 1;
1221 }
1222
1223 static bool _rtl88e_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
1224 u8 channel, u8 *stage, u8 *step,
1225 u32 *delay)
1226 {
1227 struct rtl_priv *rtlpriv = rtl_priv(hw);
1228 struct rtl_phy *rtlphy = &rtlpriv->phy;
1229 struct swchnlcmd precommoncmd[MAX_PRECMD_CNT];
1230 u32 precommoncmdcnt;
1231 struct swchnlcmd postcommoncmd[MAX_POSTCMD_CNT];
1232 u32 postcommoncmdcnt;
1233 struct swchnlcmd rfdependcmd[MAX_RFDEPENDCMD_CNT];
1234 u32 rfdependcmdcnt;
1235 struct swchnlcmd *currentcmd = NULL;
1236 u8 rfpath;
1237 u8 num_total_rfpath = rtlphy->num_total_rfpath;
1238
1239 precommoncmdcnt = 0;
1240 _rtl88e_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
1241 MAX_PRECMD_CNT,
1242 CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0);
1243 _rtl88e_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
1244 MAX_PRECMD_CNT, CMDID_END, 0, 0, 0);
1245
1246 postcommoncmdcnt = 0;
1247
1248 _rtl88e_phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++,
1249 MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0);
1250
1251 rfdependcmdcnt = 0;
1252
1253 WARN_ONCE((channel < 1 || channel > 14),
1254 "rtl8188ee: illegal channel for Zebra: %d\n", channel);
1255
1256 _rtl88e_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
1257 MAX_RFDEPENDCMD_CNT, CMDID_RF_WRITEREG,
1258 RF_CHNLBW, channel, 10);
1259
1260 _rtl88e_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
1261 MAX_RFDEPENDCMD_CNT, CMDID_END, 0, 0,
1262 0);
1263
1264 do {
1265 switch (*stage) {
1266 case 0:
1267 currentcmd = &precommoncmd[*step];
1268 break;
1269 case 1:
1270 currentcmd = &rfdependcmd[*step];
1271 break;
1272 case 2:
1273 currentcmd = &postcommoncmd[*step];
1274 break;
1275 default:
1276 pr_err("Invalid 'stage' = %d, Check it!\n",
1277 *stage);
1278 return true;
1279 }
1280
1281 if (currentcmd->cmdid == CMDID_END) {
1282 if ((*stage) == 2)
1283 return true;
1284 (*stage)++;
1285 (*step) = 0;
1286 continue;
1287 }
1288
1289 switch (currentcmd->cmdid) {
1290 case CMDID_SET_TXPOWEROWER_LEVEL:
1291 rtl88e_phy_set_txpower_level(hw, channel);
1292 break;
1293 case CMDID_WRITEPORT_ULONG:
1294 rtl_write_dword(rtlpriv, currentcmd->para1,
1295 currentcmd->para2);
1296 break;
1297 case CMDID_WRITEPORT_USHORT:
1298 rtl_write_word(rtlpriv, currentcmd->para1,
1299 (u16)currentcmd->para2);
1300 break;
1301 case CMDID_WRITEPORT_UCHAR:
1302 rtl_write_byte(rtlpriv, currentcmd->para1,
1303 (u8)currentcmd->para2);
1304 break;
1305 case CMDID_RF_WRITEREG:
1306 for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) {
1307 rtlphy->rfreg_chnlval[rfpath] =
1308 ((rtlphy->rfreg_chnlval[rfpath] &
1309 0xfffffc00) | currentcmd->para2);
1310
1311 rtl_set_rfreg(hw, (enum radio_path)rfpath,
1312 currentcmd->para1,
1313 RFREG_OFFSET_MASK,
1314 rtlphy->rfreg_chnlval[rfpath]);
1315 }
1316 break;
1317 default:
1318 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
1319 "switch case %#x not processed\n",
1320 currentcmd->cmdid);
1321 break;
1322 }
1323
1324 break;
1325 } while (true);
1326
1327 (*delay) = currentcmd->msdelay;
1328 (*step)++;
1329 return false;
1330 }
1331
1332 static bool _rtl88e_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
1333 u32 cmdtableidx, u32 cmdtablesz,
1334 enum swchnlcmd_id cmdid,
1335 u32 para1, u32 para2, u32 msdelay)
1336 {
1337 struct swchnlcmd *pcmd;
1338
1339 if (cmdtable == NULL) {
1340 WARN_ONCE(true, "rtl8188ee: cmdtable cannot be NULL.\n");
1341 return false;
1342 }
1343
1344 if (cmdtableidx >= cmdtablesz)
1345 return false;
1346
1347 pcmd = cmdtable + cmdtableidx;
1348 pcmd->cmdid = cmdid;
1349 pcmd->para1 = para1;
1350 pcmd->para2 = para2;
1351 pcmd->msdelay = msdelay;
1352 return true;
1353 }
1354
1355 static u8 _rtl88e_phy_path_a_iqk(struct ieee80211_hw *hw, bool config_pathb)
1356 {
1357 u32 reg_eac, reg_e94, reg_e9c, reg_ea4;
1358 u8 result = 0x00;
1359
1360 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c1c);
1361 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x30008c1c);
1362 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x8214032a);
1363 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x28160000);
1364
1365 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911);
1366 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000);
1367 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000);
1368
1369 mdelay(IQK_DELAY_TIME);
1370
1371 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1372 reg_e94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD);
1373 reg_e9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD);
1374 reg_ea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD);
1375
1376 if (!(reg_eac & BIT(28)) &&
1377 (((reg_e94 & 0x03FF0000) >> 16) != 0x142) &&
1378 (((reg_e9c & 0x03FF0000) >> 16) != 0x42))
1379 result |= 0x01;
1380 return result;
1381 }
1382
1383 static u8 _rtl88e_phy_path_b_iqk(struct ieee80211_hw *hw)
1384 {
1385 u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc;
1386 u8 result = 0x00;
1387
1388 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000002);
1389 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000000);
1390 mdelay(IQK_DELAY_TIME);
1391 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1392 reg_eb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD);
1393 reg_ebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD);
1394 reg_ec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD);
1395 reg_ecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD);
1396
1397 if (!(reg_eac & BIT(31)) &&
1398 (((reg_eb4 & 0x03FF0000) >> 16) != 0x142) &&
1399 (((reg_ebc & 0x03FF0000) >> 16) != 0x42))
1400 result |= 0x01;
1401 else
1402 return result;
1403 if (!(reg_eac & BIT(30)) &&
1404 (((reg_ec4 & 0x03FF0000) >> 16) != 0x132) &&
1405 (((reg_ecc & 0x03FF0000) >> 16) != 0x36))
1406 result |= 0x02;
1407 return result;
1408 }
1409
1410 static u8 _rtl88e_phy_path_a_rx_iqk(struct ieee80211_hw *hw, bool config_pathb)
1411 {
1412 u32 reg_eac, reg_e94, reg_e9c, reg_ea4, u32temp;
1413 u8 result = 0x00;
1414
1415 /*Get TXIMR Setting*/
1416 /*Modify RX IQK mode table*/
1417 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
1418 rtl_set_rfreg(hw, RF90_PATH_A, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0);
1419 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000);
1420 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f);
1421 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf117b);
1422 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);
1423
1424 /*IQK Setting*/
1425 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00);
1426 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x81004800);
1427
1428 /*path a IQK setting*/
1429 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x10008c1c);
1430 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x30008c1c);
1431 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160804);
1432 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28160000);
1433
1434 /*LO calibration Setting*/
1435 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911);
1436 /*one shot,path A LOK & iqk*/
1437 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000);
1438 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);
1439
1440 mdelay(IQK_DELAY_TIME);
1441
1442 reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);
1443 reg_e94 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, MASKDWORD);
1444 reg_e9c = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, MASKDWORD);
1445
1446
1447 if (!(reg_eac & BIT(28)) &&
1448 (((reg_e94 & 0x03FF0000) >> 16) != 0x142) &&
1449 (((reg_e9c & 0x03FF0000) >> 16) != 0x42))
1450 result |= 0x01;
1451 else
1452 return result;
1453
1454 u32temp = 0x80007C00 | (reg_e94&0x3FF0000) |
1455 ((reg_e9c&0x3FF0000) >> 16);
1456 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, u32temp);
1457 /*RX IQK*/
1458 /*Modify RX IQK mode table*/
1459 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000);
1460 rtl_set_rfreg(hw, RF90_PATH_A, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0);
1461 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000);
1462 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f);
1463 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf7ffa);
1464 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000);
1465
1466 /*IQK Setting*/
1467 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800);
1468
1469 /*path a IQK setting*/
1470 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x30008c1c);
1471 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x10008c1c);
1472 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160c05);
1473 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28160c05);
1474
1475 /*LO calibration Setting*/
1476 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911);
1477 /*one shot,path A LOK & iqk*/
1478 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000);
1479 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000);
1480
1481 mdelay(IQK_DELAY_TIME);
1482
1483 reg_eac = rtl_get_bbreg(hw, RRX_POWER_AFTER_IQK_A_2, MASKDWORD);
1484 reg_e94 = rtl_get_bbreg(hw, RTX_POWER_BEFORE_IQK_A, MASKDWORD);
1485 reg_e9c = rtl_get_bbreg(hw, RTX_POWER_AFTER_IQK_A, MASKDWORD);
1486 reg_ea4 = rtl_get_bbreg(hw, RRX_POWER_BEFORE_IQK_A_2, MASKDWORD);
1487
1488 if (!(reg_eac & BIT(27)) &&
1489 (((reg_ea4 & 0x03FF0000) >> 16) != 0x132) &&
1490 (((reg_eac & 0x03FF0000) >> 16) != 0x36))
1491 result |= 0x02;
1492 return result;
1493 }
1494
1495 static void _rtl88e_phy_path_a_fill_iqk_matrix(struct ieee80211_hw *hw,
1496 bool iqk_ok, long result[][8],
1497 u8 final_candidate, bool btxonly)
1498 {
1499 u32 oldval_0, x, tx0_a, reg;
1500 long y, tx0_c;
1501
1502 if (final_candidate == 0xFF) {
1503 return;
1504 } else if (iqk_ok) {
1505 oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
1506 MASKDWORD) >> 22) & 0x3FF;
1507 x = result[final_candidate][0];
1508 if ((x & 0x00000200) != 0)
1509 x = x | 0xFFFFFC00;
1510 tx0_a = (x * oldval_0) >> 8;
1511 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx0_a);
1512 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(31),
1513 ((x * oldval_0 >> 7) & 0x1));
1514 y = result[final_candidate][1];
1515 if ((y & 0x00000200) != 0)
1516 y = y | 0xFFFFFC00;
1517 tx0_c = (y * oldval_0) >> 8;
1518 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000,
1519 ((tx0_c & 0x3C0) >> 6));
1520 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x003F0000,
1521 (tx0_c & 0x3F));
1522 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(29),
1523 ((y * oldval_0 >> 7) & 0x1));
1524 if (btxonly)
1525 return;
1526 reg = result[final_candidate][2];
1527 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg);
1528 reg = result[final_candidate][3] & 0x3F;
1529 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg);
1530 reg = (result[final_candidate][3] >> 6) & 0xF;
1531 rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg);
1532 }
1533 }
1534
1535 static void _rtl88e_phy_save_adda_registers(struct ieee80211_hw *hw,
1536 u32 *addareg, u32 *addabackup,
1537 u32 registernum)
1538 {
1539 u32 i;
1540
1541 for (i = 0; i < registernum; i++)
1542 addabackup[i] = rtl_get_bbreg(hw, addareg[i], MASKDWORD);
1543 }
1544
1545 static void _rtl88e_phy_save_mac_registers(struct ieee80211_hw *hw,
1546 u32 *macreg, u32 *macbackup)
1547 {
1548 struct rtl_priv *rtlpriv = rtl_priv(hw);
1549 u32 i;
1550
1551 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1552 macbackup[i] = rtl_read_byte(rtlpriv, macreg[i]);
1553 macbackup[i] = rtl_read_dword(rtlpriv, macreg[i]);
1554 }
1555
1556 static void _rtl88e_phy_reload_adda_registers(struct ieee80211_hw *hw,
1557 u32 *addareg, u32 *addabackup,
1558 u32 regiesternum)
1559 {
1560 u32 i;
1561
1562 for (i = 0; i < regiesternum; i++)
1563 rtl_set_bbreg(hw, addareg[i], MASKDWORD, addabackup[i]);
1564 }
1565
1566 static void _rtl88e_phy_reload_mac_registers(struct ieee80211_hw *hw,
1567 u32 *macreg, u32 *macbackup)
1568 {
1569 struct rtl_priv *rtlpriv = rtl_priv(hw);
1570 u32 i;
1571
1572 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1573 rtl_write_byte(rtlpriv, macreg[i], (u8) macbackup[i]);
1574 rtl_write_dword(rtlpriv, macreg[i], macbackup[i]);
1575 }
1576
1577 static void _rtl88e_phy_path_adda_on(struct ieee80211_hw *hw,
1578 u32 *addareg, bool is_patha_on, bool is2t)
1579 {
1580 u32 pathon;
1581 u32 i;
1582
1583 pathon = is_patha_on ? 0x04db25a4 : 0x0b1b25a4;
1584 if (false == is2t) {
1585 pathon = 0x0bdb25a0;
1586 rtl_set_bbreg(hw, addareg[0], MASKDWORD, 0x0b1b25a0);
1587 } else {
1588 rtl_set_bbreg(hw, addareg[0], MASKDWORD, pathon);
1589 }
1590
1591 for (i = 1; i < IQK_ADDA_REG_NUM; i++)
1592 rtl_set_bbreg(hw, addareg[i], MASKDWORD, pathon);
1593 }
1594
1595 static void _rtl88e_phy_mac_setting_calibration(struct ieee80211_hw *hw,
1596 u32 *macreg, u32 *macbackup)
1597 {
1598 struct rtl_priv *rtlpriv = rtl_priv(hw);
1599 u32 i = 0;
1600
1601 rtl_write_byte(rtlpriv, macreg[i], 0x3F);
1602
1603 for (i = 1; i < (IQK_MAC_REG_NUM - 1); i++)
1604 rtl_write_byte(rtlpriv, macreg[i],
1605 (u8) (macbackup[i] & (~BIT(3))));
1606 rtl_write_byte(rtlpriv, macreg[i], (u8) (macbackup[i] & (~BIT(5))));
1607 }
1608
1609 static void _rtl88e_phy_path_a_standby(struct ieee80211_hw *hw)
1610 {
1611 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0);
1612 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000);
1613 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
1614 }
1615
1616 static void _rtl88e_phy_pi_mode_switch(struct ieee80211_hw *hw, bool pi_mode)
1617 {
1618 u32 mode;
1619
1620 mode = pi_mode ? 0x01000100 : 0x01000000;
1621 rtl_set_bbreg(hw, 0x820, MASKDWORD, mode);
1622 rtl_set_bbreg(hw, 0x828, MASKDWORD, mode);
1623 }
1624
1625 static bool _rtl88e_phy_simularity_compare(struct ieee80211_hw *hw,
1626 long result[][8], u8 c1, u8 c2)
1627 {
1628 u32 i, j, diff, simularity_bitmap, bound;
1629 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1630
1631 u8 final_candidate[2] = { 0xFF, 0xFF };
1632 bool bresult = true, is2t = IS_92C_SERIAL(rtlhal->version);
1633
1634 if (is2t)
1635 bound = 8;
1636 else
1637 bound = 4;
1638
1639 simularity_bitmap = 0;
1640
1641 for (i = 0; i < bound; i++) {
1642 diff = (result[c1][i] > result[c2][i]) ?
1643 (result[c1][i] - result[c2][i]) :
1644 (result[c2][i] - result[c1][i]);
1645
1646 if (diff > MAX_TOLERANCE) {
1647 if ((i == 2 || i == 6) && !simularity_bitmap) {
1648 if (result[c1][i] + result[c1][i + 1] == 0)
1649 final_candidate[(i / 4)] = c2;
1650 else if (result[c2][i] + result[c2][i + 1] == 0)
1651 final_candidate[(i / 4)] = c1;
1652 else
1653 simularity_bitmap = simularity_bitmap |
1654 (1 << i);
1655 } else
1656 simularity_bitmap =
1657 simularity_bitmap | (1 << i);
1658 }
1659 }
1660
1661 if (simularity_bitmap == 0) {
1662 for (i = 0; i < (bound / 4); i++) {
1663 if (final_candidate[i] != 0xFF) {
1664 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
1665 result[3][j] =
1666 result[final_candidate[i]][j];
1667 bresult = false;
1668 }
1669 }
1670 return bresult;
1671 } else if (!(simularity_bitmap & 0x0F)) {
1672 for (i = 0; i < 4; i++)
1673 result[3][i] = result[c1][i];
1674 return false;
1675 } else if (!(simularity_bitmap & 0xF0) && is2t) {
1676 for (i = 4; i < 8; i++)
1677 result[3][i] = result[c1][i];
1678 return false;
1679 } else {
1680 return false;
1681 }
1682
1683 }
1684
1685 static void _rtl88e_phy_iq_calibrate(struct ieee80211_hw *hw,
1686 long result[][8], u8 t, bool is2t)
1687 {
1688 struct rtl_priv *rtlpriv = rtl_priv(hw);
1689 struct rtl_phy *rtlphy = &rtlpriv->phy;
1690 u32 i;
1691 u8 patha_ok, pathb_ok;
1692 u32 adda_reg[IQK_ADDA_REG_NUM] = {
1693 0x85c, 0xe6c, 0xe70, 0xe74,
1694 0xe78, 0xe7c, 0xe80, 0xe84,
1695 0xe88, 0xe8c, 0xed0, 0xed4,
1696 0xed8, 0xedc, 0xee0, 0xeec
1697 };
1698 u32 iqk_mac_reg[IQK_MAC_REG_NUM] = {
1699 0x522, 0x550, 0x551, 0x040
1700 };
1701 u32 iqk_bb_reg[IQK_BB_REG_NUM] = {
1702 ROFDM0_TRXPATHENABLE, ROFDM0_TRMUXPAR,
1703 RFPGA0_XCD_RFINTERFACESW, 0xb68, 0xb6c,
1704 0x870, 0x860, 0x864, 0x800
1705 };
1706 const u32 retrycount = 2;
1707
1708 if (t == 0) {
1709 _rtl88e_phy_save_adda_registers(hw, adda_reg,
1710 rtlphy->adda_backup, 16);
1711 _rtl88e_phy_save_mac_registers(hw, iqk_mac_reg,
1712 rtlphy->iqk_mac_backup);
1713 _rtl88e_phy_save_adda_registers(hw, iqk_bb_reg,
1714 rtlphy->iqk_bb_backup,
1715 IQK_BB_REG_NUM);
1716 }
1717 _rtl88e_phy_path_adda_on(hw, adda_reg, true, is2t);
1718 if (t == 0) {
1719 rtlphy->rfpi_enable =
1720 (u8)rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1, BIT(8));
1721 }
1722
1723 if (!rtlphy->rfpi_enable)
1724 _rtl88e_phy_pi_mode_switch(hw, true);
1725 /*BB Setting*/
1726 rtl_set_bbreg(hw, 0x800, BIT(24), 0x00);
1727 rtl_set_bbreg(hw, 0xc04, MASKDWORD, 0x03a05600);
1728 rtl_set_bbreg(hw, 0xc08, MASKDWORD, 0x000800e4);
1729 rtl_set_bbreg(hw, 0x874, MASKDWORD, 0x22204000);
1730
1731 rtl_set_bbreg(hw, 0x870, BIT(10), 0x01);
1732 rtl_set_bbreg(hw, 0x870, BIT(26), 0x01);
1733 rtl_set_bbreg(hw, 0x860, BIT(10), 0x00);
1734 rtl_set_bbreg(hw, 0x864, BIT(10), 0x00);
1735
1736 if (is2t) {
1737 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000);
1738 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00010000);
1739 }
1740 _rtl88e_phy_mac_setting_calibration(hw, iqk_mac_reg,
1741 rtlphy->iqk_mac_backup);
1742 rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x0f600000);
1743 if (is2t)
1744 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x0f600000);
1745
1746 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
1747 rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x01007c00);
1748 rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x81004800);
1749 for (i = 0; i < retrycount; i++) {
1750 patha_ok = _rtl88e_phy_path_a_iqk(hw, is2t);
1751 if (patha_ok == 0x01) {
1752 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1753 "Path A Tx IQK Success!!\n");
1754 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &
1755 0x3FF0000) >> 16;
1756 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) &
1757 0x3FF0000) >> 16;
1758 break;
1759 }
1760 }
1761
1762 for (i = 0; i < retrycount; i++) {
1763 patha_ok = _rtl88e_phy_path_a_rx_iqk(hw, is2t);
1764 if (patha_ok == 0x03) {
1765 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1766 "Path A Rx IQK Success!!\n");
1767 result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) &
1768 0x3FF0000) >> 16;
1769 result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) &
1770 0x3FF0000) >> 16;
1771 break;
1772 } else {
1773 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1774 "Path a RX iqk fail!!!\n");
1775 }
1776 }
1777
1778 if (0 == patha_ok)
1779 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1780 "Path A IQK Success!!\n");
1781 if (is2t) {
1782 _rtl88e_phy_path_a_standby(hw);
1783 _rtl88e_phy_path_adda_on(hw, adda_reg, false, is2t);
1784 for (i = 0; i < retrycount; i++) {
1785 pathb_ok = _rtl88e_phy_path_b_iqk(hw);
1786 if (pathb_ok == 0x03) {
1787 result[t][4] = (rtl_get_bbreg(hw,
1788 0xeb4,
1789 MASKDWORD) &
1790 0x3FF0000) >> 16;
1791 result[t][5] =
1792 (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
1793 0x3FF0000) >> 16;
1794 result[t][6] =
1795 (rtl_get_bbreg(hw, 0xec4, MASKDWORD) &
1796 0x3FF0000) >> 16;
1797 result[t][7] =
1798 (rtl_get_bbreg(hw, 0xecc, MASKDWORD) &
1799 0x3FF0000) >> 16;
1800 break;
1801 } else if (i == (retrycount - 1) && pathb_ok == 0x01) {
1802 result[t][4] = (rtl_get_bbreg(hw,
1803 0xeb4,
1804 MASKDWORD) &
1805 0x3FF0000) >> 16;
1806 }
1807 result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
1808 0x3FF0000) >> 16;
1809 }
1810 }
1811
1812 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0);
1813
1814 if (t != 0) {
1815 if (!rtlphy->rfpi_enable)
1816 _rtl88e_phy_pi_mode_switch(hw, false);
1817 _rtl88e_phy_reload_adda_registers(hw, adda_reg,
1818 rtlphy->adda_backup, 16);
1819 _rtl88e_phy_reload_mac_registers(hw, iqk_mac_reg,
1820 rtlphy->iqk_mac_backup);
1821 _rtl88e_phy_reload_adda_registers(hw, iqk_bb_reg,
1822 rtlphy->iqk_bb_backup,
1823 IQK_BB_REG_NUM);
1824
1825 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00032ed3);
1826 if (is2t)
1827 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00032ed3);
1828 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x01008c00);
1829 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x01008c00);
1830 }
1831 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "88ee IQK Finish!!\n");
1832 }
1833
1834 static void _rtl88e_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t)
1835 {
1836 u8 tmpreg;
1837 u32 rf_a_mode = 0, rf_b_mode = 0, lc_cal;
1838 struct rtl_priv *rtlpriv = rtl_priv(hw);
1839
1840 tmpreg = rtl_read_byte(rtlpriv, 0xd03);
1841
1842 if ((tmpreg & 0x70) != 0)
1843 rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F);
1844 else
1845 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1846
1847 if ((tmpreg & 0x70) != 0) {
1848 rf_a_mode = rtl_get_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS);
1849
1850 if (is2t)
1851 rf_b_mode = rtl_get_rfreg(hw, RF90_PATH_B, 0x00,
1852 MASK12BITS);
1853
1854 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS,
1855 (rf_a_mode & 0x8FFFF) | 0x10000);
1856
1857 if (is2t)
1858 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
1859 (rf_b_mode & 0x8FFFF) | 0x10000);
1860 }
1861 lc_cal = rtl_get_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS);
1862
1863 rtl_set_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS, lc_cal | 0x08000);
1864
1865 mdelay(100);
1866
1867 if ((tmpreg & 0x70) != 0) {
1868 rtl_write_byte(rtlpriv, 0xd03, tmpreg);
1869 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, rf_a_mode);
1870
1871 if (is2t)
1872 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
1873 rf_b_mode);
1874 } else {
1875 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
1876 }
1877 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "\n");
1878 }
1879
1880 static void _rtl88e_phy_set_rfpath_switch(struct ieee80211_hw *hw,
1881 bool bmain, bool is2t)
1882 {
1883 struct rtl_priv *rtlpriv = rtl_priv(hw);
1884 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1885 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1886 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "\n");
1887
1888 if (is_hal_stop(rtlhal)) {
1889 u8 u1btmp;
1890 u1btmp = rtl_read_byte(rtlpriv, REG_LEDCFG0);
1891 rtl_write_byte(rtlpriv, REG_LEDCFG0, u1btmp | BIT(7));
1892 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(13), 0x01);
1893 }
1894 if (is2t) {
1895 if (bmain)
1896 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
1897 BIT(5) | BIT(6), 0x1);
1898 else
1899 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
1900 BIT(5) | BIT(6), 0x2);
1901 } else {
1902 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BIT(8) | BIT(9), 0);
1903 rtl_set_bbreg(hw, 0x914, MASKLWORD, 0x0201);
1904
1905 /* We use the RF definition of MAIN and AUX,
1906 * left antenna and right antenna repectively.
1907 * Default output at AUX.
1908 */
1909 if (bmain) {
1910 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE,
1911 BIT(14) | BIT(13) | BIT(12), 0);
1912 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
1913 BIT(5) | BIT(4) | BIT(3), 0);
1914 if (rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV)
1915 rtl_set_bbreg(hw, RCONFIG_RAM64x16, BIT(31), 0);
1916 } else {
1917 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE,
1918 BIT(14) | BIT(13) | BIT(12), 1);
1919 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
1920 BIT(5) | BIT(4) | BIT(3), 1);
1921 if (rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV)
1922 rtl_set_bbreg(hw, RCONFIG_RAM64x16, BIT(31), 1);
1923 }
1924 }
1925 }
1926
1927 #undef IQK_ADDA_REG_NUM
1928 #undef IQK_DELAY_TIME
1929
1930 void rtl88e_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery)
1931 {
1932 struct rtl_priv *rtlpriv = rtl_priv(hw);
1933 struct rtl_phy *rtlphy = &rtlpriv->phy;
1934 long result[4][8];
1935 u8 i, final_candidate;
1936 bool b_patha_ok;
1937 long reg_e94, reg_e9c, reg_ea4, reg_eb4, reg_ebc,
1938 reg_tmp = 0;
1939 bool is12simular, is13simular, is23simular;
1940 u32 iqk_bb_reg[9] = {
1941 ROFDM0_XARXIQIMBALANCE,
1942 ROFDM0_XBRXIQIMBALANCE,
1943 ROFDM0_ECCATHRESHOLD,
1944 ROFDM0_AGCRSSITABLE,
1945 ROFDM0_XATXIQIMBALANCE,
1946 ROFDM0_XBTXIQIMBALANCE,
1947 ROFDM0_XCTXAFE,
1948 ROFDM0_XDTXAFE,
1949 ROFDM0_RXIQEXTANTA
1950 };
1951
1952 if (b_recovery) {
1953 _rtl88e_phy_reload_adda_registers(hw,
1954 iqk_bb_reg,
1955 rtlphy->iqk_bb_backup, 9);
1956 return;
1957 }
1958
1959 for (i = 0; i < 8; i++) {
1960 result[0][i] = 0;
1961 result[1][i] = 0;
1962 result[2][i] = 0;
1963 result[3][i] = 0;
1964 }
1965 final_candidate = 0xff;
1966 b_patha_ok = false;
1967 is12simular = false;
1968 is23simular = false;
1969 is13simular = false;
1970 for (i = 0; i < 3; i++) {
1971 if (get_rf_type(rtlphy) == RF_2T2R)
1972 _rtl88e_phy_iq_calibrate(hw, result, i, true);
1973 else
1974 _rtl88e_phy_iq_calibrate(hw, result, i, false);
1975 if (i == 1) {
1976 is12simular =
1977 _rtl88e_phy_simularity_compare(hw, result, 0, 1);
1978 if (is12simular) {
1979 final_candidate = 0;
1980 break;
1981 }
1982 }
1983 if (i == 2) {
1984 is13simular =
1985 _rtl88e_phy_simularity_compare(hw, result, 0, 2);
1986 if (is13simular) {
1987 final_candidate = 0;
1988 break;
1989 }
1990 is23simular =
1991 _rtl88e_phy_simularity_compare(hw, result, 1, 2);
1992 if (is23simular) {
1993 final_candidate = 1;
1994 } else {
1995 for (i = 0; i < 8; i++)
1996 reg_tmp += result[3][i];
1997
1998 if (reg_tmp != 0)
1999 final_candidate = 3;
2000 else
2001 final_candidate = 0xFF;
2002 }
2003 }
2004 }
2005 for (i = 0; i < 4; i++) {
2006 reg_e94 = result[i][0];
2007 reg_e9c = result[i][1];
2008 reg_ea4 = result[i][2];
2009 reg_eb4 = result[i][4];
2010 reg_ebc = result[i][5];
2011 }
2012 if (final_candidate != 0xff) {
2013 reg_e94 = result[final_candidate][0];
2014 reg_e9c = result[final_candidate][1];
2015 reg_ea4 = result[final_candidate][2];
2016 reg_eb4 = result[final_candidate][4];
2017 reg_ebc = result[final_candidate][5];
2018 rtlphy->reg_eb4 = reg_eb4;
2019 rtlphy->reg_ebc = reg_ebc;
2020 rtlphy->reg_e94 = reg_e94;
2021 rtlphy->reg_e9c = reg_e9c;
2022 b_patha_ok = true;
2023 } else {
2024 rtlphy->reg_e94 = 0x100;
2025 rtlphy->reg_eb4 = 0x100;
2026 rtlphy->reg_e9c = 0x0;
2027 rtlphy->reg_ebc = 0x0;
2028 }
2029 if (reg_e94 != 0) /*&&(reg_ea4 != 0) */
2030 _rtl88e_phy_path_a_fill_iqk_matrix(hw, b_patha_ok, result,
2031 final_candidate,
2032 (reg_ea4 == 0));
2033 if (final_candidate != 0xFF) {
2034 for (i = 0; i < IQK_MATRIX_REG_NUM; i++)
2035 rtlphy->iqk_matrix[0].value[0][i] =
2036 result[final_candidate][i];
2037 rtlphy->iqk_matrix[0].iqk_done = true;
2038
2039 }
2040 _rtl88e_phy_save_adda_registers(hw, iqk_bb_reg,
2041 rtlphy->iqk_bb_backup, 9);
2042 }
2043
2044 void rtl88e_phy_lc_calibrate(struct ieee80211_hw *hw)
2045 {
2046 struct rtl_priv *rtlpriv = rtl_priv(hw);
2047 struct rtl_phy *rtlphy = &rtlpriv->phy;
2048 struct rtl_hal *rtlhal = &rtlpriv->rtlhal;
2049 u32 timeout = 2000, timecount = 0;
2050
2051 while (rtlpriv->mac80211.act_scanning && timecount < timeout) {
2052 udelay(50);
2053 timecount += 50;
2054 }
2055
2056 rtlphy->lck_inprogress = true;
2057 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2058 "LCK:Start!!! currentband %x delay %d ms\n",
2059 rtlhal->current_bandtype, timecount);
2060
2061 _rtl88e_phy_lc_calibrate(hw, false);
2062
2063 rtlphy->lck_inprogress = false;
2064 }
2065
2066 void rtl88e_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain)
2067 {
2068 _rtl88e_phy_set_rfpath_switch(hw, bmain, false);
2069 }
2070
2071 bool rtl88e_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype)
2072 {
2073 struct rtl_priv *rtlpriv = rtl_priv(hw);
2074 struct rtl_phy *rtlphy = &rtlpriv->phy;
2075 bool postprocessing = false;
2076
2077 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
2078 "-->IO Cmd(%#x), set_io_inprogress(%d)\n",
2079 iotype, rtlphy->set_io_inprogress);
2080 do {
2081 switch (iotype) {
2082 case IO_CMD_RESUME_DM_BY_SCAN:
2083 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
2084 "[IO CMD] Resume DM after scan.\n");
2085 postprocessing = true;
2086 break;
2087 case IO_CMD_PAUSE_BAND0_DM_BY_SCAN:
2088 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
2089 "[IO CMD] Pause DM before scan.\n");
2090 postprocessing = true;
2091 break;
2092 default:
2093 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
2094 "switch case %#x not processed\n", iotype);
2095 break;
2096 }
2097 } while (false);
2098 if (postprocessing && !rtlphy->set_io_inprogress) {
2099 rtlphy->set_io_inprogress = true;
2100 rtlphy->current_io_type = iotype;
2101 } else {
2102 return false;
2103 }
2104 rtl88e_phy_set_io(hw);
2105 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, "IO Type(%#x)\n", iotype);
2106 return true;
2107 }
2108
2109 static void rtl88e_phy_set_io(struct ieee80211_hw *hw)
2110 {
2111 struct rtl_priv *rtlpriv = rtl_priv(hw);
2112 struct rtl_phy *rtlphy = &rtlpriv->phy;
2113 struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
2114
2115 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
2116 "--->Cmd(%#x), set_io_inprogress(%d)\n",
2117 rtlphy->current_io_type, rtlphy->set_io_inprogress);
2118 switch (rtlphy->current_io_type) {
2119 case IO_CMD_RESUME_DM_BY_SCAN:
2120 dm_digtable->cur_igvalue = rtlphy->initgain_backup.xaagccore1;
2121 /*rtl92c_dm_write_dig(hw);*/
2122 rtl88e_phy_set_txpower_level(hw, rtlphy->current_channel);
2123 rtl_set_bbreg(hw, RCCK0_CCA, 0xff0000, 0x83);
2124 break;
2125 case IO_CMD_PAUSE_BAND0_DM_BY_SCAN:
2126 rtlphy->initgain_backup.xaagccore1 = dm_digtable->cur_igvalue;
2127 dm_digtable->cur_igvalue = 0x17;
2128 rtl_set_bbreg(hw, RCCK0_CCA, 0xff0000, 0x40);
2129 break;
2130 default:
2131 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
2132 "switch case %#x not processed\n",
2133 rtlphy->current_io_type);
2134 break;
2135 }
2136 rtlphy->set_io_inprogress = false;
2137 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
2138 "(%#x)\n", rtlphy->current_io_type);
2139 }
2140
2141 static void rtl88ee_phy_set_rf_on(struct ieee80211_hw *hw)
2142 {
2143 struct rtl_priv *rtlpriv = rtl_priv(hw);
2144
2145 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
2146 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
2147 /*rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);*/
2148 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
2149 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
2150 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
2151 }
2152
2153 static void _rtl88ee_phy_set_rf_sleep(struct ieee80211_hw *hw)
2154 {
2155 struct rtl_priv *rtlpriv = rtl_priv(hw);
2156
2157 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
2158 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
2159 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
2160 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22);
2161 }
2162
2163 static bool _rtl88ee_phy_set_rf_power_state(struct ieee80211_hw *hw,
2164 enum rf_pwrstate rfpwr_state)
2165 {
2166 struct rtl_priv *rtlpriv = rtl_priv(hw);
2167 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2168 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2169 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2170 bool bresult = true;
2171 u8 i, queue_id;
2172 struct rtl8192_tx_ring *ring = NULL;
2173
2174 switch (rfpwr_state) {
2175 case ERFON:
2176 if ((ppsc->rfpwr_state == ERFOFF) &&
2177 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
2178 bool rtstatus;
2179 u32 initializecount = 0;
2180
2181 do {
2182 initializecount++;
2183 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2184 "IPS Set eRf nic enable\n");
2185 rtstatus = rtl_ps_enable_nic(hw);
2186 } while (!rtstatus &&
2187 (initializecount < 10));
2188 RT_CLEAR_PS_LEVEL(ppsc,
2189 RT_RF_OFF_LEVL_HALT_NIC);
2190 } else {
2191 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2192 "Set ERFON sleeped:%d ms\n",
2193 jiffies_to_msecs(jiffies -
2194 ppsc->
2195 last_sleep_jiffies));
2196 ppsc->last_awake_jiffies = jiffies;
2197 rtl88ee_phy_set_rf_on(hw);
2198 }
2199 if (mac->link_state == MAC80211_LINKED) {
2200 rtlpriv->cfg->ops->led_control(hw,
2201 LED_CTL_LINK);
2202 } else {
2203 rtlpriv->cfg->ops->led_control(hw,
2204 LED_CTL_NO_LINK);
2205 }
2206 break;
2207 case ERFOFF:
2208 for (queue_id = 0, i = 0;
2209 queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
2210 ring = &pcipriv->dev.tx_ring[queue_id];
2211 if (queue_id == BEACON_QUEUE ||
2212 skb_queue_len(&ring->queue) == 0) {
2213 queue_id++;
2214 continue;
2215 } else {
2216 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
2217 "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n",
2218 (i + 1), queue_id,
2219 skb_queue_len(&ring->queue));
2220
2221 udelay(10);
2222 i++;
2223 }
2224 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
2225 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
2226 "\n ERFSLEEP: %d times TcbBusyQueue[%d] = %d !\n",
2227 MAX_DOZE_WAITING_TIMES_9x,
2228 queue_id,
2229 skb_queue_len(&ring->queue));
2230 break;
2231 }
2232 }
2233
2234 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
2235 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2236 "IPS Set eRf nic disable\n");
2237 rtl_ps_disable_nic(hw);
2238 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2239 } else {
2240 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) {
2241 rtlpriv->cfg->ops->led_control(hw,
2242 LED_CTL_NO_LINK);
2243 } else {
2244 rtlpriv->cfg->ops->led_control(hw,
2245 LED_CTL_POWER_OFF);
2246 }
2247 }
2248 break;
2249 case ERFSLEEP:{
2250 if (ppsc->rfpwr_state == ERFOFF)
2251 break;
2252 for (queue_id = 0, i = 0;
2253 queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
2254 ring = &pcipriv->dev.tx_ring[queue_id];
2255 if (skb_queue_len(&ring->queue) == 0) {
2256 queue_id++;
2257 continue;
2258 } else {
2259 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
2260 "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n",
2261 (i + 1), queue_id,
2262 skb_queue_len(&ring->queue));
2263
2264 udelay(10);
2265 i++;
2266 }
2267 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
2268 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
2269 "\n ERFSLEEP: %d times TcbBusyQueue[%d] = %d !\n",
2270 MAX_DOZE_WAITING_TIMES_9x,
2271 queue_id,
2272 skb_queue_len(&ring->queue));
2273 break;
2274 }
2275 }
2276 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2277 "Set ERFSLEEP awaked:%d ms\n",
2278 jiffies_to_msecs(jiffies -
2279 ppsc->last_awake_jiffies));
2280 ppsc->last_sleep_jiffies = jiffies;
2281 _rtl88ee_phy_set_rf_sleep(hw);
2282 break;
2283 }
2284 default:
2285 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
2286 "switch case %#x not processed\n", rfpwr_state);
2287 bresult = false;
2288 break;
2289 }
2290 if (bresult)
2291 ppsc->rfpwr_state = rfpwr_state;
2292 return bresult;
2293 }
2294
2295 bool rtl88e_phy_set_rf_power_state(struct ieee80211_hw *hw,
2296 enum rf_pwrstate rfpwr_state)
2297 {
2298 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2299
2300 bool bresult = false;
2301
2302 if (rfpwr_state == ppsc->rfpwr_state)
2303 return bresult;
2304 bresult = _rtl88ee_phy_set_rf_power_state(hw, rfpwr_state);
2305 return bresult;
2306 }
Linux with added FPC-III support