drivers/net/wireless/realtek/rtlwifi/rtl8192se/def.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /* Copyright(c) 2009-2012  Realtek Corporation.*/
   3
   4 #ifndef __REALTEK_92S_DEF_H__
   5 #define __REALTEK_92S_DEF_H__
   6
   7 #define RX_MPDU_QUEUE                           0
   8 #define RX_CMD_QUEUE                            1
   9
  10 #define SHORT_SLOT_TIME                         9
  11 #define NON_SHORT_SLOT_TIME                     20
  12
  13 /* Queue Select Value in TxDesc */
  14 #define QSLT_BK                                 0x2
  15 #define QSLT_BE                                 0x0
  16 #define QSLT_VI                                 0x5
  17 #define QSLT_VO                                 0x6
  18 #define QSLT_BEACON                             0x10
  19 #define QSLT_HIGH                               0x11
  20 #define QSLT_MGNT                               0x12
  21 #define QSLT_CMD                                0x13
  22
  23 /* Tx Desc */
  24 #define TX_DESC_SIZE_RTL8192S                   (16 * 4)
  25 #define TX_CMDDESC_SIZE_RTL8192S                (16 * 4)
  26
  27 /* macros to read/write various fields in RX or TX descriptors */
  28
  29 /* Dword 0 */
  30 static inline void set_tx_desc_pkt_size(__le32 *__pdesc, u32 __val)
  31 {
  32         le32p_replace_bits(__pdesc, __val, GENMASK(15, 0));
  33 }
  34
  35 static inline void set_tx_desc_offset(__le32 *__pdesc, u32 __val)
  36 {
  37         le32p_replace_bits(__pdesc, __val, GENMASK(23, 16));
  38 }
  39
  40 static inline void set_tx_desc_last_seg(__le32 *__pdesc, u32 __val)
  41 {
  42         le32p_replace_bits(__pdesc, __val, BIT(26));
  43 }
  44
  45 static inline void set_tx_desc_first_seg(__le32 *__pdesc, u32 __val)
  46 {
  47         le32p_replace_bits(__pdesc, __val, BIT(27));
  48 }
  49
  50 static inline void set_tx_desc_linip(__le32 *__pdesc, u32 __val)
  51 {
  52         le32p_replace_bits(__pdesc, __val, BIT(28));
  53 }
  54
  55 static inline void set_tx_desc_own(__le32 *__pdesc, u32 __val)
  56 {
  57         le32p_replace_bits(__pdesc, __val, BIT(31));
  58 }
  59
  60 static inline u32 get_tx_desc_own(__le32 *__pdesc)
  61 {
  62         return le32_get_bits(*(__pdesc), BIT(31));
  63 }
  64
  65 /* Dword 1 */
  66 static inline void set_tx_desc_macid(__le32 *__pdesc, u32 __val)
  67 {
  68         le32p_replace_bits((__pdesc + 1), __val, GENMASK(4, 0));
  69 }
  70
  71 static inline void set_tx_desc_queue_sel(__le32 *__pdesc, u32 __val)
  72 {
  73         le32p_replace_bits((__pdesc + 1), __val, GENMASK(12, 8));
  74 }
  75
  76 static inline void set_tx_desc_non_qos(__le32 *__pdesc, u32 __val)
  77 {
  78         le32p_replace_bits((__pdesc + 1), __val, BIT(16));
  79 }
  80
  81 static inline void set_tx_desc_sec_type(__le32 *__pdesc, u32 __val)
  82 {
  83         le32p_replace_bits((__pdesc + 1), __val, GENMASK(23, 22));
  84 }
  85
  86 /* Dword 2 */
  87 static inline void      set_tx_desc_rsvd_macid(__le32 *__pdesc, u32 __val)
  88 {
  89         le32p_replace_bits((__pdesc + 2), __val, GENMASK(28, 24));
  90 }
  91
  92 static inline void set_tx_desc_agg_enable(__le32 *__pdesc, u32 __val)
  93 {
  94         le32p_replace_bits((__pdesc + 2), __val, BIT(29));
  95 }
  96
  97 /* Dword 3 */
  98 static inline void set_tx_desc_seq(__le32 *__pdesc, u32 __val)
  99 {
 100         le32p_replace_bits((__pdesc + 3), __val, GENMASK(27, 16));
 101 }
 102
 103 /* Dword 4 */
 104 static inline void set_tx_desc_rts_rate(__le32 *__pdesc, u32 __val)
 105 {
 106         le32p_replace_bits((__pdesc + 4), __val, GENMASK(5, 0));
 107 }
 108
 109 static inline void set_tx_desc_cts_enable(__le32 *__pdesc, u32 __val)
 110 {
 111         le32p_replace_bits((__pdesc + 4), __val, BIT(11));
 112 }
 113
 114 static inline void set_tx_desc_rts_enable(__le32 *__pdesc, u32 __val)
 115 {
 116         le32p_replace_bits((__pdesc + 4), __val, BIT(12));
 117 }
 118
 119 static inline void set_tx_desc_ra_brsr_id(__le32 *__pdesc, u32 __val)
 120 {
 121         le32p_replace_bits((__pdesc + 4), __val, GENMASK(15, 13));
 122 }
 123
 124 static inline void set_tx_desc_txht(__le32 *__pdesc, u32 __val)
 125 {
 126         le32p_replace_bits((__pdesc + 4), __val, BIT(16));
 127 }
 128
 129 static inline void set_tx_desc_tx_short(__le32 *__pdesc, u32 __val)
 130 {
 131         le32p_replace_bits((__pdesc + 4), __val, BIT(17));
 132 }
 133
 134 static inline void set_tx_desc_tx_bandwidth(__le32 *__pdesc, u32 __val)
 135 {
 136         le32p_replace_bits((__pdesc + 4), __val, BIT(18));
 137 }
 138
 139 static inline void set_tx_desc_tx_sub_carrier(__le32 *__pdesc, u32 __val)
 140 {
 141         le32p_replace_bits((__pdesc + 4), __val, GENMASK(20, 19));
 142 }
 143
 144 static inline void set_tx_desc_rts_short(__le32 *__pdesc, u32 __val)
 145 {
 146         le32p_replace_bits((__pdesc + 4), __val, BIT(25));
 147 }
 148
 149 static inline void set_tx_desc_rts_bandwidth(__le32 *__pdesc, u32 __val)
 150 {
 151         le32p_replace_bits((__pdesc + 4), __val, BIT(26));
 152 }
 153
 154 static inline void set_tx_desc_rts_sub_carrier(__le32 *__pdesc, u32 __val)
 155 {
 156         le32p_replace_bits((__pdesc + 4), __val, GENMASK(28, 27));
 157 }
 158
 159 static inline void set_tx_desc_rts_stbc(__le32 *__pdesc, u32 __val)
 160 {
 161         le32p_replace_bits((__pdesc + 4), __val, GENMASK(30, 29));
 162 }
 163
 164 static inline void set_tx_desc_user_rate(__le32 *__pdesc, u32 __val)
 165 {
 166         le32p_replace_bits((__pdesc + 4), __val, BIT(31));
 167 }
 168
 169 /* Dword 5 */
 170 static inline void set_tx_desc_packet_id(__le32 *__pdesc, u32 __val)
 171 {
 172         le32p_replace_bits((__pdesc + 5), __val, GENMASK(8, 0));
 173 }
 174
 175 static inline void set_tx_desc_tx_rate(__le32 *__pdesc, u32 __val)
 176 {
 177         le32p_replace_bits((__pdesc + 5), __val, GENMASK(14, 9));
 178 }
 179
 180 static inline void set_tx_desc_data_rate_fb_limit(__le32 *__pdesc, u32 __val)
 181 {
 182         le32p_replace_bits((__pdesc + 5), __val, GENMASK(20, 16));
 183 }
 184
 185 /* Dword 7 */
 186 static inline void set_tx_desc_tx_buffer_size(__le32 *__pdesc, u32 __val)
 187 {
 188         le32p_replace_bits((__pdesc + 7), __val, GENMASK(15, 0));
 189 }
 190
 191 /* Dword 8 */
 192 static inline void set_tx_desc_tx_buffer_address(__le32 *__pdesc, u32 __val)
 193 {
 194         *(__pdesc + 8) = cpu_to_le32(__val);
 195 }
 196
 197 static inline u32 get_tx_desc_tx_buffer_address(__le32 *__pdesc)
 198 {
 199         return le32_to_cpu(*((__pdesc + 8)));
 200 }
 201
 202 /* Dword 9 */
 203 static inline void set_tx_desc_next_desc_address(__le32 *__pdesc, u32 __val)
 204 {
 205         *(__pdesc + 9) = cpu_to_le32(__val);
 206 }
 207
 208 /* Because the PCI Tx descriptors are chaied at the
 209  * initialization and all the NextDescAddresses in
 210  * these descriptors cannot not be cleared (,or
 211  * driver/HW cannot find the next descriptor), the
 212  * offset 36 (NextDescAddresses) is reserved when
 213  * the desc is cleared. */
 214 #define TX_DESC_NEXT_DESC_OFFSET                        36
 215 #define CLEAR_PCI_TX_DESC_CONTENT(__pdesc, _size)               \
 216         memset(__pdesc, 0, min_t(size_t, _size, TX_DESC_NEXT_DESC_OFFSET))
 217
 218 /* Rx Desc */
 219 #define RX_STATUS_DESC_SIZE                             24
 220 #define RX_DRV_INFO_SIZE_UNIT                           8
 221
 222 /* DWORD 0 */
 223 static inline void set_rx_status_desc_pkt_len(__le32 *__pdesc, u32 __val)
 224 {
 225         le32p_replace_bits(__pdesc, __val, GENMASK(13, 0));
 226 }
 227
 228 static inline void set_rx_status_desc_eor(__le32 *__pdesc, u32 __val)
 229 {
 230         le32p_replace_bits(__pdesc, __val, BIT(30));
 231 }
 232
 233 static inline void set_rx_status_desc_own(__le32 *__pdesc, u32 __val)
 234 {
 235         le32p_replace_bits(__pdesc, __val, BIT(31));
 236 }
 237
 238 static inline u32 get_rx_status_desc_pkt_len(__le32 *__pdesc)
 239 {
 240         return le32_get_bits(*(__pdesc), GENMASK(13, 0));
 241 }
 242
 243 static inline u32 get_rx_status_desc_crc32(__le32 *__pdesc)
 244 {
 245         return le32_get_bits(*(__pdesc), BIT(14));
 246 }
 247
 248 static inline u32 get_rx_status_desc_icv(__le32 *__pdesc)
 249 {
 250         return le32_get_bits(*(__pdesc), BIT(15));
 251 }
 252
 253 static inline u32 get_rx_status_desc_drvinfo_size(__le32 *__pdesc)
 254 {
 255         return le32_get_bits(*(__pdesc), GENMASK(19, 16));
 256 }
 257
 258 static inline u32 get_rx_status_desc_shift(__le32 *__pdesc)
 259 {
 260         return le32_get_bits(*(__pdesc), GENMASK(25, 24));
 261 }
 262
 263 static inline u32 get_rx_status_desc_phy_status(__le32 *__pdesc)
 264 {
 265         return le32_get_bits(*(__pdesc), BIT(26));
 266 }
 267
 268 static inline u32 get_rx_status_desc_swdec(__le32 *__pdesc)
 269 {
 270         return le32_get_bits(*(__pdesc), BIT(27));
 271 }
 272
 273 static inline u32 get_rx_status_desc_own(__le32 *__pdesc)
 274 {
 275         return le32_get_bits(*(__pdesc), BIT(31));
 276 }
 277
 278 /* DWORD 1 */
 279 static inline u32 get_rx_status_desc_paggr(__le32 *__pdesc)
 280 {
 281         return le32_get_bits(*(__pdesc + 1), BIT(14));
 282 }
 283
 284 static inline u32 get_rx_status_desc_faggr(__le32 *__pdesc)
 285 {
 286         return le32_get_bits(*(__pdesc + 1), BIT(15));
 287 }
 288
 289 /* DWORD 3 */
 290 static inline u32 get_rx_status_desc_rx_mcs(__le32 *__pdesc)
 291 {
 292         return le32_get_bits(*(__pdesc + 3), GENMASK(5, 0));
 293 }
 294
 295 static inline u32 get_rx_status_desc_rx_ht(__le32 *__pdesc)
 296 {
 297         return le32_get_bits(*(__pdesc + 3), BIT(6));
 298 }
 299
 300 static inline u32 get_rx_status_desc_splcp(__le32 *__pdesc)
 301 {
 302         return le32_get_bits(*(__pdesc + 3), BIT(8));
 303 }
 304
 305 static inline u32 get_rx_status_desc_bw(__le32 *__pdesc)
 306 {
 307         return le32_get_bits(*(__pdesc + 3), BIT(9));
 308 }
 309
 310 /* DWORD 5 */
 311 static inline u32 get_rx_status_desc_tsfl(__le32 *__pdesc)
 312 {
 313         return le32_to_cpu(*((__pdesc + 5)));
 314 }
 315
 316 /* DWORD 6 */
 317 static inline void set_rx_status__desc_buff_addr(__le32 *__pdesc, u32 __val)
 318 {
 319         *(__pdesc + 6) = cpu_to_le32(__val);
 320 }
 321
 322 static inline u32 get_rx_status_desc_buff_addr(__le32 *__pdesc)
 323 {
 324         return le32_to_cpu(*(__pdesc + 6));
 325 }
 326
 327 #define SE_RX_HAL_IS_CCK_RATE(_pdesc)\
 328         (get_rx_status_desc_rx_mcs(_pdesc) == DESC_RATE1M ||    \
 329          get_rx_status_desc_rx_mcs(_pdesc) == DESC_RATE2M ||    \
 330          get_rx_status_desc_rx_mcs(_pdesc) == DESC_RATE5_5M ||\
 331          get_rx_status_desc_rx_mcs(_pdesc) == DESC_RATE11M)
 332
 333 enum rf_optype {
 334         RF_OP_BY_SW_3WIRE = 0,
 335         RF_OP_BY_FW,
 336         RF_OP_MAX
 337 };
 338
 339 enum ic_inferiority {
 340         IC_INFERIORITY_A = 0,
 341         IC_INFERIORITY_B = 1,
 342 };
 343
 344 enum fwcmd_iotype {
 345         /* For DIG DM */
 346         FW_CMD_DIG_ENABLE = 0,
 347         FW_CMD_DIG_DISABLE = 1,
 348         FW_CMD_DIG_HALT = 2,
 349         FW_CMD_DIG_RESUME = 3,
 350         /* For High Power DM */
 351         FW_CMD_HIGH_PWR_ENABLE = 4,
 352         FW_CMD_HIGH_PWR_DISABLE = 5,
 353         /* For Rate adaptive DM */
 354         FW_CMD_RA_RESET = 6,
 355         FW_CMD_RA_ACTIVE = 7,
 356         FW_CMD_RA_REFRESH_N = 8,
 357         FW_CMD_RA_REFRESH_BG = 9,
 358         FW_CMD_RA_INIT = 10,
 359         /* For FW supported IQK */
 360         FW_CMD_IQK_INIT = 11,
 361         /* Tx power tracking switch,
 362          * MP driver only */
 363         FW_CMD_TXPWR_TRACK_ENABLE = 12,
 364         /* Tx power tracking switch,
 365          * MP driver only */
 366         FW_CMD_TXPWR_TRACK_DISABLE = 13,
 367         /* Tx power tracking with thermal
 368          * indication, for Normal driver */
 369         FW_CMD_TXPWR_TRACK_THERMAL = 14,
 370         FW_CMD_PAUSE_DM_BY_SCAN = 15,
 371         FW_CMD_RESUME_DM_BY_SCAN = 16,
 372         FW_CMD_RA_REFRESH_N_COMB = 17,
 373         FW_CMD_RA_REFRESH_BG_COMB = 18,
 374         FW_CMD_ANTENNA_SW_ENABLE = 19,
 375         FW_CMD_ANTENNA_SW_DISABLE = 20,
 376         /* Tx Status report for CCX from FW */
 377         FW_CMD_TX_FEEDBACK_CCX_ENABLE = 21,
 378         /* Indifate firmware that driver
 379          * enters LPS, For PS-Poll issue */
 380         FW_CMD_LPS_ENTER = 22,
 381         /* Indicate firmware that driver
 382          * leave LPS*/
 383         FW_CMD_LPS_LEAVE = 23,
 384         /* Set DIG mode to signal strength */
 385         FW_CMD_DIG_MODE_SS = 24,
 386         /* Set DIG mode to false alarm. */
 387         FW_CMD_DIG_MODE_FA = 25,
 388         FW_CMD_ADD_A2_ENTRY = 26,
 389         FW_CMD_CTRL_DM_BY_DRIVER = 27,
 390         FW_CMD_CTRL_DM_BY_DRIVER_NEW = 28,
 391         FW_CMD_PAPE_CONTROL = 29,
 392         FW_CMD_IQK_ENABLE = 30,
 393 };
 394
 395 /* Driver info contain PHY status
 396  * and other variabel size info
 397  * PHY Status content as below
 398  */
 399 struct  rx_fwinfo {
 400         /* DWORD 0 */
 401         u8 gain_trsw[4];
 402         /* DWORD 1 */
 403         u8 pwdb_all;
 404         u8 cfosho[4];
 405         /* DWORD 2 */
 406         u8 cfotail[4];
 407         /* DWORD 3 */
 408         s8 rxevm[2];
 409         s8 rxsnr[4];
 410         /* DWORD 4 */
 411         u8 pdsnr[2];
 412         /* DWORD 5 */
 413         u8 csi_current[2];
 414         u8 csi_target[2];
 415         /* DWORD 6 */
 416         u8 sigevm;
 417         u8 max_ex_pwr;
 418         u8 ex_intf_flag:1;
 419         u8 sgi_en:1;
 420         u8 rxsc:2;
 421         u8 reserve:4;
 422 };
 423
 424 struct phy_sts_cck_8192s_t {
 425         u8 adc_pwdb_x[4];
 426         u8 sq_rpt;
 427         u8 cck_agc_rpt;
 428 };
 429
 430 #endif
 431