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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / net / wireless / realtek / rtlwifi / rtl8192se / phy.c
blobd5c0eb462315512052915b7479f2a1892a22dafe
1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2012 Realtek Corporation.*/
3
4 #include "../wifi.h"
5 #include "../pci.h"
6 #include "../ps.h"
7 #include "../core.h"
8 #include "reg.h"
9 #include "def.h"
10 #include "phy.h"
11 #include "rf.h"
12 #include "dm.h"
13 #include "fw.h"
14 #include "hw.h"
15 #include "table.h"
16
17 static u32 _rtl92s_phy_calculate_bit_shift(u32 bitmask)
18 {
19 u32 i;
20
21 for (i = 0; i <= 31; i++) {
22 if (((bitmask >> i) & 0x1) == 1)
23 break;
24 }
25
26 return i;
27 }
28
29 u32 rtl92s_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask)
30 {
31 struct rtl_priv *rtlpriv = rtl_priv(hw);
32 u32 returnvalue = 0, originalvalue, bitshift;
33
34 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "regaddr(%#x), bitmask(%#x)\n",
35 regaddr, bitmask);
36
37 originalvalue = rtl_read_dword(rtlpriv, regaddr);
38 bitshift = _rtl92s_phy_calculate_bit_shift(bitmask);
39 returnvalue = (originalvalue & bitmask) >> bitshift;
40
41 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "BBR MASK=0x%x Addr[0x%x]=0x%x\n",
42 bitmask, regaddr, originalvalue);
43
44 return returnvalue;
45
46 }
47
48 void rtl92s_phy_set_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask,
49 u32 data)
50 {
51 struct rtl_priv *rtlpriv = rtl_priv(hw);
52 u32 originalvalue, bitshift;
53
54 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
55 "regaddr(%#x), bitmask(%#x), data(%#x)\n",
56 regaddr, bitmask, data);
57
58 if (bitmask != MASKDWORD) {
59 originalvalue = rtl_read_dword(rtlpriv, regaddr);
60 bitshift = _rtl92s_phy_calculate_bit_shift(bitmask);
61 data = ((originalvalue & (~bitmask)) | (data << bitshift));
62 }
63
64 rtl_write_dword(rtlpriv, regaddr, data);
65
66 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
67 "regaddr(%#x), bitmask(%#x), data(%#x)\n",
68 regaddr, bitmask, data);
69
70 }
71
72 static u32 _rtl92s_phy_rf_serial_read(struct ieee80211_hw *hw,
73 enum radio_path rfpath, u32 offset)
74 {
75
76 struct rtl_priv *rtlpriv = rtl_priv(hw);
77 struct rtl_phy *rtlphy = &(rtlpriv->phy);
78 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
79 u32 newoffset;
80 u32 tmplong, tmplong2;
81 u8 rfpi_enable = 0;
82 u32 retvalue = 0;
83
84 offset &= 0x3f;
85 newoffset = offset;
86
87 tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD);
88
89 if (rfpath == RF90_PATH_A)
90 tmplong2 = tmplong;
91 else
92 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD);
93
94 tmplong2 = (tmplong2 & (~BLSSI_READADDRESS)) | (newoffset << 23) |
95 BLSSI_READEDGE;
96
97 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
98 tmplong & (~BLSSI_READEDGE));
99
100 mdelay(1);
101
102 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2);
103 mdelay(1);
104
105 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD, tmplong |
106 BLSSI_READEDGE);
107 mdelay(1);
108
109 if (rfpath == RF90_PATH_A)
110 rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,
111 BIT(8));
112 else if (rfpath == RF90_PATH_B)
113 rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1,
114 BIT(8));
115
116 if (rfpi_enable)
117 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rbpi,
118 BLSSI_READBACK_DATA);
119 else
120 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb,
121 BLSSI_READBACK_DATA);
122
123 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb,
124 BLSSI_READBACK_DATA);
125
126 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFR-%d Addr[0x%x]=0x%x\n",
127 rfpath, pphyreg->rf_rb, retvalue);
128
129 return retvalue;
130
131 }
132
133 static void _rtl92s_phy_rf_serial_write(struct ieee80211_hw *hw,
134 enum radio_path rfpath, u32 offset,
135 u32 data)
136 {
137 struct rtl_priv *rtlpriv = rtl_priv(hw);
138 struct rtl_phy *rtlphy = &(rtlpriv->phy);
139 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
140 u32 data_and_addr = 0;
141 u32 newoffset;
142
143 offset &= 0x3f;
144 newoffset = offset;
145
146 data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff;
147 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);
148
149 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFW-%d Addr[0x%x]=0x%x\n",
150 rfpath, pphyreg->rf3wire_offset, data_and_addr);
151 }
152
153
154 u32 rtl92s_phy_query_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath,
155 u32 regaddr, u32 bitmask)
156 {
157 struct rtl_priv *rtlpriv = rtl_priv(hw);
158 u32 original_value, readback_value, bitshift;
159
160 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
161 "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n",
162 regaddr, rfpath, bitmask);
163
164 spin_lock(&rtlpriv->locks.rf_lock);
165
166 original_value = _rtl92s_phy_rf_serial_read(hw, rfpath, regaddr);
167
168 bitshift = _rtl92s_phy_calculate_bit_shift(bitmask);
169 readback_value = (original_value & bitmask) >> bitshift;
170
171 spin_unlock(&rtlpriv->locks.rf_lock);
172
173 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
174 "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n",
175 regaddr, rfpath, bitmask, original_value);
176
177 return readback_value;
178 }
179
180 void rtl92s_phy_set_rf_reg(struct ieee80211_hw *hw, enum radio_path rfpath,
181 u32 regaddr, u32 bitmask, u32 data)
182 {
183 struct rtl_priv *rtlpriv = rtl_priv(hw);
184 struct rtl_phy *rtlphy = &(rtlpriv->phy);
185 u32 original_value, bitshift;
186
187 if (!((rtlphy->rf_pathmap >> rfpath) & 0x1))
188 return;
189
190 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
191 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
192 regaddr, bitmask, data, rfpath);
193
194 spin_lock(&rtlpriv->locks.rf_lock);
195
196 if (bitmask != RFREG_OFFSET_MASK) {
197 original_value = _rtl92s_phy_rf_serial_read(hw, rfpath,
198 regaddr);
199 bitshift = _rtl92s_phy_calculate_bit_shift(bitmask);
200 data = ((original_value & (~bitmask)) | (data << bitshift));
201 }
202
203 _rtl92s_phy_rf_serial_write(hw, rfpath, regaddr, data);
204
205 spin_unlock(&rtlpriv->locks.rf_lock);
206
207 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
208 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
209 regaddr, bitmask, data, rfpath);
210
211 }
212
213 void rtl92s_phy_scan_operation_backup(struct ieee80211_hw *hw,
214 u8 operation)
215 {
216 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
217
218 if (!is_hal_stop(rtlhal)) {
219 switch (operation) {
220 case SCAN_OPT_BACKUP:
221 rtl92s_phy_set_fw_cmd(hw, FW_CMD_PAUSE_DM_BY_SCAN);
222 break;
223 case SCAN_OPT_RESTORE:
224 rtl92s_phy_set_fw_cmd(hw, FW_CMD_RESUME_DM_BY_SCAN);
225 break;
226 default:
227 pr_err("Unknown operation\n");
228 break;
229 }
230 }
231 }
232
233 void rtl92s_phy_set_bw_mode(struct ieee80211_hw *hw,
234 enum nl80211_channel_type ch_type)
235 {
236 struct rtl_priv *rtlpriv = rtl_priv(hw);
237 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
238 struct rtl_phy *rtlphy = &(rtlpriv->phy);
239 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
240 u8 reg_bw_opmode;
241
242 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "Switch to %s bandwidth\n",
243 rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
244 "20MHz" : "40MHz");
245
246 if (rtlphy->set_bwmode_inprogress)
247 return;
248 if (is_hal_stop(rtlhal))
249 return;
250
251 rtlphy->set_bwmode_inprogress = true;
252
253 reg_bw_opmode = rtl_read_byte(rtlpriv, BW_OPMODE);
254 /* dummy read */
255 rtl_read_byte(rtlpriv, RRSR + 2);
256
257 switch (rtlphy->current_chan_bw) {
258 case HT_CHANNEL_WIDTH_20:
259 reg_bw_opmode |= BW_OPMODE_20MHZ;
260 rtl_write_byte(rtlpriv, BW_OPMODE, reg_bw_opmode);
261 break;
262 case HT_CHANNEL_WIDTH_20_40:
263 reg_bw_opmode &= ~BW_OPMODE_20MHZ;
264 rtl_write_byte(rtlpriv, BW_OPMODE, reg_bw_opmode);
265 break;
266 default:
267 pr_err("unknown bandwidth: %#X\n",
268 rtlphy->current_chan_bw);
269 break;
270 }
271
272 switch (rtlphy->current_chan_bw) {
273 case HT_CHANNEL_WIDTH_20:
274 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0);
275 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0);
276
277 if (rtlhal->version >= VERSION_8192S_BCUT)
278 rtl_write_byte(rtlpriv, RFPGA0_ANALOGPARAMETER2, 0x58);
279 break;
280 case HT_CHANNEL_WIDTH_20_40:
281 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1);
282 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1);
283
284 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND,
285 (mac->cur_40_prime_sc >> 1));
286 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc);
287
288 if (rtlhal->version >= VERSION_8192S_BCUT)
289 rtl_write_byte(rtlpriv, RFPGA0_ANALOGPARAMETER2, 0x18);
290 break;
291 default:
292 pr_err("unknown bandwidth: %#X\n",
293 rtlphy->current_chan_bw);
294 break;
295 }
296
297 rtl92s_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
298 rtlphy->set_bwmode_inprogress = false;
299 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
300 }
301
302 static bool _rtl92s_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
303 u32 cmdtableidx, u32 cmdtablesz, enum swchnlcmd_id cmdid,
304 u32 para1, u32 para2, u32 msdelay)
305 {
306 struct swchnlcmd *pcmd;
307
308 if (cmdtable == NULL) {
309 WARN_ONCE(true, "rtl8192se: cmdtable cannot be NULL\n");
310 return false;
311 }
312
313 if (cmdtableidx >= cmdtablesz)
314 return false;
315
316 pcmd = cmdtable + cmdtableidx;
317 pcmd->cmdid = cmdid;
318 pcmd->para1 = para1;
319 pcmd->para2 = para2;
320 pcmd->msdelay = msdelay;
321
322 return true;
323 }
324
325 static bool _rtl92s_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
326 u8 channel, u8 *stage, u8 *step, u32 *delay)
327 {
328 struct rtl_priv *rtlpriv = rtl_priv(hw);
329 struct rtl_phy *rtlphy = &(rtlpriv->phy);
330 struct swchnlcmd precommoncmd[MAX_PRECMD_CNT];
331 u32 precommoncmdcnt;
332 struct swchnlcmd postcommoncmd[MAX_POSTCMD_CNT];
333 u32 postcommoncmdcnt;
334 struct swchnlcmd rfdependcmd[MAX_RFDEPENDCMD_CNT];
335 u32 rfdependcmdcnt;
336 struct swchnlcmd *currentcmd = NULL;
337 u8 rfpath;
338 u8 num_total_rfpath = rtlphy->num_total_rfpath;
339
340 precommoncmdcnt = 0;
341 _rtl92s_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
342 MAX_PRECMD_CNT, CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0);
343 _rtl92s_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
344 MAX_PRECMD_CNT, CMDID_END, 0, 0, 0);
345
346 postcommoncmdcnt = 0;
347
348 _rtl92s_phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++,
349 MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0);
350
351 rfdependcmdcnt = 0;
352
353 WARN_ONCE((channel < 1 || channel > 14),
354 "rtl8192se: invalid channel for Zebra: %d\n", channel);
355
356 _rtl92s_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
357 MAX_RFDEPENDCMD_CNT, CMDID_RF_WRITEREG,
358 RF_CHNLBW, channel, 10);
359
360 _rtl92s_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
361 MAX_RFDEPENDCMD_CNT, CMDID_END, 0, 0, 0);
362
363 do {
364 switch (*stage) {
365 case 0:
366 currentcmd = &precommoncmd[*step];
367 break;
368 case 1:
369 currentcmd = &rfdependcmd[*step];
370 break;
371 case 2:
372 currentcmd = &postcommoncmd[*step];
373 break;
374 default:
375 return true;
376 }
377
378 if (currentcmd->cmdid == CMDID_END) {
379 if ((*stage) == 2) {
380 return true;
381 } else {
382 (*stage)++;
383 (*step) = 0;
384 continue;
385 }
386 }
387
388 switch (currentcmd->cmdid) {
389 case CMDID_SET_TXPOWEROWER_LEVEL:
390 rtl92s_phy_set_txpower(hw, channel);
391 break;
392 case CMDID_WRITEPORT_ULONG:
393 rtl_write_dword(rtlpriv, currentcmd->para1,
394 currentcmd->para2);
395 break;
396 case CMDID_WRITEPORT_USHORT:
397 rtl_write_word(rtlpriv, currentcmd->para1,
398 (u16)currentcmd->para2);
399 break;
400 case CMDID_WRITEPORT_UCHAR:
401 rtl_write_byte(rtlpriv, currentcmd->para1,
402 (u8)currentcmd->para2);
403 break;
404 case CMDID_RF_WRITEREG:
405 for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) {
406 rtlphy->rfreg_chnlval[rfpath] =
407 ((rtlphy->rfreg_chnlval[rfpath] &
408 0xfffffc00) | currentcmd->para2);
409 rtl_set_rfreg(hw, (enum radio_path)rfpath,
410 currentcmd->para1,
411 RFREG_OFFSET_MASK,
412 rtlphy->rfreg_chnlval[rfpath]);
413 }
414 break;
415 default:
416 pr_err("switch case %#x not processed\n",
417 currentcmd->cmdid);
418 break;
419 }
420
421 break;
422 } while (true);
423
424 (*delay) = currentcmd->msdelay;
425 (*step)++;
426 return false;
427 }
428
429 u8 rtl92s_phy_sw_chnl(struct ieee80211_hw *hw)
430 {
431 struct rtl_priv *rtlpriv = rtl_priv(hw);
432 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
433 struct rtl_phy *rtlphy = &(rtlpriv->phy);
434 u32 delay;
435 bool ret;
436
437 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "switch to channel%d\n",
438 rtlphy->current_channel);
439
440 if (rtlphy->sw_chnl_inprogress)
441 return 0;
442
443 if (rtlphy->set_bwmode_inprogress)
444 return 0;
445
446 if (is_hal_stop(rtlhal))
447 return 0;
448
449 rtlphy->sw_chnl_inprogress = true;
450 rtlphy->sw_chnl_stage = 0;
451 rtlphy->sw_chnl_step = 0;
452
453 do {
454 if (!rtlphy->sw_chnl_inprogress)
455 break;
456
457 ret = _rtl92s_phy_sw_chnl_step_by_step(hw,
458 rtlphy->current_channel,
459 &rtlphy->sw_chnl_stage,
460 &rtlphy->sw_chnl_step, &delay);
461 if (!ret) {
462 if (delay > 0)
463 mdelay(delay);
464 else
465 continue;
466 } else {
467 rtlphy->sw_chnl_inprogress = false;
468 }
469 break;
470 } while (true);
471
472 rtlphy->sw_chnl_inprogress = false;
473
474 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
475
476 return 1;
477 }
478
479 static void _rtl92se_phy_set_rf_sleep(struct ieee80211_hw *hw)
480 {
481 struct rtl_priv *rtlpriv = rtl_priv(hw);
482 u8 u1btmp;
483
484 u1btmp = rtl_read_byte(rtlpriv, LDOV12D_CTRL);
485 u1btmp |= BIT(0);
486
487 rtl_write_byte(rtlpriv, LDOV12D_CTRL, u1btmp);
488 rtl_write_byte(rtlpriv, SPS1_CTRL, 0x0);
489 rtl_write_byte(rtlpriv, TXPAUSE, 0xFF);
490 rtl_write_word(rtlpriv, CMDR, 0x57FC);
491 udelay(100);
492
493 rtl_write_word(rtlpriv, CMDR, 0x77FC);
494 rtl_write_byte(rtlpriv, PHY_CCA, 0x0);
495 udelay(10);
496
497 rtl_write_word(rtlpriv, CMDR, 0x37FC);
498 udelay(10);
499
500 rtl_write_word(rtlpriv, CMDR, 0x77FC);
501 udelay(10);
502
503 rtl_write_word(rtlpriv, CMDR, 0x57FC);
504
505 /* we should chnge GPIO to input mode
506 * this will drop away current about 25mA*/
507 rtl8192se_gpiobit3_cfg_inputmode(hw);
508 }
509
510 bool rtl92s_phy_set_rf_power_state(struct ieee80211_hw *hw,
511 enum rf_pwrstate rfpwr_state)
512 {
513 struct rtl_priv *rtlpriv = rtl_priv(hw);
514 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
515 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
516 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
517 bool bresult = true;
518 u8 i, queue_id;
519 struct rtl8192_tx_ring *ring = NULL;
520
521 if (rfpwr_state == ppsc->rfpwr_state)
522 return false;
523
524 switch (rfpwr_state) {
525 case ERFON:{
526 if ((ppsc->rfpwr_state == ERFOFF) &&
527 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
528
529 bool rtstatus;
530 u32 initializecount = 0;
531 do {
532 initializecount++;
533 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
534 "IPS Set eRf nic enable\n");
535 rtstatus = rtl_ps_enable_nic(hw);
536 } while (!rtstatus && (initializecount < 10));
537
538 RT_CLEAR_PS_LEVEL(ppsc,
539 RT_RF_OFF_LEVL_HALT_NIC);
540 } else {
541 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
542 "awake, sleeped:%d ms state_inap:%x\n",
543 jiffies_to_msecs(jiffies -
544 ppsc->
545 last_sleep_jiffies),
546 rtlpriv->psc.state_inap);
547 ppsc->last_awake_jiffies = jiffies;
548 rtl_write_word(rtlpriv, CMDR, 0x37FC);
549 rtl_write_byte(rtlpriv, TXPAUSE, 0x00);
550 rtl_write_byte(rtlpriv, PHY_CCA, 0x3);
551 }
552
553 if (mac->link_state == MAC80211_LINKED)
554 rtlpriv->cfg->ops->led_control(hw,
555 LED_CTL_LINK);
556 else
557 rtlpriv->cfg->ops->led_control(hw,
558 LED_CTL_NO_LINK);
559 break;
560 }
561 case ERFOFF:{
562 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
563 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
564 "IPS Set eRf nic disable\n");
565 rtl_ps_disable_nic(hw);
566 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
567 } else {
568 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
569 rtlpriv->cfg->ops->led_control(hw,
570 LED_CTL_NO_LINK);
571 else
572 rtlpriv->cfg->ops->led_control(hw,
573 LED_CTL_POWER_OFF);
574 }
575 break;
576 }
577 case ERFSLEEP:
578 if (ppsc->rfpwr_state == ERFOFF)
579 return false;
580
581 for (queue_id = 0, i = 0;
582 queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
583 ring = &pcipriv->dev.tx_ring[queue_id];
584 if (skb_queue_len(&ring->queue) == 0 ||
585 queue_id == BEACON_QUEUE) {
586 queue_id++;
587 continue;
588 } else {
589 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
590 "eRf Off/Sleep: %d times TcbBusyQueue[%d] = %d before doze!\n",
591 i + 1, queue_id,
592 skb_queue_len(&ring->queue));
593
594 udelay(10);
595 i++;
596 }
597
598 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
599 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
600 "ERFOFF: %d times TcbBusyQueue[%d] = %d !\n",
601 MAX_DOZE_WAITING_TIMES_9x,
602 queue_id,
603 skb_queue_len(&ring->queue));
604 break;
605 }
606 }
607
608 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
609 "Set ERFSLEEP awaked:%d ms\n",
610 jiffies_to_msecs(jiffies -
611 ppsc->last_awake_jiffies));
612
613 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
614 "sleep awaked:%d ms state_inap:%x\n",
615 jiffies_to_msecs(jiffies -
616 ppsc->last_awake_jiffies),
617 rtlpriv->psc.state_inap);
618 ppsc->last_sleep_jiffies = jiffies;
619 _rtl92se_phy_set_rf_sleep(hw);
620 break;
621 default:
622 pr_err("switch case %#x not processed\n",
623 rfpwr_state);
624 bresult = false;
625 break;
626 }
627
628 if (bresult)
629 ppsc->rfpwr_state = rfpwr_state;
630
631 return bresult;
632 }
633
634 static bool _rtl92s_phy_config_rfpa_bias_current(struct ieee80211_hw *hw,
635 enum radio_path rfpath)
636 {
637 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
638 bool rtstatus = true;
639 u32 tmpval = 0;
640
641 /* If inferiority IC, we have to increase the PA bias current */
642 if (rtlhal->ic_class != IC_INFERIORITY_A) {
643 tmpval = rtl92s_phy_query_rf_reg(hw, rfpath, RF_IPA, 0xf);
644 rtl92s_phy_set_rf_reg(hw, rfpath, RF_IPA, 0xf, tmpval + 1);
645 }
646
647 return rtstatus;
648 }
649
650 static void _rtl92s_store_pwrindex_diffrate_offset(struct ieee80211_hw *hw,
651 u32 reg_addr, u32 bitmask, u32 data)
652 {
653 struct rtl_priv *rtlpriv = rtl_priv(hw);
654 struct rtl_phy *rtlphy = &(rtlpriv->phy);
655 int index;
656
657 if (reg_addr == RTXAGC_RATE18_06)
658 index = 0;
659 else if (reg_addr == RTXAGC_RATE54_24)
660 index = 1;
661 else if (reg_addr == RTXAGC_CCK_MCS32)
662 index = 6;
663 else if (reg_addr == RTXAGC_MCS03_MCS00)
664 index = 2;
665 else if (reg_addr == RTXAGC_MCS07_MCS04)
666 index = 3;
667 else if (reg_addr == RTXAGC_MCS11_MCS08)
668 index = 4;
669 else if (reg_addr == RTXAGC_MCS15_MCS12)
670 index = 5;
671 else
672 return;
673
674 rtlphy->mcs_offset[rtlphy->pwrgroup_cnt][index] = data;
675 if (index == 5)
676 rtlphy->pwrgroup_cnt++;
677 }
678
679 static void _rtl92s_phy_init_register_definition(struct ieee80211_hw *hw)
680 {
681 struct rtl_priv *rtlpriv = rtl_priv(hw);
682 struct rtl_phy *rtlphy = &(rtlpriv->phy);
683
684 /*RF Interface Sowrtware Control */
685 rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;
686 rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;
687 rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW;
688 rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW;
689
690 /* RF Interface Readback Value */
691 rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB;
692 rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB;
693 rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB;
694 rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB;
695
696 /* RF Interface Output (and Enable) */
697 rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE;
698 rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;
699 rtlphy->phyreg_def[RF90_PATH_C].rfintfo = RFPGA0_XC_RFINTERFACEOE;
700 rtlphy->phyreg_def[RF90_PATH_D].rfintfo = RFPGA0_XD_RFINTERFACEOE;
701
702 /* RF Interface (Output and) Enable */
703 rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE;
704 rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;
705 rtlphy->phyreg_def[RF90_PATH_C].rfintfe = RFPGA0_XC_RFINTERFACEOE;
706 rtlphy->phyreg_def[RF90_PATH_D].rfintfe = RFPGA0_XD_RFINTERFACEOE;
707
708 /* Addr of LSSI. Wirte RF register by driver */
709 rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset =
710 RFPGA0_XA_LSSIPARAMETER;
711 rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset =
712 RFPGA0_XB_LSSIPARAMETER;
713 rtlphy->phyreg_def[RF90_PATH_C].rf3wire_offset =
714 RFPGA0_XC_LSSIPARAMETER;
715 rtlphy->phyreg_def[RF90_PATH_D].rf3wire_offset =
716 RFPGA0_XD_LSSIPARAMETER;
717
718 /* RF parameter */
719 rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = RFPGA0_XAB_RFPARAMETER;
720 rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = RFPGA0_XAB_RFPARAMETER;
721 rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = RFPGA0_XCD_RFPARAMETER;
722 rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = RFPGA0_XCD_RFPARAMETER;
723
724 /* Tx AGC Gain Stage (same for all path. Should we remove this?) */
725 rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE;
726 rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE;
727 rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE;
728 rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE;
729
730 /* Tranceiver A~D HSSI Parameter-1 */
731 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1;
732 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1;
733 rtlphy->phyreg_def[RF90_PATH_C].rfhssi_para1 = RFPGA0_XC_HSSIPARAMETER1;
734 rtlphy->phyreg_def[RF90_PATH_D].rfhssi_para1 = RFPGA0_XD_HSSIPARAMETER1;
735
736 /* Tranceiver A~D HSSI Parameter-2 */
737 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2;
738 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2;
739 rtlphy->phyreg_def[RF90_PATH_C].rfhssi_para2 = RFPGA0_XC_HSSIPARAMETER2;
740 rtlphy->phyreg_def[RF90_PATH_D].rfhssi_para2 = RFPGA0_XD_HSSIPARAMETER2;
741
742 /* RF switch Control */
743 rtlphy->phyreg_def[RF90_PATH_A].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;
744 rtlphy->phyreg_def[RF90_PATH_B].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;
745 rtlphy->phyreg_def[RF90_PATH_C].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;
746 rtlphy->phyreg_def[RF90_PATH_D].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;
747
748 /* AGC control 1 */
749 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1;
750 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1;
751 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1;
752 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1;
753
754 /* AGC control 2 */
755 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2;
756 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2;
757 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2;
758 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2;
759
760 /* RX AFE control 1 */
761 rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbal = ROFDM0_XARXIQIMBALANCE;
762 rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbal = ROFDM0_XBRXIQIMBALANCE;
763 rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbal = ROFDM0_XCRXIQIMBALANCE;
764 rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbal = ROFDM0_XDRXIQIMBALANCE;
765
766 /* RX AFE control 1 */
767 rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE;
768 rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE;
769 rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE;
770 rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE;
771
772 /* Tx AFE control 1 */
773 rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbal = ROFDM0_XATXIQIMBALANCE;
774 rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbal = ROFDM0_XBTXIQIMBALANCE;
775 rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbal = ROFDM0_XCTXIQIMBALANCE;
776 rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbal = ROFDM0_XDTXIQIMBALANCE;
777
778 /* Tx AFE control 2 */
779 rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATXAFE;
780 rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTXAFE;
781 rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTXAFE;
782 rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTXAFE;
783
784 /* Tranceiver LSSI Readback */
785 rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RFPGA0_XA_LSSIREADBACK;
786 rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK;
787 rtlphy->phyreg_def[RF90_PATH_C].rf_rb = RFPGA0_XC_LSSIREADBACK;
788 rtlphy->phyreg_def[RF90_PATH_D].rf_rb = RFPGA0_XD_LSSIREADBACK;
789
790 /* Tranceiver LSSI Readback PI mode */
791 rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = TRANSCEIVERA_HSPI_READBACK;
792 rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVERB_HSPI_READBACK;
793 }
794
795
796 static bool _rtl92s_phy_config_bb(struct ieee80211_hw *hw, u8 configtype)
797 {
798 int i;
799 u32 *phy_reg_table;
800 u32 *agc_table;
801 u16 phy_reg_len, agc_len;
802
803 agc_len = AGCTAB_ARRAYLENGTH;
804 agc_table = rtl8192seagctab_array;
805 /* Default RF_type: 2T2R */
806 phy_reg_len = PHY_REG_2T2RARRAYLENGTH;
807 phy_reg_table = rtl8192sephy_reg_2t2rarray;
808
809 if (configtype == BASEBAND_CONFIG_PHY_REG) {
810 for (i = 0; i < phy_reg_len; i = i + 2) {
811 rtl_addr_delay(phy_reg_table[i]);
812
813 /* Add delay for ECS T20 & LG malow platform, */
814 udelay(1);
815
816 rtl92s_phy_set_bb_reg(hw, phy_reg_table[i], MASKDWORD,
817 phy_reg_table[i + 1]);
818 }
819 } else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
820 for (i = 0; i < agc_len; i = i + 2) {
821 rtl92s_phy_set_bb_reg(hw, agc_table[i], MASKDWORD,
822 agc_table[i + 1]);
823
824 /* Add delay for ECS T20 & LG malow platform */
825 udelay(1);
826 }
827 }
828
829 return true;
830 }
831
832 static bool _rtl92s_phy_set_bb_to_diff_rf(struct ieee80211_hw *hw,
833 u8 configtype)
834 {
835 struct rtl_priv *rtlpriv = rtl_priv(hw);
836 struct rtl_phy *rtlphy = &(rtlpriv->phy);
837 u32 *phy_regarray2xtxr_table;
838 u16 phy_regarray2xtxr_len;
839 int i;
840
841 if (rtlphy->rf_type == RF_1T1R) {
842 phy_regarray2xtxr_table = rtl8192sephy_changeto_1t1rarray;
843 phy_regarray2xtxr_len = PHY_CHANGETO_1T1RARRAYLENGTH;
844 } else if (rtlphy->rf_type == RF_1T2R) {
845 phy_regarray2xtxr_table = rtl8192sephy_changeto_1t2rarray;
846 phy_regarray2xtxr_len = PHY_CHANGETO_1T2RARRAYLENGTH;
847 } else {
848 return false;
849 }
850
851 if (configtype == BASEBAND_CONFIG_PHY_REG) {
852 for (i = 0; i < phy_regarray2xtxr_len; i = i + 3) {
853 rtl_addr_delay(phy_regarray2xtxr_table[i]);
854
855 rtl92s_phy_set_bb_reg(hw, phy_regarray2xtxr_table[i],
856 phy_regarray2xtxr_table[i + 1],
857 phy_regarray2xtxr_table[i + 2]);
858 }
859 }
860
861 return true;
862 }
863
864 static bool _rtl92s_phy_config_bb_with_pg(struct ieee80211_hw *hw,
865 u8 configtype)
866 {
867 int i;
868 u32 *phy_table_pg;
869 u16 phy_pg_len;
870
871 phy_pg_len = PHY_REG_ARRAY_PGLENGTH;
872 phy_table_pg = rtl8192sephy_reg_array_pg;
873
874 if (configtype == BASEBAND_CONFIG_PHY_REG) {
875 for (i = 0; i < phy_pg_len; i = i + 3) {
876 rtl_addr_delay(phy_table_pg[i]);
877
878 _rtl92s_store_pwrindex_diffrate_offset(hw,
879 phy_table_pg[i],
880 phy_table_pg[i + 1],
881 phy_table_pg[i + 2]);
882 rtl92s_phy_set_bb_reg(hw, phy_table_pg[i],
883 phy_table_pg[i + 1],
884 phy_table_pg[i + 2]);
885 }
886 }
887
888 return true;
889 }
890
891 static bool _rtl92s_phy_bb_config_parafile(struct ieee80211_hw *hw)
892 {
893 struct rtl_priv *rtlpriv = rtl_priv(hw);
894 struct rtl_phy *rtlphy = &(rtlpriv->phy);
895 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
896 bool rtstatus = true;
897
898 /* 1. Read PHY_REG.TXT BB INIT!! */
899 /* We will separate as 1T1R/1T2R/1T2R_GREEN/2T2R */
900 if (rtlphy->rf_type == RF_1T2R || rtlphy->rf_type == RF_2T2R ||
901 rtlphy->rf_type == RF_1T1R || rtlphy->rf_type == RF_2T2R_GREEN) {
902 rtstatus = _rtl92s_phy_config_bb(hw, BASEBAND_CONFIG_PHY_REG);
903
904 if (rtlphy->rf_type != RF_2T2R &&
905 rtlphy->rf_type != RF_2T2R_GREEN)
906 /* so we should reconfig BB reg with the right
907 * PHY parameters. */
908 rtstatus = _rtl92s_phy_set_bb_to_diff_rf(hw,
909 BASEBAND_CONFIG_PHY_REG);
910 } else {
911 rtstatus = false;
912 }
913
914 if (!rtstatus) {
915 pr_err("Write BB Reg Fail!!\n");
916 goto phy_bb8190_config_parafile_fail;
917 }
918
919 /* 2. If EEPROM or EFUSE autoload OK, We must config by
920 * PHY_REG_PG.txt */
921 if (rtlefuse->autoload_failflag == false) {
922 rtlphy->pwrgroup_cnt = 0;
923
924 rtstatus = _rtl92s_phy_config_bb_with_pg(hw,
925 BASEBAND_CONFIG_PHY_REG);
926 }
927 if (!rtstatus) {
928 pr_err("_rtl92s_phy_bb_config_parafile(): BB_PG Reg Fail!!\n");
929 goto phy_bb8190_config_parafile_fail;
930 }
931
932 /* 3. BB AGC table Initialization */
933 rtstatus = _rtl92s_phy_config_bb(hw, BASEBAND_CONFIG_AGC_TAB);
934
935 if (!rtstatus) {
936 pr_err("%s(): AGC Table Fail\n", __func__);
937 goto phy_bb8190_config_parafile_fail;
938 }
939
940 /* Check if the CCK HighPower is turned ON. */
941 /* This is used to calculate PWDB. */
942 rtlphy->cck_high_power = (bool)(rtl92s_phy_query_bb_reg(hw,
943 RFPGA0_XA_HSSIPARAMETER2, 0x200));
944
945 phy_bb8190_config_parafile_fail:
946 return rtstatus;
947 }
948
949 u8 rtl92s_phy_config_rf(struct ieee80211_hw *hw, enum radio_path rfpath)
950 {
951 struct rtl_priv *rtlpriv = rtl_priv(hw);
952 struct rtl_phy *rtlphy = &(rtlpriv->phy);
953 int i;
954 bool rtstatus = true;
955 u32 *radio_a_table;
956 u32 *radio_b_table;
957 u16 radio_a_tblen, radio_b_tblen;
958
959 radio_a_tblen = RADIOA_1T_ARRAYLENGTH;
960 radio_a_table = rtl8192seradioa_1t_array;
961
962 /* Using Green mode array table for RF_2T2R_GREEN */
963 if (rtlphy->rf_type == RF_2T2R_GREEN) {
964 radio_b_table = rtl8192seradiob_gm_array;
965 radio_b_tblen = RADIOB_GM_ARRAYLENGTH;
966 } else {
967 radio_b_table = rtl8192seradiob_array;
968 radio_b_tblen = RADIOB_ARRAYLENGTH;
969 }
970
971 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Radio No %x\n", rfpath);
972 rtstatus = true;
973
974 switch (rfpath) {
975 case RF90_PATH_A:
976 for (i = 0; i < radio_a_tblen; i = i + 2) {
977 rtl_rfreg_delay(hw, rfpath, radio_a_table[i],
978 MASK20BITS, radio_a_table[i + 1]);
979
980 }
981
982 /* PA Bias current for inferiority IC */
983 _rtl92s_phy_config_rfpa_bias_current(hw, rfpath);
984 break;
985 case RF90_PATH_B:
986 for (i = 0; i < radio_b_tblen; i = i + 2) {
987 rtl_rfreg_delay(hw, rfpath, radio_b_table[i],
988 MASK20BITS, radio_b_table[i + 1]);
989 }
990 break;
991 case RF90_PATH_C:
992 ;
993 break;
994 case RF90_PATH_D:
995 ;
996 break;
997 default:
998 break;
999 }
1000
1001 return rtstatus;
1002 }
1003
1004
1005 bool rtl92s_phy_mac_config(struct ieee80211_hw *hw)
1006 {
1007 struct rtl_priv *rtlpriv = rtl_priv(hw);
1008 u32 i;
1009 u32 arraylength;
1010 u32 *ptrarray;
1011
1012 arraylength = MAC_2T_ARRAYLENGTH;
1013 ptrarray = rtl8192semac_2t_array;
1014
1015 for (i = 0; i < arraylength; i = i + 2)
1016 rtl_write_byte(rtlpriv, ptrarray[i], (u8)ptrarray[i + 1]);
1017
1018 return true;
1019 }
1020
1021
1022 bool rtl92s_phy_bb_config(struct ieee80211_hw *hw)
1023 {
1024 struct rtl_priv *rtlpriv = rtl_priv(hw);
1025 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1026 bool rtstatus = true;
1027 u8 pathmap, index, rf_num = 0;
1028 u8 path1, path2;
1029
1030 _rtl92s_phy_init_register_definition(hw);
1031
1032 /* Config BB and AGC */
1033 rtstatus = _rtl92s_phy_bb_config_parafile(hw);
1034
1035
1036 /* Check BB/RF confiuration setting. */
1037 /* We only need to configure RF which is turned on. */
1038 path1 = (u8)(rtl92s_phy_query_bb_reg(hw, RFPGA0_TXINFO, 0xf));
1039 mdelay(10);
1040 path2 = (u8)(rtl92s_phy_query_bb_reg(hw, ROFDM0_TRXPATHENABLE, 0xf));
1041 pathmap = path1 | path2;
1042
1043 rtlphy->rf_pathmap = pathmap;
1044 for (index = 0; index < 4; index++) {
1045 if ((pathmap >> index) & 0x1)
1046 rf_num++;
1047 }
1048
1049 if ((rtlphy->rf_type == RF_1T1R && rf_num != 1) ||
1050 (rtlphy->rf_type == RF_1T2R && rf_num != 2) ||
1051 (rtlphy->rf_type == RF_2T2R && rf_num != 2) ||
1052 (rtlphy->rf_type == RF_2T2R_GREEN && rf_num != 2)) {
1053 pr_err("RF_Type(%x) does not match RF_Num(%x)!!\n",
1054 rtlphy->rf_type, rf_num);
1055 pr_err("path1 0x%x, path2 0x%x, pathmap 0x%x\n",
1056 path1, path2, pathmap);
1057 }
1058
1059 return rtstatus;
1060 }
1061
1062 bool rtl92s_phy_rf_config(struct ieee80211_hw *hw)
1063 {
1064 struct rtl_priv *rtlpriv = rtl_priv(hw);
1065 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1066
1067 /* Initialize general global value */
1068 if (rtlphy->rf_type == RF_1T1R)
1069 rtlphy->num_total_rfpath = 1;
1070 else
1071 rtlphy->num_total_rfpath = 2;
1072
1073 /* Config BB and RF */
1074 return rtl92s_phy_rf6052_config(hw);
1075 }
1076
1077 void rtl92s_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
1078 {
1079 struct rtl_priv *rtlpriv = rtl_priv(hw);
1080 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1081
1082 /* read rx initial gain */
1083 rtlphy->default_initialgain[0] = rtl_get_bbreg(hw,
1084 ROFDM0_XAAGCCORE1, MASKBYTE0);
1085 rtlphy->default_initialgain[1] = rtl_get_bbreg(hw,
1086 ROFDM0_XBAGCCORE1, MASKBYTE0);
1087 rtlphy->default_initialgain[2] = rtl_get_bbreg(hw,
1088 ROFDM0_XCAGCCORE1, MASKBYTE0);
1089 rtlphy->default_initialgain[3] = rtl_get_bbreg(hw,
1090 ROFDM0_XDAGCCORE1, MASKBYTE0);
1091 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1092 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x)\n",
1093 rtlphy->default_initialgain[0],
1094 rtlphy->default_initialgain[1],
1095 rtlphy->default_initialgain[2],
1096 rtlphy->default_initialgain[3]);
1097
1098 /* read framesync */
1099 rtlphy->framesync = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR3, MASKBYTE0);
1100 rtlphy->framesync_c34 = rtl_get_bbreg(hw, ROFDM0_RXDETECTOR2,
1101 MASKDWORD);
1102 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1103 "Default framesync (0x%x) = 0x%x\n",
1104 ROFDM0_RXDETECTOR3, rtlphy->framesync);
1105
1106 }
1107
1108 static void _rtl92s_phy_get_txpower_index(struct ieee80211_hw *hw, u8 channel,
1109 u8 *cckpowerlevel, u8 *ofdmpowerlevel)
1110 {
1111 struct rtl_priv *rtlpriv = rtl_priv(hw);
1112 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1113 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1114 u8 index = (channel - 1);
1115
1116 /* 1. CCK */
1117 /* RF-A */
1118 cckpowerlevel[0] = rtlefuse->txpwrlevel_cck[0][index];
1119 /* RF-B */
1120 cckpowerlevel[1] = rtlefuse->txpwrlevel_cck[1][index];
1121
1122 /* 2. OFDM for 1T or 2T */
1123 if (rtlphy->rf_type == RF_1T2R || rtlphy->rf_type == RF_1T1R) {
1124 /* Read HT 40 OFDM TX power */
1125 ofdmpowerlevel[0] = rtlefuse->txpwrlevel_ht40_1s[0][index];
1126 ofdmpowerlevel[1] = rtlefuse->txpwrlevel_ht40_1s[1][index];
1127 } else if (rtlphy->rf_type == RF_2T2R) {
1128 /* Read HT 40 OFDM TX power */
1129 ofdmpowerlevel[0] = rtlefuse->txpwrlevel_ht40_2s[0][index];
1130 ofdmpowerlevel[1] = rtlefuse->txpwrlevel_ht40_2s[1][index];
1131 } else {
1132 ofdmpowerlevel[0] = 0;
1133 ofdmpowerlevel[1] = 0;
1134 }
1135 }
1136
1137 static void _rtl92s_phy_ccxpower_indexcheck(struct ieee80211_hw *hw,
1138 u8 channel, u8 *cckpowerlevel, u8 *ofdmpowerlevel)
1139 {
1140 struct rtl_priv *rtlpriv = rtl_priv(hw);
1141 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1142
1143 rtlphy->cur_cck_txpwridx = cckpowerlevel[0];
1144 rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0];
1145 }
1146
1147 void rtl92s_phy_set_txpower(struct ieee80211_hw *hw, u8 channel)
1148 {
1149 struct rtl_priv *rtlpriv = rtl_priv(hw);
1150 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1151 /* [0]:RF-A, [1]:RF-B */
1152 u8 cckpowerlevel[2], ofdmpowerlevel[2];
1153
1154 if (!rtlefuse->txpwr_fromeprom)
1155 return;
1156
1157 /* Mainly we use RF-A Tx Power to write the Tx Power registers,
1158 * but the RF-B Tx Power must be calculated by the antenna diff.
1159 * So we have to rewrite Antenna gain offset register here.
1160 * Please refer to BB register 0x80c
1161 * 1. For CCK.
1162 * 2. For OFDM 1T or 2T */
1163 _rtl92s_phy_get_txpower_index(hw, channel, &cckpowerlevel[0],
1164 &ofdmpowerlevel[0]);
1165
1166 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
1167 "Channel-%d, cckPowerLevel (A / B) = 0x%x / 0x%x, ofdmPowerLevel (A / B) = 0x%x / 0x%x\n",
1168 channel, cckpowerlevel[0], cckpowerlevel[1],
1169 ofdmpowerlevel[0], ofdmpowerlevel[1]);
1170
1171 _rtl92s_phy_ccxpower_indexcheck(hw, channel, &cckpowerlevel[0],
1172 &ofdmpowerlevel[0]);
1173
1174 rtl92s_phy_rf6052_set_ccktxpower(hw, cckpowerlevel[0]);
1175 rtl92s_phy_rf6052_set_ofdmtxpower(hw, &ofdmpowerlevel[0], channel);
1176
1177 }
1178
1179 void rtl92s_phy_chk_fwcmd_iodone(struct ieee80211_hw *hw)
1180 {
1181 struct rtl_priv *rtlpriv = rtl_priv(hw);
1182 u16 pollingcnt = 10000;
1183 u32 tmpvalue;
1184
1185 /* Make sure that CMD IO has be accepted by FW. */
1186 do {
1187 udelay(10);
1188
1189 tmpvalue = rtl_read_dword(rtlpriv, WFM5);
1190 if (tmpvalue == 0)
1191 break;
1192 } while (--pollingcnt);
1193
1194 if (pollingcnt == 0)
1195 pr_err("Set FW Cmd fail!!\n");
1196 }
1197
1198
1199 static void _rtl92s_phy_set_fwcmd_io(struct ieee80211_hw *hw)
1200 {
1201 struct rtl_priv *rtlpriv = rtl_priv(hw);
1202 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1203 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1204 u32 input, current_aid = 0;
1205
1206 if (is_hal_stop(rtlhal))
1207 return;
1208
1209 if (hal_get_firmwareversion(rtlpriv) < 0x34)
1210 goto skip;
1211 /* We re-map RA related CMD IO to combinational ones */
1212 /* if FW version is v.52 or later. */
1213 switch (rtlhal->current_fwcmd_io) {
1214 case FW_CMD_RA_REFRESH_N:
1215 rtlhal->current_fwcmd_io = FW_CMD_RA_REFRESH_N_COMB;
1216 break;
1217 case FW_CMD_RA_REFRESH_BG:
1218 rtlhal->current_fwcmd_io = FW_CMD_RA_REFRESH_BG_COMB;
1219 break;
1220 default:
1221 break;
1222 }
1223
1224 skip:
1225 switch (rtlhal->current_fwcmd_io) {
1226 case FW_CMD_RA_RESET:
1227 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_RA_RESET\n");
1228 rtl_write_dword(rtlpriv, WFM5, FW_RA_RESET);
1229 rtl92s_phy_chk_fwcmd_iodone(hw);
1230 break;
1231 case FW_CMD_RA_ACTIVE:
1232 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_RA_ACTIVE\n");
1233 rtl_write_dword(rtlpriv, WFM5, FW_RA_ACTIVE);
1234 rtl92s_phy_chk_fwcmd_iodone(hw);
1235 break;
1236 case FW_CMD_RA_REFRESH_N:
1237 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_RA_REFRESH_N\n");
1238 input = FW_RA_REFRESH;
1239 rtl_write_dword(rtlpriv, WFM5, input);
1240 rtl92s_phy_chk_fwcmd_iodone(hw);
1241 rtl_write_dword(rtlpriv, WFM5, FW_RA_ENABLE_RSSI_MASK);
1242 rtl92s_phy_chk_fwcmd_iodone(hw);
1243 break;
1244 case FW_CMD_RA_REFRESH_BG:
1245 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG,
1246 "FW_CMD_RA_REFRESH_BG\n");
1247 rtl_write_dword(rtlpriv, WFM5, FW_RA_REFRESH);
1248 rtl92s_phy_chk_fwcmd_iodone(hw);
1249 rtl_write_dword(rtlpriv, WFM5, FW_RA_DISABLE_RSSI_MASK);
1250 rtl92s_phy_chk_fwcmd_iodone(hw);
1251 break;
1252 case FW_CMD_RA_REFRESH_N_COMB:
1253 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG,
1254 "FW_CMD_RA_REFRESH_N_COMB\n");
1255 input = FW_RA_IOT_N_COMB;
1256 rtl_write_dword(rtlpriv, WFM5, input);
1257 rtl92s_phy_chk_fwcmd_iodone(hw);
1258 break;
1259 case FW_CMD_RA_REFRESH_BG_COMB:
1260 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG,
1261 "FW_CMD_RA_REFRESH_BG_COMB\n");
1262 input = FW_RA_IOT_BG_COMB;
1263 rtl_write_dword(rtlpriv, WFM5, input);
1264 rtl92s_phy_chk_fwcmd_iodone(hw);
1265 break;
1266 case FW_CMD_IQK_ENABLE:
1267 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_IQK_ENABLE\n");
1268 rtl_write_dword(rtlpriv, WFM5, FW_IQK_ENABLE);
1269 rtl92s_phy_chk_fwcmd_iodone(hw);
1270 break;
1271 case FW_CMD_PAUSE_DM_BY_SCAN:
1272 /* Lower initial gain */
1273 rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0, 0x17);
1274 rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0, 0x17);
1275 /* CCA threshold */
1276 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0x40);
1277 break;
1278 case FW_CMD_RESUME_DM_BY_SCAN:
1279 /* CCA threshold */
1280 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd);
1281 rtl92s_phy_set_txpower(hw, rtlphy->current_channel);
1282 break;
1283 case FW_CMD_HIGH_PWR_DISABLE:
1284 if (rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE)
1285 break;
1286
1287 /* Lower initial gain */
1288 rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0, 0x17);
1289 rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0, 0x17);
1290 /* CCA threshold */
1291 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0x40);
1292 break;
1293 case FW_CMD_HIGH_PWR_ENABLE:
1294 if ((rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) ||
1295 rtlpriv->dm.dynamic_txpower_enable)
1296 break;
1297
1298 /* CCA threshold */
1299 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd);
1300 break;
1301 case FW_CMD_LPS_ENTER:
1302 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_LPS_ENTER\n");
1303 current_aid = rtlpriv->mac80211.assoc_id;
1304 rtl_write_dword(rtlpriv, WFM5, (FW_LPS_ENTER |
1305 ((current_aid | 0xc000) << 8)));
1306 rtl92s_phy_chk_fwcmd_iodone(hw);
1307 /* FW set TXOP disable here, so disable EDCA
1308 * turbo mode until driver leave LPS */
1309 break;
1310 case FW_CMD_LPS_LEAVE:
1311 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_LPS_LEAVE\n");
1312 rtl_write_dword(rtlpriv, WFM5, FW_LPS_LEAVE);
1313 rtl92s_phy_chk_fwcmd_iodone(hw);
1314 break;
1315 case FW_CMD_ADD_A2_ENTRY:
1316 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, "FW_CMD_ADD_A2_ENTRY\n");
1317 rtl_write_dword(rtlpriv, WFM5, FW_ADD_A2_ENTRY);
1318 rtl92s_phy_chk_fwcmd_iodone(hw);
1319 break;
1320 case FW_CMD_CTRL_DM_BY_DRIVER:
1321 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1322 "FW_CMD_CTRL_DM_BY_DRIVER\n");
1323 rtl_write_dword(rtlpriv, WFM5, FW_CTRL_DM_BY_DRIVER);
1324 rtl92s_phy_chk_fwcmd_iodone(hw);
1325 break;
1326
1327 default:
1328 break;
1329 }
1330
1331 rtl92s_phy_chk_fwcmd_iodone(hw);
1332
1333 /* Clear FW CMD operation flag. */
1334 rtlhal->set_fwcmd_inprogress = false;
1335 }
1336
1337 bool rtl92s_phy_set_fw_cmd(struct ieee80211_hw *hw, enum fwcmd_iotype fw_cmdio)
1338 {
1339 struct rtl_priv *rtlpriv = rtl_priv(hw);
1340 struct dig_t *digtable = &rtlpriv->dm_digtable;
1341 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1342 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1343 u32 fw_param = FW_CMD_IO_PARA_QUERY(rtlpriv);
1344 u16 fw_cmdmap = FW_CMD_IO_QUERY(rtlpriv);
1345 bool postprocessing = false;
1346
1347 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1348 "Set FW Cmd(%#x), set_fwcmd_inprogress(%d)\n",
1349 fw_cmdio, rtlhal->set_fwcmd_inprogress);
1350
1351 do {
1352 /* We re-map to combined FW CMD ones if firmware version */
1353 /* is v.53 or later. */
1354 if (hal_get_firmwareversion(rtlpriv) >= 0x35) {
1355 switch (fw_cmdio) {
1356 case FW_CMD_RA_REFRESH_N:
1357 fw_cmdio = FW_CMD_RA_REFRESH_N_COMB;
1358 break;
1359 case FW_CMD_RA_REFRESH_BG:
1360 fw_cmdio = FW_CMD_RA_REFRESH_BG_COMB;
1361 break;
1362 default:
1363 break;
1364 }
1365 } else {
1366 if ((fw_cmdio == FW_CMD_IQK_ENABLE) ||
1367 (fw_cmdio == FW_CMD_RA_REFRESH_N) ||
1368 (fw_cmdio == FW_CMD_RA_REFRESH_BG)) {
1369 postprocessing = true;
1370 break;
1371 }
1372 }
1373
1374 /* If firmware version is v.62 or later,
1375 * use FW_CMD_IO_SET for FW_CMD_CTRL_DM_BY_DRIVER */
1376 if (hal_get_firmwareversion(rtlpriv) >= 0x3E) {
1377 if (fw_cmdio == FW_CMD_CTRL_DM_BY_DRIVER)
1378 fw_cmdio = FW_CMD_CTRL_DM_BY_DRIVER_NEW;
1379 }
1380
1381
1382 /* We shall revise all FW Cmd IO into Reg0x364
1383 * DM map table in the future. */
1384 switch (fw_cmdio) {
1385 case FW_CMD_RA_INIT:
1386 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, "RA init!!\n");
1387 fw_cmdmap |= FW_RA_INIT_CTL;
1388 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1389 /* Clear control flag to sync with FW. */
1390 FW_CMD_IO_CLR(rtlpriv, FW_RA_INIT_CTL);
1391 break;
1392 case FW_CMD_DIG_DISABLE:
1393 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1394 "Set DIG disable!!\n");
1395 fw_cmdmap &= ~FW_DIG_ENABLE_CTL;
1396 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1397 break;
1398 case FW_CMD_DIG_ENABLE:
1399 case FW_CMD_DIG_RESUME:
1400 if (!(rtlpriv->dm.dm_flag & HAL_DM_DIG_DISABLE)) {
1401 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1402 "Set DIG enable or resume!!\n");
1403 fw_cmdmap |= (FW_DIG_ENABLE_CTL | FW_SS_CTL);
1404 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1405 }
1406 break;
1407 case FW_CMD_DIG_HALT:
1408 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1409 "Set DIG halt!!\n");
1410 fw_cmdmap &= ~(FW_DIG_ENABLE_CTL | FW_SS_CTL);
1411 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1412 break;
1413 case FW_CMD_TXPWR_TRACK_THERMAL: {
1414 u8 thermalval = 0;
1415 fw_cmdmap |= FW_PWR_TRK_CTL;
1416
1417 /* Clear FW parameter in terms of thermal parts. */
1418 fw_param &= FW_PWR_TRK_PARAM_CLR;
1419
1420 thermalval = rtlpriv->dm.thermalvalue;
1421 fw_param |= ((thermalval << 24) |
1422 (rtlefuse->thermalmeter[0] << 16));
1423
1424 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1425 "Set TxPwr tracking!! FwCmdMap(%#x), FwParam(%#x)\n",
1426 fw_cmdmap, fw_param);
1427
1428 FW_CMD_PARA_SET(rtlpriv, fw_param);
1429 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1430
1431 /* Clear control flag to sync with FW. */
1432 FW_CMD_IO_CLR(rtlpriv, FW_PWR_TRK_CTL);
1433 }
1434 break;
1435 /* The following FW CMDs are only compatible to
1436 * v.53 or later. */
1437 case FW_CMD_RA_REFRESH_N_COMB:
1438 fw_cmdmap |= FW_RA_N_CTL;
1439
1440 /* Clear RA BG mode control. */
1441 fw_cmdmap &= ~(FW_RA_BG_CTL | FW_RA_INIT_CTL);
1442
1443 /* Clear FW parameter in terms of RA parts. */
1444 fw_param &= FW_RA_PARAM_CLR;
1445
1446 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1447 "[FW CMD] [New Version] Set RA/IOT Comb in n mode!! FwCmdMap(%#x), FwParam(%#x)\n",
1448 fw_cmdmap, fw_param);
1449
1450 FW_CMD_PARA_SET(rtlpriv, fw_param);
1451 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1452
1453 /* Clear control flag to sync with FW. */
1454 FW_CMD_IO_CLR(rtlpriv, FW_RA_N_CTL);
1455 break;
1456 case FW_CMD_RA_REFRESH_BG_COMB:
1457 fw_cmdmap |= FW_RA_BG_CTL;
1458
1459 /* Clear RA n-mode control. */
1460 fw_cmdmap &= ~(FW_RA_N_CTL | FW_RA_INIT_CTL);
1461 /* Clear FW parameter in terms of RA parts. */
1462 fw_param &= FW_RA_PARAM_CLR;
1463
1464 FW_CMD_PARA_SET(rtlpriv, fw_param);
1465 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1466
1467 /* Clear control flag to sync with FW. */
1468 FW_CMD_IO_CLR(rtlpriv, FW_RA_BG_CTL);
1469 break;
1470 case FW_CMD_IQK_ENABLE:
1471 fw_cmdmap |= FW_IQK_CTL;
1472 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1473 /* Clear control flag to sync with FW. */
1474 FW_CMD_IO_CLR(rtlpriv, FW_IQK_CTL);
1475 break;
1476 /* The following FW CMD is compatible to v.62 or later. */
1477 case FW_CMD_CTRL_DM_BY_DRIVER_NEW:
1478 fw_cmdmap |= FW_DRIVER_CTRL_DM_CTL;
1479 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1480 break;
1481 /* The followed FW Cmds needs post-processing later. */
1482 case FW_CMD_RESUME_DM_BY_SCAN:
1483 fw_cmdmap |= (FW_DIG_ENABLE_CTL |
1484 FW_HIGH_PWR_ENABLE_CTL |
1485 FW_SS_CTL);
1486
1487 if (rtlpriv->dm.dm_flag & HAL_DM_DIG_DISABLE ||
1488 !digtable->dig_enable_flag)
1489 fw_cmdmap &= ~FW_DIG_ENABLE_CTL;
1490
1491 if ((rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) ||
1492 rtlpriv->dm.dynamic_txpower_enable)
1493 fw_cmdmap &= ~FW_HIGH_PWR_ENABLE_CTL;
1494
1495 if ((digtable->dig_ext_port_stage ==
1496 DIG_EXT_PORT_STAGE_0) ||
1497 (digtable->dig_ext_port_stage ==
1498 DIG_EXT_PORT_STAGE_1))
1499 fw_cmdmap &= ~FW_DIG_ENABLE_CTL;
1500
1501 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1502 postprocessing = true;
1503 break;
1504 case FW_CMD_PAUSE_DM_BY_SCAN:
1505 fw_cmdmap &= ~(FW_DIG_ENABLE_CTL |
1506 FW_HIGH_PWR_ENABLE_CTL |
1507 FW_SS_CTL);
1508 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1509 postprocessing = true;
1510 break;
1511 case FW_CMD_HIGH_PWR_DISABLE:
1512 fw_cmdmap &= ~FW_HIGH_PWR_ENABLE_CTL;
1513 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1514 postprocessing = true;
1515 break;
1516 case FW_CMD_HIGH_PWR_ENABLE:
1517 if (!(rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) &&
1518 !rtlpriv->dm.dynamic_txpower_enable) {
1519 fw_cmdmap |= (FW_HIGH_PWR_ENABLE_CTL |
1520 FW_SS_CTL);
1521 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1522 postprocessing = true;
1523 }
1524 break;
1525 case FW_CMD_DIG_MODE_FA:
1526 fw_cmdmap |= FW_FA_CTL;
1527 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1528 break;
1529 case FW_CMD_DIG_MODE_SS:
1530 fw_cmdmap &= ~FW_FA_CTL;
1531 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1532 break;
1533 case FW_CMD_PAPE_CONTROL:
1534 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
1535 "[FW CMD] Set PAPE Control\n");
1536 fw_cmdmap &= ~FW_PAPE_CTL_BY_SW_HW;
1537
1538 FW_CMD_IO_SET(rtlpriv, fw_cmdmap);
1539 break;
1540 default:
1541 /* Pass to original FW CMD processing callback
1542 * routine. */
1543 postprocessing = true;
1544 break;
1545 }
1546 } while (false);
1547
1548 /* We shall post processing these FW CMD if
1549 * variable postprocessing is set.
1550 */
1551 if (postprocessing && !rtlhal->set_fwcmd_inprogress) {
1552 rtlhal->set_fwcmd_inprogress = true;
1553 /* Update current FW Cmd for callback use. */
1554 rtlhal->current_fwcmd_io = fw_cmdio;
1555 } else {
1556 return false;
1557 }
1558
1559 _rtl92s_phy_set_fwcmd_io(hw);
1560 return true;
1561 }
1562
1563 static void _rtl92s_phy_check_ephy_switchready(struct ieee80211_hw *hw)
1564 {
1565 struct rtl_priv *rtlpriv = rtl_priv(hw);
1566 u32 delay = 100;
1567 u8 regu1;
1568
1569 regu1 = rtl_read_byte(rtlpriv, 0x554);
1570 while ((regu1 & BIT(5)) && (delay > 0)) {
1571 regu1 = rtl_read_byte(rtlpriv, 0x554);
1572 delay--;
1573 /* We delay only 50us to prevent
1574 * being scheduled out. */
1575 udelay(50);
1576 }
1577 }
1578
1579 void rtl92s_phy_switch_ephy_parameter(struct ieee80211_hw *hw)
1580 {
1581 struct rtl_priv *rtlpriv = rtl_priv(hw);
1582 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1583
1584 /* The way to be capable to switch clock request
1585 * when the PG setting does not support clock request.
1586 * This is the backdoor solution to switch clock
1587 * request before ASPM or D3. */
1588 rtl_write_dword(rtlpriv, 0x540, 0x73c11);
1589 rtl_write_dword(rtlpriv, 0x548, 0x2407c);
1590
1591 /* Switch EPHY parameter!!!! */
1592 rtl_write_word(rtlpriv, 0x550, 0x1000);
1593 rtl_write_byte(rtlpriv, 0x554, 0x20);
1594 _rtl92s_phy_check_ephy_switchready(hw);
1595
1596 rtl_write_word(rtlpriv, 0x550, 0xa0eb);
1597 rtl_write_byte(rtlpriv, 0x554, 0x3e);
1598 _rtl92s_phy_check_ephy_switchready(hw);
1599
1600 rtl_write_word(rtlpriv, 0x550, 0xff80);
1601 rtl_write_byte(rtlpriv, 0x554, 0x39);
1602 _rtl92s_phy_check_ephy_switchready(hw);
1603
1604 /* Delay L1 enter time */
1605 if (ppsc->support_aspm && !ppsc->support_backdoor)
1606 rtl_write_byte(rtlpriv, 0x560, 0x40);
1607 else
1608 rtl_write_byte(rtlpriv, 0x560, 0x00);
1609
1610 }
1611
1612 void rtl92s_phy_set_beacon_hwreg(struct ieee80211_hw *hw, u16 beaconinterval)
1613 {
1614 struct rtl_priv *rtlpriv = rtl_priv(hw);
1615 u32 new_bcn_num = 0;
1616
1617 if (hal_get_firmwareversion(rtlpriv) >= 0x33) {
1618 /* Fw v.51 and later. */
1619 rtl_write_dword(rtlpriv, WFM5, 0xF1000000 |
1620 (beaconinterval << 8));
1621 } else {
1622 new_bcn_num = beaconinterval * 32 - 64;
1623 rtl_write_dword(rtlpriv, WFM3 + 4, new_bcn_num);
1624 rtl_write_dword(rtlpriv, WFM3, 0xB026007C);
1625 }
1626 }
Linux with added FPC-III support