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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / net / wireless / realtek / rtlwifi / rtl8723be / hw.c
blob979e5bfe5f457e31d432947b6b2f6158e8fabf6d
1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2014 Realtek Corporation.*/
3
4 #include "../wifi.h"
5 #include "../efuse.h"
6 #include "../base.h"
7 #include "../regd.h"
8 #include "../cam.h"
9 #include "../ps.h"
10 #include "../pci.h"
11 #include "reg.h"
12 #include "def.h"
13 #include "phy.h"
14 #include "../rtl8723com/phy_common.h"
15 #include "dm.h"
16 #include "../rtl8723com/dm_common.h"
17 #include "fw.h"
18 #include "../rtl8723com/fw_common.h"
19 #include "led.h"
20 #include "hw.h"
21 #include "../pwrseqcmd.h"
22 #include "pwrseq.h"
23 #include "../btcoexist/rtl_btc.h"
24 #include <linux/kernel.h>
25
26 #define LLT_CONFIG 5
27
28 static void _rtl8723be_return_beacon_queue_skb(struct ieee80211_hw *hw)
29 {
30 struct rtl_priv *rtlpriv = rtl_priv(hw);
31 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
32 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[BEACON_QUEUE];
33 unsigned long flags;
34
35 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
36 while (skb_queue_len(&ring->queue)) {
37 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
38 struct sk_buff *skb = __skb_dequeue(&ring->queue);
39
40 pci_unmap_single(rtlpci->pdev,
41 rtlpriv->cfg->ops->get_desc(
42 hw,
43 (u8 *)entry, true, HW_DESC_TXBUFF_ADDR),
44 skb->len, PCI_DMA_TODEVICE);
45 kfree_skb(skb);
46 ring->idx = (ring->idx + 1) % ring->entries;
47 }
48 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
49 }
50
51 static void _rtl8723be_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
52 u8 set_bits, u8 clear_bits)
53 {
54 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
55 struct rtl_priv *rtlpriv = rtl_priv(hw);
56
57 rtlpci->reg_bcn_ctrl_val |= set_bits;
58 rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
59
60 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val);
61 }
62
63 static void _rtl8723be_stop_tx_beacon(struct ieee80211_hw *hw)
64 {
65 struct rtl_priv *rtlpriv = rtl_priv(hw);
66 u8 tmp1byte;
67
68 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
69 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
70 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
71 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
72 tmp1byte &= ~(BIT(0));
73 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
74 }
75
76 static void _rtl8723be_resume_tx_beacon(struct ieee80211_hw *hw)
77 {
78 struct rtl_priv *rtlpriv = rtl_priv(hw);
79 u8 tmp1byte;
80
81 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
82 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
83 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
84 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
85 tmp1byte |= BIT(1);
86 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
87 }
88
89 static void _rtl8723be_enable_bcn_sub_func(struct ieee80211_hw *hw)
90 {
91 _rtl8723be_set_bcn_ctrl_reg(hw, 0, BIT(1));
92 }
93
94 static void _rtl8723be_disable_bcn_sub_func(struct ieee80211_hw *hw)
95 {
96 _rtl8723be_set_bcn_ctrl_reg(hw, BIT(1), 0);
97 }
98
99 static void _rtl8723be_set_fw_clock_on(struct ieee80211_hw *hw, u8 rpwm_val,
100 bool b_need_turn_off_ckk)
101 {
102 struct rtl_priv *rtlpriv = rtl_priv(hw);
103 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
104 bool b_support_remote_wake_up;
105 u32 count = 0, isr_regaddr, content;
106 bool b_schedule_timer = b_need_turn_off_ckk;
107 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
108 (u8 *)(&b_support_remote_wake_up));
109
110 if (!rtlhal->fw_ready)
111 return;
112 if (!rtlpriv->psc.fw_current_inpsmode)
113 return;
114
115 while (1) {
116 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
117 if (rtlhal->fw_clk_change_in_progress) {
118 while (rtlhal->fw_clk_change_in_progress) {
119 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
120 count++;
121 udelay(100);
122 if (count > 1000)
123 return;
124 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
125 }
126 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
127 } else {
128 rtlhal->fw_clk_change_in_progress = false;
129 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
130 break;
131 }
132 }
133
134 if (IS_IN_LOW_POWER_STATE(rtlhal->fw_ps_state)) {
135 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_SET_RPWM,
136 (u8 *)(&rpwm_val));
137 if (FW_PS_IS_ACK(rpwm_val)) {
138 isr_regaddr = REG_HISR;
139 content = rtl_read_dword(rtlpriv, isr_regaddr);
140 while (!(content & IMR_CPWM) && (count < 500)) {
141 udelay(50);
142 count++;
143 content = rtl_read_dword(rtlpriv, isr_regaddr);
144 }
145
146 if (content & IMR_CPWM) {
147 rtl_write_word(rtlpriv, isr_regaddr, 0x0100);
148 rtlhal->fw_ps_state = FW_PS_STATE_RF_ON;
149 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
150 "Receive CPWM INT!!! Set pHalData->FwPSState = %X\n",
151 rtlhal->fw_ps_state);
152 }
153 }
154
155 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
156 rtlhal->fw_clk_change_in_progress = false;
157 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
158 if (b_schedule_timer)
159 mod_timer(&rtlpriv->works.fw_clockoff_timer,
160 jiffies + MSECS(10));
161 } else {
162 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
163 rtlhal->fw_clk_change_in_progress = false;
164 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
165 }
166 }
167
168 static void _rtl8723be_set_fw_clock_off(struct ieee80211_hw *hw, u8 rpwm_val)
169 {
170 struct rtl_priv *rtlpriv = rtl_priv(hw);
171 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
172 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
173 struct rtl8192_tx_ring *ring;
174 enum rf_pwrstate rtstate;
175 bool b_schedule_timer = false;
176 u8 queue;
177
178 if (!rtlhal->fw_ready)
179 return;
180 if (!rtlpriv->psc.fw_current_inpsmode)
181 return;
182 if (!rtlhal->allow_sw_to_change_hwclc)
183 return;
184 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, (u8 *)(&rtstate));
185 if (rtstate == ERFOFF || rtlpriv->psc.inactive_pwrstate == ERFOFF)
186 return;
187
188 for (queue = 0; queue < RTL_PCI_MAX_TX_QUEUE_COUNT; queue++) {
189 ring = &rtlpci->tx_ring[queue];
190 if (skb_queue_len(&ring->queue)) {
191 b_schedule_timer = true;
192 break;
193 }
194 }
195
196 if (b_schedule_timer) {
197 mod_timer(&rtlpriv->works.fw_clockoff_timer,
198 jiffies + MSECS(10));
199 return;
200 }
201
202 if (FW_PS_STATE(rtlhal->fw_ps_state) != FW_PS_STATE_RF_OFF_LOW_PWR) {
203 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
204 if (!rtlhal->fw_clk_change_in_progress) {
205 rtlhal->fw_clk_change_in_progress = true;
206 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
207 rtlhal->fw_ps_state = FW_PS_STATE(rpwm_val);
208 rtl_write_word(rtlpriv, REG_HISR, 0x0100);
209 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
210 (u8 *)(&rpwm_val));
211 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
212 rtlhal->fw_clk_change_in_progress = false;
213 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
214 } else {
215 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
216 mod_timer(&rtlpriv->works.fw_clockoff_timer,
217 jiffies + MSECS(10));
218 }
219 }
220
221 }
222
223 static void _rtl8723be_set_fw_ps_rf_on(struct ieee80211_hw *hw)
224 {
225 u8 rpwm_val = 0;
226 rpwm_val |= (FW_PS_STATE_RF_OFF | FW_PS_ACK);
227 _rtl8723be_set_fw_clock_on(hw, rpwm_val, true);
228 }
229
230 static void _rtl8723be_fwlps_leave(struct ieee80211_hw *hw)
231 {
232 struct rtl_priv *rtlpriv = rtl_priv(hw);
233 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
234 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
235 bool fw_current_inps = false;
236 u8 rpwm_val = 0, fw_pwrmode = FW_PS_ACTIVE_MODE;
237
238 if (ppsc->low_power_enable) {
239 rpwm_val = (FW_PS_STATE_ALL_ON | FW_PS_ACK);/* RF on */
240 _rtl8723be_set_fw_clock_on(hw, rpwm_val, false);
241 rtlhal->allow_sw_to_change_hwclc = false;
242 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
243 (u8 *)(&fw_pwrmode));
244 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
245 (u8 *)(&fw_current_inps));
246 } else {
247 rpwm_val = FW_PS_STATE_ALL_ON; /* RF on */
248 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
249 (u8 *)(&rpwm_val));
250 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
251 (u8 *)(&fw_pwrmode));
252 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
253 (u8 *)(&fw_current_inps));
254 }
255
256 }
257
258 static void _rtl8723be_fwlps_enter(struct ieee80211_hw *hw)
259 {
260 struct rtl_priv *rtlpriv = rtl_priv(hw);
261 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
262 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
263 bool fw_current_inps = true;
264 u8 rpwm_val;
265
266 if (ppsc->low_power_enable) {
267 rpwm_val = FW_PS_STATE_RF_OFF_LOW_PWR; /* RF off */
268 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
269 (u8 *)(&fw_current_inps));
270 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
271 (u8 *)(&ppsc->fwctrl_psmode));
272 rtlhal->allow_sw_to_change_hwclc = true;
273 _rtl8723be_set_fw_clock_off(hw, rpwm_val);
274 } else {
275 rpwm_val = FW_PS_STATE_RF_OFF; /* RF off */
276 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
277 (u8 *)(&fw_current_inps));
278 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
279 (u8 *)(&ppsc->fwctrl_psmode));
280 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
281 (u8 *)(&rpwm_val));
282 }
283
284 }
285
286 void rtl8723be_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
287 {
288 struct rtl_priv *rtlpriv = rtl_priv(hw);
289 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
290 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
291
292 switch (variable) {
293 case HW_VAR_RCR:
294 *((u32 *)(val)) = rtlpci->receive_config;
295 break;
296 case HW_VAR_RF_STATE:
297 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
298 break;
299 case HW_VAR_FWLPS_RF_ON:{
300 enum rf_pwrstate rfstate;
301 u32 val_rcr;
302
303 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE,
304 (u8 *)(&rfstate));
305 if (rfstate == ERFOFF) {
306 *((bool *)(val)) = true;
307 } else {
308 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
309 val_rcr &= 0x00070000;
310 if (val_rcr)
311 *((bool *)(val)) = false;
312 else
313 *((bool *)(val)) = true;
314 }
315 }
316 break;
317 case HW_VAR_FW_PSMODE_STATUS:
318 *((bool *)(val)) = ppsc->fw_current_inpsmode;
319 break;
320 case HW_VAR_CORRECT_TSF:{
321 u64 tsf;
322 u32 *ptsf_low = (u32 *)&tsf;
323 u32 *ptsf_high = ((u32 *)&tsf) + 1;
324
325 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
326 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
327
328 *((u64 *)(val)) = tsf;
329 }
330 break;
331 case HAL_DEF_WOWLAN:
332 break;
333 default:
334 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
335 "switch case %#x not processed\n", variable);
336 break;
337 }
338 }
339
340 static void _rtl8723be_download_rsvd_page(struct ieee80211_hw *hw)
341 {
342 struct rtl_priv *rtlpriv = rtl_priv(hw);
343 u8 tmp_regcr, tmp_reg422, bcnvalid_reg;
344 u8 count = 0, dlbcn_count = 0;
345 bool b_recover = false;
346
347 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
348 rtl_write_byte(rtlpriv, REG_CR + 1,
349 (tmp_regcr | BIT(0)));
350
351 _rtl8723be_set_bcn_ctrl_reg(hw, 0, BIT(3));
352 _rtl8723be_set_bcn_ctrl_reg(hw, BIT(4), 0);
353
354 tmp_reg422 = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
355 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp_reg422 & (~BIT(6)));
356 if (tmp_reg422 & BIT(6))
357 b_recover = true;
358
359 do {
360 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2);
361 rtl_write_byte(rtlpriv, REG_TDECTRL + 2,
362 (bcnvalid_reg | BIT(0)));
363 _rtl8723be_return_beacon_queue_skb(hw);
364
365 rtl8723be_set_fw_rsvdpagepkt(hw, 0);
366 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2);
367 count = 0;
368 while (!(bcnvalid_reg & BIT(0)) && count < 20) {
369 count++;
370 udelay(10);
371 bcnvalid_reg = rtl_read_byte(rtlpriv,
372 REG_TDECTRL + 2);
373 }
374 dlbcn_count++;
375 } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5);
376
377 if (bcnvalid_reg & BIT(0))
378 rtl_write_byte(rtlpriv, REG_TDECTRL + 2, BIT(0));
379
380 _rtl8723be_set_bcn_ctrl_reg(hw, BIT(3), 0);
381 _rtl8723be_set_bcn_ctrl_reg(hw, 0, BIT(4));
382
383 if (b_recover)
384 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp_reg422);
385
386 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
387 rtl_write_byte(rtlpriv, REG_CR + 1, (tmp_regcr & ~(BIT(0))));
388 }
389
390 void rtl8723be_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
391 {
392 struct rtl_priv *rtlpriv = rtl_priv(hw);
393 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
394 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
395 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
396 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
397 u8 idx;
398
399 switch (variable) {
400 case HW_VAR_ETHER_ADDR:
401 for (idx = 0; idx < ETH_ALEN; idx++)
402 rtl_write_byte(rtlpriv, (REG_MACID + idx), val[idx]);
403 break;
404 case HW_VAR_BASIC_RATE:{
405 u16 b_rate_cfg = ((u16 *)val)[0];
406 u8 rate_index = 0;
407 b_rate_cfg = b_rate_cfg & 0x15f;
408 b_rate_cfg |= 0x01;
409 rtl_write_byte(rtlpriv, REG_RRSR, b_rate_cfg & 0xff);
410 rtl_write_byte(rtlpriv, REG_RRSR + 1, (b_rate_cfg >> 8) & 0xff);
411 while (b_rate_cfg > 0x1) {
412 b_rate_cfg = (b_rate_cfg >> 1);
413 rate_index++;
414 }
415 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, rate_index);
416 }
417 break;
418 case HW_VAR_BSSID:
419 for (idx = 0; idx < ETH_ALEN; idx++)
420 rtl_write_byte(rtlpriv, (REG_BSSID + idx), val[idx]);
421
422 break;
423 case HW_VAR_SIFS:
424 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
425 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
426
427 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
428 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
429
430 if (!mac->ht_enable)
431 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM, 0x0e0e);
432 else
433 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
434 *((u16 *)val));
435 break;
436 case HW_VAR_SLOT_TIME:{
437 u8 e_aci;
438
439 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
440 "HW_VAR_SLOT_TIME %x\n", val[0]);
441
442 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
443
444 for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
445 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM,
446 (u8 *)(&e_aci));
447 }
448 }
449 break;
450 case HW_VAR_ACK_PREAMBLE:{
451 u8 reg_tmp;
452 u8 short_preamble = (bool)(*(u8 *)val);
453 reg_tmp = rtl_read_byte(rtlpriv, REG_TRXPTCL_CTL + 2);
454 if (short_preamble) {
455 reg_tmp |= 0x02;
456 rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL + 2, reg_tmp);
457 } else {
458 reg_tmp &= 0xFD;
459 rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL + 2, reg_tmp);
460 }
461 }
462 break;
463 case HW_VAR_WPA_CONFIG:
464 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *)val));
465 break;
466 case HW_VAR_AMPDU_MIN_SPACE:{
467 u8 min_spacing_to_set;
468 u8 sec_min_space;
469
470 min_spacing_to_set = *((u8 *)val);
471 if (min_spacing_to_set <= 7) {
472 sec_min_space = 0;
473
474 if (min_spacing_to_set < sec_min_space)
475 min_spacing_to_set = sec_min_space;
476
477 mac->min_space_cfg = ((mac->min_space_cfg & 0xf8) |
478 min_spacing_to_set);
479
480 *val = min_spacing_to_set;
481
482 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
483 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
484 mac->min_space_cfg);
485
486 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
487 mac->min_space_cfg);
488 }
489 }
490 break;
491 case HW_VAR_SHORTGI_DENSITY:{
492 u8 density_to_set;
493
494 density_to_set = *((u8 *)val);
495 mac->min_space_cfg |= (density_to_set << 3);
496
497 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
498 "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
499 mac->min_space_cfg);
500
501 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
502 mac->min_space_cfg);
503 }
504 break;
505 case HW_VAR_AMPDU_FACTOR:{
506 u8 regtoset_normal[4] = {0x41, 0xa8, 0x72, 0xb9};
507 u8 factor_toset;
508 u8 *p_regtoset = NULL;
509 u8 index = 0;
510
511 p_regtoset = regtoset_normal;
512
513 factor_toset = *((u8 *)val);
514 if (factor_toset <= 3) {
515 factor_toset = (1 << (factor_toset + 2));
516 if (factor_toset > 0xf)
517 factor_toset = 0xf;
518
519 for (index = 0; index < 4; index++) {
520 if ((p_regtoset[index] & 0xf0) >
521 (factor_toset << 4))
522 p_regtoset[index] =
523 (p_regtoset[index] & 0x0f) |
524 (factor_toset << 4);
525
526 if ((p_regtoset[index] & 0x0f) > factor_toset)
527 p_regtoset[index] =
528 (p_regtoset[index] & 0xf0) |
529 (factor_toset);
530
531 rtl_write_byte(rtlpriv,
532 (REG_AGGLEN_LMT + index),
533 p_regtoset[index]);
534
535 }
536
537 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
538 "Set HW_VAR_AMPDU_FACTOR: %#x\n",
539 factor_toset);
540 }
541 }
542 break;
543 case HW_VAR_AC_PARAM:{
544 u8 e_aci = *((u8 *)val);
545 rtl8723_dm_init_edca_turbo(hw);
546
547 if (rtlpci->acm_method != EACMWAY2_SW)
548 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ACM_CTRL,
549 (u8 *)(&e_aci));
550 }
551 break;
552 case HW_VAR_ACM_CTRL:{
553 u8 e_aci = *((u8 *)val);
554 union aci_aifsn *p_aci_aifsn =
555 (union aci_aifsn *)(&(mac->ac[0].aifs));
556 u8 acm = p_aci_aifsn->f.acm;
557 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
558
559 acm_ctrl =
560 acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
561
562 if (acm) {
563 switch (e_aci) {
564 case AC0_BE:
565 acm_ctrl |= ACMHW_BEQEN;
566 break;
567 case AC2_VI:
568 acm_ctrl |= ACMHW_VIQEN;
569 break;
570 case AC3_VO:
571 acm_ctrl |= ACMHW_VOQEN;
572 break;
573 default:
574 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
575 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
576 acm);
577 break;
578 }
579 } else {
580 switch (e_aci) {
581 case AC0_BE:
582 acm_ctrl &= (~ACMHW_BEQEN);
583 break;
584 case AC2_VI:
585 acm_ctrl &= (~ACMHW_VIQEN);
586 break;
587 case AC3_VO:
588 acm_ctrl &= (~ACMHW_VOQEN);
589 break;
590 default:
591 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
592 "switch case %#x not processed\n",
593 e_aci);
594 break;
595 }
596 }
597
598 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
599 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
600 acm_ctrl);
601 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
602 }
603 break;
604 case HW_VAR_RCR:
605 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *)(val))[0]);
606 rtlpci->receive_config = ((u32 *)(val))[0];
607 break;
608 case HW_VAR_RETRY_LIMIT:{
609 u8 retry_limit = ((u8 *)(val))[0];
610
611 rtl_write_word(rtlpriv, REG_RL,
612 retry_limit << RETRY_LIMIT_SHORT_SHIFT |
613 retry_limit << RETRY_LIMIT_LONG_SHIFT);
614 }
615 break;
616 case HW_VAR_DUAL_TSF_RST:
617 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
618 break;
619 case HW_VAR_EFUSE_BYTES:
620 rtlefuse->efuse_usedbytes = *((u16 *)val);
621 break;
622 case HW_VAR_EFUSE_USAGE:
623 rtlefuse->efuse_usedpercentage = *((u8 *)val);
624 break;
625 case HW_VAR_IO_CMD:
626 rtl8723be_phy_set_io_cmd(hw, (*(enum io_type *)val));
627 break;
628 case HW_VAR_SET_RPWM:{
629 u8 rpwm_val;
630
631 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
632 udelay(1);
633
634 if (rpwm_val & BIT(7)) {
635 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, (*(u8 *)val));
636 } else {
637 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
638 ((*(u8 *)val) | BIT(7)));
639 }
640 }
641 break;
642 case HW_VAR_H2C_FW_PWRMODE:
643 rtl8723be_set_fw_pwrmode_cmd(hw, (*(u8 *)val));
644 break;
645 case HW_VAR_FW_PSMODE_STATUS:
646 ppsc->fw_current_inpsmode = *((bool *)val);
647 break;
648 case HW_VAR_RESUME_CLK_ON:
649 _rtl8723be_set_fw_ps_rf_on(hw);
650 break;
651 case HW_VAR_FW_LPS_ACTION:{
652 bool b_enter_fwlps = *((bool *)val);
653
654 if (b_enter_fwlps)
655 _rtl8723be_fwlps_enter(hw);
656 else
657 _rtl8723be_fwlps_leave(hw);
658 }
659 break;
660 case HW_VAR_H2C_FW_JOINBSSRPT:{
661 u8 mstatus = (*(u8 *)val);
662
663 if (mstatus == RT_MEDIA_CONNECT) {
664 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID, NULL);
665 _rtl8723be_download_rsvd_page(hw);
666 }
667 rtl8723be_set_fw_media_status_rpt_cmd(hw, mstatus);
668 }
669 break;
670 case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
671 rtl8723be_set_p2p_ps_offload_cmd(hw, (*(u8 *)val));
672 break;
673 case HW_VAR_AID:{
674 u16 u2btmp;
675 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
676 u2btmp &= 0xC000;
677 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT,
678 (u2btmp | mac->assoc_id));
679 }
680 break;
681 case HW_VAR_CORRECT_TSF:{
682 u8 btype_ibss = ((u8 *)(val))[0];
683
684 if (btype_ibss)
685 _rtl8723be_stop_tx_beacon(hw);
686
687 _rtl8723be_set_bcn_ctrl_reg(hw, 0, BIT(3));
688
689 rtl_write_dword(rtlpriv, REG_TSFTR,
690 (u32) (mac->tsf & 0xffffffff));
691 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
692 (u32) ((mac->tsf >> 32) & 0xffffffff));
693
694 _rtl8723be_set_bcn_ctrl_reg(hw, BIT(3), 0);
695
696 if (btype_ibss)
697 _rtl8723be_resume_tx_beacon(hw);
698 }
699 break;
700 case HW_VAR_KEEP_ALIVE:{
701 u8 array[2];
702 array[0] = 0xff;
703 array[1] = *((u8 *)val);
704 rtl8723be_fill_h2c_cmd(hw, H2C_8723B_KEEP_ALIVE_CTRL, 2, array);
705 }
706 break;
707 default:
708 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
709 "switch case %#x not processed\n", variable);
710 break;
711 }
712 }
713
714 static bool _rtl8723be_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
715 {
716 struct rtl_priv *rtlpriv = rtl_priv(hw);
717 bool status = true;
718 long count = 0;
719 u32 value = _LLT_INIT_ADDR(address) | _LLT_INIT_DATA(data) |
720 _LLT_OP(_LLT_WRITE_ACCESS);
721
722 rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
723
724 do {
725 value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
726 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
727 break;
728
729 if (count > POLLING_LLT_THRESHOLD) {
730 pr_err("Failed to polling write LLT done at address %d!\n",
731 address);
732 status = false;
733 break;
734 }
735 } while (++count);
736
737 return status;
738 }
739
740 static bool _rtl8723be_llt_table_init(struct ieee80211_hw *hw)
741 {
742 struct rtl_priv *rtlpriv = rtl_priv(hw);
743 unsigned short i;
744 u8 txpktbuf_bndy;
745 u8 maxpage;
746 bool status;
747
748 maxpage = 255;
749 txpktbuf_bndy = 245;
750
751 rtl_write_dword(rtlpriv, REG_TRXFF_BNDY,
752 (0x27FF0000 | txpktbuf_bndy));
753 rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
754
755 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
756 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
757
758 rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy);
759 rtl_write_byte(rtlpriv, REG_PBP, 0x31);
760 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
761
762 for (i = 0; i < (txpktbuf_bndy - 1); i++) {
763 status = _rtl8723be_llt_write(hw, i, i + 1);
764 if (!status)
765 return status;
766 }
767
768 status = _rtl8723be_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
769
770 if (!status)
771 return status;
772
773 for (i = txpktbuf_bndy; i < maxpage; i++) {
774 status = _rtl8723be_llt_write(hw, i, (i + 1));
775 if (!status)
776 return status;
777 }
778
779 status = _rtl8723be_llt_write(hw, maxpage, txpktbuf_bndy);
780 if (!status)
781 return status;
782
783 rtl_write_dword(rtlpriv, REG_RQPN, 0x80e40808);
784 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x00);
785
786 return true;
787 }
788
789 static void _rtl8723be_gen_refresh_led_state(struct ieee80211_hw *hw)
790 {
791 struct rtl_priv *rtlpriv = rtl_priv(hw);
792 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
793 struct rtl_led *pled0 = &rtlpriv->ledctl.sw_led0;
794
795 if (rtlpriv->rtlhal.up_first_time)
796 return;
797
798 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
799 rtl8723be_sw_led_on(hw, pled0);
800 else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
801 rtl8723be_sw_led_on(hw, pled0);
802 else
803 rtl8723be_sw_led_off(hw, pled0);
804 }
805
806 static bool _rtl8723be_init_mac(struct ieee80211_hw *hw)
807 {
808 struct rtl_priv *rtlpriv = rtl_priv(hw);
809 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
810 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
811 unsigned char bytetmp;
812 unsigned short wordtmp;
813
814 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
815
816 /*Auto Power Down to CHIP-off State*/
817 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) & (~BIT(7));
818 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);
819
820 /* HW Power on sequence */
821 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK,
822 PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,
823 RTL8723_NIC_ENABLE_FLOW)) {
824 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
825 "init MAC Fail as power on failure\n");
826 return false;
827 }
828
829 if (rtlpriv->cfg->ops->get_btc_status())
830 rtlpriv->btcoexist.btc_ops->btc_power_on_setting(rtlpriv);
831
832 bytetmp = rtl_read_byte(rtlpriv, REG_MULTI_FUNC_CTRL);
833 rtl_write_byte(rtlpriv, REG_MULTI_FUNC_CTRL, bytetmp | BIT(3));
834
835 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO) | BIT(4);
836 rtl_write_byte(rtlpriv, REG_APS_FSMCO, bytetmp);
837
838 bytetmp = rtl_read_byte(rtlpriv, REG_CR);
839 bytetmp = 0xff;
840 rtl_write_byte(rtlpriv, REG_CR, bytetmp);
841 mdelay(2);
842
843 bytetmp = rtl_read_byte(rtlpriv, REG_HWSEQ_CTRL);
844 bytetmp |= 0x7f;
845 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, bytetmp);
846 mdelay(2);
847
848 bytetmp = rtl_read_byte(rtlpriv, REG_SYS_CFG + 3);
849 if (bytetmp & BIT(0)) {
850 bytetmp = rtl_read_byte(rtlpriv, 0x7c);
851 rtl_write_byte(rtlpriv, 0x7c, bytetmp | BIT(6));
852 }
853
854 bytetmp = rtl_read_byte(rtlpriv, REG_SYS_CLKR);
855 rtl_write_byte(rtlpriv, REG_SYS_CLKR, bytetmp | BIT(3));
856 bytetmp = rtl_read_byte(rtlpriv, REG_GPIO_MUXCFG + 1);
857 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG + 1, bytetmp & (~BIT(4)));
858
859 rtl_write_word(rtlpriv, REG_CR, 0x2ff);
860
861 if (!rtlhal->mac_func_enable) {
862 if (_rtl8723be_llt_table_init(hw) == false)
863 return false;
864 }
865
866 rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
867 rtl_write_dword(rtlpriv, REG_HISRE, 0xffffffff);
868
869 /* Enable FW Beamformer Interrupt */
870 bytetmp = rtl_read_byte(rtlpriv, REG_FWIMR + 3);
871 rtl_write_byte(rtlpriv, REG_FWIMR + 3, bytetmp | BIT(6));
872
873 wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
874 wordtmp &= 0xf;
875 wordtmp |= 0xF5B1;
876 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
877
878 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);
879 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
880 rtl_write_word(rtlpriv, REG_RXFLTMAP2, 0xFFFF);
881 rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);
882
883 rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
884 ((u64) rtlpci->tx_ring[BEACON_QUEUE].dma) &
885 DMA_BIT_MASK(32));
886 rtl_write_dword(rtlpriv, REG_MGQ_DESA,
887 (u64) rtlpci->tx_ring[MGNT_QUEUE].dma &
888 DMA_BIT_MASK(32));
889 rtl_write_dword(rtlpriv, REG_VOQ_DESA,
890 (u64) rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
891 rtl_write_dword(rtlpriv, REG_VIQ_DESA,
892 (u64) rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
893 rtl_write_dword(rtlpriv, REG_BEQ_DESA,
894 (u64) rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
895 rtl_write_dword(rtlpriv, REG_BKQ_DESA,
896 (u64) rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
897 rtl_write_dword(rtlpriv, REG_HQ_DESA,
898 (u64) rtlpci->tx_ring[HIGH_QUEUE].dma &
899 DMA_BIT_MASK(32));
900 rtl_write_dword(rtlpriv, REG_RX_DESA,
901 (u64) rtlpci->rx_ring[RX_MPDU_QUEUE].dma &
902 DMA_BIT_MASK(32));
903
904 bytetmp = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG + 3);
905 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, bytetmp | 0x77);
906
907 rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
908
909 rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);
910
911 rtl_write_byte(rtlpriv, REG_SECONDARY_CCA_CTRL, 0x3);
912
913 /* <20130114, Kordan> The following setting is
914 * only for DPDT and Fixed board type.
915 * TODO: A better solution is configure it
916 * according EFUSE during the run-time.
917 */
918 rtl_set_bbreg(hw, 0x64, BIT(20), 0x0);/* 0x66[4]=0 */
919 rtl_set_bbreg(hw, 0x64, BIT(24), 0x0);/* 0x66[8]=0 */
920 rtl_set_bbreg(hw, 0x40, BIT(4), 0x0)/* 0x40[4]=0 */;
921 rtl_set_bbreg(hw, 0x40, BIT(3), 0x1)/* 0x40[3]=1 */;
922 rtl_set_bbreg(hw, 0x4C, BIT(24) | BIT(23), 0x2)/* 0x4C[24:23]=10 */;
923 rtl_set_bbreg(hw, 0x944, BIT(1) | BIT(0), 0x3)/* 0x944[1:0]=11 */;
924 rtl_set_bbreg(hw, 0x930, MASKBYTE0, 0x77)/* 0x930[7:0]=77 */;
925 rtl_set_bbreg(hw, 0x38, BIT(11), 0x1)/* 0x38[11]=1 */;
926
927 bytetmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
928 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, bytetmp & (~BIT(2)));
929
930 _rtl8723be_gen_refresh_led_state(hw);
931 return true;
932 }
933
934 static void _rtl8723be_hw_configure(struct ieee80211_hw *hw)
935 {
936 struct rtl_priv *rtlpriv = rtl_priv(hw);
937 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
938 u32 reg_rrsr;
939
940 reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
941 /* Init value for RRSR. */
942 rtl_write_dword(rtlpriv, REG_RRSR, reg_rrsr);
943
944 /* ARFB table 9 for 11ac 5G 2SS */
945 rtl_write_dword(rtlpriv, REG_ARFR0 + 4, 0xfffff000);
946
947 /* ARFB table 10 for 11ac 5G 1SS */
948 rtl_write_dword(rtlpriv, REG_ARFR1 + 4, 0x003ff000);
949
950 /* CF-End setting. */
951 rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F00);
952
953 /* 0x456 = 0x70, sugguested by Zhilin */
954 rtl_write_byte(rtlpriv, REG_AMPDU_MAX_TIME, 0x70);
955
956 /* Set retry limit */
957 rtl_write_word(rtlpriv, REG_RL, 0x0707);
958
959 /* Set Data / Response auto rate fallack retry count */
960 rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);
961 rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);
962 rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);
963 rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);
964
965 rtlpci->reg_bcn_ctrl_val = 0x1d;
966 rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);
967
968 /* TBTT prohibit hold time. Suggested by designer TimChen. */
969 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); /* 8 ms */
970
971 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0040);
972
973 /*For Rx TP. Suggested by SD1 Richard. Added by tynli. 2010.04.12.*/
974 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666);
975
976 rtl_write_byte(rtlpriv, REG_HT_SINGLE_AMPDU, 0x80);
977
978 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x20);
979
980 rtl_write_byte(rtlpriv, REG_MAX_AGGR_NUM, 0x1F);
981 }
982
983 static u8 _rtl8723be_dbi_read(struct rtl_priv *rtlpriv, u16 addr)
984 {
985 u16 read_addr = addr & 0xfffc;
986 u8 ret = 0, tmp = 0, count = 0;
987
988 rtl_write_word(rtlpriv, REG_DBI_ADDR, read_addr);
989 rtl_write_byte(rtlpriv, REG_DBI_FLAG, 0x2);
990 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
991 count = 0;
992 while (tmp && count < 20) {
993 udelay(10);
994 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
995 count++;
996 }
997 if (0 == tmp) {
998 read_addr = REG_DBI_RDATA + addr % 4;
999 ret = rtl_read_byte(rtlpriv, read_addr);
1000 }
1001
1002 return ret;
1003 }
1004
1005 static void _rtl8723be_dbi_write(struct rtl_priv *rtlpriv, u16 addr, u8 data)
1006 {
1007 u8 tmp = 0, count = 0;
1008 u16 write_addr = 0, remainder = addr % 4;
1009
1010 /* Write DBI 1Byte Data */
1011 write_addr = REG_DBI_WDATA + remainder;
1012 rtl_write_byte(rtlpriv, write_addr, data);
1013
1014 /* Write DBI 2Byte Address & Write Enable */
1015 write_addr = (addr & 0xfffc) | (BIT(0) << (remainder + 12));
1016 rtl_write_word(rtlpriv, REG_DBI_ADDR, write_addr);
1017
1018 /* Write DBI Write Flag */
1019 rtl_write_byte(rtlpriv, REG_DBI_FLAG, 0x1);
1020
1021 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1022 count = 0;
1023 while (tmp && count < 20) {
1024 udelay(10);
1025 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1026 count++;
1027 }
1028 }
1029
1030 static u16 _rtl8723be_mdio_read(struct rtl_priv *rtlpriv, u8 addr)
1031 {
1032 u16 ret = 0;
1033 u8 tmp = 0, count = 0;
1034
1035 rtl_write_byte(rtlpriv, REG_MDIO_CTL, addr | BIT(6));
1036 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(6);
1037 count = 0;
1038 while (tmp && count < 20) {
1039 udelay(10);
1040 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(6);
1041 count++;
1042 }
1043
1044 if (0 == tmp)
1045 ret = rtl_read_word(rtlpriv, REG_MDIO_RDATA);
1046
1047 return ret;
1048 }
1049
1050 static void _rtl8723be_mdio_write(struct rtl_priv *rtlpriv, u8 addr, u16 data)
1051 {
1052 u8 tmp = 0, count = 0;
1053
1054 rtl_write_word(rtlpriv, REG_MDIO_WDATA, data);
1055 rtl_write_byte(rtlpriv, REG_MDIO_CTL, addr | BIT(5));
1056 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(5);
1057 count = 0;
1058 while (tmp && count < 20) {
1059 udelay(10);
1060 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(5);
1061 count++;
1062 }
1063 }
1064
1065 static void _rtl8723be_enable_aspm_back_door(struct ieee80211_hw *hw)
1066 {
1067 struct rtl_priv *rtlpriv = rtl_priv(hw);
1068 u8 tmp8 = 0;
1069 u16 tmp16 = 0;
1070
1071 /* <Roger_Notes> Overwrite following ePHY parameter for
1072 * some platform compatibility issue,
1073 * especially when CLKReq is enabled, 2012.11.09.
1074 */
1075 tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x01);
1076 if (tmp16 != 0x0663)
1077 _rtl8723be_mdio_write(rtlpriv, 0x01, 0x0663);
1078
1079 tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x04);
1080 if (tmp16 != 0x7544)
1081 _rtl8723be_mdio_write(rtlpriv, 0x04, 0x7544);
1082
1083 tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x06);
1084 if (tmp16 != 0xB880)
1085 _rtl8723be_mdio_write(rtlpriv, 0x06, 0xB880);
1086
1087 tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x07);
1088 if (tmp16 != 0x4000)
1089 _rtl8723be_mdio_write(rtlpriv, 0x07, 0x4000);
1090
1091 tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x08);
1092 if (tmp16 != 0x9003)
1093 _rtl8723be_mdio_write(rtlpriv, 0x08, 0x9003);
1094
1095 tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x09);
1096 if (tmp16 != 0x0D03)
1097 _rtl8723be_mdio_write(rtlpriv, 0x09, 0x0D03);
1098
1099 tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x0A);
1100 if (tmp16 != 0x4037)
1101 _rtl8723be_mdio_write(rtlpriv, 0x0A, 0x4037);
1102
1103 tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x0B);
1104 if (tmp16 != 0x0070)
1105 _rtl8723be_mdio_write(rtlpriv, 0x0B, 0x0070);
1106
1107 /* Configuration Space offset 0x70f BIT7 is used to control L0S */
1108 tmp8 = _rtl8723be_dbi_read(rtlpriv, 0x70f);
1109 _rtl8723be_dbi_write(rtlpriv, 0x70f, tmp8 | BIT(7) |
1110 ASPM_L1_LATENCY << 3);
1111
1112 /* Configuration Space offset 0x719 Bit3 is for L1
1113 * BIT4 is for clock request
1114 */
1115 tmp8 = _rtl8723be_dbi_read(rtlpriv, 0x719);
1116 _rtl8723be_dbi_write(rtlpriv, 0x719, tmp8 | BIT(3) | BIT(4));
1117 }
1118
1119 void rtl8723be_enable_hw_security_config(struct ieee80211_hw *hw)
1120 {
1121 struct rtl_priv *rtlpriv = rtl_priv(hw);
1122 u8 sec_reg_value;
1123
1124 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1125 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
1126 rtlpriv->sec.pairwise_enc_algorithm,
1127 rtlpriv->sec.group_enc_algorithm);
1128
1129 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
1130 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1131 "not open hw encryption\n");
1132 return;
1133 }
1134
1135 sec_reg_value = SCR_TXENCENABLE | SCR_RXDECENABLE;
1136
1137 if (rtlpriv->sec.use_defaultkey) {
1138 sec_reg_value |= SCR_TXUSEDK;
1139 sec_reg_value |= SCR_RXUSEDK;
1140 }
1141
1142 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
1143
1144 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
1145
1146 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1147 "The SECR-value %x\n", sec_reg_value);
1148
1149 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
1150 }
1151
1152 static void _rtl8723be_poweroff_adapter(struct ieee80211_hw *hw)
1153 {
1154 struct rtl_priv *rtlpriv = rtl_priv(hw);
1155 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1156 u8 u1b_tmp;
1157
1158 rtlhal->mac_func_enable = false;
1159 /* Combo (PCIe + USB) Card and PCIe-MF Card */
1160 /* 1. Run LPS WL RFOFF flow */
1161 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1162 PWR_INTF_PCI_MSK, RTL8723_NIC_LPS_ENTER_FLOW);
1163
1164 /* 2. 0x1F[7:0] = 0 */
1165 /* turn off RF */
1166 /* rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00); */
1167 if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) &&
1168 rtlhal->fw_ready) {
1169 rtl8723be_firmware_selfreset(hw);
1170 }
1171
1172 /* Reset MCU. Suggested by Filen. */
1173 u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1174 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, (u1b_tmp & (~BIT(2))));
1175
1176 /* g. MCUFWDL 0x80[1:0]=0 */
1177 /* reset MCU ready status */
1178 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1179
1180 /* HW card disable configuration. */
1181 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1182 PWR_INTF_PCI_MSK, RTL8723_NIC_DISABLE_FLOW);
1183
1184 /* Reset MCU IO Wrapper */
1185 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1186 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp & (~BIT(0))));
1187 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1188 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, u1b_tmp | BIT(0));
1189
1190 /* 7. RSV_CTRL 0x1C[7:0] = 0x0E */
1191 /* lock ISO/CLK/Power control register */
1192 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e);
1193 }
1194
1195 static bool _rtl8723be_check_pcie_dma_hang(struct rtl_priv *rtlpriv)
1196 {
1197 u8 tmp;
1198
1199 /* write reg 0x350 Bit[26]=1. Enable debug port. */
1200 tmp = rtl_read_byte(rtlpriv, REG_DBI_CTRL + 3);
1201 if (!(tmp & BIT(2))) {
1202 rtl_write_byte(rtlpriv, REG_DBI_CTRL + 3, (tmp | BIT(2)));
1203 mdelay(100); /* Suggested by DD Justin_tsai. */
1204 }
1205
1206 /* read reg 0x350 Bit[25] if 1 : RX hang
1207 * read reg 0x350 Bit[24] if 1 : TX hang
1208 */
1209 tmp = rtl_read_byte(rtlpriv, REG_DBI_CTRL + 3);
1210 if ((tmp & BIT(0)) || (tmp & BIT(1))) {
1211 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1212 "CheckPcieDMAHang8723BE(): true!!\n");
1213 return true;
1214 }
1215 return false;
1216 }
1217
1218 static void _rtl8723be_reset_pcie_interface_dma(struct rtl_priv *rtlpriv,
1219 bool mac_power_on)
1220 {
1221 u8 tmp;
1222 bool release_mac_rx_pause;
1223 u8 backup_pcie_dma_pause;
1224
1225 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1226 "ResetPcieInterfaceDMA8723BE()\n");
1227
1228 /* Revise Note: Follow the document "PCIe RX DMA Hang Reset Flow_v03"
1229 * released by SD1 Alan.
1230 * 2013.05.07, by tynli.
1231 */
1232
1233 /* 1. disable register write lock
1234 * write 0x1C bit[1:0] = 2'h0
1235 * write 0xCC bit[2] = 1'b1
1236 */
1237 tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL);
1238 tmp &= ~(BIT(1) | BIT(0));
1239 rtl_write_byte(rtlpriv, REG_RSV_CTRL, tmp);
1240 tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2);
1241 tmp |= BIT(2);
1242 rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp);
1243
1244 /* 2. Check and pause TRX DMA
1245 * write 0x284 bit[18] = 1'b1
1246 * write 0x301 = 0xFF
1247 */
1248 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1249 if (tmp & BIT(2)) {
1250 /* Already pause before the function for another purpose. */
1251 release_mac_rx_pause = false;
1252 } else {
1253 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp | BIT(2)));
1254 release_mac_rx_pause = true;
1255 }
1256
1257 backup_pcie_dma_pause = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG + 1);
1258 if (backup_pcie_dma_pause != 0xFF)
1259 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFF);
1260
1261 if (mac_power_on) {
1262 /* 3. reset TRX function
1263 * write 0x100 = 0x00
1264 */
1265 rtl_write_byte(rtlpriv, REG_CR, 0);
1266 }
1267
1268 /* 4. Reset PCIe DMA
1269 * write 0x003 bit[0] = 0
1270 */
1271 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1272 tmp &= ~(BIT(0));
1273 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp);
1274
1275 /* 5. Enable PCIe DMA
1276 * write 0x003 bit[0] = 1
1277 */
1278 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1279 tmp |= BIT(0);
1280 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp);
1281
1282 if (mac_power_on) {
1283 /* 6. enable TRX function
1284 * write 0x100 = 0xFF
1285 */
1286 rtl_write_byte(rtlpriv, REG_CR, 0xFF);
1287
1288 /* We should init LLT & RQPN and
1289 * prepare Tx/Rx descrptor address later
1290 * because MAC function is reset.
1291 */
1292 }
1293
1294 /* 7. Restore PCIe autoload down bit
1295 * write 0xF8 bit[17] = 1'b1
1296 */
1297 tmp = rtl_read_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL + 2);
1298 tmp |= BIT(1);
1299 rtl_write_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL + 2, tmp);
1300
1301 /* In MAC power on state, BB and RF maybe in ON state,
1302 * if we release TRx DMA here
1303 * it will cause packets to be started to Tx/Rx,
1304 * so we release Tx/Rx DMA later.
1305 */
1306 if (!mac_power_on) {
1307 /* 8. release TRX DMA
1308 * write 0x284 bit[18] = 1'b0
1309 * write 0x301 = 0x00
1310 */
1311 if (release_mac_rx_pause) {
1312 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1313 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL,
1314 (tmp & (~BIT(2))));
1315 }
1316 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1,
1317 backup_pcie_dma_pause);
1318 }
1319
1320 /* 9. lock system register
1321 * write 0xCC bit[2] = 1'b0
1322 */
1323 tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2);
1324 tmp &= ~(BIT(2));
1325 rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp);
1326 }
1327
1328 int rtl8723be_hw_init(struct ieee80211_hw *hw)
1329 {
1330 struct rtl_priv *rtlpriv = rtl_priv(hw);
1331 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1332 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1333 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1334 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1335 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1336 bool rtstatus = true;
1337 int err;
1338 u8 tmp_u1b;
1339 unsigned long flags;
1340
1341 /* reenable interrupts to not interfere with other devices */
1342 local_save_flags(flags);
1343 local_irq_enable();
1344
1345 rtlhal->fw_ready = false;
1346 rtlpriv->rtlhal.being_init_adapter = true;
1347 rtlpriv->intf_ops->disable_aspm(hw);
1348
1349 tmp_u1b = rtl_read_byte(rtlpriv, REG_CR);
1350 if (tmp_u1b != 0 && tmp_u1b != 0xea) {
1351 rtlhal->mac_func_enable = true;
1352 } else {
1353 rtlhal->mac_func_enable = false;
1354 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON;
1355 }
1356
1357 if (_rtl8723be_check_pcie_dma_hang(rtlpriv)) {
1358 _rtl8723be_reset_pcie_interface_dma(rtlpriv,
1359 rtlhal->mac_func_enable);
1360 rtlhal->mac_func_enable = false;
1361 }
1362 if (rtlhal->mac_func_enable) {
1363 _rtl8723be_poweroff_adapter(hw);
1364 rtlhal->mac_func_enable = false;
1365 }
1366 rtstatus = _rtl8723be_init_mac(hw);
1367 if (!rtstatus) {
1368 pr_err("Init MAC failed\n");
1369 err = 1;
1370 goto exit;
1371 }
1372
1373 tmp_u1b = rtl_read_byte(rtlpriv, REG_SYS_CFG);
1374 rtl_write_byte(rtlpriv, REG_SYS_CFG, tmp_u1b & 0x7F);
1375
1376 err = rtl8723_download_fw(hw, true, FW_8723B_POLLING_TIMEOUT_COUNT);
1377 if (err) {
1378 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1379 "Failed to download FW. Init HW without FW now..\n");
1380 err = 1;
1381 goto exit;
1382 }
1383 rtlhal->fw_ready = true;
1384
1385 rtlhal->last_hmeboxnum = 0;
1386 rtl8723be_phy_mac_config(hw);
1387 /* because last function modify RCR, so we update
1388 * rcr var here, or TP will unstable for receive_config
1389 * is wrong, RX RCR_ACRC32 will cause TP unstable & Rx
1390 * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252
1391 */
1392 rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR);
1393 rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
1394 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
1395
1396 rtl8723be_phy_bb_config(hw);
1397 rtl8723be_phy_rf_config(hw);
1398
1399 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
1400 RF_CHNLBW, RFREG_OFFSET_MASK);
1401 rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,
1402 RF_CHNLBW, RFREG_OFFSET_MASK);
1403 rtlphy->rfreg_chnlval[0] &= 0xFFF03FF;
1404 rtlphy->rfreg_chnlval[0] |= (BIT(10) | BIT(11));
1405
1406 _rtl8723be_hw_configure(hw);
1407 rtlhal->mac_func_enable = true;
1408 rtl_cam_reset_all_entry(hw);
1409 rtl8723be_enable_hw_security_config(hw);
1410
1411 ppsc->rfpwr_state = ERFON;
1412
1413 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1414 _rtl8723be_enable_aspm_back_door(hw);
1415 rtlpriv->intf_ops->enable_aspm(hw);
1416
1417 rtl8723be_bt_hw_init(hw);
1418
1419 if (ppsc->rfpwr_state == ERFON) {
1420 rtl8723be_phy_set_rfpath_switch(hw, 1);
1421 /* when use 1ant NIC, iqk will disturb BT music
1422 * root cause is not clear now, is something
1423 * related with 'mdelay' and Reg[0x948]
1424 */
1425 if (rtlpriv->btcoexist.btc_info.ant_num == ANT_X2 ||
1426 !rtlpriv->cfg->ops->get_btc_status()) {
1427 rtl8723be_phy_iq_calibrate(hw,
1428 (rtlphy->iqk_initialized ?
1429 true : false));
1430 rtlphy->iqk_initialized = true;
1431 }
1432 rtl8723be_dm_check_txpower_tracking(hw);
1433 rtl8723be_phy_lc_calibrate(hw);
1434 }
1435 rtl_write_byte(rtlpriv, REG_NAV_UPPER, ((30000 + 127) / 128));
1436
1437 /* Release Rx DMA. */
1438 tmp_u1b = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1439 if (tmp_u1b & BIT(2)) {
1440 /* Release Rx DMA if needed */
1441 tmp_u1b &= (~BIT(2));
1442 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, tmp_u1b);
1443 }
1444 /* Release Tx/Rx PCIE DMA. */
1445 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0);
1446
1447 rtl8723be_dm_init(hw);
1448 exit:
1449 local_irq_restore(flags);
1450 rtlpriv->rtlhal.being_init_adapter = false;
1451 return err;
1452 }
1453
1454 static enum version_8723e _rtl8723be_read_chip_version(struct ieee80211_hw *hw)
1455 {
1456 struct rtl_priv *rtlpriv = rtl_priv(hw);
1457 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1458 enum version_8723e version = VERSION_UNKNOWN;
1459 u32 value32;
1460
1461 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG1);
1462 if ((value32 & (CHIP_8723B)) != CHIP_8723B)
1463 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "unknown chip version\n");
1464 else
1465 version = (enum version_8723e)CHIP_8723B;
1466
1467 rtlphy->rf_type = RF_1T1R;
1468
1469 /* treat rtl8723be chip as MP version in default */
1470 version = (enum version_8723e)(version | NORMAL_CHIP);
1471
1472 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
1473 /* cut version */
1474 version |= (enum version_8723e)(value32 & CHIP_VER_RTL_MASK);
1475 /* Manufacture */
1476 if (((value32 & EXT_VENDOR_ID) >> 18) == 0x01)
1477 version = (enum version_8723e)(version | CHIP_VENDOR_SMIC);
1478
1479 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1480 "Chip RF Type: %s\n", (rtlphy->rf_type == RF_2T2R) ?
1481 "RF_2T2R" : "RF_1T1R");
1482
1483 return version;
1484 }
1485
1486 static int _rtl8723be_set_media_status(struct ieee80211_hw *hw,
1487 enum nl80211_iftype type)
1488 {
1489 struct rtl_priv *rtlpriv = rtl_priv(hw);
1490 u8 bt_msr = rtl_read_byte(rtlpriv, MSR) & 0xfc;
1491 enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1492 u8 mode = MSR_NOLINK;
1493
1494 switch (type) {
1495 case NL80211_IFTYPE_UNSPECIFIED:
1496 mode = MSR_NOLINK;
1497 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1498 "Set Network type to NO LINK!\n");
1499 break;
1500 case NL80211_IFTYPE_ADHOC:
1501 case NL80211_IFTYPE_MESH_POINT:
1502 mode = MSR_ADHOC;
1503 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1504 "Set Network type to Ad Hoc!\n");
1505 break;
1506 case NL80211_IFTYPE_STATION:
1507 mode = MSR_INFRA;
1508 ledaction = LED_CTL_LINK;
1509 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1510 "Set Network type to STA!\n");
1511 break;
1512 case NL80211_IFTYPE_AP:
1513 mode = MSR_AP;
1514 ledaction = LED_CTL_LINK;
1515 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1516 "Set Network type to AP!\n");
1517 break;
1518 default:
1519 pr_err("Network type %d not support!\n", type);
1520 return 1;
1521 }
1522
1523 /* MSR_INFRA == Link in infrastructure network;
1524 * MSR_ADHOC == Link in ad hoc network;
1525 * Therefore, check link state is necessary.
1526 *
1527 * MSR_AP == AP mode; link state is not cared here.
1528 */
1529 if (mode != MSR_AP && rtlpriv->mac80211.link_state < MAC80211_LINKED) {
1530 mode = MSR_NOLINK;
1531 ledaction = LED_CTL_NO_LINK;
1532 }
1533
1534 if (mode == MSR_NOLINK || mode == MSR_INFRA) {
1535 _rtl8723be_stop_tx_beacon(hw);
1536 _rtl8723be_enable_bcn_sub_func(hw);
1537 } else if (mode == MSR_ADHOC || mode == MSR_AP) {
1538 _rtl8723be_resume_tx_beacon(hw);
1539 _rtl8723be_disable_bcn_sub_func(hw);
1540 } else {
1541 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1542 "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n",
1543 mode);
1544 }
1545
1546 rtl_write_byte(rtlpriv, MSR, bt_msr | mode);
1547 rtlpriv->cfg->ops->led_control(hw, ledaction);
1548 if (mode == MSR_AP)
1549 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1550 else
1551 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1552 return 0;
1553 }
1554
1555 void rtl8723be_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1556 {
1557 struct rtl_priv *rtlpriv = rtl_priv(hw);
1558 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1559 u32 reg_rcr = rtlpci->receive_config;
1560
1561 if (rtlpriv->psc.rfpwr_state != ERFON)
1562 return;
1563
1564 if (check_bssid) {
1565 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1566 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1567 (u8 *)(&reg_rcr));
1568 _rtl8723be_set_bcn_ctrl_reg(hw, 0, BIT(4));
1569 } else if (!check_bssid) {
1570 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1571 _rtl8723be_set_bcn_ctrl_reg(hw, BIT(4), 0);
1572 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1573 (u8 *)(&reg_rcr));
1574 }
1575
1576 }
1577
1578 int rtl8723be_set_network_type(struct ieee80211_hw *hw,
1579 enum nl80211_iftype type)
1580 {
1581 struct rtl_priv *rtlpriv = rtl_priv(hw);
1582
1583 if (_rtl8723be_set_media_status(hw, type))
1584 return -EOPNOTSUPP;
1585
1586 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1587 if (type != NL80211_IFTYPE_AP)
1588 rtl8723be_set_check_bssid(hw, true);
1589 } else {
1590 rtl8723be_set_check_bssid(hw, false);
1591 }
1592
1593 return 0;
1594 }
1595
1596 /* don't set REG_EDCA_BE_PARAM here
1597 * because mac80211 will send pkt when scan
1598 */
1599 void rtl8723be_set_qos(struct ieee80211_hw *hw, int aci)
1600 {
1601 struct rtl_priv *rtlpriv = rtl_priv(hw);
1602
1603 rtl8723_dm_init_edca_turbo(hw);
1604 switch (aci) {
1605 case AC1_BK:
1606 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
1607 break;
1608 case AC0_BE:
1609 break;
1610 case AC2_VI:
1611 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
1612 break;
1613 case AC3_VO:
1614 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);
1615 break;
1616 default:
1617 WARN_ONCE(true, "rtl8723be: invalid aci: %d !\n", aci);
1618 break;
1619 }
1620 }
1621
1622 void rtl8723be_enable_interrupt(struct ieee80211_hw *hw)
1623 {
1624 struct rtl_priv *rtlpriv = rtl_priv(hw);
1625 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1626
1627 rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);
1628 rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);
1629 rtlpci->irq_enabled = true;
1630
1631 /*enable system interrupt*/
1632 rtl_write_dword(rtlpriv, REG_HSIMR, rtlpci->sys_irq_mask & 0xFFFFFFFF);
1633 }
1634
1635 void rtl8723be_disable_interrupt(struct ieee80211_hw *hw)
1636 {
1637 struct rtl_priv *rtlpriv = rtl_priv(hw);
1638 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1639
1640 rtl_write_dword(rtlpriv, REG_HIMR, IMR_DISABLED);
1641 rtl_write_dword(rtlpriv, REG_HIMRE, IMR_DISABLED);
1642 rtlpci->irq_enabled = false;
1643 /*synchronize_irq(rtlpci->pdev->irq);*/
1644 }
1645
1646 void rtl8723be_card_disable(struct ieee80211_hw *hw)
1647 {
1648 struct rtl_priv *rtlpriv = rtl_priv(hw);
1649 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1650 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1651 enum nl80211_iftype opmode;
1652
1653 mac->link_state = MAC80211_NOLINK;
1654 opmode = NL80211_IFTYPE_UNSPECIFIED;
1655 _rtl8723be_set_media_status(hw, opmode);
1656 if (rtlpriv->rtlhal.driver_is_goingto_unload ||
1657 ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1658 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1659 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1660 _rtl8723be_poweroff_adapter(hw);
1661
1662 /* after power off we should do iqk again */
1663 if (!rtlpriv->cfg->ops->get_btc_status())
1664 rtlpriv->phy.iqk_initialized = false;
1665 }
1666
1667 void rtl8723be_interrupt_recognized(struct ieee80211_hw *hw,
1668 struct rtl_int *intvec)
1669 {
1670 struct rtl_priv *rtlpriv = rtl_priv(hw);
1671 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1672
1673 intvec->inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1674 rtl_write_dword(rtlpriv, ISR, intvec->inta);
1675
1676 intvec->intb = rtl_read_dword(rtlpriv, REG_HISRE) &
1677 rtlpci->irq_mask[1];
1678 rtl_write_dword(rtlpriv, REG_HISRE, intvec->intb);
1679 }
1680
1681 void rtl8723be_set_beacon_related_registers(struct ieee80211_hw *hw)
1682 {
1683 struct rtl_priv *rtlpriv = rtl_priv(hw);
1684 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1685 u16 bcn_interval, atim_window;
1686
1687 bcn_interval = mac->beacon_interval;
1688 atim_window = 2; /*FIX MERGE */
1689 rtl8723be_disable_interrupt(hw);
1690 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1691 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1692 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
1693 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
1694 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
1695 rtl_write_byte(rtlpriv, 0x606, 0x30);
1696 rtl8723be_enable_interrupt(hw);
1697 }
1698
1699 void rtl8723be_set_beacon_interval(struct ieee80211_hw *hw)
1700 {
1701 struct rtl_priv *rtlpriv = rtl_priv(hw);
1702 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1703 u16 bcn_interval = mac->beacon_interval;
1704
1705 RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
1706 "beacon_interval:%d\n", bcn_interval);
1707 rtl8723be_disable_interrupt(hw);
1708 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1709 rtl8723be_enable_interrupt(hw);
1710 }
1711
1712 void rtl8723be_update_interrupt_mask(struct ieee80211_hw *hw,
1713 u32 add_msr, u32 rm_msr)
1714 {
1715 struct rtl_priv *rtlpriv = rtl_priv(hw);
1716 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1717
1718 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1719 "add_msr:%x, rm_msr:%x\n", add_msr, rm_msr);
1720
1721 if (add_msr)
1722 rtlpci->irq_mask[0] |= add_msr;
1723 if (rm_msr)
1724 rtlpci->irq_mask[0] &= (~rm_msr);
1725 rtl8723be_disable_interrupt(hw);
1726 rtl8723be_enable_interrupt(hw);
1727 }
1728
1729 static u8 _rtl8723be_get_chnl_group(u8 chnl)
1730 {
1731 u8 group;
1732
1733 if (chnl < 3)
1734 group = 0;
1735 else if (chnl < 9)
1736 group = 1;
1737 else
1738 group = 2;
1739 return group;
1740 }
1741
1742 static void _rtl8723be_read_power_value_fromprom(struct ieee80211_hw *hw,
1743 struct txpower_info_2g *pw2g,
1744 struct txpower_info_5g *pw5g,
1745 bool autoload_fail, u8 *hwinfo)
1746 {
1747 struct rtl_priv *rtlpriv = rtl_priv(hw);
1748 u32 path, addr = EEPROM_TX_PWR_INX, group, cnt = 0;
1749
1750 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1751 "hal_ReadPowerValueFromPROM8723BE(): PROMContent[0x%x]=0x%x\n",
1752 (addr + 1), hwinfo[addr + 1]);
1753 if (0xFF == hwinfo[addr + 1]) /*YJ,add,120316*/
1754 autoload_fail = true;
1755
1756 if (autoload_fail) {
1757 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1758 "auto load fail : Use Default value!\n");
1759 for (path = 0; path < MAX_RF_PATH; path++) {
1760 /* 2.4G default value */
1761 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
1762 pw2g->index_cck_base[path][group] = 0x2D;
1763 pw2g->index_bw40_base[path][group] = 0x2D;
1764 }
1765 for (cnt = 0; cnt < MAX_TX_COUNT; cnt++) {
1766 if (cnt == 0) {
1767 pw2g->bw20_diff[path][0] = 0x02;
1768 pw2g->ofdm_diff[path][0] = 0x04;
1769 } else {
1770 pw2g->bw20_diff[path][cnt] = 0xFE;
1771 pw2g->bw40_diff[path][cnt] = 0xFE;
1772 pw2g->cck_diff[path][cnt] = 0xFE;
1773 pw2g->ofdm_diff[path][cnt] = 0xFE;
1774 }
1775 }
1776 }
1777 return;
1778 }
1779
1780 for (path = 0; path < MAX_RF_PATH; path++) {
1781 /*2.4G default value*/
1782 for (group = 0; group < MAX_CHNL_GROUP_24G; group++) {
1783 pw2g->index_cck_base[path][group] = hwinfo[addr++];
1784 if (pw2g->index_cck_base[path][group] == 0xFF)
1785 pw2g->index_cck_base[path][group] = 0x2D;
1786
1787 }
1788 for (group = 0; group < MAX_CHNL_GROUP_24G - 1; group++) {
1789 pw2g->index_bw40_base[path][group] = hwinfo[addr++];
1790 if (pw2g->index_bw40_base[path][group] == 0xFF)
1791 pw2g->index_bw40_base[path][group] = 0x2D;
1792 }
1793 for (cnt = 0; cnt < MAX_TX_COUNT; cnt++) {
1794 if (cnt == 0) {
1795 pw2g->bw40_diff[path][cnt] = 0;
1796 if (hwinfo[addr] == 0xFF) {
1797 pw2g->bw20_diff[path][cnt] = 0x02;
1798 } else {
1799 pw2g->bw20_diff[path][cnt] =
1800 (hwinfo[addr] & 0xf0) >> 4;
1801 /*bit sign number to 8 bit sign number*/
1802 if (pw2g->bw20_diff[path][cnt] & BIT(3))
1803 pw2g->bw20_diff[path][cnt] |=
1804 0xF0;
1805 }
1806
1807 if (hwinfo[addr] == 0xFF) {
1808 pw2g->ofdm_diff[path][cnt] = 0x04;
1809 } else {
1810 pw2g->ofdm_diff[path][cnt] =
1811 (hwinfo[addr] & 0x0f);
1812 /*bit sign number to 8 bit sign number*/
1813 if (pw2g->ofdm_diff[path][cnt] & BIT(3))
1814 pw2g->ofdm_diff[path][cnt] |=
1815 0xF0;
1816 }
1817 pw2g->cck_diff[path][cnt] = 0;
1818 addr++;
1819 } else {
1820 if (hwinfo[addr] == 0xFF) {
1821 pw2g->bw40_diff[path][cnt] = 0xFE;
1822 } else {
1823 pw2g->bw40_diff[path][cnt] =
1824 (hwinfo[addr] & 0xf0) >> 4;
1825 if (pw2g->bw40_diff[path][cnt] & BIT(3))
1826 pw2g->bw40_diff[path][cnt] |=
1827 0xF0;
1828 }
1829
1830 if (hwinfo[addr] == 0xFF) {
1831 pw2g->bw20_diff[path][cnt] = 0xFE;
1832 } else {
1833 pw2g->bw20_diff[path][cnt] =
1834 (hwinfo[addr] & 0x0f);
1835 if (pw2g->bw20_diff[path][cnt] & BIT(3))
1836 pw2g->bw20_diff[path][cnt] |=
1837 0xF0;
1838 }
1839 addr++;
1840
1841 if (hwinfo[addr] == 0xFF) {
1842 pw2g->ofdm_diff[path][cnt] = 0xFE;
1843 } else {
1844 pw2g->ofdm_diff[path][cnt] =
1845 (hwinfo[addr] & 0xf0) >> 4;
1846 if (pw2g->ofdm_diff[path][cnt] & BIT(3))
1847 pw2g->ofdm_diff[path][cnt] |=
1848 0xF0;
1849 }
1850
1851 if (hwinfo[addr] == 0xFF)
1852 pw2g->cck_diff[path][cnt] = 0xFE;
1853 else {
1854 pw2g->cck_diff[path][cnt] =
1855 (hwinfo[addr] & 0x0f);
1856 if (pw2g->cck_diff[path][cnt] & BIT(3))
1857 pw2g->cck_diff[path][cnt] |=
1858 0xF0;
1859 }
1860 addr++;
1861 }
1862 }
1863
1864 /*5G default value*/
1865 for (group = 0; group < MAX_CHNL_GROUP_5G; group++) {
1866 pw5g->index_bw40_base[path][group] = hwinfo[addr++];
1867 if (pw5g->index_bw40_base[path][group] == 0xFF)
1868 pw5g->index_bw40_base[path][group] = 0xFE;
1869 }
1870
1871 for (cnt = 0; cnt < MAX_TX_COUNT; cnt++) {
1872 if (cnt == 0) {
1873 pw5g->bw40_diff[path][cnt] = 0;
1874
1875 if (hwinfo[addr] == 0xFF) {
1876 pw5g->bw20_diff[path][cnt] = 0;
1877 } else {
1878 pw5g->bw20_diff[path][0] =
1879 (hwinfo[addr] & 0xf0) >> 4;
1880 if (pw5g->bw20_diff[path][cnt] & BIT(3))
1881 pw5g->bw20_diff[path][cnt] |=
1882 0xF0;
1883 }
1884
1885 if (hwinfo[addr] == 0xFF)
1886 pw5g->ofdm_diff[path][cnt] = 0x04;
1887 else {
1888 pw5g->ofdm_diff[path][0] =
1889 (hwinfo[addr] & 0x0f);
1890 if (pw5g->ofdm_diff[path][cnt] & BIT(3))
1891 pw5g->ofdm_diff[path][cnt] |=
1892 0xF0;
1893 }
1894 addr++;
1895 } else {
1896 if (hwinfo[addr] == 0xFF) {
1897 pw5g->bw40_diff[path][cnt] = 0xFE;
1898 } else {
1899 pw5g->bw40_diff[path][cnt] =
1900 (hwinfo[addr] & 0xf0) >> 4;
1901 if (pw5g->bw40_diff[path][cnt] & BIT(3))
1902 pw5g->bw40_diff[path][cnt] |= 0xF0;
1903 }
1904
1905 if (hwinfo[addr] == 0xFF) {
1906 pw5g->bw20_diff[path][cnt] = 0xFE;
1907 } else {
1908 pw5g->bw20_diff[path][cnt] =
1909 (hwinfo[addr] & 0x0f);
1910 if (pw5g->bw20_diff[path][cnt] & BIT(3))
1911 pw5g->bw20_diff[path][cnt] |= 0xF0;
1912 }
1913 addr++;
1914 }
1915 }
1916
1917 if (hwinfo[addr] == 0xFF) {
1918 pw5g->ofdm_diff[path][1] = 0xFE;
1919 pw5g->ofdm_diff[path][2] = 0xFE;
1920 } else {
1921 pw5g->ofdm_diff[path][1] = (hwinfo[addr] & 0xf0) >> 4;
1922 pw5g->ofdm_diff[path][2] = (hwinfo[addr] & 0x0f);
1923 }
1924 addr++;
1925
1926 if (hwinfo[addr] == 0xFF)
1927 pw5g->ofdm_diff[path][3] = 0xFE;
1928 else
1929 pw5g->ofdm_diff[path][3] = (hwinfo[addr] & 0x0f);
1930 addr++;
1931
1932 for (cnt = 1; cnt < MAX_TX_COUNT; cnt++) {
1933 if (pw5g->ofdm_diff[path][cnt] == 0xFF)
1934 pw5g->ofdm_diff[path][cnt] = 0xFE;
1935 else if (pw5g->ofdm_diff[path][cnt] & BIT(3))
1936 pw5g->ofdm_diff[path][cnt] |= 0xF0;
1937 }
1938 }
1939 }
1940
1941 static void _rtl8723be_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1942 bool autoload_fail,
1943 u8 *hwinfo)
1944 {
1945 struct rtl_priv *rtlpriv = rtl_priv(hw);
1946 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1947 struct txpower_info_2g pw2g;
1948 struct txpower_info_5g pw5g;
1949 u8 rf_path, index;
1950 u8 i;
1951
1952 _rtl8723be_read_power_value_fromprom(hw, &pw2g, &pw5g, autoload_fail,
1953 hwinfo);
1954
1955 for (rf_path = 0; rf_path < 2; rf_path++) {
1956 for (i = 0; i < 14; i++) {
1957 index = _rtl8723be_get_chnl_group(i+1);
1958
1959 rtlefuse->txpwrlevel_cck[rf_path][i] =
1960 pw2g.index_cck_base[rf_path][index];
1961 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
1962 pw2g.index_bw40_base[rf_path][index];
1963 }
1964 for (i = 0; i < MAX_TX_COUNT; i++) {
1965 rtlefuse->txpwr_ht20diff[rf_path][i] =
1966 pw2g.bw20_diff[rf_path][i];
1967 rtlefuse->txpwr_ht40diff[rf_path][i] =
1968 pw2g.bw40_diff[rf_path][i];
1969 rtlefuse->txpwr_legacyhtdiff[rf_path][i] =
1970 pw2g.ofdm_diff[rf_path][i];
1971 }
1972
1973 for (i = 0; i < 14; i++) {
1974 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1975 "RF(%d)-Ch(%d) [CCK / HT40_1S ] = [0x%x / 0x%x ]\n",
1976 rf_path, i,
1977 rtlefuse->txpwrlevel_cck[rf_path][i],
1978 rtlefuse->txpwrlevel_ht40_1s[rf_path][i]);
1979 }
1980 }
1981
1982 if (!autoload_fail)
1983 rtlefuse->eeprom_thermalmeter =
1984 hwinfo[EEPROM_THERMAL_METER_88E];
1985 else
1986 rtlefuse->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
1987
1988 if (rtlefuse->eeprom_thermalmeter == 0xff || autoload_fail) {
1989 rtlefuse->apk_thermalmeterignore = true;
1990 rtlefuse->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
1991 }
1992
1993 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
1994 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1995 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
1996
1997 if (!autoload_fail) {
1998 rtlefuse->eeprom_regulatory =
1999 hwinfo[EEPROM_RF_BOARD_OPTION_88E] & 0x07;/*bit0~2*/
2000 if (hwinfo[EEPROM_RF_BOARD_OPTION_88E] == 0xFF)
2001 rtlefuse->eeprom_regulatory = 0;
2002 } else {
2003 rtlefuse->eeprom_regulatory = 0;
2004 }
2005 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
2006 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
2007 }
2008
2009 static u8 _rtl8723be_read_package_type(struct ieee80211_hw *hw)
2010 {
2011 u8 package_type;
2012 u8 value;
2013
2014 efuse_power_switch(hw, false, true);
2015 if (!efuse_one_byte_read(hw, 0x1FB, &value))
2016 value = 0;
2017 efuse_power_switch(hw, false, false);
2018
2019 switch (value & 0x7) {
2020 case 0x4:
2021 package_type = PACKAGE_TFBGA79;
2022 break;
2023 case 0x5:
2024 package_type = PACKAGE_TFBGA90;
2025 break;
2026 case 0x6:
2027 package_type = PACKAGE_QFN68;
2028 break;
2029 case 0x7:
2030 package_type = PACKAGE_TFBGA80;
2031 break;
2032 default:
2033 package_type = PACKAGE_DEFAULT;
2034 break;
2035 }
2036
2037 return package_type;
2038 }
2039
2040 static void _rtl8723be_read_adapter_info(struct ieee80211_hw *hw,
2041 bool pseudo_test)
2042 {
2043 struct rtl_priv *rtlpriv = rtl_priv(hw);
2044 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2045 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2046 int params[] = {RTL8723BE_EEPROM_ID, EEPROM_VID, EEPROM_DID,
2047 EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR,
2048 EEPROM_CHANNELPLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID,
2049 COUNTRY_CODE_WORLD_WIDE_13};
2050 u8 *hwinfo;
2051 int i;
2052 bool is_toshiba_smid1 = false;
2053 bool is_toshiba_smid2 = false;
2054 bool is_samsung_smid = false;
2055 bool is_lenovo_smid = false;
2056 u16 toshiba_smid1[] = {
2057 0x6151, 0x6152, 0x6154, 0x6155, 0x6177, 0x6178, 0x6179, 0x6180,
2058 0x7151, 0x7152, 0x7154, 0x7155, 0x7177, 0x7178, 0x7179, 0x7180,
2059 0x8151, 0x8152, 0x8154, 0x8155, 0x8181, 0x8182, 0x8184, 0x8185,
2060 0x9151, 0x9152, 0x9154, 0x9155, 0x9181, 0x9182, 0x9184, 0x9185
2061 };
2062 u16 toshiba_smid2[] = {
2063 0x6181, 0x6184, 0x6185, 0x7181, 0x7182, 0x7184, 0x7185, 0x8181,
2064 0x8182, 0x8184, 0x8185, 0x9181, 0x9182, 0x9184, 0x9185
2065 };
2066 u16 samsung_smid[] = {
2067 0x6191, 0x6192, 0x6193, 0x7191, 0x7192, 0x7193, 0x8191, 0x8192,
2068 0x8193, 0x9191, 0x9192, 0x9193
2069 };
2070 u16 lenovo_smid[] = {
2071 0x8195, 0x9195, 0x7194, 0x8200, 0x8201, 0x8202, 0x9199, 0x9200
2072 };
2073
2074 if (pseudo_test) {
2075 /* needs to be added */
2076 return;
2077 }
2078
2079 hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL);
2080 if (!hwinfo)
2081 return;
2082
2083 if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params))
2084 goto exit;
2085
2086 /*parse xtal*/
2087 rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_8723BE];
2088 if (rtlefuse->crystalcap == 0xFF)
2089 rtlefuse->crystalcap = 0x20;
2090
2091 _rtl8723be_read_txpower_info_from_hwpg(hw, rtlefuse->autoload_failflag,
2092 hwinfo);
2093
2094 rtl8723be_read_bt_coexist_info_from_hwpg(hw,
2095 rtlefuse->autoload_failflag,
2096 hwinfo);
2097
2098 if (rtlpriv->btcoexist.btc_info.btcoexist == 1)
2099 rtlefuse->board_type |= BIT(2); /* ODM_BOARD_BT */
2100
2101 rtlhal->board_type = rtlefuse->board_type;
2102 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2103 "board_type = 0x%x\n", rtlefuse->board_type);
2104
2105 rtlhal->package_type = _rtl8723be_read_package_type(hw);
2106
2107 /* set channel plan from efuse */
2108 rtlefuse->channel_plan = rtlefuse->eeprom_channelplan;
2109
2110 if (rtlhal->oem_id == RT_CID_DEFAULT) {
2111 /* Does this one have a Toshiba SMID from group 1? */
2112 for (i = 0; i < ARRAY_SIZE(toshiba_smid1); i++) {
2113 if (rtlefuse->eeprom_smid == toshiba_smid1[i]) {
2114 is_toshiba_smid1 = true;
2115 break;
2116 }
2117 }
2118 /* Does this one have a Toshiba SMID from group 2? */
2119 for (i = 0; i < ARRAY_SIZE(toshiba_smid2); i++) {
2120 if (rtlefuse->eeprom_smid == toshiba_smid2[i]) {
2121 is_toshiba_smid2 = true;
2122 break;
2123 }
2124 }
2125 /* Does this one have a Samsung SMID? */
2126 for (i = 0; i < ARRAY_SIZE(samsung_smid); i++) {
2127 if (rtlefuse->eeprom_smid == samsung_smid[i]) {
2128 is_samsung_smid = true;
2129 break;
2130 }
2131 }
2132 /* Does this one have a Lenovo SMID? */
2133 for (i = 0; i < ARRAY_SIZE(lenovo_smid); i++) {
2134 if (rtlefuse->eeprom_smid == lenovo_smid[i]) {
2135 is_lenovo_smid = true;
2136 break;
2137 }
2138 }
2139 switch (rtlefuse->eeprom_oemid) {
2140 case EEPROM_CID_DEFAULT:
2141 if (rtlefuse->eeprom_did == 0x8176) {
2142 if (rtlefuse->eeprom_svid == 0x10EC &&
2143 is_toshiba_smid1) {
2144 rtlhal->oem_id = RT_CID_TOSHIBA;
2145 } else if (rtlefuse->eeprom_svid == 0x1025) {
2146 rtlhal->oem_id = RT_CID_819X_ACER;
2147 } else if (rtlefuse->eeprom_svid == 0x10EC &&
2148 is_samsung_smid) {
2149 rtlhal->oem_id = RT_CID_819X_SAMSUNG;
2150 } else if (rtlefuse->eeprom_svid == 0x10EC &&
2151 is_lenovo_smid) {
2152 rtlhal->oem_id = RT_CID_819X_LENOVO;
2153 } else if ((rtlefuse->eeprom_svid == 0x10EC &&
2154 rtlefuse->eeprom_smid == 0x8197) ||
2155 (rtlefuse->eeprom_svid == 0x10EC &&
2156 rtlefuse->eeprom_smid == 0x9196)) {
2157 rtlhal->oem_id = RT_CID_819X_CLEVO;
2158 } else if ((rtlefuse->eeprom_svid == 0x1028 &&
2159 rtlefuse->eeprom_smid == 0x8194) ||
2160 (rtlefuse->eeprom_svid == 0x1028 &&
2161 rtlefuse->eeprom_smid == 0x8198) ||
2162 (rtlefuse->eeprom_svid == 0x1028 &&
2163 rtlefuse->eeprom_smid == 0x9197) ||
2164 (rtlefuse->eeprom_svid == 0x1028 &&
2165 rtlefuse->eeprom_smid == 0x9198)) {
2166 rtlhal->oem_id = RT_CID_819X_DELL;
2167 } else if ((rtlefuse->eeprom_svid == 0x103C &&
2168 rtlefuse->eeprom_smid == 0x1629)) {
2169 rtlhal->oem_id = RT_CID_819X_HP;
2170 } else if ((rtlefuse->eeprom_svid == 0x1A32 &&
2171 rtlefuse->eeprom_smid == 0x2315)) {
2172 rtlhal->oem_id = RT_CID_819X_QMI;
2173 } else if ((rtlefuse->eeprom_svid == 0x10EC &&
2174 rtlefuse->eeprom_smid == 0x8203)) {
2175 rtlhal->oem_id = RT_CID_819X_PRONETS;
2176 } else if ((rtlefuse->eeprom_svid == 0x1043 &&
2177 rtlefuse->eeprom_smid == 0x84B5)) {
2178 rtlhal->oem_id = RT_CID_819X_EDIMAX_ASUS;
2179 } else {
2180 rtlhal->oem_id = RT_CID_DEFAULT;
2181 }
2182 } else if (rtlefuse->eeprom_did == 0x8178) {
2183 if (rtlefuse->eeprom_svid == 0x10EC &&
2184 is_toshiba_smid2)
2185 rtlhal->oem_id = RT_CID_TOSHIBA;
2186 else if (rtlefuse->eeprom_svid == 0x1025)
2187 rtlhal->oem_id = RT_CID_819X_ACER;
2188 else if ((rtlefuse->eeprom_svid == 0x10EC &&
2189 rtlefuse->eeprom_smid == 0x8186))
2190 rtlhal->oem_id = RT_CID_819X_PRONETS;
2191 else if ((rtlefuse->eeprom_svid == 0x1043 &&
2192 rtlefuse->eeprom_smid == 0x84B6))
2193 rtlhal->oem_id =
2194 RT_CID_819X_EDIMAX_ASUS;
2195 else
2196 rtlhal->oem_id = RT_CID_DEFAULT;
2197 } else {
2198 rtlhal->oem_id = RT_CID_DEFAULT;
2199 }
2200 break;
2201 case EEPROM_CID_TOSHIBA:
2202 rtlhal->oem_id = RT_CID_TOSHIBA;
2203 break;
2204 case EEPROM_CID_CCX:
2205 rtlhal->oem_id = RT_CID_CCX;
2206 break;
2207 case EEPROM_CID_QMI:
2208 rtlhal->oem_id = RT_CID_819X_QMI;
2209 break;
2210 case EEPROM_CID_WHQL:
2211 break;
2212 default:
2213 rtlhal->oem_id = RT_CID_DEFAULT;
2214 break;
2215 }
2216 }
2217 exit:
2218 kfree(hwinfo);
2219 }
2220
2221 static void _rtl8723be_hal_customized_behavior(struct ieee80211_hw *hw)
2222 {
2223 struct rtl_priv *rtlpriv = rtl_priv(hw);
2224 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2225
2226 rtlpriv->ledctl.led_opendrain = true;
2227 switch (rtlhal->oem_id) {
2228 case RT_CID_819X_HP:
2229 rtlpriv->ledctl.led_opendrain = true;
2230 break;
2231 case RT_CID_819X_LENOVO:
2232 case RT_CID_DEFAULT:
2233 case RT_CID_TOSHIBA:
2234 case RT_CID_CCX:
2235 case RT_CID_819X_ACER:
2236 case RT_CID_WHQL:
2237 default:
2238 break;
2239 }
2240 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2241 "RT Customized ID: 0x%02X\n", rtlhal->oem_id);
2242 }
2243
2244 void rtl8723be_read_eeprom_info(struct ieee80211_hw *hw)
2245 {
2246 struct rtl_priv *rtlpriv = rtl_priv(hw);
2247 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2248 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2249 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2250 u8 tmp_u1b;
2251
2252 rtlhal->version = _rtl8723be_read_chip_version(hw);
2253 if (get_rf_type(rtlphy) == RF_1T1R)
2254 rtlpriv->dm.rfpath_rxenable[0] = true;
2255 else
2256 rtlpriv->dm.rfpath_rxenable[0] =
2257 rtlpriv->dm.rfpath_rxenable[1] = true;
2258 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
2259 rtlhal->version);
2260 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
2261 if (tmp_u1b & BIT(4)) {
2262 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
2263 rtlefuse->epromtype = EEPROM_93C46;
2264 } else {
2265 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
2266 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
2267 }
2268 if (tmp_u1b & BIT(5)) {
2269 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
2270 rtlefuse->autoload_failflag = false;
2271 _rtl8723be_read_adapter_info(hw, false);
2272 } else {
2273 pr_err("Autoload ERR!!\n");
2274 }
2275 _rtl8723be_hal_customized_behavior(hw);
2276 }
2277
2278 static u8 _rtl8723be_mrate_idx_to_arfr_id(struct ieee80211_hw *hw,
2279 u8 rate_index)
2280 {
2281 u8 ret = 0;
2282 switch (rate_index) {
2283 case RATR_INX_WIRELESS_NGB:
2284 ret = 1;
2285 break;
2286 case RATR_INX_WIRELESS_N:
2287 case RATR_INX_WIRELESS_NG:
2288 ret = 5;
2289 break;
2290 case RATR_INX_WIRELESS_NB:
2291 ret = 3;
2292 break;
2293 case RATR_INX_WIRELESS_GB:
2294 ret = 6;
2295 break;
2296 case RATR_INX_WIRELESS_G:
2297 ret = 7;
2298 break;
2299 case RATR_INX_WIRELESS_B:
2300 ret = 8;
2301 break;
2302 default:
2303 ret = 0;
2304 break;
2305 }
2306 return ret;
2307 }
2308
2309 static void rtl8723be_update_hal_rate_mask(struct ieee80211_hw *hw,
2310 struct ieee80211_sta *sta,
2311 u8 rssi_level, bool update_bw)
2312 {
2313 struct rtl_priv *rtlpriv = rtl_priv(hw);
2314 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2315 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2316 struct rtl_sta_info *sta_entry = NULL;
2317 u32 ratr_bitmap;
2318 u8 ratr_index;
2319 u8 curtxbw_40mhz = (sta->ht_cap.cap &
2320 IEEE80211_HT_CAP_SUP_WIDTH_20_40) ? 1 : 0;
2321 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2322 1 : 0;
2323 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2324 1 : 0;
2325 enum wireless_mode wirelessmode = 0;
2326 bool shortgi = false;
2327 u8 rate_mask[7];
2328 u8 macid = 0;
2329
2330 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
2331 wirelessmode = sta_entry->wireless_mode;
2332 if (mac->opmode == NL80211_IFTYPE_STATION ||
2333 mac->opmode == NL80211_IFTYPE_MESH_POINT)
2334 curtxbw_40mhz = mac->bw_40;
2335 else if (mac->opmode == NL80211_IFTYPE_AP ||
2336 mac->opmode == NL80211_IFTYPE_ADHOC)
2337 macid = sta->aid + 1;
2338
2339 ratr_bitmap = sta->supp_rates[0];
2340
2341 if (mac->opmode == NL80211_IFTYPE_ADHOC)
2342 ratr_bitmap = 0xfff;
2343
2344 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2345 sta->ht_cap.mcs.rx_mask[0] << 12);
2346 switch (wirelessmode) {
2347 case WIRELESS_MODE_B:
2348 ratr_index = RATR_INX_WIRELESS_B;
2349 if (ratr_bitmap & 0x0000000c)
2350 ratr_bitmap &= 0x0000000d;
2351 else
2352 ratr_bitmap &= 0x0000000f;
2353 break;
2354 case WIRELESS_MODE_G:
2355 ratr_index = RATR_INX_WIRELESS_GB;
2356
2357 if (rssi_level == 1)
2358 ratr_bitmap &= 0x00000f00;
2359 else if (rssi_level == 2)
2360 ratr_bitmap &= 0x00000ff0;
2361 else
2362 ratr_bitmap &= 0x00000ff5;
2363 break;
2364 case WIRELESS_MODE_N_24G:
2365 case WIRELESS_MODE_N_5G:
2366 ratr_index = RATR_INX_WIRELESS_NGB;
2367 if (rtlphy->rf_type == RF_1T1R) {
2368 if (curtxbw_40mhz) {
2369 if (rssi_level == 1)
2370 ratr_bitmap &= 0x000f0000;
2371 else if (rssi_level == 2)
2372 ratr_bitmap &= 0x000ff000;
2373 else
2374 ratr_bitmap &= 0x000ff015;
2375 } else {
2376 if (rssi_level == 1)
2377 ratr_bitmap &= 0x000f0000;
2378 else if (rssi_level == 2)
2379 ratr_bitmap &= 0x000ff000;
2380 else
2381 ratr_bitmap &= 0x000ff005;
2382 }
2383 } else {
2384 if (curtxbw_40mhz) {
2385 if (rssi_level == 1)
2386 ratr_bitmap &= 0x0f8f0000;
2387 else if (rssi_level == 2)
2388 ratr_bitmap &= 0x0f8ff000;
2389 else
2390 ratr_bitmap &= 0x0f8ff015;
2391 } else {
2392 if (rssi_level == 1)
2393 ratr_bitmap &= 0x0f8f0000;
2394 else if (rssi_level == 2)
2395 ratr_bitmap &= 0x0f8ff000;
2396 else
2397 ratr_bitmap &= 0x0f8ff005;
2398 }
2399 }
2400 if ((curtxbw_40mhz && curshortgi_40mhz) ||
2401 (!curtxbw_40mhz && curshortgi_20mhz)) {
2402 if (macid == 0)
2403 shortgi = true;
2404 else if (macid == 1)
2405 shortgi = false;
2406 }
2407 break;
2408 default:
2409 ratr_index = RATR_INX_WIRELESS_NGB;
2410
2411 if (rtlphy->rf_type == RF_1T2R)
2412 ratr_bitmap &= 0x000ff0ff;
2413 else
2414 ratr_bitmap &= 0x0f0ff0ff;
2415 break;
2416 }
2417
2418 sta_entry->ratr_index = ratr_index;
2419
2420 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2421 "ratr_bitmap :%x\n", ratr_bitmap);
2422 *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) |
2423 (ratr_index << 28);
2424 rate_mask[0] = macid;
2425 rate_mask[1] = _rtl8723be_mrate_idx_to_arfr_id(hw, ratr_index) |
2426 (shortgi ? 0x80 : 0x00);
2427 rate_mask[2] = curtxbw_40mhz | ((!update_bw) << 3);
2428
2429 rate_mask[3] = (u8)(ratr_bitmap & 0x000000ff);
2430 rate_mask[4] = (u8)((ratr_bitmap & 0x0000ff00) >> 8);
2431 rate_mask[5] = (u8)((ratr_bitmap & 0x00ff0000) >> 16);
2432 rate_mask[6] = (u8)((ratr_bitmap & 0xff000000) >> 24);
2433
2434 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2435 "Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x:%x:%x\n",
2436 ratr_index, ratr_bitmap,
2437 rate_mask[0], rate_mask[1],
2438 rate_mask[2], rate_mask[3],
2439 rate_mask[4], rate_mask[5],
2440 rate_mask[6]);
2441 rtl8723be_fill_h2c_cmd(hw, H2C_8723B_RA_MASK, 7, rate_mask);
2442 _rtl8723be_set_bcn_ctrl_reg(hw, BIT(3), 0);
2443 }
2444
2445 void rtl8723be_update_hal_rate_tbl(struct ieee80211_hw *hw,
2446 struct ieee80211_sta *sta,
2447 u8 rssi_level, bool update_bw)
2448 {
2449 struct rtl_priv *rtlpriv = rtl_priv(hw);
2450 if (rtlpriv->dm.useramask)
2451 rtl8723be_update_hal_rate_mask(hw, sta, rssi_level, update_bw);
2452 }
2453
2454 void rtl8723be_update_channel_access_setting(struct ieee80211_hw *hw)
2455 {
2456 struct rtl_priv *rtlpriv = rtl_priv(hw);
2457 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2458 u16 sifs_timer;
2459
2460 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME, &mac->slot_time);
2461 if (!mac->ht_enable)
2462 sifs_timer = 0x0a0a;
2463 else
2464 sifs_timer = 0x0e0e;
2465 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2466 }
2467
2468 bool rtl8723be_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2469 {
2470 struct rtl_priv *rtlpriv = rtl_priv(hw);
2471 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2472 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2473 enum rf_pwrstate e_rfpowerstate_toset;
2474 u8 u1tmp;
2475 bool b_actuallyset = false;
2476
2477 if (rtlpriv->rtlhal.being_init_adapter)
2478 return false;
2479
2480 if (ppsc->swrf_processing)
2481 return false;
2482
2483 spin_lock(&rtlpriv->locks.rf_ps_lock);
2484 if (ppsc->rfchange_inprogress) {
2485 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2486 return false;
2487 } else {
2488 ppsc->rfchange_inprogress = true;
2489 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2490 }
2491
2492 rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL_2,
2493 rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL_2) & ~(BIT(1)));
2494
2495 u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL_2);
2496
2497 if (rtlphy->polarity_ctl)
2498 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFOFF : ERFON;
2499 else
2500 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFON : ERFOFF;
2501
2502 if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) {
2503 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2504 "GPIOChangeRF - HW Radio ON, RF ON\n");
2505
2506 e_rfpowerstate_toset = ERFON;
2507 ppsc->hwradiooff = false;
2508 b_actuallyset = true;
2509 } else if (!ppsc->hwradiooff && (e_rfpowerstate_toset == ERFOFF)) {
2510 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2511 "GPIOChangeRF - HW Radio OFF, RF OFF\n");
2512
2513 e_rfpowerstate_toset = ERFOFF;
2514 ppsc->hwradiooff = true;
2515 b_actuallyset = true;
2516 }
2517
2518 if (b_actuallyset) {
2519 spin_lock(&rtlpriv->locks.rf_ps_lock);
2520 ppsc->rfchange_inprogress = false;
2521 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2522 } else {
2523 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
2524 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2525
2526 spin_lock(&rtlpriv->locks.rf_ps_lock);
2527 ppsc->rfchange_inprogress = false;
2528 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2529 }
2530
2531 *valid = 1;
2532 return !ppsc->hwradiooff;
2533
2534 }
2535
2536 void rtl8723be_set_key(struct ieee80211_hw *hw, u32 key_index,
2537 u8 *p_macaddr, bool is_group, u8 enc_algo,
2538 bool is_wepkey, bool clear_all)
2539 {
2540 struct rtl_priv *rtlpriv = rtl_priv(hw);
2541 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2542 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2543 u8 *macaddr = p_macaddr;
2544 u32 entry_id = 0;
2545 bool is_pairwise = false;
2546
2547 static u8 cam_const_addr[4][6] = {
2548 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2549 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2550 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2551 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2552 };
2553 static u8 cam_const_broad[] = {
2554 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2555 };
2556
2557 if (clear_all) {
2558 u8 idx = 0;
2559 u8 cam_offset = 0;
2560 u8 clear_number = 5;
2561
2562 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
2563
2564 for (idx = 0; idx < clear_number; idx++) {
2565 rtl_cam_mark_invalid(hw, cam_offset + idx);
2566 rtl_cam_empty_entry(hw, cam_offset + idx);
2567
2568 if (idx < 5) {
2569 memset(rtlpriv->sec.key_buf[idx], 0,
2570 MAX_KEY_LEN);
2571 rtlpriv->sec.key_len[idx] = 0;
2572 }
2573 }
2574
2575 } else {
2576 switch (enc_algo) {
2577 case WEP40_ENCRYPTION:
2578 enc_algo = CAM_WEP40;
2579 break;
2580 case WEP104_ENCRYPTION:
2581 enc_algo = CAM_WEP104;
2582 break;
2583 case TKIP_ENCRYPTION:
2584 enc_algo = CAM_TKIP;
2585 break;
2586 case AESCCMP_ENCRYPTION:
2587 enc_algo = CAM_AES;
2588 break;
2589 default:
2590 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
2591 "switch case %#x not processed\n", enc_algo);
2592 enc_algo = CAM_TKIP;
2593 break;
2594 }
2595
2596 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2597 macaddr = cam_const_addr[key_index];
2598 entry_id = key_index;
2599 } else {
2600 if (is_group) {
2601 macaddr = cam_const_broad;
2602 entry_id = key_index;
2603 } else {
2604 if (mac->opmode == NL80211_IFTYPE_AP) {
2605 entry_id = rtl_cam_get_free_entry(hw,
2606 p_macaddr);
2607 if (entry_id >= TOTAL_CAM_ENTRY) {
2608 pr_err("Can not find free hw security cam entry\n");
2609 return;
2610 }
2611 } else {
2612 entry_id = CAM_PAIRWISE_KEY_POSITION;
2613 }
2614
2615 key_index = PAIRWISE_KEYIDX;
2616 is_pairwise = true;
2617 }
2618 }
2619
2620 if (rtlpriv->sec.key_len[key_index] == 0) {
2621 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2622 "delete one entry, entry_id is %d\n",
2623 entry_id);
2624 if (mac->opmode == NL80211_IFTYPE_AP)
2625 rtl_cam_del_entry(hw, p_macaddr);
2626 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2627 } else {
2628 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2629 "add one entry\n");
2630 if (is_pairwise) {
2631 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2632 "set Pairwise key\n");
2633
2634 rtl_cam_add_one_entry(hw, macaddr, key_index,
2635 entry_id, enc_algo,
2636 CAM_CONFIG_NO_USEDK,
2637 rtlpriv->sec.key_buf[key_index]);
2638 } else {
2639 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2640 "set group key\n");
2641
2642 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2643 rtl_cam_add_one_entry(hw,
2644 rtlefuse->dev_addr,
2645 PAIRWISE_KEYIDX,
2646 CAM_PAIRWISE_KEY_POSITION,
2647 enc_algo,
2648 CAM_CONFIG_NO_USEDK,
2649 rtlpriv->sec.key_buf
2650 [entry_id]);
2651 }
2652
2653 rtl_cam_add_one_entry(hw, macaddr, key_index,
2654 entry_id, enc_algo,
2655 CAM_CONFIG_NO_USEDK,
2656 rtlpriv->sec.key_buf[entry_id]);
2657 }
2658 }
2659 }
2660 }
2661
2662 void rtl8723be_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
2663 bool auto_load_fail, u8 *hwinfo)
2664 {
2665 struct rtl_priv *rtlpriv = rtl_priv(hw);
2666 struct rtl_mod_params *mod_params = rtlpriv->cfg->mod_params;
2667 u8 value;
2668 u32 tmpu_32;
2669
2670 if (!auto_load_fail) {
2671 tmpu_32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL);
2672 if (tmpu_32 & BIT(18))
2673 rtlpriv->btcoexist.btc_info.btcoexist = 1;
2674 else
2675 rtlpriv->btcoexist.btc_info.btcoexist = 0;
2676 value = hwinfo[EEPROM_RF_BT_SETTING_8723B];
2677 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8723B;
2678 rtlpriv->btcoexist.btc_info.ant_num = (value & 0x1);
2679 rtlpriv->btcoexist.btc_info.single_ant_path =
2680 (value & 0x40 ? ANT_AUX : ANT_MAIN); /*0xc3[6]*/
2681 } else {
2682 rtlpriv->btcoexist.btc_info.btcoexist = 0;
2683 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8723B;
2684 rtlpriv->btcoexist.btc_info.ant_num = ANT_X2;
2685 rtlpriv->btcoexist.btc_info.single_ant_path = ANT_MAIN;
2686 }
2687
2688 /* override ant_num / ant_path */
2689 if (mod_params->ant_sel) {
2690 rtlpriv->btcoexist.btc_info.ant_num =
2691 (mod_params->ant_sel == 1 ? ANT_X1 : ANT_X2);
2692
2693 rtlpriv->btcoexist.btc_info.single_ant_path =
2694 (mod_params->ant_sel == 1 ? ANT_AUX : ANT_MAIN);
2695 }
2696 }
2697
2698 void rtl8723be_bt_reg_init(struct ieee80211_hw *hw)
2699 {
2700 struct rtl_priv *rtlpriv = rtl_priv(hw);
2701
2702 /* 0:Low, 1:High, 2:From Efuse. */
2703 rtlpriv->btcoexist.reg_bt_iso = 2;
2704 /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
2705 rtlpriv->btcoexist.reg_bt_sco = 3;
2706 /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
2707 rtlpriv->btcoexist.reg_bt_sco = 0;
2708 }
2709
2710 void rtl8723be_bt_hw_init(struct ieee80211_hw *hw)
2711 {
2712 struct rtl_priv *rtlpriv = rtl_priv(hw);
2713
2714 if (rtlpriv->cfg->ops->get_btc_status())
2715 rtlpriv->btcoexist.btc_ops->btc_init_hw_config(rtlpriv);
2716
2717 }
2718
2719 void rtl8723be_suspend(struct ieee80211_hw *hw)
2720 {
2721 }
2722
2723 void rtl8723be_resume(struct ieee80211_hw *hw)
2724 {
2725 }
Linux with added FPC-III support