drivers/net/wireless/realtek/rtw88/pci.h

   1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
   2 /* Copyright(c) 2018-2019  Realtek Corporation
   3  */
   4
   5 #ifndef __RTK_PCI_H_
   6 #define __RTK_PCI_H_
   7
   8 #define RTK_PCI_DEVICE(vend, dev, hw_config)    \
   9         PCI_DEVICE(vend, dev),                  \
  10         .driver_data = (kernel_ulong_t)&(hw_config),
  11
  12 #define RTK_DEFAULT_TX_DESC_NUM 128
  13 #define RTK_BEQ_TX_DESC_NUM     256
  14
  15 #define RTK_MAX_RX_DESC_NUM     512
  16 /* 8K + rx desc size */
  17 #define RTK_PCI_RX_BUF_SIZE     (8192 + 24)
  18
  19 #define RTK_PCI_CTRL            0x300
  20 #define BIT_RST_TRXDMA_INTF     BIT(20)
  21 #define BIT_RX_TAG_EN           BIT(15)
  22 #define REG_DBI_WDATA_V1        0x03E8
  23 #define REG_DBI_RDATA_V1        0x03EC
  24 #define REG_DBI_FLAG_V1         0x03F0
  25 #define BIT_DBI_RFLAG           BIT(17)
  26 #define BIT_DBI_WFLAG           BIT(16)
  27 #define BITS_DBI_WREN           GENMASK(15, 12)
  28 #define BITS_DBI_ADDR_MASK      GENMASK(11, 2)
  29
  30 #define REG_MDIO_V1             0x03F4
  31 #define REG_PCIE_MIX_CFG        0x03F8
  32 #define BITS_MDIO_ADDR_MASK     GENMASK(4, 0)
  33 #define BIT_MDIO_WFLAG_V1       BIT(5)
  34 #define RTW_PCI_MDIO_PG_SZ      BIT(5)
  35 #define RTW_PCI_MDIO_PG_OFFS_G1 0
  36 #define RTW_PCI_MDIO_PG_OFFS_G2 2
  37 #define RTW_PCI_WR_RETRY_CNT    20
  38
  39 #define RTK_PCIE_LINK_CFG       0x0719
  40 #define BIT_CLKREQ_SW_EN        BIT(4)
  41 #define BIT_L1_SW_EN            BIT(3)
  42
  43 #define BIT_PCI_BCNQ_FLAG       BIT(4)
  44 #define RTK_PCI_TXBD_DESA_BCNQ  0x308
  45 #define RTK_PCI_TXBD_DESA_H2CQ  0x1320
  46 #define RTK_PCI_TXBD_DESA_MGMTQ 0x310
  47 #define RTK_PCI_TXBD_DESA_BKQ   0x330
  48 #define RTK_PCI_TXBD_DESA_BEQ   0x328
  49 #define RTK_PCI_TXBD_DESA_VIQ   0x320
  50 #define RTK_PCI_TXBD_DESA_VOQ   0x318
  51 #define RTK_PCI_TXBD_DESA_HI0Q  0x340
  52 #define RTK_PCI_RXBD_DESA_MPDUQ 0x338
  53
  54 /* BCNQ is specialized for rsvd page, does not need to specify a number */
  55 #define RTK_PCI_TXBD_NUM_H2CQ   0x1328
  56 #define RTK_PCI_TXBD_NUM_MGMTQ  0x380
  57 #define RTK_PCI_TXBD_NUM_BKQ    0x38A
  58 #define RTK_PCI_TXBD_NUM_BEQ    0x388
  59 #define RTK_PCI_TXBD_NUM_VIQ    0x386
  60 #define RTK_PCI_TXBD_NUM_VOQ    0x384
  61 #define RTK_PCI_TXBD_NUM_HI0Q   0x38C
  62 #define RTK_PCI_RXBD_NUM_MPDUQ  0x382
  63 #define RTK_PCI_TXBD_IDX_H2CQ   0x132C
  64 #define RTK_PCI_TXBD_IDX_MGMTQ  0x3B0
  65 #define RTK_PCI_TXBD_IDX_BKQ    0x3AC
  66 #define RTK_PCI_TXBD_IDX_BEQ    0x3A8
  67 #define RTK_PCI_TXBD_IDX_VIQ    0x3A4
  68 #define RTK_PCI_TXBD_IDX_VOQ    0x3A0
  69 #define RTK_PCI_TXBD_IDX_HI0Q   0x3B8
  70 #define RTK_PCI_RXBD_IDX_MPDUQ  0x3B4
  71
  72 #define RTK_PCI_TXBD_RWPTR_CLR  0x39C
  73 #define RTK_PCI_TXBD_H2CQ_CSR   0x1330
  74
  75 #define BIT_CLR_H2CQ_HOST_IDX   BIT(16)
  76 #define BIT_CLR_H2CQ_HW_IDX     BIT(8)
  77
  78 #define RTK_PCI_HIMR0           0x0B0
  79 #define RTK_PCI_HISR0           0x0B4
  80 #define RTK_PCI_HIMR1           0x0B8
  81 #define RTK_PCI_HISR1           0x0BC
  82 #define RTK_PCI_HIMR2           0x10B0
  83 #define RTK_PCI_HISR2           0x10B4
  84 #define RTK_PCI_HIMR3           0x10B8
  85 #define RTK_PCI_HISR3           0x10BC
  86 /* IMR 0 */
  87 #define IMR_TIMER2              BIT(31)
  88 #define IMR_TIMER1              BIT(30)
  89 #define IMR_PSTIMEOUT           BIT(29)
  90 #define IMR_GTINT4              BIT(28)
  91 #define IMR_GTINT3              BIT(27)
  92 #define IMR_TBDER               BIT(26)
  93 #define IMR_TBDOK               BIT(25)
  94 #define IMR_TSF_BIT32_TOGGLE    BIT(24)
  95 #define IMR_BCNDMAINT0          BIT(20)
  96 #define IMR_BCNDOK0             BIT(16)
  97 #define IMR_HSISR_IND_ON_INT    BIT(15)
  98 #define IMR_BCNDMAINT_E         BIT(14)
  99 #define IMR_ATIMEND             BIT(12)
 100 #define IMR_HISR1_IND_INT       BIT(11)
 101 #define IMR_C2HCMD              BIT(10)
 102 #define IMR_CPWM2               BIT(9)
 103 #define IMR_CPWM                BIT(8)
 104 #define IMR_HIGHDOK             BIT(7)
 105 #define IMR_MGNTDOK             BIT(6)
 106 #define IMR_BKDOK               BIT(5)
 107 #define IMR_BEDOK               BIT(4)
 108 #define IMR_VIDOK               BIT(3)
 109 #define IMR_VODOK               BIT(2)
 110 #define IMR_RDU                 BIT(1)
 111 #define IMR_ROK                 BIT(0)
 112 /* IMR 1 */
 113 #define IMR_TXFIFO_TH_INT       BIT(30)
 114 #define IMR_BTON_STS_UPDATE     BIT(29)
 115 #define IMR_MCUERR              BIT(28)
 116 #define IMR_BCNDMAINT7          BIT(27)
 117 #define IMR_BCNDMAINT6          BIT(26)
 118 #define IMR_BCNDMAINT5          BIT(25)
 119 #define IMR_BCNDMAINT4          BIT(24)
 120 #define IMR_BCNDMAINT3          BIT(23)
 121 #define IMR_BCNDMAINT2          BIT(22)
 122 #define IMR_BCNDMAINT1          BIT(21)
 123 #define IMR_BCNDOK7             BIT(20)
 124 #define IMR_BCNDOK6             BIT(19)
 125 #define IMR_BCNDOK5             BIT(18)
 126 #define IMR_BCNDOK4             BIT(17)
 127 #define IMR_BCNDOK3             BIT(16)
 128 #define IMR_BCNDOK2             BIT(15)
 129 #define IMR_BCNDOK1             BIT(14)
 130 #define IMR_ATIMEND_E           BIT(13)
 131 #define IMR_ATIMEND             BIT(12)
 132 #define IMR_TXERR               BIT(11)
 133 #define IMR_RXERR               BIT(10)
 134 #define IMR_TXFOVW              BIT(9)
 135 #define IMR_RXFOVW              BIT(8)
 136 #define IMR_CPU_MGQ_TXDONE      BIT(5)
 137 #define IMR_PS_TIMER_C          BIT(4)
 138 #define IMR_PS_TIMER_B          BIT(3)
 139 #define IMR_PS_TIMER_A          BIT(2)
 140 #define IMR_CPUMGQ_TX_TIMER     BIT(1)
 141 /* IMR 3 */
 142 #define IMR_H2CDOK              BIT(16)
 143
 144 /* one element is reserved to know if the ring is closed */
 145 static inline int avail_desc(u32 wp, u32 rp, u32 len)
 146 {
 147         if (rp > wp)
 148                 return rp - wp - 1;
 149         else
 150                 return len - wp + rp - 1;
 151 }
 152
 153 #define RTK_PCI_TXBD_OWN_OFFSET 15
 154 #define RTK_PCI_TXBD_BCN_WORK   0x383
 155
 156 struct rtw_pci_tx_buffer_desc {
 157         __le16 buf_size;
 158         __le16 psb_len;
 159         __le32 dma;
 160 };
 161
 162 struct rtw_pci_tx_data {
 163         dma_addr_t dma;
 164         u8 sn;
 165 };
 166
 167 struct rtw_pci_ring {
 168         u8 *head;
 169         dma_addr_t dma;
 170
 171         u8 desc_size;
 172
 173         u32 len;
 174         u32 wp;
 175         u32 rp;
 176 };
 177
 178 struct rtw_pci_tx_ring {
 179         struct rtw_pci_ring r;
 180         struct sk_buff_head queue;
 181         bool queue_stopped;
 182 };
 183
 184 struct rtw_pci_rx_buffer_desc {
 185         __le16 buf_size;
 186         __le16 total_pkt_size;
 187         __le32 dma;
 188 };
 189
 190 struct rtw_pci_rx_ring {
 191         struct rtw_pci_ring r;
 192         struct sk_buff *buf[RTK_MAX_RX_DESC_NUM];
 193 };
 194
 195 #define RX_TAG_MAX      8192
 196
 197 struct rtw_pci {
 198         struct pci_dev *pdev;
 199
 200         /* used for pci interrupt */
 201         spinlock_t irq_lock;
 202         u32 irq_mask[4];
 203         bool irq_enabled;
 204
 205         u16 rx_tag;
 206         struct rtw_pci_tx_ring tx_rings[RTK_MAX_TX_QUEUE_NUM];
 207         struct rtw_pci_rx_ring rx_rings[RTK_MAX_RX_QUEUE_NUM];
 208         u16 link_ctrl;
 209
 210         void __iomem *mmap;
 211 };
 212
 213 static inline u32 max_num_of_tx_queue(u8 queue)
 214 {
 215         u32 max_num;
 216
 217         switch (queue) {
 218         case RTW_TX_QUEUE_BE:
 219                 max_num = RTK_BEQ_TX_DESC_NUM;
 220                 break;
 221         case RTW_TX_QUEUE_BCN:
 222                 max_num = 1;
 223                 break;
 224         default:
 225                 max_num = RTK_DEFAULT_TX_DESC_NUM;
 226                 break;
 227         }
 228
 229         return max_num;
 230 }
 231
 232 static inline struct
 233 rtw_pci_tx_data *rtw_pci_get_tx_data(struct sk_buff *skb)
 234 {
 235         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
 236
 237         BUILD_BUG_ON(sizeof(struct rtw_pci_tx_data) >
 238                      sizeof(info->status.status_driver_data));
 239
 240         return (struct rtw_pci_tx_data *)info->status.status_driver_data;
 241 }
 242
 243 static inline
 244 struct rtw_pci_tx_buffer_desc *get_tx_buffer_desc(struct rtw_pci_tx_ring *ring,
 245                                                   u32 size)
 246 {
 247         u8 *buf_desc;
 248
 249         buf_desc = ring->r.head + ring->r.wp * size;
 250         return (struct rtw_pci_tx_buffer_desc *)buf_desc;
 251 }
 252
 253 #endif