drivers/pci/controller/cadence/pcie-cadence-ep.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 // Copyright (c) 2017 Cadence
   3 // Cadence PCIe endpoint controller driver.
   4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
   5
   6 #include <linux/delay.h>
   7 #include <linux/kernel.h>
   8 #include <linux/of.h>
   9 #include <linux/pci-epc.h>
  10 #include <linux/platform_device.h>
  11 #include <linux/pm_runtime.h>
  12 #include <linux/sizes.h>
  13
  14 #include "pcie-cadence.h"
  15
  16 #define CDNS_PCIE_EP_MIN_APERTURE               128     /* 128 bytes */
  17 #define CDNS_PCIE_EP_IRQ_PCI_ADDR_NONE          0x1
  18 #define CDNS_PCIE_EP_IRQ_PCI_ADDR_LEGACY        0x3
  19
  20 static int cdns_pcie_ep_write_header(struct pci_epc *epc, u8 fn,
  21                                      struct pci_epf_header *hdr)
  22 {
  23         struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
  24         struct cdns_pcie *pcie = &ep->pcie;
  25
  26         cdns_pcie_ep_fn_writew(pcie, fn, PCI_DEVICE_ID, hdr->deviceid);
  27         cdns_pcie_ep_fn_writeb(pcie, fn, PCI_REVISION_ID, hdr->revid);
  28         cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CLASS_PROG, hdr->progif_code);
  29         cdns_pcie_ep_fn_writew(pcie, fn, PCI_CLASS_DEVICE,
  30                                hdr->subclass_code | hdr->baseclass_code << 8);
  31         cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CACHE_LINE_SIZE,
  32                                hdr->cache_line_size);
  33         cdns_pcie_ep_fn_writew(pcie, fn, PCI_SUBSYSTEM_ID, hdr->subsys_id);
  34         cdns_pcie_ep_fn_writeb(pcie, fn, PCI_INTERRUPT_PIN, hdr->interrupt_pin);
  35
  36         /*
  37          * Vendor ID can only be modified from function 0, all other functions
  38          * use the same vendor ID as function 0.
  39          */
  40         if (fn == 0) {
  41                 /* Update the vendor IDs. */
  42                 u32 id = CDNS_PCIE_LM_ID_VENDOR(hdr->vendorid) |
  43                          CDNS_PCIE_LM_ID_SUBSYS(hdr->subsys_vendor_id);
  44
  45                 cdns_pcie_writel(pcie, CDNS_PCIE_LM_ID, id);
  46         }
  47
  48         return 0;
  49 }
  50
  51 static int cdns_pcie_ep_set_bar(struct pci_epc *epc, u8 fn,
  52                                 struct pci_epf_bar *epf_bar)
  53 {
  54         struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
  55         struct cdns_pcie *pcie = &ep->pcie;
  56         dma_addr_t bar_phys = epf_bar->phys_addr;
  57         enum pci_barno bar = epf_bar->barno;
  58         int flags = epf_bar->flags;
  59         u32 addr0, addr1, reg, cfg, b, aperture, ctrl;
  60         u64 sz;
  61
  62         /* BAR size is 2^(aperture + 7) */
  63         sz = max_t(size_t, epf_bar->size, CDNS_PCIE_EP_MIN_APERTURE);
  64         /*
  65          * roundup_pow_of_two() returns an unsigned long, which is not suited
  66          * for 64bit values.
  67          */
  68         sz = 1ULL << fls64(sz - 1);
  69         aperture = ilog2(sz) - 7; /* 128B -> 0, 256B -> 1, 512B -> 2, ... */
  70
  71         if ((flags & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
  72                 ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS;
  73         } else {
  74                 bool is_prefetch = !!(flags & PCI_BASE_ADDRESS_MEM_PREFETCH);
  75                 bool is_64bits = sz > SZ_2G;
  76
  77                 if (is_64bits && (bar & 1))
  78                         return -EINVAL;
  79
  80                 if (is_64bits && !(flags & PCI_BASE_ADDRESS_MEM_TYPE_64))
  81                         epf_bar->flags |= PCI_BASE_ADDRESS_MEM_TYPE_64;
  82
  83                 if (is_64bits && is_prefetch)
  84                         ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS;
  85                 else if (is_prefetch)
  86                         ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS;
  87                 else if (is_64bits)
  88                         ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS;
  89                 else
  90                         ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS;
  91         }
  92
  93         addr0 = lower_32_bits(bar_phys);
  94         addr1 = upper_32_bits(bar_phys);
  95         cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar),
  96                          addr0);
  97         cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar),
  98                          addr1);
  99
 100         if (bar < BAR_4) {
 101                 reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn);
 102                 b = bar;
 103         } else {
 104                 reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn);
 105                 b = bar - BAR_4;
 106         }
 107
 108         cfg = cdns_pcie_readl(pcie, reg);
 109         cfg &= ~(CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) |
 110                  CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b));
 111         cfg |= (CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, aperture) |
 112                 CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl));
 113         cdns_pcie_writel(pcie, reg, cfg);
 114
 115         return 0;
 116 }
 117
 118 static void cdns_pcie_ep_clear_bar(struct pci_epc *epc, u8 fn,
 119                                    struct pci_epf_bar *epf_bar)
 120 {
 121         struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
 122         struct cdns_pcie *pcie = &ep->pcie;
 123         enum pci_barno bar = epf_bar->barno;
 124         u32 reg, cfg, b, ctrl;
 125
 126         if (bar < BAR_4) {
 127                 reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn);
 128                 b = bar;
 129         } else {
 130                 reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn);
 131                 b = bar - BAR_4;
 132         }
 133
 134         ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED;
 135         cfg = cdns_pcie_readl(pcie, reg);
 136         cfg &= ~(CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) |
 137                  CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b));
 138         cfg |= CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl);
 139         cdns_pcie_writel(pcie, reg, cfg);
 140
 141         cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar), 0);
 142         cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar), 0);
 143 }
 144
 145 static int cdns_pcie_ep_map_addr(struct pci_epc *epc, u8 fn, phys_addr_t addr,
 146                                  u64 pci_addr, size_t size)
 147 {
 148         struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
 149         struct cdns_pcie *pcie = &ep->pcie;
 150         u32 r;
 151
 152         r = find_first_zero_bit(&ep->ob_region_map,
 153                                 sizeof(ep->ob_region_map) * BITS_PER_LONG);
 154         if (r >= ep->max_regions - 1) {
 155                 dev_err(&epc->dev, "no free outbound region\n");
 156                 return -EINVAL;
 157         }
 158
 159         cdns_pcie_set_outbound_region(pcie, fn, r, false, addr, pci_addr, size);
 160
 161         set_bit(r, &ep->ob_region_map);
 162         ep->ob_addr[r] = addr;
 163
 164         return 0;
 165 }
 166
 167 static void cdns_pcie_ep_unmap_addr(struct pci_epc *epc, u8 fn,
 168                                     phys_addr_t addr)
 169 {
 170         struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
 171         struct cdns_pcie *pcie = &ep->pcie;
 172         u32 r;
 173
 174         for (r = 0; r < ep->max_regions - 1; r++)
 175                 if (ep->ob_addr[r] == addr)
 176                         break;
 177
 178         if (r == ep->max_regions - 1)
 179                 return;
 180
 181         cdns_pcie_reset_outbound_region(pcie, r);
 182
 183         ep->ob_addr[r] = 0;
 184         clear_bit(r, &ep->ob_region_map);
 185 }
 186
 187 static int cdns_pcie_ep_set_msi(struct pci_epc *epc, u8 fn, u8 mmc)
 188 {
 189         struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
 190         struct cdns_pcie *pcie = &ep->pcie;
 191         u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET;
 192         u16 flags;
 193
 194         /*
 195          * Set the Multiple Message Capable bitfield into the Message Control
 196          * register.
 197          */
 198         flags = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS);
 199         flags = (flags & ~PCI_MSI_FLAGS_QMASK) | (mmc << 1);
 200         flags |= PCI_MSI_FLAGS_64BIT;
 201         flags &= ~PCI_MSI_FLAGS_MASKBIT;
 202         cdns_pcie_ep_fn_writew(pcie, fn, cap + PCI_MSI_FLAGS, flags);
 203
 204         return 0;
 205 }
 206
 207 static int cdns_pcie_ep_get_msi(struct pci_epc *epc, u8 fn)
 208 {
 209         struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
 210         struct cdns_pcie *pcie = &ep->pcie;
 211         u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET;
 212         u16 flags, mme;
 213
 214         /* Validate that the MSI feature is actually enabled. */
 215         flags = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS);
 216         if (!(flags & PCI_MSI_FLAGS_ENABLE))
 217                 return -EINVAL;
 218
 219         /*
 220          * Get the Multiple Message Enable bitfield from the Message Control
 221          * register.
 222          */
 223         mme = (flags & PCI_MSI_FLAGS_QSIZE) >> 4;
 224
 225         return mme;
 226 }
 227
 228 static void cdns_pcie_ep_assert_intx(struct cdns_pcie_ep *ep, u8 fn,
 229                                      u8 intx, bool is_asserted)
 230 {
 231         struct cdns_pcie *pcie = &ep->pcie;
 232         u32 offset;
 233         u16 status;
 234         u8 msg_code;
 235
 236         intx &= 3;
 237
 238         /* Set the outbound region if needed. */
 239         if (unlikely(ep->irq_pci_addr != CDNS_PCIE_EP_IRQ_PCI_ADDR_LEGACY ||
 240                      ep->irq_pci_fn != fn)) {
 241                 /* First region was reserved for IRQ writes. */
 242                 cdns_pcie_set_outbound_region_for_normal_msg(pcie, fn, 0,
 243                                                              ep->irq_phys_addr);
 244                 ep->irq_pci_addr = CDNS_PCIE_EP_IRQ_PCI_ADDR_LEGACY;
 245                 ep->irq_pci_fn = fn;
 246         }
 247
 248         if (is_asserted) {
 249                 ep->irq_pending |= BIT(intx);
 250                 msg_code = MSG_CODE_ASSERT_INTA + intx;
 251         } else {
 252                 ep->irq_pending &= ~BIT(intx);
 253                 msg_code = MSG_CODE_DEASSERT_INTA + intx;
 254         }
 255
 256         status = cdns_pcie_ep_fn_readw(pcie, fn, PCI_STATUS);
 257         if (((status & PCI_STATUS_INTERRUPT) != 0) ^ (ep->irq_pending != 0)) {
 258                 status ^= PCI_STATUS_INTERRUPT;
 259                 cdns_pcie_ep_fn_writew(pcie, fn, PCI_STATUS, status);
 260         }
 261
 262         offset = CDNS_PCIE_NORMAL_MSG_ROUTING(MSG_ROUTING_LOCAL) |
 263                  CDNS_PCIE_NORMAL_MSG_CODE(msg_code) |
 264                  CDNS_PCIE_MSG_NO_DATA;
 265         writel(0, ep->irq_cpu_addr + offset);
 266 }
 267
 268 static int cdns_pcie_ep_send_legacy_irq(struct cdns_pcie_ep *ep, u8 fn, u8 intx)
 269 {
 270         u16 cmd;
 271
 272         cmd = cdns_pcie_ep_fn_readw(&ep->pcie, fn, PCI_COMMAND);
 273         if (cmd & PCI_COMMAND_INTX_DISABLE)
 274                 return -EINVAL;
 275
 276         cdns_pcie_ep_assert_intx(ep, fn, intx, true);
 277         /*
 278          * The mdelay() value was taken from dra7xx_pcie_raise_legacy_irq()
 279          * from drivers/pci/dwc/pci-dra7xx.c
 280          */
 281         mdelay(1);
 282         cdns_pcie_ep_assert_intx(ep, fn, intx, false);
 283         return 0;
 284 }
 285
 286 static int cdns_pcie_ep_send_msi_irq(struct cdns_pcie_ep *ep, u8 fn,
 287                                      u8 interrupt_num)
 288 {
 289         struct cdns_pcie *pcie = &ep->pcie;
 290         u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET;
 291         u16 flags, mme, data, data_mask;
 292         u8 msi_count;
 293         u64 pci_addr, pci_addr_mask = 0xff;
 294
 295         /* Check whether the MSI feature has been enabled by the PCI host. */
 296         flags = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS);
 297         if (!(flags & PCI_MSI_FLAGS_ENABLE))
 298                 return -EINVAL;
 299
 300         /* Get the number of enabled MSIs */
 301         mme = (flags & PCI_MSI_FLAGS_QSIZE) >> 4;
 302         msi_count = 1 << mme;
 303         if (!interrupt_num || interrupt_num > msi_count)
 304                 return -EINVAL;
 305
 306         /* Compute the data value to be written. */
 307         data_mask = msi_count - 1;
 308         data = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_DATA_64);
 309         data = (data & ~data_mask) | ((interrupt_num - 1) & data_mask);
 310
 311         /* Get the PCI address where to write the data into. */
 312         pci_addr = cdns_pcie_ep_fn_readl(pcie, fn, cap + PCI_MSI_ADDRESS_HI);
 313         pci_addr <<= 32;
 314         pci_addr |= cdns_pcie_ep_fn_readl(pcie, fn, cap + PCI_MSI_ADDRESS_LO);
 315         pci_addr &= GENMASK_ULL(63, 2);
 316
 317         /* Set the outbound region if needed. */
 318         if (unlikely(ep->irq_pci_addr != (pci_addr & ~pci_addr_mask) ||
 319                      ep->irq_pci_fn != fn)) {
 320                 /* First region was reserved for IRQ writes. */
 321                 cdns_pcie_set_outbound_region(pcie, fn, 0,
 322                                               false,
 323                                               ep->irq_phys_addr,
 324                                               pci_addr & ~pci_addr_mask,
 325                                               pci_addr_mask + 1);
 326                 ep->irq_pci_addr = (pci_addr & ~pci_addr_mask);
 327                 ep->irq_pci_fn = fn;
 328         }
 329         writel(data, ep->irq_cpu_addr + (pci_addr & pci_addr_mask));
 330
 331         return 0;
 332 }
 333
 334 static int cdns_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn,
 335                                   enum pci_epc_irq_type type,
 336                                   u16 interrupt_num)
 337 {
 338         struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
 339
 340         switch (type) {
 341         case PCI_EPC_IRQ_LEGACY:
 342                 return cdns_pcie_ep_send_legacy_irq(ep, fn, 0);
 343
 344         case PCI_EPC_IRQ_MSI:
 345                 return cdns_pcie_ep_send_msi_irq(ep, fn, interrupt_num);
 346
 347         default:
 348                 break;
 349         }
 350
 351         return -EINVAL;
 352 }
 353
 354 static int cdns_pcie_ep_start(struct pci_epc *epc)
 355 {
 356         struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
 357         struct cdns_pcie *pcie = &ep->pcie;
 358         struct pci_epf *epf;
 359         u32 cfg;
 360
 361         /*
 362          * BIT(0) is hardwired to 1, hence function 0 is always enabled
 363          * and can't be disabled anyway.
 364          */
 365         cfg = BIT(0);
 366         list_for_each_entry(epf, &epc->pci_epf, list)
 367                 cfg |= BIT(epf->func_no);
 368         cdns_pcie_writel(pcie, CDNS_PCIE_LM_EP_FUNC_CFG, cfg);
 369
 370         return 0;
 371 }
 372
 373 static const struct pci_epc_features cdns_pcie_epc_features = {
 374         .linkup_notifier = false,
 375         .msi_capable = true,
 376         .msix_capable = false,
 377 };
 378
 379 static const struct pci_epc_features*
 380 cdns_pcie_ep_get_features(struct pci_epc *epc, u8 func_no)
 381 {
 382         return &cdns_pcie_epc_features;
 383 }
 384
 385 static const struct pci_epc_ops cdns_pcie_epc_ops = {
 386         .write_header   = cdns_pcie_ep_write_header,
 387         .set_bar        = cdns_pcie_ep_set_bar,
 388         .clear_bar      = cdns_pcie_ep_clear_bar,
 389         .map_addr       = cdns_pcie_ep_map_addr,
 390         .unmap_addr     = cdns_pcie_ep_unmap_addr,
 391         .set_msi        = cdns_pcie_ep_set_msi,
 392         .get_msi        = cdns_pcie_ep_get_msi,
 393         .raise_irq      = cdns_pcie_ep_raise_irq,
 394         .start          = cdns_pcie_ep_start,
 395         .get_features   = cdns_pcie_ep_get_features,
 396 };
 397
 398
 399 int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep)
 400 {
 401         struct device *dev = ep->pcie.dev;
 402         struct platform_device *pdev = to_platform_device(dev);
 403         struct device_node *np = dev->of_node;
 404         struct cdns_pcie *pcie = &ep->pcie;
 405         struct resource *res;
 406         struct pci_epc *epc;
 407         int ret;
 408
 409         pcie->is_rc = false;
 410
 411         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "reg");
 412         pcie->reg_base = devm_ioremap_resource(dev, res);
 413         if (IS_ERR(pcie->reg_base)) {
 414                 dev_err(dev, "missing \"reg\"\n");
 415                 return PTR_ERR(pcie->reg_base);
 416         }
 417
 418         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem");
 419         if (!res) {
 420                 dev_err(dev, "missing \"mem\"\n");
 421                 return -EINVAL;
 422         }
 423         pcie->mem_res = res;
 424
 425         ret = of_property_read_u32(np, "cdns,max-outbound-regions",
 426                                    &ep->max_regions);
 427         if (ret < 0) {
 428                 dev_err(dev, "missing \"cdns,max-outbound-regions\"\n");
 429                 return ret;
 430         }
 431         ep->ob_addr = devm_kcalloc(dev,
 432                                    ep->max_regions, sizeof(*ep->ob_addr),
 433                                    GFP_KERNEL);
 434         if (!ep->ob_addr)
 435                 return -ENOMEM;
 436
 437         /* Disable all but function 0 (anyway BIT(0) is hardwired to 1). */
 438         cdns_pcie_writel(pcie, CDNS_PCIE_LM_EP_FUNC_CFG, BIT(0));
 439
 440         epc = devm_pci_epc_create(dev, &cdns_pcie_epc_ops);
 441         if (IS_ERR(epc)) {
 442                 dev_err(dev, "failed to create epc device\n");
 443                 ret = PTR_ERR(epc);
 444                 goto err_init;
 445         }
 446
 447         epc_set_drvdata(epc, ep);
 448
 449         if (of_property_read_u8(np, "max-functions", &epc->max_functions) < 0)
 450                 epc->max_functions = 1;
 451
 452         ret = pci_epc_mem_init(epc, pcie->mem_res->start,
 453                                resource_size(pcie->mem_res));
 454         if (ret < 0) {
 455                 dev_err(dev, "failed to initialize the memory space\n");
 456                 goto err_init;
 457         }
 458
 459         ep->irq_cpu_addr = pci_epc_mem_alloc_addr(epc, &ep->irq_phys_addr,
 460                                                   SZ_128K);
 461         if (!ep->irq_cpu_addr) {
 462                 dev_err(dev, "failed to reserve memory space for MSI\n");
 463                 ret = -ENOMEM;
 464                 goto free_epc_mem;
 465         }
 466         ep->irq_pci_addr = CDNS_PCIE_EP_IRQ_PCI_ADDR_NONE;
 467         /* Reserve region 0 for IRQs */
 468         set_bit(0, &ep->ob_region_map);
 469
 470         return 0;
 471
 472  free_epc_mem:
 473         pci_epc_mem_exit(epc);
 474
 475  err_init:
 476         pm_runtime_put_sync(dev);
 477
 478         return ret;
 479 }