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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / pci / controller / dwc / pci-meson.c
blob3772b02a5c55deffcd10a6536f0e99f647b8c778
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * PCIe host controller driver for Amlogic MESON SoCs
4 *
5 * Copyright (c) 2018 Amlogic, inc.
6 * Author: Yue Wang <yue.wang@amlogic.com>
7 */
8
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/gpio/consumer.h>
12 #include <linux/of_device.h>
13 #include <linux/of_gpio.h>
14 #include <linux/pci.h>
15 #include <linux/platform_device.h>
16 #include <linux/reset.h>
17 #include <linux/resource.h>
18 #include <linux/types.h>
19 #include <linux/phy/phy.h>
20
21 #include "pcie-designware.h"
22
23 #define to_meson_pcie(x) dev_get_drvdata((x)->dev)
24
25 /* External local bus interface registers */
26 #define PLR_OFFSET 0x700
27 #define PCIE_PORT_LINK_CTRL_OFF (PLR_OFFSET + 0x10)
28 #define FAST_LINK_MODE BIT(7)
29 #define LINK_CAPABLE_MASK GENMASK(21, 16)
30 #define LINK_CAPABLE_X1 BIT(16)
31
32 #define PCIE_GEN2_CTRL_OFF (PLR_OFFSET + 0x10c)
33 #define NUM_OF_LANES_MASK GENMASK(12, 8)
34 #define NUM_OF_LANES_X1 BIT(8)
35 #define DIRECT_SPEED_CHANGE BIT(17)
36
37 #define TYPE1_HDR_OFFSET 0x0
38 #define PCIE_STATUS_COMMAND (TYPE1_HDR_OFFSET + 0x04)
39 #define PCI_IO_EN BIT(0)
40 #define PCI_MEM_SPACE_EN BIT(1)
41 #define PCI_BUS_MASTER_EN BIT(2)
42
43 #define PCIE_BASE_ADDR0 (TYPE1_HDR_OFFSET + 0x10)
44 #define PCIE_BASE_ADDR1 (TYPE1_HDR_OFFSET + 0x14)
45
46 #define PCIE_CAP_OFFSET 0x70
47 #define PCIE_DEV_CTRL_DEV_STUS (PCIE_CAP_OFFSET + 0x08)
48 #define PCIE_CAP_MAX_PAYLOAD_MASK GENMASK(7, 5)
49 #define PCIE_CAP_MAX_PAYLOAD_SIZE(x) ((x) << 5)
50 #define PCIE_CAP_MAX_READ_REQ_MASK GENMASK(14, 12)
51 #define PCIE_CAP_MAX_READ_REQ_SIZE(x) ((x) << 12)
52
53 /* PCIe specific config registers */
54 #define PCIE_CFG0 0x0
55 #define APP_LTSSM_ENABLE BIT(7)
56
57 #define PCIE_CFG_STATUS12 0x30
58 #define IS_SMLH_LINK_UP(x) ((x) & (1 << 6))
59 #define IS_RDLH_LINK_UP(x) ((x) & (1 << 16))
60 #define IS_LTSSM_UP(x) ((((x) >> 10) & 0x1f) == 0x11)
61
62 #define PCIE_CFG_STATUS17 0x44
63 #define PM_CURRENT_STATE(x) (((x) >> 7) & 0x1)
64
65 #define WAIT_LINKUP_TIMEOUT 4000
66 #define PORT_CLK_RATE 100000000UL
67 #define MAX_PAYLOAD_SIZE 256
68 #define MAX_READ_REQ_SIZE 256
69 #define MESON_PCIE_PHY_POWERUP 0x1c
70 #define PCIE_RESET_DELAY 500
71 #define PCIE_SHARED_RESET 1
72 #define PCIE_NORMAL_RESET 0
73
74 enum pcie_data_rate {
75 PCIE_GEN1,
76 PCIE_GEN2,
77 PCIE_GEN3,
78 PCIE_GEN4
79 };
80
81 struct meson_pcie_mem_res {
82 void __iomem *elbi_base;
83 void __iomem *cfg_base;
84 void __iomem *phy_base;
85 };
86
87 struct meson_pcie_clk_res {
88 struct clk *clk;
89 struct clk *mipi_gate;
90 struct clk *port_clk;
91 struct clk *general_clk;
92 };
93
94 struct meson_pcie_rc_reset {
95 struct reset_control *phy;
96 struct reset_control *port;
97 struct reset_control *apb;
98 };
99
100 struct meson_pcie_param {
101 bool has_shared_phy;
102 };
103
104 struct meson_pcie {
105 struct dw_pcie pci;
106 struct meson_pcie_mem_res mem_res;
107 struct meson_pcie_clk_res clk_res;
108 struct meson_pcie_rc_reset mrst;
109 struct gpio_desc *reset_gpio;
110 struct phy *phy;
111 const struct meson_pcie_param *param;
112 };
113
114 static struct reset_control *meson_pcie_get_reset(struct meson_pcie *mp,
115 const char *id,
116 u32 reset_type)
117 {
118 struct device *dev = mp->pci.dev;
119 struct reset_control *reset;
120
121 if (reset_type == PCIE_SHARED_RESET)
122 reset = devm_reset_control_get_shared(dev, id);
123 else
124 reset = devm_reset_control_get(dev, id);
125
126 return reset;
127 }
128
129 static int meson_pcie_get_resets(struct meson_pcie *mp)
130 {
131 struct meson_pcie_rc_reset *mrst = &mp->mrst;
132
133 if (!mp->param->has_shared_phy) {
134 mrst->phy = meson_pcie_get_reset(mp, "phy", PCIE_SHARED_RESET);
135 if (IS_ERR(mrst->phy))
136 return PTR_ERR(mrst->phy);
137 reset_control_deassert(mrst->phy);
138 }
139
140 mrst->port = meson_pcie_get_reset(mp, "port", PCIE_NORMAL_RESET);
141 if (IS_ERR(mrst->port))
142 return PTR_ERR(mrst->port);
143 reset_control_deassert(mrst->port);
144
145 mrst->apb = meson_pcie_get_reset(mp, "apb", PCIE_SHARED_RESET);
146 if (IS_ERR(mrst->apb))
147 return PTR_ERR(mrst->apb);
148 reset_control_deassert(mrst->apb);
149
150 return 0;
151 }
152
153 static void __iomem *meson_pcie_get_mem(struct platform_device *pdev,
154 struct meson_pcie *mp,
155 const char *id)
156 {
157 struct device *dev = mp->pci.dev;
158 struct resource *res;
159
160 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, id);
161
162 return devm_ioremap_resource(dev, res);
163 }
164
165 static void __iomem *meson_pcie_get_mem_shared(struct platform_device *pdev,
166 struct meson_pcie *mp,
167 const char *id)
168 {
169 struct device *dev = mp->pci.dev;
170 struct resource *res;
171
172 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, id);
173 if (!res) {
174 dev_err(dev, "No REG resource %s\n", id);
175 return ERR_PTR(-ENXIO);
176 }
177
178 return devm_ioremap(dev, res->start, resource_size(res));
179 }
180
181 static int meson_pcie_get_mems(struct platform_device *pdev,
182 struct meson_pcie *mp)
183 {
184 mp->mem_res.elbi_base = meson_pcie_get_mem(pdev, mp, "elbi");
185 if (IS_ERR(mp->mem_res.elbi_base))
186 return PTR_ERR(mp->mem_res.elbi_base);
187
188 mp->mem_res.cfg_base = meson_pcie_get_mem(pdev, mp, "cfg");
189 if (IS_ERR(mp->mem_res.cfg_base))
190 return PTR_ERR(mp->mem_res.cfg_base);
191
192 /* Meson AXG SoC has two PCI controllers use same phy register */
193 if (!mp->param->has_shared_phy) {
194 mp->mem_res.phy_base =
195 meson_pcie_get_mem_shared(pdev, mp, "phy");
196 if (IS_ERR(mp->mem_res.phy_base))
197 return PTR_ERR(mp->mem_res.phy_base);
198 }
199
200 return 0;
201 }
202
203 static int meson_pcie_power_on(struct meson_pcie *mp)
204 {
205 int ret = 0;
206
207 if (mp->param->has_shared_phy) {
208 ret = phy_init(mp->phy);
209 if (ret)
210 return ret;
211
212 ret = phy_power_on(mp->phy);
213 if (ret) {
214 phy_exit(mp->phy);
215 return ret;
216 }
217 } else
218 writel(MESON_PCIE_PHY_POWERUP, mp->mem_res.phy_base);
219
220 return 0;
221 }
222
223 static int meson_pcie_reset(struct meson_pcie *mp)
224 {
225 struct meson_pcie_rc_reset *mrst = &mp->mrst;
226 int ret = 0;
227
228 if (mp->param->has_shared_phy) {
229 ret = phy_reset(mp->phy);
230 if (ret)
231 return ret;
232 } else {
233 reset_control_assert(mrst->phy);
234 udelay(PCIE_RESET_DELAY);
235 reset_control_deassert(mrst->phy);
236 udelay(PCIE_RESET_DELAY);
237 }
238
239 reset_control_assert(mrst->port);
240 reset_control_assert(mrst->apb);
241 udelay(PCIE_RESET_DELAY);
242 reset_control_deassert(mrst->port);
243 reset_control_deassert(mrst->apb);
244 udelay(PCIE_RESET_DELAY);
245
246 return 0;
247 }
248
249 static inline struct clk *meson_pcie_probe_clock(struct device *dev,
250 const char *id, u64 rate)
251 {
252 struct clk *clk;
253 int ret;
254
255 clk = devm_clk_get(dev, id);
256 if (IS_ERR(clk))
257 return clk;
258
259 if (rate) {
260 ret = clk_set_rate(clk, rate);
261 if (ret) {
262 dev_err(dev, "set clk rate failed, ret = %d\n", ret);
263 return ERR_PTR(ret);
264 }
265 }
266
267 ret = clk_prepare_enable(clk);
268 if (ret) {
269 dev_err(dev, "couldn't enable clk\n");
270 return ERR_PTR(ret);
271 }
272
273 devm_add_action_or_reset(dev,
274 (void (*) (void *))clk_disable_unprepare,
275 clk);
276
277 return clk;
278 }
279
280 static int meson_pcie_probe_clocks(struct meson_pcie *mp)
281 {
282 struct device *dev = mp->pci.dev;
283 struct meson_pcie_clk_res *res = &mp->clk_res;
284
285 res->port_clk = meson_pcie_probe_clock(dev, "port", PORT_CLK_RATE);
286 if (IS_ERR(res->port_clk))
287 return PTR_ERR(res->port_clk);
288
289 if (!mp->param->has_shared_phy) {
290 res->mipi_gate = meson_pcie_probe_clock(dev, "mipi", 0);
291 if (IS_ERR(res->mipi_gate))
292 return PTR_ERR(res->mipi_gate);
293 }
294
295 res->general_clk = meson_pcie_probe_clock(dev, "general", 0);
296 if (IS_ERR(res->general_clk))
297 return PTR_ERR(res->general_clk);
298
299 res->clk = meson_pcie_probe_clock(dev, "pclk", 0);
300 if (IS_ERR(res->clk))
301 return PTR_ERR(res->clk);
302
303 return 0;
304 }
305
306 static inline void meson_elb_writel(struct meson_pcie *mp, u32 val, u32 reg)
307 {
308 writel(val, mp->mem_res.elbi_base + reg);
309 }
310
311 static inline u32 meson_elb_readl(struct meson_pcie *mp, u32 reg)
312 {
313 return readl(mp->mem_res.elbi_base + reg);
314 }
315
316 static inline u32 meson_cfg_readl(struct meson_pcie *mp, u32 reg)
317 {
318 return readl(mp->mem_res.cfg_base + reg);
319 }
320
321 static inline void meson_cfg_writel(struct meson_pcie *mp, u32 val, u32 reg)
322 {
323 writel(val, mp->mem_res.cfg_base + reg);
324 }
325
326 static void meson_pcie_assert_reset(struct meson_pcie *mp)
327 {
328 gpiod_set_value_cansleep(mp->reset_gpio, 1);
329 udelay(500);
330 gpiod_set_value_cansleep(mp->reset_gpio, 0);
331 }
332
333 static void meson_pcie_init_dw(struct meson_pcie *mp)
334 {
335 u32 val;
336
337 val = meson_cfg_readl(mp, PCIE_CFG0);
338 val |= APP_LTSSM_ENABLE;
339 meson_cfg_writel(mp, val, PCIE_CFG0);
340
341 val = meson_elb_readl(mp, PCIE_PORT_LINK_CTRL_OFF);
342 val &= ~LINK_CAPABLE_MASK;
343 meson_elb_writel(mp, val, PCIE_PORT_LINK_CTRL_OFF);
344
345 val = meson_elb_readl(mp, PCIE_PORT_LINK_CTRL_OFF);
346 val |= LINK_CAPABLE_X1 | FAST_LINK_MODE;
347 meson_elb_writel(mp, val, PCIE_PORT_LINK_CTRL_OFF);
348
349 val = meson_elb_readl(mp, PCIE_GEN2_CTRL_OFF);
350 val &= ~NUM_OF_LANES_MASK;
351 meson_elb_writel(mp, val, PCIE_GEN2_CTRL_OFF);
352
353 val = meson_elb_readl(mp, PCIE_GEN2_CTRL_OFF);
354 val |= NUM_OF_LANES_X1 | DIRECT_SPEED_CHANGE;
355 meson_elb_writel(mp, val, PCIE_GEN2_CTRL_OFF);
356
357 meson_elb_writel(mp, 0x0, PCIE_BASE_ADDR0);
358 meson_elb_writel(mp, 0x0, PCIE_BASE_ADDR1);
359 }
360
361 static int meson_size_to_payload(struct meson_pcie *mp, int size)
362 {
363 struct device *dev = mp->pci.dev;
364
365 /*
366 * dwc supports 2^(val+7) payload size, which val is 0~5 default to 1.
367 * So if input size is not 2^order alignment or less than 2^7 or bigger
368 * than 2^12, just set to default size 2^(1+7).
369 */
370 if (!is_power_of_2(size) || size < 128 || size > 4096) {
371 dev_warn(dev, "payload size %d, set to default 256\n", size);
372 return 1;
373 }
374
375 return fls(size) - 8;
376 }
377
378 static void meson_set_max_payload(struct meson_pcie *mp, int size)
379 {
380 u32 val;
381 int max_payload_size = meson_size_to_payload(mp, size);
382
383 val = meson_elb_readl(mp, PCIE_DEV_CTRL_DEV_STUS);
384 val &= ~PCIE_CAP_MAX_PAYLOAD_MASK;
385 meson_elb_writel(mp, val, PCIE_DEV_CTRL_DEV_STUS);
386
387 val = meson_elb_readl(mp, PCIE_DEV_CTRL_DEV_STUS);
388 val |= PCIE_CAP_MAX_PAYLOAD_SIZE(max_payload_size);
389 meson_elb_writel(mp, val, PCIE_DEV_CTRL_DEV_STUS);
390 }
391
392 static void meson_set_max_rd_req_size(struct meson_pcie *mp, int size)
393 {
394 u32 val;
395 int max_rd_req_size = meson_size_to_payload(mp, size);
396
397 val = meson_elb_readl(mp, PCIE_DEV_CTRL_DEV_STUS);
398 val &= ~PCIE_CAP_MAX_READ_REQ_MASK;
399 meson_elb_writel(mp, val, PCIE_DEV_CTRL_DEV_STUS);
400
401 val = meson_elb_readl(mp, PCIE_DEV_CTRL_DEV_STUS);
402 val |= PCIE_CAP_MAX_READ_REQ_SIZE(max_rd_req_size);
403 meson_elb_writel(mp, val, PCIE_DEV_CTRL_DEV_STUS);
404 }
405
406 static inline void meson_enable_memory_space(struct meson_pcie *mp)
407 {
408 /* Set the RC Bus Master, Memory Space and I/O Space enables */
409 meson_elb_writel(mp, PCI_IO_EN | PCI_MEM_SPACE_EN | PCI_BUS_MASTER_EN,
410 PCIE_STATUS_COMMAND);
411 }
412
413 static int meson_pcie_establish_link(struct meson_pcie *mp)
414 {
415 struct dw_pcie *pci = &mp->pci;
416 struct pcie_port *pp = &pci->pp;
417
418 meson_pcie_init_dw(mp);
419 meson_set_max_payload(mp, MAX_PAYLOAD_SIZE);
420 meson_set_max_rd_req_size(mp, MAX_READ_REQ_SIZE);
421
422 dw_pcie_setup_rc(pp);
423 meson_enable_memory_space(mp);
424
425 meson_pcie_assert_reset(mp);
426
427 return dw_pcie_wait_for_link(pci);
428 }
429
430 static void meson_pcie_enable_interrupts(struct meson_pcie *mp)
431 {
432 if (IS_ENABLED(CONFIG_PCI_MSI))
433 dw_pcie_msi_init(&mp->pci.pp);
434 }
435
436 static int meson_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
437 u32 *val)
438 {
439 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
440 int ret;
441
442 ret = dw_pcie_read(pci->dbi_base + where, size, val);
443 if (ret != PCIBIOS_SUCCESSFUL)
444 return ret;
445
446 /*
447 * There is a bug in the MESON AXG PCIe controller whereby software
448 * cannot program the PCI_CLASS_DEVICE register, so we must fabricate
449 * the return value in the config accessors.
450 */
451 if (where == PCI_CLASS_REVISION && size == 4)
452 *val = (PCI_CLASS_BRIDGE_PCI << 16) | (*val & 0xffff);
453 else if (where == PCI_CLASS_DEVICE && size == 2)
454 *val = PCI_CLASS_BRIDGE_PCI;
455 else if (where == PCI_CLASS_DEVICE && size == 1)
456 *val = PCI_CLASS_BRIDGE_PCI & 0xff;
457 else if (where == PCI_CLASS_DEVICE + 1 && size == 1)
458 *val = (PCI_CLASS_BRIDGE_PCI >> 8) & 0xff;
459
460 return PCIBIOS_SUCCESSFUL;
461 }
462
463 static int meson_pcie_wr_own_conf(struct pcie_port *pp, int where,
464 int size, u32 val)
465 {
466 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
467
468 return dw_pcie_write(pci->dbi_base + where, size, val);
469 }
470
471 static int meson_pcie_link_up(struct dw_pcie *pci)
472 {
473 struct meson_pcie *mp = to_meson_pcie(pci);
474 struct device *dev = pci->dev;
475 u32 speed_okay = 0;
476 u32 cnt = 0;
477 u32 state12, state17, smlh_up, ltssm_up, rdlh_up;
478
479 do {
480 state12 = meson_cfg_readl(mp, PCIE_CFG_STATUS12);
481 state17 = meson_cfg_readl(mp, PCIE_CFG_STATUS17);
482 smlh_up = IS_SMLH_LINK_UP(state12);
483 rdlh_up = IS_RDLH_LINK_UP(state12);
484 ltssm_up = IS_LTSSM_UP(state12);
485
486 if (PM_CURRENT_STATE(state17) < PCIE_GEN3)
487 speed_okay = 1;
488
489 if (smlh_up)
490 dev_dbg(dev, "smlh_link_up is on\n");
491 if (rdlh_up)
492 dev_dbg(dev, "rdlh_link_up is on\n");
493 if (ltssm_up)
494 dev_dbg(dev, "ltssm_up is on\n");
495 if (speed_okay)
496 dev_dbg(dev, "speed_okay\n");
497
498 if (smlh_up && rdlh_up && ltssm_up && speed_okay)
499 return 1;
500
501 cnt++;
502
503 udelay(10);
504 } while (cnt < WAIT_LINKUP_TIMEOUT);
505
506 dev_err(dev, "error: wait linkup timeout\n");
507 return 0;
508 }
509
510 static int meson_pcie_host_init(struct pcie_port *pp)
511 {
512 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
513 struct meson_pcie *mp = to_meson_pcie(pci);
514 int ret;
515
516 ret = meson_pcie_establish_link(mp);
517 if (ret)
518 return ret;
519
520 meson_pcie_enable_interrupts(mp);
521
522 return 0;
523 }
524
525 static const struct dw_pcie_host_ops meson_pcie_host_ops = {
526 .rd_own_conf = meson_pcie_rd_own_conf,
527 .wr_own_conf = meson_pcie_wr_own_conf,
528 .host_init = meson_pcie_host_init,
529 };
530
531 static int meson_add_pcie_port(struct meson_pcie *mp,
532 struct platform_device *pdev)
533 {
534 struct dw_pcie *pci = &mp->pci;
535 struct pcie_port *pp = &pci->pp;
536 struct device *dev = &pdev->dev;
537 int ret;
538
539 if (IS_ENABLED(CONFIG_PCI_MSI)) {
540 pp->msi_irq = platform_get_irq(pdev, 0);
541 if (pp->msi_irq < 0) {
542 dev_err(dev, "failed to get MSI IRQ\n");
543 return pp->msi_irq;
544 }
545 }
546
547 pp->ops = &meson_pcie_host_ops;
548 pci->dbi_base = mp->mem_res.elbi_base;
549
550 ret = dw_pcie_host_init(pp);
551 if (ret) {
552 dev_err(dev, "failed to initialize host\n");
553 return ret;
554 }
555
556 return 0;
557 }
558
559 static const struct dw_pcie_ops dw_pcie_ops = {
560 .link_up = meson_pcie_link_up,
561 };
562
563 static int meson_pcie_probe(struct platform_device *pdev)
564 {
565 const struct meson_pcie_param *match_data;
566 struct device *dev = &pdev->dev;
567 struct dw_pcie *pci;
568 struct meson_pcie *mp;
569 int ret;
570
571 mp = devm_kzalloc(dev, sizeof(*mp), GFP_KERNEL);
572 if (!mp)
573 return -ENOMEM;
574
575 pci = &mp->pci;
576 pci->dev = dev;
577 pci->ops = &dw_pcie_ops;
578
579 match_data = of_device_get_match_data(dev);
580 if (!match_data) {
581 dev_err(dev, "failed to get match data\n");
582 return -ENODEV;
583 }
584 mp->param = match_data;
585
586 if (mp->param->has_shared_phy) {
587 mp->phy = devm_phy_get(dev, "pcie");
588 if (IS_ERR(mp->phy))
589 return PTR_ERR(mp->phy);
590 }
591
592 mp->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
593 if (IS_ERR(mp->reset_gpio)) {
594 dev_err(dev, "get reset gpio failed\n");
595 return PTR_ERR(mp->reset_gpio);
596 }
597
598 ret = meson_pcie_get_resets(mp);
599 if (ret) {
600 dev_err(dev, "get reset resource failed, %d\n", ret);
601 return ret;
602 }
603
604 ret = meson_pcie_get_mems(pdev, mp);
605 if (ret) {
606 dev_err(dev, "get memory resource failed, %d\n", ret);
607 return ret;
608 }
609
610 ret = meson_pcie_power_on(mp);
611 if (ret) {
612 dev_err(dev, "phy power on failed, %d\n", ret);
613 return ret;
614 }
615
616 ret = meson_pcie_reset(mp);
617 if (ret) {
618 dev_err(dev, "reset failed, %d\n", ret);
619 goto err_phy;
620 }
621
622 ret = meson_pcie_probe_clocks(mp);
623 if (ret) {
624 dev_err(dev, "init clock resources failed, %d\n", ret);
625 goto err_phy;
626 }
627
628 platform_set_drvdata(pdev, mp);
629
630 ret = meson_add_pcie_port(mp, pdev);
631 if (ret < 0) {
632 dev_err(dev, "Add PCIe port failed, %d\n", ret);
633 goto err_phy;
634 }
635
636 return 0;
637
638 err_phy:
639 if (mp->param->has_shared_phy) {
640 phy_power_off(mp->phy);
641 phy_exit(mp->phy);
642 }
643
644 return ret;
645 }
646
647 static struct meson_pcie_param meson_pcie_axg_param = {
648 .has_shared_phy = false,
649 };
650
651 static struct meson_pcie_param meson_pcie_g12a_param = {
652 .has_shared_phy = true,
653 };
654
655 static const struct of_device_id meson_pcie_of_match[] = {
656 {
657 .compatible = "amlogic,axg-pcie",
658 .data = &meson_pcie_axg_param,
659 },
660 {
661 .compatible = "amlogic,g12a-pcie",
662 .data = &meson_pcie_g12a_param,
663 },
664 {},
665 };
666
667 static struct platform_driver meson_pcie_driver = {
668 .probe = meson_pcie_probe,
669 .driver = {
670 .name = "meson-pcie",
671 .of_match_table = meson_pcie_of_match,
672 },
673 };
674
675 builtin_platform_driver(meson_pcie_driver);
Linux with added FPC-III support