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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / pci / controller / dwc / pcie-artpec6.c
blob28d5a10952000e45c8d94286b7a66da0bb133e5f
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * PCIe host controller driver for Axis ARTPEC-6 SoC
4 *
5 * Author: Niklas Cassel <niklas.cassel@axis.com>
6 *
7 * Based on work done by Phil Edworthy <phil@edworthys.org>
8 */
9
10 #include <linux/delay.h>
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/of_device.h>
14 #include <linux/pci.h>
15 #include <linux/platform_device.h>
16 #include <linux/resource.h>
17 #include <linux/signal.h>
18 #include <linux/types.h>
19 #include <linux/interrupt.h>
20 #include <linux/mfd/syscon.h>
21 #include <linux/regmap.h>
22
23 #include "pcie-designware.h"
24
25 #define to_artpec6_pcie(x) dev_get_drvdata((x)->dev)
26
27 enum artpec_pcie_variants {
28 ARTPEC6,
29 ARTPEC7,
30 };
31
32 struct artpec6_pcie {
33 struct dw_pcie *pci;
34 struct regmap *regmap; /* DT axis,syscon-pcie */
35 void __iomem *phy_base; /* DT phy */
36 enum artpec_pcie_variants variant;
37 enum dw_pcie_device_mode mode;
38 };
39
40 struct artpec_pcie_of_data {
41 enum artpec_pcie_variants variant;
42 enum dw_pcie_device_mode mode;
43 };
44
45 static const struct of_device_id artpec6_pcie_of_match[];
46
47 /* PCIe Port Logic registers (memory-mapped) */
48 #define PL_OFFSET 0x700
49
50 #define ACK_F_ASPM_CTRL_OFF (PL_OFFSET + 0xc)
51 #define ACK_N_FTS_MASK GENMASK(15, 8)
52 #define ACK_N_FTS(x) (((x) << 8) & ACK_N_FTS_MASK)
53
54 /* ARTPEC-6 specific registers */
55 #define PCIECFG 0x18
56 #define PCIECFG_DBG_OEN BIT(24)
57 #define PCIECFG_CORE_RESET_REQ BIT(21)
58 #define PCIECFG_LTSSM_ENABLE BIT(20)
59 #define PCIECFG_DEVICE_TYPE_MASK GENMASK(19, 16)
60 #define PCIECFG_CLKREQ_B BIT(11)
61 #define PCIECFG_REFCLK_ENABLE BIT(10)
62 #define PCIECFG_PLL_ENABLE BIT(9)
63 #define PCIECFG_PCLK_ENABLE BIT(8)
64 #define PCIECFG_RISRCREN BIT(4)
65 #define PCIECFG_MODE_TX_DRV_EN BIT(3)
66 #define PCIECFG_CISRREN BIT(2)
67 #define PCIECFG_MACRO_ENABLE BIT(0)
68 /* ARTPEC-7 specific fields */
69 #define PCIECFG_REFCLKSEL BIT(23)
70 #define PCIECFG_NOC_RESET BIT(3)
71
72 #define PCIESTAT 0x1c
73 /* ARTPEC-7 specific fields */
74 #define PCIESTAT_EXTREFCLK BIT(3)
75
76 #define NOCCFG 0x40
77 #define NOCCFG_ENABLE_CLK_PCIE BIT(4)
78 #define NOCCFG_POWER_PCIE_IDLEACK BIT(3)
79 #define NOCCFG_POWER_PCIE_IDLE BIT(2)
80 #define NOCCFG_POWER_PCIE_IDLEREQ BIT(1)
81
82 #define PHY_STATUS 0x118
83 #define PHY_COSPLLLOCK BIT(0)
84
85 #define PHY_TX_ASIC_OUT 0x4040
86 #define PHY_TX_ASIC_OUT_TX_ACK BIT(0)
87
88 #define PHY_RX_ASIC_OUT 0x405c
89 #define PHY_RX_ASIC_OUT_ACK BIT(0)
90
91 static u32 artpec6_pcie_readl(struct artpec6_pcie *artpec6_pcie, u32 offset)
92 {
93 u32 val;
94
95 regmap_read(artpec6_pcie->regmap, offset, &val);
96 return val;
97 }
98
99 static void artpec6_pcie_writel(struct artpec6_pcie *artpec6_pcie, u32 offset, u32 val)
100 {
101 regmap_write(artpec6_pcie->regmap, offset, val);
102 }
103
104 static u64 artpec6_pcie_cpu_addr_fixup(struct dw_pcie *pci, u64 pci_addr)
105 {
106 struct artpec6_pcie *artpec6_pcie = to_artpec6_pcie(pci);
107 struct pcie_port *pp = &pci->pp;
108 struct dw_pcie_ep *ep = &pci->ep;
109
110 switch (artpec6_pcie->mode) {
111 case DW_PCIE_RC_TYPE:
112 return pci_addr - pp->cfg0_base;
113 case DW_PCIE_EP_TYPE:
114 return pci_addr - ep->phys_base;
115 default:
116 dev_err(pci->dev, "UNKNOWN device type\n");
117 }
118 return pci_addr;
119 }
120
121 static int artpec6_pcie_establish_link(struct dw_pcie *pci)
122 {
123 struct artpec6_pcie *artpec6_pcie = to_artpec6_pcie(pci);
124 u32 val;
125
126 val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
127 val |= PCIECFG_LTSSM_ENABLE;
128 artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
129
130 return 0;
131 }
132
133 static void artpec6_pcie_stop_link(struct dw_pcie *pci)
134 {
135 struct artpec6_pcie *artpec6_pcie = to_artpec6_pcie(pci);
136 u32 val;
137
138 val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
139 val &= ~PCIECFG_LTSSM_ENABLE;
140 artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
141 }
142
143 static const struct dw_pcie_ops dw_pcie_ops = {
144 .cpu_addr_fixup = artpec6_pcie_cpu_addr_fixup,
145 .start_link = artpec6_pcie_establish_link,
146 .stop_link = artpec6_pcie_stop_link,
147 };
148
149 static void artpec6_pcie_wait_for_phy_a6(struct artpec6_pcie *artpec6_pcie)
150 {
151 struct dw_pcie *pci = artpec6_pcie->pci;
152 struct device *dev = pci->dev;
153 u32 val;
154 unsigned int retries;
155
156 retries = 50;
157 do {
158 usleep_range(1000, 2000);
159 val = artpec6_pcie_readl(artpec6_pcie, NOCCFG);
160 retries--;
161 } while (retries &&
162 (val & (NOCCFG_POWER_PCIE_IDLEACK | NOCCFG_POWER_PCIE_IDLE)));
163 if (!retries)
164 dev_err(dev, "PCIe clock manager did not leave idle state\n");
165
166 retries = 50;
167 do {
168 usleep_range(1000, 2000);
169 val = readl(artpec6_pcie->phy_base + PHY_STATUS);
170 retries--;
171 } while (retries && !(val & PHY_COSPLLLOCK));
172 if (!retries)
173 dev_err(dev, "PHY PLL did not lock\n");
174 }
175
176 static void artpec6_pcie_wait_for_phy_a7(struct artpec6_pcie *artpec6_pcie)
177 {
178 struct dw_pcie *pci = artpec6_pcie->pci;
179 struct device *dev = pci->dev;
180 u32 val;
181 u16 phy_status_tx, phy_status_rx;
182 unsigned int retries;
183
184 retries = 50;
185 do {
186 usleep_range(1000, 2000);
187 val = artpec6_pcie_readl(artpec6_pcie, NOCCFG);
188 retries--;
189 } while (retries &&
190 (val & (NOCCFG_POWER_PCIE_IDLEACK | NOCCFG_POWER_PCIE_IDLE)));
191 if (!retries)
192 dev_err(dev, "PCIe clock manager did not leave idle state\n");
193
194 retries = 50;
195 do {
196 usleep_range(1000, 2000);
197 phy_status_tx = readw(artpec6_pcie->phy_base + PHY_TX_ASIC_OUT);
198 phy_status_rx = readw(artpec6_pcie->phy_base + PHY_RX_ASIC_OUT);
199 retries--;
200 } while (retries && ((phy_status_tx & PHY_TX_ASIC_OUT_TX_ACK) ||
201 (phy_status_rx & PHY_RX_ASIC_OUT_ACK)));
202 if (!retries)
203 dev_err(dev, "PHY did not enter Pn state\n");
204 }
205
206 static void artpec6_pcie_wait_for_phy(struct artpec6_pcie *artpec6_pcie)
207 {
208 switch (artpec6_pcie->variant) {
209 case ARTPEC6:
210 artpec6_pcie_wait_for_phy_a6(artpec6_pcie);
211 break;
212 case ARTPEC7:
213 artpec6_pcie_wait_for_phy_a7(artpec6_pcie);
214 break;
215 }
216 }
217
218 static void artpec6_pcie_init_phy_a6(struct artpec6_pcie *artpec6_pcie)
219 {
220 u32 val;
221
222 val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
223 val |= PCIECFG_RISRCREN | /* Receiver term. 50 Ohm */
224 PCIECFG_MODE_TX_DRV_EN |
225 PCIECFG_CISRREN | /* Reference clock term. 100 Ohm */
226 PCIECFG_MACRO_ENABLE;
227 val |= PCIECFG_REFCLK_ENABLE;
228 val &= ~PCIECFG_DBG_OEN;
229 val &= ~PCIECFG_CLKREQ_B;
230 artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
231 usleep_range(5000, 6000);
232
233 val = artpec6_pcie_readl(artpec6_pcie, NOCCFG);
234 val |= NOCCFG_ENABLE_CLK_PCIE;
235 artpec6_pcie_writel(artpec6_pcie, NOCCFG, val);
236 usleep_range(20, 30);
237
238 val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
239 val |= PCIECFG_PCLK_ENABLE | PCIECFG_PLL_ENABLE;
240 artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
241 usleep_range(6000, 7000);
242
243 val = artpec6_pcie_readl(artpec6_pcie, NOCCFG);
244 val &= ~NOCCFG_POWER_PCIE_IDLEREQ;
245 artpec6_pcie_writel(artpec6_pcie, NOCCFG, val);
246 }
247
248 static void artpec6_pcie_init_phy_a7(struct artpec6_pcie *artpec6_pcie)
249 {
250 struct dw_pcie *pci = artpec6_pcie->pci;
251 u32 val;
252 bool extrefclk;
253
254 /* Check if external reference clock is connected */
255 val = artpec6_pcie_readl(artpec6_pcie, PCIESTAT);
256 extrefclk = !!(val & PCIESTAT_EXTREFCLK);
257 dev_dbg(pci->dev, "Using reference clock: %s\n",
258 extrefclk ? "external" : "internal");
259
260 val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
261 val |= PCIECFG_RISRCREN | /* Receiver term. 50 Ohm */
262 PCIECFG_PCLK_ENABLE;
263 if (extrefclk)
264 val |= PCIECFG_REFCLKSEL;
265 else
266 val &= ~PCIECFG_REFCLKSEL;
267 artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
268 usleep_range(10, 20);
269
270 val = artpec6_pcie_readl(artpec6_pcie, NOCCFG);
271 val |= NOCCFG_ENABLE_CLK_PCIE;
272 artpec6_pcie_writel(artpec6_pcie, NOCCFG, val);
273 usleep_range(20, 30);
274
275 val = artpec6_pcie_readl(artpec6_pcie, NOCCFG);
276 val &= ~NOCCFG_POWER_PCIE_IDLEREQ;
277 artpec6_pcie_writel(artpec6_pcie, NOCCFG, val);
278 }
279
280 static void artpec6_pcie_init_phy(struct artpec6_pcie *artpec6_pcie)
281 {
282 switch (artpec6_pcie->variant) {
283 case ARTPEC6:
284 artpec6_pcie_init_phy_a6(artpec6_pcie);
285 break;
286 case ARTPEC7:
287 artpec6_pcie_init_phy_a7(artpec6_pcie);
288 break;
289 }
290 }
291
292 static void artpec6_pcie_set_nfts(struct artpec6_pcie *artpec6_pcie)
293 {
294 struct dw_pcie *pci = artpec6_pcie->pci;
295 u32 val;
296
297 if (artpec6_pcie->variant != ARTPEC7)
298 return;
299
300 /*
301 * Increase the N_FTS (Number of Fast Training Sequences)
302 * to be transmitted when transitioning from L0s to L0.
303 */
304 val = dw_pcie_readl_dbi(pci, ACK_F_ASPM_CTRL_OFF);
305 val &= ~ACK_N_FTS_MASK;
306 val |= ACK_N_FTS(180);
307 dw_pcie_writel_dbi(pci, ACK_F_ASPM_CTRL_OFF, val);
308
309 /*
310 * Set the Number of Fast Training Sequences that the core
311 * advertises as its N_FTS during Gen2 or Gen3 link training.
312 */
313 dw_pcie_link_set_n_fts(pci, 180);
314 }
315
316 static void artpec6_pcie_assert_core_reset(struct artpec6_pcie *artpec6_pcie)
317 {
318 u32 val;
319
320 val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
321 switch (artpec6_pcie->variant) {
322 case ARTPEC6:
323 val |= PCIECFG_CORE_RESET_REQ;
324 break;
325 case ARTPEC7:
326 val &= ~PCIECFG_NOC_RESET;
327 break;
328 }
329 artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
330 }
331
332 static void artpec6_pcie_deassert_core_reset(struct artpec6_pcie *artpec6_pcie)
333 {
334 u32 val;
335
336 val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
337 switch (artpec6_pcie->variant) {
338 case ARTPEC6:
339 val &= ~PCIECFG_CORE_RESET_REQ;
340 break;
341 case ARTPEC7:
342 val |= PCIECFG_NOC_RESET;
343 break;
344 }
345 artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
346 usleep_range(100, 200);
347 }
348
349 static void artpec6_pcie_enable_interrupts(struct artpec6_pcie *artpec6_pcie)
350 {
351 struct dw_pcie *pci = artpec6_pcie->pci;
352 struct pcie_port *pp = &pci->pp;
353
354 if (IS_ENABLED(CONFIG_PCI_MSI))
355 dw_pcie_msi_init(pp);
356 }
357
358 static int artpec6_pcie_host_init(struct pcie_port *pp)
359 {
360 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
361 struct artpec6_pcie *artpec6_pcie = to_artpec6_pcie(pci);
362
363 artpec6_pcie_assert_core_reset(artpec6_pcie);
364 artpec6_pcie_init_phy(artpec6_pcie);
365 artpec6_pcie_deassert_core_reset(artpec6_pcie);
366 artpec6_pcie_wait_for_phy(artpec6_pcie);
367 artpec6_pcie_set_nfts(artpec6_pcie);
368 dw_pcie_setup_rc(pp);
369 artpec6_pcie_establish_link(pci);
370 dw_pcie_wait_for_link(pci);
371 artpec6_pcie_enable_interrupts(artpec6_pcie);
372
373 return 0;
374 }
375
376 static const struct dw_pcie_host_ops artpec6_pcie_host_ops = {
377 .host_init = artpec6_pcie_host_init,
378 };
379
380 static int artpec6_add_pcie_port(struct artpec6_pcie *artpec6_pcie,
381 struct platform_device *pdev)
382 {
383 struct dw_pcie *pci = artpec6_pcie->pci;
384 struct pcie_port *pp = &pci->pp;
385 struct device *dev = pci->dev;
386 int ret;
387
388 if (IS_ENABLED(CONFIG_PCI_MSI)) {
389 pp->msi_irq = platform_get_irq_byname(pdev, "msi");
390 if (pp->msi_irq < 0) {
391 dev_err(dev, "failed to get MSI irq\n");
392 return pp->msi_irq;
393 }
394 }
395
396 pp->ops = &artpec6_pcie_host_ops;
397
398 ret = dw_pcie_host_init(pp);
399 if (ret) {
400 dev_err(dev, "failed to initialize host\n");
401 return ret;
402 }
403
404 return 0;
405 }
406
407 static void artpec6_pcie_ep_init(struct dw_pcie_ep *ep)
408 {
409 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
410 struct artpec6_pcie *artpec6_pcie = to_artpec6_pcie(pci);
411 enum pci_barno bar;
412
413 artpec6_pcie_assert_core_reset(artpec6_pcie);
414 artpec6_pcie_init_phy(artpec6_pcie);
415 artpec6_pcie_deassert_core_reset(artpec6_pcie);
416 artpec6_pcie_wait_for_phy(artpec6_pcie);
417 artpec6_pcie_set_nfts(artpec6_pcie);
418
419 for (bar = 0; bar < PCI_STD_NUM_BARS; bar++)
420 dw_pcie_ep_reset_bar(pci, bar);
421 }
422
423 static int artpec6_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
424 enum pci_epc_irq_type type, u16 interrupt_num)
425 {
426 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
427
428 switch (type) {
429 case PCI_EPC_IRQ_LEGACY:
430 dev_err(pci->dev, "EP cannot trigger legacy IRQs\n");
431 return -EINVAL;
432 case PCI_EPC_IRQ_MSI:
433 return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
434 default:
435 dev_err(pci->dev, "UNKNOWN IRQ type\n");
436 }
437
438 return 0;
439 }
440
441 static const struct dw_pcie_ep_ops pcie_ep_ops = {
442 .ep_init = artpec6_pcie_ep_init,
443 .raise_irq = artpec6_pcie_raise_irq,
444 };
445
446 static int artpec6_add_pcie_ep(struct artpec6_pcie *artpec6_pcie,
447 struct platform_device *pdev)
448 {
449 int ret;
450 struct dw_pcie_ep *ep;
451 struct resource *res;
452 struct device *dev = &pdev->dev;
453 struct dw_pcie *pci = artpec6_pcie->pci;
454
455 ep = &pci->ep;
456 ep->ops = &pcie_ep_ops;
457
458 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi2");
459 pci->dbi_base2 = devm_ioremap_resource(dev, res);
460 if (IS_ERR(pci->dbi_base2))
461 return PTR_ERR(pci->dbi_base2);
462
463 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space");
464 if (!res)
465 return -EINVAL;
466
467 ep->phys_base = res->start;
468 ep->addr_size = resource_size(res);
469
470 ret = dw_pcie_ep_init(ep);
471 if (ret) {
472 dev_err(dev, "failed to initialize endpoint\n");
473 return ret;
474 }
475
476 return 0;
477 }
478
479 static int artpec6_pcie_probe(struct platform_device *pdev)
480 {
481 struct device *dev = &pdev->dev;
482 struct dw_pcie *pci;
483 struct artpec6_pcie *artpec6_pcie;
484 struct resource *dbi_base;
485 struct resource *phy_base;
486 int ret;
487 const struct of_device_id *match;
488 const struct artpec_pcie_of_data *data;
489 enum artpec_pcie_variants variant;
490 enum dw_pcie_device_mode mode;
491
492 match = of_match_device(artpec6_pcie_of_match, dev);
493 if (!match)
494 return -EINVAL;
495
496 data = (struct artpec_pcie_of_data *)match->data;
497 variant = (enum artpec_pcie_variants)data->variant;
498 mode = (enum dw_pcie_device_mode)data->mode;
499
500 artpec6_pcie = devm_kzalloc(dev, sizeof(*artpec6_pcie), GFP_KERNEL);
501 if (!artpec6_pcie)
502 return -ENOMEM;
503
504 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
505 if (!pci)
506 return -ENOMEM;
507
508 pci->dev = dev;
509 pci->ops = &dw_pcie_ops;
510
511 artpec6_pcie->pci = pci;
512 artpec6_pcie->variant = variant;
513 artpec6_pcie->mode = mode;
514
515 dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
516 pci->dbi_base = devm_ioremap_resource(dev, dbi_base);
517 if (IS_ERR(pci->dbi_base))
518 return PTR_ERR(pci->dbi_base);
519
520 phy_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
521 artpec6_pcie->phy_base = devm_ioremap_resource(dev, phy_base);
522 if (IS_ERR(artpec6_pcie->phy_base))
523 return PTR_ERR(artpec6_pcie->phy_base);
524
525 artpec6_pcie->regmap =
526 syscon_regmap_lookup_by_phandle(dev->of_node,
527 "axis,syscon-pcie");
528 if (IS_ERR(artpec6_pcie->regmap))
529 return PTR_ERR(artpec6_pcie->regmap);
530
531 platform_set_drvdata(pdev, artpec6_pcie);
532
533 switch (artpec6_pcie->mode) {
534 case DW_PCIE_RC_TYPE:
535 if (!IS_ENABLED(CONFIG_PCIE_ARTPEC6_HOST))
536 return -ENODEV;
537
538 ret = artpec6_add_pcie_port(artpec6_pcie, pdev);
539 if (ret < 0)
540 return ret;
541 break;
542 case DW_PCIE_EP_TYPE: {
543 u32 val;
544
545 if (!IS_ENABLED(CONFIG_PCIE_ARTPEC6_EP))
546 return -ENODEV;
547
548 val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
549 val &= ~PCIECFG_DEVICE_TYPE_MASK;
550 artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
551 ret = artpec6_add_pcie_ep(artpec6_pcie, pdev);
552 if (ret < 0)
553 return ret;
554 break;
555 }
556 default:
557 dev_err(dev, "INVALID device type %d\n", artpec6_pcie->mode);
558 }
559
560 return 0;
561 }
562
563 static const struct artpec_pcie_of_data artpec6_pcie_rc_of_data = {
564 .variant = ARTPEC6,
565 .mode = DW_PCIE_RC_TYPE,
566 };
567
568 static const struct artpec_pcie_of_data artpec6_pcie_ep_of_data = {
569 .variant = ARTPEC6,
570 .mode = DW_PCIE_EP_TYPE,
571 };
572
573 static const struct artpec_pcie_of_data artpec7_pcie_rc_of_data = {
574 .variant = ARTPEC7,
575 .mode = DW_PCIE_RC_TYPE,
576 };
577
578 static const struct artpec_pcie_of_data artpec7_pcie_ep_of_data = {
579 .variant = ARTPEC7,
580 .mode = DW_PCIE_EP_TYPE,
581 };
582
583 static const struct of_device_id artpec6_pcie_of_match[] = {
584 {
585 .compatible = "axis,artpec6-pcie",
586 .data = &artpec6_pcie_rc_of_data,
587 },
588 {
589 .compatible = "axis,artpec6-pcie-ep",
590 .data = &artpec6_pcie_ep_of_data,
591 },
592 {
593 .compatible = "axis,artpec7-pcie",
594 .data = &artpec7_pcie_rc_of_data,
595 },
596 {
597 .compatible = "axis,artpec7-pcie-ep",
598 .data = &artpec7_pcie_ep_of_data,
599 },
600 {},
601 };
602
603 static struct platform_driver artpec6_pcie_driver = {
604 .probe = artpec6_pcie_probe,
605 .driver = {
606 .name = "artpec6-pcie",
607 .of_match_table = artpec6_pcie_of_match,
608 .suppress_bind_attrs = true,
609 },
610 };
611 builtin_platform_driver(artpec6_pcie_driver);
Linux with added FPC-III support