drivers/perf/arm_pmu_acpi.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * ACPI probing code for ARM performance counters.
   4  *
   5  * Copyright (C) 2017 ARM Ltd.
   6  */
   7
   8 #include <linux/acpi.h>
   9 #include <linux/cpumask.h>
  10 #include <linux/init.h>
  11 #include <linux/irq.h>
  12 #include <linux/irqdesc.h>
  13 #include <linux/percpu.h>
  14 #include <linux/perf/arm_pmu.h>
  15
  16 #include <asm/cputype.h>
  17
  18 static DEFINE_PER_CPU(struct arm_pmu *, probed_pmus);
  19 static DEFINE_PER_CPU(int, pmu_irqs);
  20
  21 static int arm_pmu_acpi_register_irq(int cpu)
  22 {
  23         struct acpi_madt_generic_interrupt *gicc;
  24         int gsi, trigger;
  25
  26         gicc = acpi_cpu_get_madt_gicc(cpu);
  27         if (WARN_ON(!gicc))
  28                 return -EINVAL;
  29
  30         gsi = gicc->performance_interrupt;
  31
  32         /*
  33          * Per the ACPI spec, the MADT cannot describe a PMU that doesn't
  34          * have an interrupt. QEMU advertises this by using a GSI of zero,
  35          * which is not known to be valid on any hardware despite being
  36          * valid per the spec. Take the pragmatic approach and reject a
  37          * GSI of zero for now.
  38          */
  39         if (!gsi)
  40                 return 0;
  41
  42         if (gicc->flags & ACPI_MADT_PERFORMANCE_IRQ_MODE)
  43                 trigger = ACPI_EDGE_SENSITIVE;
  44         else
  45                 trigger = ACPI_LEVEL_SENSITIVE;
  46
  47         /*
  48          * Helpfully, the MADT GICC doesn't have a polarity flag for the
  49          * "performance interrupt". Luckily, on compliant GICs the polarity is
  50          * a fixed value in HW (for both SPIs and PPIs) that we cannot change
  51          * from SW.
  52          *
  53          * Here we pass in ACPI_ACTIVE_HIGH to keep the core code happy. This
  54          * may not match the real polarity, but that should not matter.
  55          *
  56          * Other interrupt controllers are not supported with ACPI.
  57          */
  58         return acpi_register_gsi(NULL, gsi, trigger, ACPI_ACTIVE_HIGH);
  59 }
  60
  61 static void arm_pmu_acpi_unregister_irq(int cpu)
  62 {
  63         struct acpi_madt_generic_interrupt *gicc;
  64         int gsi;
  65
  66         gicc = acpi_cpu_get_madt_gicc(cpu);
  67         if (!gicc)
  68                 return;
  69
  70         gsi = gicc->performance_interrupt;
  71         acpi_unregister_gsi(gsi);
  72 }
  73
  74 #if IS_ENABLED(CONFIG_ARM_SPE_PMU)
  75 static struct resource spe_resources[] = {
  76         {
  77                 /* irq */
  78                 .flags          = IORESOURCE_IRQ,
  79         }
  80 };
  81
  82 static struct platform_device spe_dev = {
  83         .name = ARMV8_SPE_PDEV_NAME,
  84         .id = -1,
  85         .resource = spe_resources,
  86         .num_resources = ARRAY_SIZE(spe_resources)
  87 };
  88
  89 /*
  90  * For lack of a better place, hook the normal PMU MADT walk
  91  * and create a SPE device if we detect a recent MADT with
  92  * a homogeneous PPI mapping.
  93  */
  94 static void arm_spe_acpi_register_device(void)
  95 {
  96         int cpu, hetid, irq, ret;
  97         bool first = true;
  98         u16 gsi = 0;
  99
 100         /*
 101          * Sanity check all the GICC tables for the same interrupt number.
 102          * For now, we only support homogeneous ACPI/SPE machines.
 103          */
 104         for_each_possible_cpu(cpu) {
 105                 struct acpi_madt_generic_interrupt *gicc;
 106
 107                 gicc = acpi_cpu_get_madt_gicc(cpu);
 108                 if (gicc->header.length < ACPI_MADT_GICC_SPE)
 109                         return;
 110
 111                 if (first) {
 112                         gsi = gicc->spe_interrupt;
 113                         if (!gsi)
 114                                 return;
 115                         hetid = find_acpi_cpu_topology_hetero_id(cpu);
 116                         first = false;
 117                 } else if ((gsi != gicc->spe_interrupt) ||
 118                            (hetid != find_acpi_cpu_topology_hetero_id(cpu))) {
 119                         pr_warn("ACPI: SPE must be homogeneous\n");
 120                         return;
 121                 }
 122         }
 123
 124         irq = acpi_register_gsi(NULL, gsi, ACPI_LEVEL_SENSITIVE,
 125                                 ACPI_ACTIVE_HIGH);
 126         if (irq < 0) {
 127                 pr_warn("ACPI: SPE Unable to register interrupt: %d\n", gsi);
 128                 return;
 129         }
 130
 131         spe_resources[0].start = irq;
 132         ret = platform_device_register(&spe_dev);
 133         if (ret < 0) {
 134                 pr_warn("ACPI: SPE: Unable to register device\n");
 135                 acpi_unregister_gsi(gsi);
 136         }
 137 }
 138 #else
 139 static inline void arm_spe_acpi_register_device(void)
 140 {
 141 }
 142 #endif /* CONFIG_ARM_SPE_PMU */
 143
 144 static int arm_pmu_acpi_parse_irqs(void)
 145 {
 146         int irq, cpu, irq_cpu, err;
 147
 148         for_each_possible_cpu(cpu) {
 149                 irq = arm_pmu_acpi_register_irq(cpu);
 150                 if (irq < 0) {
 151                         err = irq;
 152                         pr_warn("Unable to parse ACPI PMU IRQ for CPU%d: %d\n",
 153                                 cpu, err);
 154                         goto out_err;
 155                 } else if (irq == 0) {
 156                         pr_warn("No ACPI PMU IRQ for CPU%d\n", cpu);
 157                 }
 158
 159                 /*
 160                  * Log and request the IRQ so the core arm_pmu code can manage
 161                  * it. We'll have to sanity-check IRQs later when we associate
 162                  * them with their PMUs.
 163                  */
 164                 per_cpu(pmu_irqs, cpu) = irq;
 165                 armpmu_request_irq(irq, cpu);
 166         }
 167
 168         return 0;
 169
 170 out_err:
 171         for_each_possible_cpu(cpu) {
 172                 irq = per_cpu(pmu_irqs, cpu);
 173                 if (!irq)
 174                         continue;
 175
 176                 arm_pmu_acpi_unregister_irq(cpu);
 177
 178                 /*
 179                  * Blat all copies of the IRQ so that we only unregister the
 180                  * corresponding GSI once (e.g. when we have PPIs).
 181                  */
 182                 for_each_possible_cpu(irq_cpu) {
 183                         if (per_cpu(pmu_irqs, irq_cpu) == irq)
 184                                 per_cpu(pmu_irqs, irq_cpu) = 0;
 185                 }
 186         }
 187
 188         return err;
 189 }
 190
 191 static struct arm_pmu *arm_pmu_acpi_find_alloc_pmu(void)
 192 {
 193         unsigned long cpuid = read_cpuid_id();
 194         struct arm_pmu *pmu;
 195         int cpu;
 196
 197         for_each_possible_cpu(cpu) {
 198                 pmu = per_cpu(probed_pmus, cpu);
 199                 if (!pmu || pmu->acpi_cpuid != cpuid)
 200                         continue;
 201
 202                 return pmu;
 203         }
 204
 205         pmu = armpmu_alloc_atomic();
 206         if (!pmu) {
 207                 pr_warn("Unable to allocate PMU for CPU%d\n",
 208                         smp_processor_id());
 209                 return NULL;
 210         }
 211
 212         pmu->acpi_cpuid = cpuid;
 213
 214         return pmu;
 215 }
 216
 217 /*
 218  * Check whether the new IRQ is compatible with those already associated with
 219  * the PMU (e.g. we don't have mismatched PPIs).
 220  */
 221 static bool pmu_irq_matches(struct arm_pmu *pmu, int irq)
 222 {
 223         struct pmu_hw_events __percpu *hw_events = pmu->hw_events;
 224         int cpu;
 225
 226         if (!irq)
 227                 return true;
 228
 229         for_each_cpu(cpu, &pmu->supported_cpus) {
 230                 int other_irq = per_cpu(hw_events->irq, cpu);
 231                 if (!other_irq)
 232                         continue;
 233
 234                 if (irq == other_irq)
 235                         continue;
 236                 if (!irq_is_percpu_devid(irq) && !irq_is_percpu_devid(other_irq))
 237                         continue;
 238
 239                 pr_warn("mismatched PPIs detected\n");
 240                 return false;
 241         }
 242
 243         return true;
 244 }
 245
 246 /*
 247  * This must run before the common arm_pmu hotplug logic, so that we can
 248  * associate a CPU and its interrupt before the common code tries to manage the
 249  * affinity and so on.
 250  *
 251  * Note that hotplug events are serialized, so we cannot race with another CPU
 252  * coming up. The perf core won't open events while a hotplug event is in
 253  * progress.
 254  */
 255 static int arm_pmu_acpi_cpu_starting(unsigned int cpu)
 256 {
 257         struct arm_pmu *pmu;
 258         struct pmu_hw_events __percpu *hw_events;
 259         int irq;
 260
 261         /* If we've already probed this CPU, we have nothing to do */
 262         if (per_cpu(probed_pmus, cpu))
 263                 return 0;
 264
 265         irq = per_cpu(pmu_irqs, cpu);
 266
 267         pmu = arm_pmu_acpi_find_alloc_pmu();
 268         if (!pmu)
 269                 return -ENOMEM;
 270
 271         per_cpu(probed_pmus, cpu) = pmu;
 272
 273         if (pmu_irq_matches(pmu, irq)) {
 274                 hw_events = pmu->hw_events;
 275                 per_cpu(hw_events->irq, cpu) = irq;
 276         }
 277
 278         cpumask_set_cpu(cpu, &pmu->supported_cpus);
 279
 280         /*
 281          * Ideally, we'd probe the PMU here when we find the first matching
 282          * CPU. We can't do that for several reasons; see the comment in
 283          * arm_pmu_acpi_init().
 284          *
 285          * So for the time being, we're done.
 286          */
 287         return 0;
 288 }
 289
 290 int arm_pmu_acpi_probe(armpmu_init_fn init_fn)
 291 {
 292         int pmu_idx = 0;
 293         int cpu, ret;
 294
 295         /*
 296          * Initialise and register the set of PMUs which we know about right
 297          * now. Ideally we'd do this in arm_pmu_acpi_cpu_starting() so that we
 298          * could handle late hotplug, but this may lead to deadlock since we
 299          * might try to register a hotplug notifier instance from within a
 300          * hotplug notifier.
 301          *
 302          * There's also the problem of having access to the right init_fn,
 303          * without tying this too deeply into the "real" PMU driver.
 304          *
 305          * For the moment, as with the platform/DT case, we need at least one
 306          * of a PMU's CPUs to be online at probe time.
 307          */
 308         for_each_possible_cpu(cpu) {
 309                 struct arm_pmu *pmu = per_cpu(probed_pmus, cpu);
 310                 char *base_name;
 311
 312                 if (!pmu || pmu->name)
 313                         continue;
 314
 315                 ret = init_fn(pmu);
 316                 if (ret == -ENODEV) {
 317                         /* PMU not handled by this driver, or not present */
 318                         continue;
 319                 } else if (ret) {
 320                         pr_warn("Unable to initialise PMU for CPU%d\n", cpu);
 321                         return ret;
 322                 }
 323
 324                 base_name = pmu->name;
 325                 pmu->name = kasprintf(GFP_KERNEL, "%s_%d", base_name, pmu_idx++);
 326                 if (!pmu->name) {
 327                         pr_warn("Unable to allocate PMU name for CPU%d\n", cpu);
 328                         return -ENOMEM;
 329                 }
 330
 331                 ret = armpmu_register(pmu);
 332                 if (ret) {
 333                         pr_warn("Failed to register PMU for CPU%d\n", cpu);
 334                         kfree(pmu->name);
 335                         return ret;
 336                 }
 337         }
 338
 339         return 0;
 340 }
 341
 342 static int arm_pmu_acpi_init(void)
 343 {
 344         int ret;
 345
 346         if (acpi_disabled)
 347                 return 0;
 348
 349         arm_spe_acpi_register_device();
 350
 351         ret = arm_pmu_acpi_parse_irqs();
 352         if (ret)
 353                 return ret;
 354
 355         ret = cpuhp_setup_state(CPUHP_AP_PERF_ARM_ACPI_STARTING,
 356                                 "perf/arm/pmu_acpi:starting",
 357                                 arm_pmu_acpi_cpu_starting, NULL);
 358
 359         return ret;
 360 }
 361 subsys_initcall(arm_pmu_acpi_init)