drivers/phy/amlogic/phy-meson8b-usb2.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Meson8, Meson8b and GXBB USB2 PHY driver
   4  *
   5  * Copyright (C) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
   6  */
   7
   8 #include <linux/clk.h>
   9 #include <linux/delay.h>
  10 #include <linux/io.h>
  11 #include <linux/module.h>
  12 #include <linux/of_device.h>
  13 #include <linux/reset.h>
  14 #include <linux/phy/phy.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/usb/of.h>
  17
  18 #define REG_CONFIG                                      0x00
  19         #define REG_CONFIG_CLK_EN                       BIT(0)
  20         #define REG_CONFIG_CLK_SEL_MASK                 GENMASK(3, 1)
  21         #define REG_CONFIG_CLK_DIV_MASK                 GENMASK(10, 4)
  22         #define REG_CONFIG_CLK_32k_ALTSEL               BIT(15)
  23         #define REG_CONFIG_TEST_TRIG                    BIT(31)
  24
  25 #define REG_CTRL                                        0x04
  26         #define REG_CTRL_SOFT_PRST                      BIT(0)
  27         #define REG_CTRL_SOFT_HRESET                    BIT(1)
  28         #define REG_CTRL_SS_SCALEDOWN_MODE_MASK         GENMASK(3, 2)
  29         #define REG_CTRL_CLK_DET_RST                    BIT(4)
  30         #define REG_CTRL_INTR_SEL                       BIT(5)
  31         #define REG_CTRL_CLK_DETECTED                   BIT(8)
  32         #define REG_CTRL_SOF_SENT_RCVD_TGL              BIT(9)
  33         #define REG_CTRL_SOF_TOGGLE_OUT                 BIT(10)
  34         #define REG_CTRL_POWER_ON_RESET                 BIT(15)
  35         #define REG_CTRL_SLEEPM                         BIT(16)
  36         #define REG_CTRL_TX_BITSTUFF_ENN_H              BIT(17)
  37         #define REG_CTRL_TX_BITSTUFF_ENN                BIT(18)
  38         #define REG_CTRL_COMMON_ON                      BIT(19)
  39         #define REG_CTRL_REF_CLK_SEL_MASK               GENMASK(21, 20)
  40         #define REG_CTRL_REF_CLK_SEL_SHIFT              20
  41         #define REG_CTRL_FSEL_MASK                      GENMASK(24, 22)
  42         #define REG_CTRL_FSEL_SHIFT                     22
  43         #define REG_CTRL_PORT_RESET                     BIT(25)
  44         #define REG_CTRL_THREAD_ID_MASK                 GENMASK(31, 26)
  45
  46 #define REG_ENDP_INTR                                   0x08
  47
  48 /* bits [31:26], [24:21] and [15:3] seem to be read-only */
  49 #define REG_ADP_BC                                      0x0c
  50         #define REG_ADP_BC_VBUS_VLD_EXT_SEL             BIT(0)
  51         #define REG_ADP_BC_VBUS_VLD_EXT                 BIT(1)
  52         #define REG_ADP_BC_OTG_DISABLE                  BIT(2)
  53         #define REG_ADP_BC_ID_PULLUP                    BIT(3)
  54         #define REG_ADP_BC_DRV_VBUS                     BIT(4)
  55         #define REG_ADP_BC_ADP_PRB_EN                   BIT(5)
  56         #define REG_ADP_BC_ADP_DISCHARGE                BIT(6)
  57         #define REG_ADP_BC_ADP_CHARGE                   BIT(7)
  58         #define REG_ADP_BC_SESS_END                     BIT(8)
  59         #define REG_ADP_BC_DEVICE_SESS_VLD              BIT(9)
  60         #define REG_ADP_BC_B_VALID                      BIT(10)
  61         #define REG_ADP_BC_A_VALID                      BIT(11)
  62         #define REG_ADP_BC_ID_DIG                       BIT(12)
  63         #define REG_ADP_BC_VBUS_VALID                   BIT(13)
  64         #define REG_ADP_BC_ADP_PROBE                    BIT(14)
  65         #define REG_ADP_BC_ADP_SENSE                    BIT(15)
  66         #define REG_ADP_BC_ACA_ENABLE                   BIT(16)
  67         #define REG_ADP_BC_DCD_ENABLE                   BIT(17)
  68         #define REG_ADP_BC_VDAT_DET_EN_B                BIT(18)
  69         #define REG_ADP_BC_VDAT_SRC_EN_B                BIT(19)
  70         #define REG_ADP_BC_CHARGE_SEL                   BIT(20)
  71         #define REG_ADP_BC_CHARGE_DETECT                BIT(21)
  72         #define REG_ADP_BC_ACA_PIN_RANGE_C              BIT(22)
  73         #define REG_ADP_BC_ACA_PIN_RANGE_B              BIT(23)
  74         #define REG_ADP_BC_ACA_PIN_RANGE_A              BIT(24)
  75         #define REG_ADP_BC_ACA_PIN_GND                  BIT(25)
  76         #define REG_ADP_BC_ACA_PIN_FLOAT                BIT(26)
  77
  78 #define REG_DBG_UART                                    0x10
  79
  80 #define REG_TEST                                        0x14
  81         #define REG_TEST_DATA_IN_MASK                   GENMASK(3, 0)
  82         #define REG_TEST_EN_MASK                        GENMASK(7, 4)
  83         #define REG_TEST_ADDR_MASK                      GENMASK(11, 8)
  84         #define REG_TEST_DATA_OUT_SEL                   BIT(12)
  85         #define REG_TEST_CLK                            BIT(13)
  86         #define REG_TEST_VA_TEST_EN_B_MASK              GENMASK(15, 14)
  87         #define REG_TEST_DATA_OUT_MASK                  GENMASK(19, 16)
  88         #define REG_TEST_DISABLE_ID_PULLUP              BIT(20)
  89
  90 #define REG_TUNE                                        0x18
  91         #define REG_TUNE_TX_RES_TUNE_MASK               GENMASK(1, 0)
  92         #define REG_TUNE_TX_HSXV_TUNE_MASK              GENMASK(3, 2)
  93         #define REG_TUNE_TX_VREF_TUNE_MASK              GENMASK(7, 4)
  94         #define REG_TUNE_TX_RISE_TUNE_MASK              GENMASK(9, 8)
  95         #define REG_TUNE_TX_PREEMP_PULSE_TUNE           BIT(10)
  96         #define REG_TUNE_TX_PREEMP_AMP_TUNE_MASK        GENMASK(12, 11)
  97         #define REG_TUNE_TX_FSLS_TUNE_MASK              GENMASK(16, 13)
  98         #define REG_TUNE_SQRX_TUNE_MASK                 GENMASK(19, 17)
  99         #define REG_TUNE_OTG_TUNE                       GENMASK(22, 20)
 100         #define REG_TUNE_COMP_DIS_TUNE                  GENMASK(25, 23)
 101         #define REG_TUNE_HOST_DM_PULLDOWN               BIT(26)
 102         #define REG_TUNE_HOST_DP_PULLDOWN               BIT(27)
 103
 104 #define RESET_COMPLETE_TIME                             500
 105 #define ACA_ENABLE_COMPLETE_TIME                        50
 106
 107 struct phy_meson8b_usb2_priv {
 108         void __iomem            *regs;
 109         enum usb_dr_mode        dr_mode;
 110         struct clk              *clk_usb_general;
 111         struct clk              *clk_usb;
 112         struct reset_control    *reset;
 113 };
 114
 115 static u32 phy_meson8b_usb2_read(struct phy_meson8b_usb2_priv *phy_priv,
 116                                  u32 reg)
 117 {
 118         return readl(phy_priv->regs + reg);
 119 }
 120
 121 static void phy_meson8b_usb2_mask_bits(struct phy_meson8b_usb2_priv *phy_priv,
 122                                        u32 reg, u32 mask, u32 value)
 123 {
 124         u32 data;
 125
 126         data = phy_meson8b_usb2_read(phy_priv, reg);
 127         data &= ~mask;
 128         data |= (value & mask);
 129
 130         writel(data, phy_priv->regs + reg);
 131 }
 132
 133 static int phy_meson8b_usb2_power_on(struct phy *phy)
 134 {
 135         struct phy_meson8b_usb2_priv *priv = phy_get_drvdata(phy);
 136         int ret;
 137
 138         if (!IS_ERR_OR_NULL(priv->reset)) {
 139                 ret = reset_control_reset(priv->reset);
 140                 if (ret) {
 141                         dev_err(&phy->dev, "Failed to trigger USB reset\n");
 142                         return ret;
 143                 }
 144         }
 145
 146         ret = clk_prepare_enable(priv->clk_usb_general);
 147         if (ret) {
 148                 dev_err(&phy->dev, "Failed to enable USB general clock\n");
 149                 return ret;
 150         }
 151
 152         ret = clk_prepare_enable(priv->clk_usb);
 153         if (ret) {
 154                 dev_err(&phy->dev, "Failed to enable USB DDR clock\n");
 155                 clk_disable_unprepare(priv->clk_usb_general);
 156                 return ret;
 157         }
 158
 159         phy_meson8b_usb2_mask_bits(priv, REG_CONFIG, REG_CONFIG_CLK_32k_ALTSEL,
 160                                    REG_CONFIG_CLK_32k_ALTSEL);
 161
 162         phy_meson8b_usb2_mask_bits(priv, REG_CTRL, REG_CTRL_REF_CLK_SEL_MASK,
 163                                    0x2 << REG_CTRL_REF_CLK_SEL_SHIFT);
 164
 165         phy_meson8b_usb2_mask_bits(priv, REG_CTRL, REG_CTRL_FSEL_MASK,
 166                                    0x5 << REG_CTRL_FSEL_SHIFT);
 167
 168         /* reset the PHY */
 169         phy_meson8b_usb2_mask_bits(priv, REG_CTRL, REG_CTRL_POWER_ON_RESET,
 170                                    REG_CTRL_POWER_ON_RESET);
 171         udelay(RESET_COMPLETE_TIME);
 172         phy_meson8b_usb2_mask_bits(priv, REG_CTRL, REG_CTRL_POWER_ON_RESET, 0);
 173         udelay(RESET_COMPLETE_TIME);
 174
 175         phy_meson8b_usb2_mask_bits(priv, REG_CTRL, REG_CTRL_SOF_TOGGLE_OUT,
 176                                    REG_CTRL_SOF_TOGGLE_OUT);
 177
 178         if (priv->dr_mode == USB_DR_MODE_HOST) {
 179                 phy_meson8b_usb2_mask_bits(priv, REG_ADP_BC,
 180                                            REG_ADP_BC_ACA_ENABLE,
 181                                            REG_ADP_BC_ACA_ENABLE);
 182
 183                 udelay(ACA_ENABLE_COMPLETE_TIME);
 184
 185                 if (phy_meson8b_usb2_read(priv, REG_ADP_BC) &
 186                         REG_ADP_BC_ACA_PIN_FLOAT) {
 187                         dev_warn(&phy->dev, "USB ID detect failed!\n");
 188                         clk_disable_unprepare(priv->clk_usb);
 189                         clk_disable_unprepare(priv->clk_usb_general);
 190                         return -EINVAL;
 191                 }
 192         }
 193
 194         return 0;
 195 }
 196
 197 static int phy_meson8b_usb2_power_off(struct phy *phy)
 198 {
 199         struct phy_meson8b_usb2_priv *priv = phy_get_drvdata(phy);
 200
 201         clk_disable_unprepare(priv->clk_usb);
 202         clk_disable_unprepare(priv->clk_usb_general);
 203
 204         return 0;
 205 }
 206
 207 static const struct phy_ops phy_meson8b_usb2_ops = {
 208         .power_on       = phy_meson8b_usb2_power_on,
 209         .power_off      = phy_meson8b_usb2_power_off,
 210         .owner          = THIS_MODULE,
 211 };
 212
 213 static int phy_meson8b_usb2_probe(struct platform_device *pdev)
 214 {
 215         struct phy_meson8b_usb2_priv *priv;
 216         struct resource *res;
 217         struct phy *phy;
 218         struct phy_provider *phy_provider;
 219
 220         priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
 221         if (!priv)
 222                 return -ENOMEM;
 223
 224         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 225         priv->regs = devm_ioremap_resource(&pdev->dev, res);
 226         if (IS_ERR(priv->regs))
 227                 return PTR_ERR(priv->regs);
 228
 229         priv->clk_usb_general = devm_clk_get(&pdev->dev, "usb_general");
 230         if (IS_ERR(priv->clk_usb_general))
 231                 return PTR_ERR(priv->clk_usb_general);
 232
 233         priv->clk_usb = devm_clk_get(&pdev->dev, "usb");
 234         if (IS_ERR(priv->clk_usb))
 235                 return PTR_ERR(priv->clk_usb);
 236
 237         priv->reset = devm_reset_control_get_optional_shared(&pdev->dev, NULL);
 238         if (PTR_ERR(priv->reset) == -EPROBE_DEFER)
 239                 return PTR_ERR(priv->reset);
 240
 241         priv->dr_mode = of_usb_get_dr_mode_by_phy(pdev->dev.of_node, -1);
 242         if (priv->dr_mode == USB_DR_MODE_UNKNOWN) {
 243                 dev_err(&pdev->dev,
 244                         "missing dual role configuration of the controller\n");
 245                 return -EINVAL;
 246         }
 247
 248         phy = devm_phy_create(&pdev->dev, NULL, &phy_meson8b_usb2_ops);
 249         if (IS_ERR(phy)) {
 250                 dev_err(&pdev->dev, "failed to create PHY\n");
 251                 return PTR_ERR(phy);
 252         }
 253
 254         phy_set_drvdata(phy, priv);
 255
 256         phy_provider =
 257                 devm_of_phy_provider_register(&pdev->dev, of_phy_simple_xlate);
 258
 259         return PTR_ERR_OR_ZERO(phy_provider);
 260 }
 261
 262 static const struct of_device_id phy_meson8b_usb2_of_match[] = {
 263         { .compatible = "amlogic,meson8-usb2-phy", },
 264         { .compatible = "amlogic,meson8b-usb2-phy", },
 265         { .compatible = "amlogic,meson-gxbb-usb2-phy", },
 266         { },
 267 };
 268 MODULE_DEVICE_TABLE(of, phy_meson8b_usb2_of_match);
 269
 270 static struct platform_driver phy_meson8b_usb2_driver = {
 271         .probe  = phy_meson8b_usb2_probe,
 272         .driver = {
 273                 .name           = "phy-meson-usb2",
 274                 .of_match_table = phy_meson8b_usb2_of_match,
 275         },
 276 };
 277 module_platform_driver(phy_meson8b_usb2_driver);
 278
 279 MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
 280 MODULE_DESCRIPTION("Meson8, Meson8b and GXBB USB2 PHY driver");
 281 MODULE_LICENSE("GPL");