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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / phy / broadcom / phy-brcm-sata.c
blob4710cfcc3037f346fe08035e3f65eef8a479f890
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Broadcom SATA3 AHCI Controller PHY Driver
4 *
5 * Copyright (C) 2016 Broadcom
6 */
7
8 #include <linux/delay.h>
9 #include <linux/device.h>
10 #include <linux/init.h>
11 #include <linux/interrupt.h>
12 #include <linux/io.h>
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/of.h>
16 #include <linux/phy/phy.h>
17 #include <linux/platform_device.h>
18
19 #define SATA_PCB_BANK_OFFSET 0x23c
20 #define SATA_PCB_REG_OFFSET(ofs) ((ofs) * 4)
21
22 #define MAX_PORTS 2
23
24 /* Register offset between PHYs in PCB space */
25 #define SATA_PCB_REG_28NM_SPACE_SIZE 0x1000
26
27 /* The older SATA PHY registers duplicated per port registers within the map,
28 * rather than having a separate map per port.
29 */
30 #define SATA_PCB_REG_40NM_SPACE_SIZE 0x10
31
32 /* Register offset between PHYs in PHY control space */
33 #define SATA_PHY_CTRL_REG_28NM_SPACE_SIZE 0x8
34
35 enum brcm_sata_phy_version {
36 BRCM_SATA_PHY_STB_16NM,
37 BRCM_SATA_PHY_STB_28NM,
38 BRCM_SATA_PHY_STB_40NM,
39 BRCM_SATA_PHY_IPROC_NS2,
40 BRCM_SATA_PHY_IPROC_NSP,
41 BRCM_SATA_PHY_IPROC_SR,
42 BRCM_SATA_PHY_DSL_28NM,
43 };
44
45 enum brcm_sata_phy_rxaeq_mode {
46 RXAEQ_MODE_OFF = 0,
47 RXAEQ_MODE_AUTO,
48 RXAEQ_MODE_MANUAL,
49 };
50
51 static enum brcm_sata_phy_rxaeq_mode rxaeq_to_val(const char *m)
52 {
53 if (!strcmp(m, "auto"))
54 return RXAEQ_MODE_AUTO;
55 else if (!strcmp(m, "manual"))
56 return RXAEQ_MODE_MANUAL;
57 else
58 return RXAEQ_MODE_OFF;
59 }
60
61 struct brcm_sata_port {
62 int portnum;
63 struct phy *phy;
64 struct brcm_sata_phy *phy_priv;
65 bool ssc_en;
66 enum brcm_sata_phy_rxaeq_mode rxaeq_mode;
67 u32 rxaeq_val;
68 };
69
70 struct brcm_sata_phy {
71 struct device *dev;
72 void __iomem *phy_base;
73 void __iomem *ctrl_base;
74 enum brcm_sata_phy_version version;
75
76 struct brcm_sata_port phys[MAX_PORTS];
77 };
78
79 enum sata_phy_regs {
80 BLOCK0_REG_BANK = 0x000,
81 BLOCK0_XGXSSTATUS = 0x81,
82 BLOCK0_XGXSSTATUS_PLL_LOCK = BIT(12),
83 BLOCK0_SPARE = 0x8d,
84 BLOCK0_SPARE_OOB_CLK_SEL_MASK = 0x3,
85 BLOCK0_SPARE_OOB_CLK_SEL_REFBY2 = 0x1,
86
87 PLL_REG_BANK_0 = 0x050,
88 PLL_REG_BANK_0_PLLCONTROL_0 = 0x81,
89 PLLCONTROL_0_FREQ_DET_RESTART = BIT(13),
90 PLLCONTROL_0_FREQ_MONITOR = BIT(12),
91 PLLCONTROL_0_SEQ_START = BIT(15),
92 PLL_CAP_CHARGE_TIME = 0x83,
93 PLL_VCO_CAL_THRESH = 0x84,
94 PLL_CAP_CONTROL = 0x85,
95 PLL_FREQ_DET_TIME = 0x86,
96 PLL_ACTRL2 = 0x8b,
97 PLL_ACTRL2_SELDIV_MASK = 0x1f,
98 PLL_ACTRL2_SELDIV_SHIFT = 9,
99 PLL_ACTRL6 = 0x86,
100
101 PLL1_REG_BANK = 0x060,
102 PLL1_ACTRL2 = 0x82,
103 PLL1_ACTRL3 = 0x83,
104 PLL1_ACTRL4 = 0x84,
105 PLL1_ACTRL5 = 0x85,
106 PLL1_ACTRL6 = 0x86,
107 PLL1_ACTRL7 = 0x87,
108 PLL1_ACTRL8 = 0x88,
109
110 TX_REG_BANK = 0x070,
111 TX_ACTRL0 = 0x80,
112 TX_ACTRL0_TXPOL_FLIP = BIT(6),
113 TX_ACTRL5 = 0x85,
114 TX_ACTRL5_SSC_EN = BIT(11),
115
116 AEQRX_REG_BANK_0 = 0xd0,
117 AEQ_CONTROL1 = 0x81,
118 AEQ_CONTROL1_ENABLE = BIT(2),
119 AEQ_CONTROL1_FREEZE = BIT(3),
120 AEQ_FRC_EQ = 0x83,
121 AEQ_FRC_EQ_FORCE = BIT(0),
122 AEQ_FRC_EQ_FORCE_VAL = BIT(1),
123 AEQ_RFZ_FRC_VAL = BIT(8),
124 AEQRX_REG_BANK_1 = 0xe0,
125 AEQRX_SLCAL0_CTRL0 = 0x82,
126 AEQRX_SLCAL1_CTRL0 = 0x86,
127
128 OOB_REG_BANK = 0x150,
129 OOB1_REG_BANK = 0x160,
130 OOB_CTRL1 = 0x80,
131 OOB_CTRL1_BURST_MAX_MASK = 0xf,
132 OOB_CTRL1_BURST_MAX_SHIFT = 12,
133 OOB_CTRL1_BURST_MIN_MASK = 0xf,
134 OOB_CTRL1_BURST_MIN_SHIFT = 8,
135 OOB_CTRL1_WAKE_IDLE_MAX_MASK = 0xf,
136 OOB_CTRL1_WAKE_IDLE_MAX_SHIFT = 4,
137 OOB_CTRL1_WAKE_IDLE_MIN_MASK = 0xf,
138 OOB_CTRL1_WAKE_IDLE_MIN_SHIFT = 0,
139 OOB_CTRL2 = 0x81,
140 OOB_CTRL2_SEL_ENA_SHIFT = 15,
141 OOB_CTRL2_SEL_ENA_RC_SHIFT = 14,
142 OOB_CTRL2_RESET_IDLE_MAX_MASK = 0x3f,
143 OOB_CTRL2_RESET_IDLE_MAX_SHIFT = 8,
144 OOB_CTRL2_BURST_CNT_MASK = 0x3,
145 OOB_CTRL2_BURST_CNT_SHIFT = 6,
146 OOB_CTRL2_RESET_IDLE_MIN_MASK = 0x3f,
147 OOB_CTRL2_RESET_IDLE_MIN_SHIFT = 0,
148
149 TXPMD_REG_BANK = 0x1a0,
150 TXPMD_CONTROL1 = 0x81,
151 TXPMD_CONTROL1_TX_SSC_EN_FRC = BIT(0),
152 TXPMD_CONTROL1_TX_SSC_EN_FRC_VAL = BIT(1),
153 TXPMD_TX_FREQ_CTRL_CONTROL1 = 0x82,
154 TXPMD_TX_FREQ_CTRL_CONTROL2 = 0x83,
155 TXPMD_TX_FREQ_CTRL_CONTROL2_FMIN_MASK = 0x3ff,
156 TXPMD_TX_FREQ_CTRL_CONTROL3 = 0x84,
157 TXPMD_TX_FREQ_CTRL_CONTROL3_FMAX_MASK = 0x3ff,
158
159 RXPMD_REG_BANK = 0x1c0,
160 RXPMD_RX_CDR_CONTROL1 = 0x81,
161 RXPMD_RX_PPM_VAL_MASK = 0x1ff,
162 RXPMD_RXPMD_EN_FRC = BIT(12),
163 RXPMD_RXPMD_EN_FRC_VAL = BIT(13),
164 RXPMD_RX_CDR_CDR_PROP_BW = 0x82,
165 RXPMD_G_CDR_PROP_BW_MASK = 0x7,
166 RXPMD_G1_CDR_PROP_BW_SHIFT = 0,
167 RXPMD_G2_CDR_PROP_BW_SHIFT = 3,
168 RXPMD_G3_CDR_PROB_BW_SHIFT = 6,
169 RXPMD_RX_CDR_CDR_ACQ_INTEG_BW = 0x83,
170 RXPMD_G_CDR_ACQ_INT_BW_MASK = 0x7,
171 RXPMD_G1_CDR_ACQ_INT_BW_SHIFT = 0,
172 RXPMD_G2_CDR_ACQ_INT_BW_SHIFT = 3,
173 RXPMD_G3_CDR_ACQ_INT_BW_SHIFT = 6,
174 RXPMD_RX_CDR_CDR_LOCK_INTEG_BW = 0x84,
175 RXPMD_G_CDR_LOCK_INT_BW_MASK = 0x7,
176 RXPMD_G1_CDR_LOCK_INT_BW_SHIFT = 0,
177 RXPMD_G2_CDR_LOCK_INT_BW_SHIFT = 3,
178 RXPMD_G3_CDR_LOCK_INT_BW_SHIFT = 6,
179 RXPMD_RX_FREQ_MON_CONTROL1 = 0x87,
180 RXPMD_MON_CORRECT_EN = BIT(8),
181 RXPMD_MON_MARGIN_VAL_MASK = 0xff,
182 };
183
184 enum sata_phy_ctrl_regs {
185 PHY_CTRL_1 = 0x0,
186 PHY_CTRL_1_RESET = BIT(0),
187 };
188
189 static inline void __iomem *brcm_sata_pcb_base(struct brcm_sata_port *port)
190 {
191 struct brcm_sata_phy *priv = port->phy_priv;
192 u32 size = 0;
193
194 switch (priv->version) {
195 case BRCM_SATA_PHY_STB_16NM:
196 case BRCM_SATA_PHY_STB_28NM:
197 case BRCM_SATA_PHY_IPROC_NS2:
198 case BRCM_SATA_PHY_DSL_28NM:
199 size = SATA_PCB_REG_28NM_SPACE_SIZE;
200 break;
201 case BRCM_SATA_PHY_STB_40NM:
202 size = SATA_PCB_REG_40NM_SPACE_SIZE;
203 break;
204 default:
205 dev_err(priv->dev, "invalid phy version\n");
206 break;
207 }
208
209 return priv->phy_base + (port->portnum * size);
210 }
211
212 static inline void __iomem *brcm_sata_ctrl_base(struct brcm_sata_port *port)
213 {
214 struct brcm_sata_phy *priv = port->phy_priv;
215 u32 size = 0;
216
217 switch (priv->version) {
218 case BRCM_SATA_PHY_IPROC_NS2:
219 size = SATA_PHY_CTRL_REG_28NM_SPACE_SIZE;
220 break;
221 default:
222 dev_err(priv->dev, "invalid phy version\n");
223 break;
224 }
225
226 return priv->ctrl_base + (port->portnum * size);
227 }
228
229 static void brcm_sata_phy_wr(void __iomem *pcb_base, u32 bank,
230 u32 ofs, u32 msk, u32 value)
231 {
232 u32 tmp;
233
234 writel(bank, pcb_base + SATA_PCB_BANK_OFFSET);
235 tmp = readl(pcb_base + SATA_PCB_REG_OFFSET(ofs));
236 tmp = (tmp & msk) | value;
237 writel(tmp, pcb_base + SATA_PCB_REG_OFFSET(ofs));
238 }
239
240 static u32 brcm_sata_phy_rd(void __iomem *pcb_base, u32 bank, u32 ofs)
241 {
242 writel(bank, pcb_base + SATA_PCB_BANK_OFFSET);
243 return readl(pcb_base + SATA_PCB_REG_OFFSET(ofs));
244 }
245
246 /* These defaults were characterized by H/W group */
247 #define STB_FMIN_VAL_DEFAULT 0x3df
248 #define STB_FMAX_VAL_DEFAULT 0x3df
249 #define STB_FMAX_VAL_SSC 0x83
250
251 static void brcm_stb_sata_ssc_init(struct brcm_sata_port *port)
252 {
253 void __iomem *base = brcm_sata_pcb_base(port);
254 struct brcm_sata_phy *priv = port->phy_priv;
255 u32 tmp;
256
257 /* override the TX spread spectrum setting */
258 tmp = TXPMD_CONTROL1_TX_SSC_EN_FRC_VAL | TXPMD_CONTROL1_TX_SSC_EN_FRC;
259 brcm_sata_phy_wr(base, TXPMD_REG_BANK, TXPMD_CONTROL1, ~tmp, tmp);
260
261 /* set fixed min freq */
262 brcm_sata_phy_wr(base, TXPMD_REG_BANK, TXPMD_TX_FREQ_CTRL_CONTROL2,
263 ~TXPMD_TX_FREQ_CTRL_CONTROL2_FMIN_MASK,
264 STB_FMIN_VAL_DEFAULT);
265
266 /* set fixed max freq depending on SSC config */
267 if (port->ssc_en) {
268 dev_info(priv->dev, "enabling SSC on port%d\n", port->portnum);
269 tmp = STB_FMAX_VAL_SSC;
270 } else {
271 tmp = STB_FMAX_VAL_DEFAULT;
272 }
273
274 brcm_sata_phy_wr(base, TXPMD_REG_BANK, TXPMD_TX_FREQ_CTRL_CONTROL3,
275 ~TXPMD_TX_FREQ_CTRL_CONTROL3_FMAX_MASK, tmp);
276 }
277
278 #define AEQ_FRC_EQ_VAL_SHIFT 2
279 #define AEQ_FRC_EQ_VAL_MASK 0x3f
280
281 static int brcm_stb_sata_rxaeq_init(struct brcm_sata_port *port)
282 {
283 void __iomem *base = brcm_sata_pcb_base(port);
284 u32 tmp = 0, reg = 0;
285
286 switch (port->rxaeq_mode) {
287 case RXAEQ_MODE_OFF:
288 return 0;
289
290 case RXAEQ_MODE_AUTO:
291 reg = AEQ_CONTROL1;
292 tmp = AEQ_CONTROL1_ENABLE | AEQ_CONTROL1_FREEZE;
293 break;
294
295 case RXAEQ_MODE_MANUAL:
296 reg = AEQ_FRC_EQ;
297 tmp = AEQ_FRC_EQ_FORCE | AEQ_FRC_EQ_FORCE_VAL;
298 if (port->rxaeq_val > AEQ_FRC_EQ_VAL_MASK)
299 return -EINVAL;
300 tmp |= port->rxaeq_val << AEQ_FRC_EQ_VAL_SHIFT;
301 break;
302 }
303
304 brcm_sata_phy_wr(base, AEQRX_REG_BANK_0, reg, ~tmp, tmp);
305 brcm_sata_phy_wr(base, AEQRX_REG_BANK_1, reg, ~tmp, tmp);
306
307 return 0;
308 }
309
310 static int brcm_stb_sata_init(struct brcm_sata_port *port)
311 {
312 brcm_stb_sata_ssc_init(port);
313
314 return brcm_stb_sata_rxaeq_init(port);
315 }
316
317 static int brcm_stb_sata_16nm_ssc_init(struct brcm_sata_port *port)
318 {
319 void __iomem *base = brcm_sata_pcb_base(port);
320 u32 tmp, value;
321
322 /* Reduce CP tail current to 1/16th of its default value */
323 brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL6, 0, 0x141);
324
325 /* Turn off CP tail current boost */
326 brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL8, 0, 0xc006);
327
328 /* Set a specific AEQ equalizer value */
329 tmp = AEQ_FRC_EQ_FORCE_VAL | AEQ_FRC_EQ_FORCE;
330 brcm_sata_phy_wr(base, AEQRX_REG_BANK_0, AEQ_FRC_EQ,
331 ~(tmp | AEQ_RFZ_FRC_VAL |
332 AEQ_FRC_EQ_VAL_MASK << AEQ_FRC_EQ_VAL_SHIFT),
333 tmp | 32 << AEQ_FRC_EQ_VAL_SHIFT);
334
335 /* Set RX PPM val center frequency */
336 if (port->ssc_en)
337 value = 0x52;
338 else
339 value = 0;
340 brcm_sata_phy_wr(base, RXPMD_REG_BANK, RXPMD_RX_CDR_CONTROL1,
341 ~RXPMD_RX_PPM_VAL_MASK, value);
342
343 /* Set proportional loop bandwith Gen1/2/3 */
344 tmp = RXPMD_G_CDR_PROP_BW_MASK << RXPMD_G1_CDR_PROP_BW_SHIFT |
345 RXPMD_G_CDR_PROP_BW_MASK << RXPMD_G2_CDR_PROP_BW_SHIFT |
346 RXPMD_G_CDR_PROP_BW_MASK << RXPMD_G3_CDR_PROB_BW_SHIFT;
347 if (port->ssc_en)
348 value = 2 << RXPMD_G1_CDR_PROP_BW_SHIFT |
349 2 << RXPMD_G2_CDR_PROP_BW_SHIFT |
350 2 << RXPMD_G3_CDR_PROB_BW_SHIFT;
351 else
352 value = 1 << RXPMD_G1_CDR_PROP_BW_SHIFT |
353 1 << RXPMD_G2_CDR_PROP_BW_SHIFT |
354 1 << RXPMD_G3_CDR_PROB_BW_SHIFT;
355 brcm_sata_phy_wr(base, RXPMD_REG_BANK, RXPMD_RX_CDR_CDR_PROP_BW, ~tmp,
356 value);
357
358 /* Set CDR integral loop acquisition bandwidth for Gen1/2/3 */
359 tmp = RXPMD_G_CDR_ACQ_INT_BW_MASK << RXPMD_G1_CDR_ACQ_INT_BW_SHIFT |
360 RXPMD_G_CDR_ACQ_INT_BW_MASK << RXPMD_G2_CDR_ACQ_INT_BW_SHIFT |
361 RXPMD_G_CDR_ACQ_INT_BW_MASK << RXPMD_G3_CDR_ACQ_INT_BW_SHIFT;
362 if (port->ssc_en)
363 value = 1 << RXPMD_G1_CDR_ACQ_INT_BW_SHIFT |
364 1 << RXPMD_G2_CDR_ACQ_INT_BW_SHIFT |
365 1 << RXPMD_G3_CDR_ACQ_INT_BW_SHIFT;
366 else
367 value = 0;
368 brcm_sata_phy_wr(base, RXPMD_REG_BANK, RXPMD_RX_CDR_CDR_ACQ_INTEG_BW,
369 ~tmp, value);
370
371 /* Set CDR integral loop locking bandwidth to 1 for Gen 1/2/3 */
372 tmp = RXPMD_G_CDR_LOCK_INT_BW_MASK << RXPMD_G1_CDR_LOCK_INT_BW_SHIFT |
373 RXPMD_G_CDR_LOCK_INT_BW_MASK << RXPMD_G2_CDR_LOCK_INT_BW_SHIFT |
374 RXPMD_G_CDR_LOCK_INT_BW_MASK << RXPMD_G3_CDR_LOCK_INT_BW_SHIFT;
375 if (port->ssc_en)
376 value = 1 << RXPMD_G1_CDR_LOCK_INT_BW_SHIFT |
377 1 << RXPMD_G2_CDR_LOCK_INT_BW_SHIFT |
378 1 << RXPMD_G3_CDR_LOCK_INT_BW_SHIFT;
379 else
380 value = 0;
381 brcm_sata_phy_wr(base, RXPMD_REG_BANK, RXPMD_RX_CDR_CDR_LOCK_INTEG_BW,
382 ~tmp, value);
383
384 /* Set no guard band and clamp CDR */
385 tmp = RXPMD_MON_CORRECT_EN | RXPMD_MON_MARGIN_VAL_MASK;
386 if (port->ssc_en)
387 value = 0x51;
388 else
389 value = 0;
390 brcm_sata_phy_wr(base, RXPMD_REG_BANK, RXPMD_RX_FREQ_MON_CONTROL1,
391 ~tmp, RXPMD_MON_CORRECT_EN | value);
392
393 /* Turn on/off SSC */
394 brcm_sata_phy_wr(base, TX_REG_BANK, TX_ACTRL5, ~TX_ACTRL5_SSC_EN,
395 port->ssc_en ? TX_ACTRL5_SSC_EN : 0);
396
397 return 0;
398 }
399
400 static int brcm_stb_sata_16nm_init(struct brcm_sata_port *port)
401 {
402 return brcm_stb_sata_16nm_ssc_init(port);
403 }
404
405 /* NS2 SATA PLL1 defaults were characterized by H/W group */
406 #define NS2_PLL1_ACTRL2_MAGIC 0x1df8
407 #define NS2_PLL1_ACTRL3_MAGIC 0x2b00
408 #define NS2_PLL1_ACTRL4_MAGIC 0x8824
409
410 static int brcm_ns2_sata_init(struct brcm_sata_port *port)
411 {
412 int try;
413 unsigned int val;
414 void __iomem *base = brcm_sata_pcb_base(port);
415 void __iomem *ctrl_base = brcm_sata_ctrl_base(port);
416 struct device *dev = port->phy_priv->dev;
417
418 /* Configure OOB control */
419 val = 0x0;
420 val |= (0xc << OOB_CTRL1_BURST_MAX_SHIFT);
421 val |= (0x4 << OOB_CTRL1_BURST_MIN_SHIFT);
422 val |= (0x9 << OOB_CTRL1_WAKE_IDLE_MAX_SHIFT);
423 val |= (0x3 << OOB_CTRL1_WAKE_IDLE_MIN_SHIFT);
424 brcm_sata_phy_wr(base, OOB_REG_BANK, OOB_CTRL1, 0x0, val);
425 val = 0x0;
426 val |= (0x1b << OOB_CTRL2_RESET_IDLE_MAX_SHIFT);
427 val |= (0x2 << OOB_CTRL2_BURST_CNT_SHIFT);
428 val |= (0x9 << OOB_CTRL2_RESET_IDLE_MIN_SHIFT);
429 brcm_sata_phy_wr(base, OOB_REG_BANK, OOB_CTRL2, 0x0, val);
430
431 /* Configure PHY PLL register bank 1 */
432 val = NS2_PLL1_ACTRL2_MAGIC;
433 brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL2, 0x0, val);
434 val = NS2_PLL1_ACTRL3_MAGIC;
435 brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL3, 0x0, val);
436 val = NS2_PLL1_ACTRL4_MAGIC;
437 brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL4, 0x0, val);
438
439 /* Configure PHY BLOCK0 register bank */
440 /* Set oob_clk_sel to refclk/2 */
441 brcm_sata_phy_wr(base, BLOCK0_REG_BANK, BLOCK0_SPARE,
442 ~BLOCK0_SPARE_OOB_CLK_SEL_MASK,
443 BLOCK0_SPARE_OOB_CLK_SEL_REFBY2);
444
445 /* Strobe PHY reset using PHY control register */
446 writel(PHY_CTRL_1_RESET, ctrl_base + PHY_CTRL_1);
447 mdelay(1);
448 writel(0x0, ctrl_base + PHY_CTRL_1);
449 mdelay(1);
450
451 /* Wait for PHY PLL lock by polling pll_lock bit */
452 try = 50;
453 while (try) {
454 val = brcm_sata_phy_rd(base, BLOCK0_REG_BANK,
455 BLOCK0_XGXSSTATUS);
456 if (val & BLOCK0_XGXSSTATUS_PLL_LOCK)
457 break;
458 msleep(20);
459 try--;
460 }
461 if (!try) {
462 /* PLL did not lock; give up */
463 dev_err(dev, "port%d PLL did not lock\n", port->portnum);
464 return -ETIMEDOUT;
465 }
466
467 dev_dbg(dev, "port%d initialized\n", port->portnum);
468
469 return 0;
470 }
471
472 static int brcm_nsp_sata_init(struct brcm_sata_port *port)
473 {
474 struct brcm_sata_phy *priv = port->phy_priv;
475 struct device *dev = port->phy_priv->dev;
476 void __iomem *base = priv->phy_base;
477 unsigned int oob_bank;
478 unsigned int val, try;
479
480 /* Configure OOB control */
481 if (port->portnum == 0)
482 oob_bank = OOB_REG_BANK;
483 else if (port->portnum == 1)
484 oob_bank = OOB1_REG_BANK;
485 else
486 return -EINVAL;
487
488 val = 0x0;
489 val |= (0x0f << OOB_CTRL1_BURST_MAX_SHIFT);
490 val |= (0x06 << OOB_CTRL1_BURST_MIN_SHIFT);
491 val |= (0x0f << OOB_CTRL1_WAKE_IDLE_MAX_SHIFT);
492 val |= (0x06 << OOB_CTRL1_WAKE_IDLE_MIN_SHIFT);
493 brcm_sata_phy_wr(base, oob_bank, OOB_CTRL1, 0x0, val);
494
495 val = 0x0;
496 val |= (0x2e << OOB_CTRL2_RESET_IDLE_MAX_SHIFT);
497 val |= (0x02 << OOB_CTRL2_BURST_CNT_SHIFT);
498 val |= (0x16 << OOB_CTRL2_RESET_IDLE_MIN_SHIFT);
499 brcm_sata_phy_wr(base, oob_bank, OOB_CTRL2, 0x0, val);
500
501
502 brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_ACTRL2,
503 ~(PLL_ACTRL2_SELDIV_MASK << PLL_ACTRL2_SELDIV_SHIFT),
504 0x0c << PLL_ACTRL2_SELDIV_SHIFT);
505
506 brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_CAP_CONTROL,
507 0xff0, 0x4f0);
508
509 val = PLLCONTROL_0_FREQ_DET_RESTART | PLLCONTROL_0_FREQ_MONITOR;
510 brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
511 ~val, val);
512 val = PLLCONTROL_0_SEQ_START;
513 brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
514 ~val, 0);
515 mdelay(10);
516 brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
517 ~val, val);
518
519 /* Wait for pll_seq_done bit */
520 try = 50;
521 while (--try) {
522 val = brcm_sata_phy_rd(base, BLOCK0_REG_BANK,
523 BLOCK0_XGXSSTATUS);
524 if (val & BLOCK0_XGXSSTATUS_PLL_LOCK)
525 break;
526 msleep(20);
527 }
528 if (!try) {
529 /* PLL did not lock; give up */
530 dev_err(dev, "port%d PLL did not lock\n", port->portnum);
531 return -ETIMEDOUT;
532 }
533
534 dev_dbg(dev, "port%d initialized\n", port->portnum);
535
536 return 0;
537 }
538
539 /* SR PHY PLL0 registers */
540 #define SR_PLL0_ACTRL6_MAGIC 0xa
541
542 /* SR PHY PLL1 registers */
543 #define SR_PLL1_ACTRL2_MAGIC 0x32
544 #define SR_PLL1_ACTRL3_MAGIC 0x2
545 #define SR_PLL1_ACTRL4_MAGIC 0x3e8
546
547 static int brcm_sr_sata_init(struct brcm_sata_port *port)
548 {
549 struct brcm_sata_phy *priv = port->phy_priv;
550 struct device *dev = port->phy_priv->dev;
551 void __iomem *base = priv->phy_base;
552 unsigned int val, try;
553
554 /* Configure PHY PLL register bank 1 */
555 val = SR_PLL1_ACTRL2_MAGIC;
556 brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL2, 0x0, val);
557 val = SR_PLL1_ACTRL3_MAGIC;
558 brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL3, 0x0, val);
559 val = SR_PLL1_ACTRL4_MAGIC;
560 brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL4, 0x0, val);
561
562 /* Configure PHY PLL register bank 0 */
563 val = SR_PLL0_ACTRL6_MAGIC;
564 brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_ACTRL6, 0x0, val);
565
566 /* Wait for PHY PLL lock by polling pll_lock bit */
567 try = 50;
568 do {
569 val = brcm_sata_phy_rd(base, BLOCK0_REG_BANK,
570 BLOCK0_XGXSSTATUS);
571 if (val & BLOCK0_XGXSSTATUS_PLL_LOCK)
572 break;
573 msleep(20);
574 try--;
575 } while (try);
576
577 if ((val & BLOCK0_XGXSSTATUS_PLL_LOCK) == 0) {
578 /* PLL did not lock; give up */
579 dev_err(dev, "port%d PLL did not lock\n", port->portnum);
580 return -ETIMEDOUT;
581 }
582
583 /* Invert Tx polarity */
584 brcm_sata_phy_wr(base, TX_REG_BANK, TX_ACTRL0,
585 ~TX_ACTRL0_TXPOL_FLIP, TX_ACTRL0_TXPOL_FLIP);
586
587 /* Configure OOB control to handle 100MHz reference clock */
588 val = ((0xc << OOB_CTRL1_BURST_MAX_SHIFT) |
589 (0x4 << OOB_CTRL1_BURST_MIN_SHIFT) |
590 (0x8 << OOB_CTRL1_WAKE_IDLE_MAX_SHIFT) |
591 (0x3 << OOB_CTRL1_WAKE_IDLE_MIN_SHIFT));
592 brcm_sata_phy_wr(base, OOB_REG_BANK, OOB_CTRL1, 0x0, val);
593 val = ((0x1b << OOB_CTRL2_RESET_IDLE_MAX_SHIFT) |
594 (0x2 << OOB_CTRL2_BURST_CNT_SHIFT) |
595 (0x9 << OOB_CTRL2_RESET_IDLE_MIN_SHIFT));
596 brcm_sata_phy_wr(base, OOB_REG_BANK, OOB_CTRL2, 0x0, val);
597
598 return 0;
599 }
600
601 static int brcm_dsl_sata_init(struct brcm_sata_port *port)
602 {
603 void __iomem *base = brcm_sata_pcb_base(port);
604 struct device *dev = port->phy_priv->dev;
605 unsigned int try;
606 u32 tmp;
607
608 brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL7, 0, 0x873);
609
610 brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL6, 0, 0xc000);
611
612 brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
613 0, 0x3089);
614 usleep_range(1000, 2000);
615
616 brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
617 0, 0x3088);
618 usleep_range(1000, 2000);
619
620 brcm_sata_phy_wr(base, AEQRX_REG_BANK_1, AEQRX_SLCAL0_CTRL0,
621 0, 0x3000);
622
623 brcm_sata_phy_wr(base, AEQRX_REG_BANK_1, AEQRX_SLCAL1_CTRL0,
624 0, 0x3000);
625 usleep_range(1000, 2000);
626
627 brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_CAP_CHARGE_TIME, 0, 0x32);
628
629 brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_VCO_CAL_THRESH, 0, 0xa);
630
631 brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_FREQ_DET_TIME, 0, 0x64);
632 usleep_range(1000, 2000);
633
634 /* Acquire PLL lock */
635 try = 50;
636 while (try) {
637 tmp = brcm_sata_phy_rd(base, BLOCK0_REG_BANK,
638 BLOCK0_XGXSSTATUS);
639 if (tmp & BLOCK0_XGXSSTATUS_PLL_LOCK)
640 break;
641 msleep(20);
642 try--;
643 };
644
645 if (!try) {
646 /* PLL did not lock; give up */
647 dev_err(dev, "port%d PLL did not lock\n", port->portnum);
648 return -ETIMEDOUT;
649 }
650
651 dev_dbg(dev, "port%d initialized\n", port->portnum);
652
653 return 0;
654 }
655
656 static int brcm_sata_phy_init(struct phy *phy)
657 {
658 int rc;
659 struct brcm_sata_port *port = phy_get_drvdata(phy);
660
661 switch (port->phy_priv->version) {
662 case BRCM_SATA_PHY_STB_16NM:
663 rc = brcm_stb_sata_16nm_init(port);
664 break;
665 case BRCM_SATA_PHY_STB_28NM:
666 case BRCM_SATA_PHY_STB_40NM:
667 rc = brcm_stb_sata_init(port);
668 break;
669 case BRCM_SATA_PHY_IPROC_NS2:
670 rc = brcm_ns2_sata_init(port);
671 break;
672 case BRCM_SATA_PHY_IPROC_NSP:
673 rc = brcm_nsp_sata_init(port);
674 break;
675 case BRCM_SATA_PHY_IPROC_SR:
676 rc = brcm_sr_sata_init(port);
677 break;
678 case BRCM_SATA_PHY_DSL_28NM:
679 rc = brcm_dsl_sata_init(port);
680 break;
681 default:
682 rc = -ENODEV;
683 }
684
685 return rc;
686 }
687
688 static void brcm_stb_sata_calibrate(struct brcm_sata_port *port)
689 {
690 void __iomem *base = brcm_sata_pcb_base(port);
691 u32 tmp = BIT(8);
692
693 brcm_sata_phy_wr(base, RXPMD_REG_BANK, RXPMD_RX_FREQ_MON_CONTROL1,
694 ~tmp, tmp);
695 }
696
697 static int brcm_sata_phy_calibrate(struct phy *phy)
698 {
699 struct brcm_sata_port *port = phy_get_drvdata(phy);
700 int rc = -EOPNOTSUPP;
701
702 switch (port->phy_priv->version) {
703 case BRCM_SATA_PHY_STB_28NM:
704 case BRCM_SATA_PHY_STB_40NM:
705 brcm_stb_sata_calibrate(port);
706 rc = 0;
707 break;
708 default:
709 break;
710 }
711
712 return rc;
713 }
714
715 static const struct phy_ops phy_ops = {
716 .init = brcm_sata_phy_init,
717 .calibrate = brcm_sata_phy_calibrate,
718 .owner = THIS_MODULE,
719 };
720
721 static const struct of_device_id brcm_sata_phy_of_match[] = {
722 { .compatible = "brcm,bcm7216-sata-phy",
723 .data = (void *)BRCM_SATA_PHY_STB_16NM },
724 { .compatible = "brcm,bcm7445-sata-phy",
725 .data = (void *)BRCM_SATA_PHY_STB_28NM },
726 { .compatible = "brcm,bcm7425-sata-phy",
727 .data = (void *)BRCM_SATA_PHY_STB_40NM },
728 { .compatible = "brcm,iproc-ns2-sata-phy",
729 .data = (void *)BRCM_SATA_PHY_IPROC_NS2 },
730 { .compatible = "brcm,iproc-nsp-sata-phy",
731 .data = (void *)BRCM_SATA_PHY_IPROC_NSP },
732 { .compatible = "brcm,iproc-sr-sata-phy",
733 .data = (void *)BRCM_SATA_PHY_IPROC_SR },
734 { .compatible = "brcm,bcm63138-sata-phy",
735 .data = (void *)BRCM_SATA_PHY_DSL_28NM },
736 {},
737 };
738 MODULE_DEVICE_TABLE(of, brcm_sata_phy_of_match);
739
740 static int brcm_sata_phy_probe(struct platform_device *pdev)
741 {
742 const char *rxaeq_mode;
743 struct device *dev = &pdev->dev;
744 struct device_node *dn = dev->of_node, *child;
745 const struct of_device_id *of_id;
746 struct brcm_sata_phy *priv;
747 struct resource *res;
748 struct phy_provider *provider;
749 int ret, count = 0;
750
751 if (of_get_child_count(dn) == 0)
752 return -ENODEV;
753
754 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
755 if (!priv)
756 return -ENOMEM;
757 dev_set_drvdata(dev, priv);
758 priv->dev = dev;
759
760 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
761 priv->phy_base = devm_ioremap_resource(dev, res);
762 if (IS_ERR(priv->phy_base))
763 return PTR_ERR(priv->phy_base);
764
765 of_id = of_match_node(brcm_sata_phy_of_match, dn);
766 if (of_id)
767 priv->version = (enum brcm_sata_phy_version)of_id->data;
768 else
769 priv->version = BRCM_SATA_PHY_STB_28NM;
770
771 if (priv->version == BRCM_SATA_PHY_IPROC_NS2) {
772 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
773 "phy-ctrl");
774 priv->ctrl_base = devm_ioremap_resource(dev, res);
775 if (IS_ERR(priv->ctrl_base))
776 return PTR_ERR(priv->ctrl_base);
777 }
778
779 for_each_available_child_of_node(dn, child) {
780 unsigned int id;
781 struct brcm_sata_port *port;
782
783 if (of_property_read_u32(child, "reg", &id)) {
784 dev_err(dev, "missing reg property in node %pOFn\n",
785 child);
786 ret = -EINVAL;
787 goto put_child;
788 }
789
790 if (id >= MAX_PORTS) {
791 dev_err(dev, "invalid reg: %u\n", id);
792 ret = -EINVAL;
793 goto put_child;
794 }
795 if (priv->phys[id].phy) {
796 dev_err(dev, "already registered port %u\n", id);
797 ret = -EINVAL;
798 goto put_child;
799 }
800
801 port = &priv->phys[id];
802 port->portnum = id;
803 port->phy_priv = priv;
804 port->phy = devm_phy_create(dev, child, &phy_ops);
805 port->rxaeq_mode = RXAEQ_MODE_OFF;
806 if (!of_property_read_string(child, "brcm,rxaeq-mode",
807 &rxaeq_mode))
808 port->rxaeq_mode = rxaeq_to_val(rxaeq_mode);
809 if (port->rxaeq_mode == RXAEQ_MODE_MANUAL)
810 of_property_read_u32(child, "brcm,rxaeq-value",
811 &port->rxaeq_val);
812 port->ssc_en = of_property_read_bool(child, "brcm,enable-ssc");
813 if (IS_ERR(port->phy)) {
814 dev_err(dev, "failed to create PHY\n");
815 ret = PTR_ERR(port->phy);
816 goto put_child;
817 }
818
819 phy_set_drvdata(port->phy, port);
820 count++;
821 }
822
823 provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
824 if (IS_ERR(provider)) {
825 dev_err(dev, "could not register PHY provider\n");
826 return PTR_ERR(provider);
827 }
828
829 dev_info(dev, "registered %d port(s)\n", count);
830
831 return 0;
832 put_child:
833 of_node_put(child);
834 return ret;
835 }
836
837 static struct platform_driver brcm_sata_phy_driver = {
838 .probe = brcm_sata_phy_probe,
839 .driver = {
840 .of_match_table = brcm_sata_phy_of_match,
841 .name = "brcm-sata-phy",
842 }
843 };
844 module_platform_driver(brcm_sata_phy_driver);
845
846 MODULE_DESCRIPTION("Broadcom SATA PHY driver");
847 MODULE_LICENSE("GPL");
848 MODULE_AUTHOR("Marc Carino");
849 MODULE_AUTHOR("Brian Norris");
850 MODULE_ALIAS("platform:phy-brcm-sata");
Linux with added FPC-III support