1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2015, Linux Foundation. All rights reserved.
6 #include "phy-qcom-ufs-qmp-14nm.h"
8 #define UFS_PHY_NAME "ufs_phy_qmp_14nm"
9 #define UFS_PHY_VDDA_PHY_UV (925000)
12 int ufs_qcom_phy_qmp_14nm_phy_calibrate(struct ufs_qcom_phy
*ufs_qcom_phy
,
15 int tbl_size_A
= ARRAY_SIZE(phy_cal_table_rate_A
);
16 int tbl_size_B
= ARRAY_SIZE(phy_cal_table_rate_B
);
19 err
= ufs_qcom_phy_calibrate(ufs_qcom_phy
, phy_cal_table_rate_A
,
20 tbl_size_A
, phy_cal_table_rate_B
, tbl_size_B
, is_rate_B
);
23 dev_err(ufs_qcom_phy
->dev
,
24 "%s: ufs_qcom_phy_calibrate() failed %d\n",
30 void ufs_qcom_phy_qmp_14nm_advertise_quirks(struct ufs_qcom_phy
*phy_common
)
33 UFS_QCOM_PHY_QUIRK_HIBERN8_EXIT_AFTER_PHY_PWR_COLLAPSE
;
37 int ufs_qcom_phy_qmp_14nm_set_mode(struct phy
*generic_phy
,
38 enum phy_mode mode
, int submode
)
40 struct ufs_qcom_phy
*phy_common
= get_ufs_qcom_phy(generic_phy
);
42 phy_common
->mode
= PHY_MODE_INVALID
;
45 phy_common
->mode
= mode
;
51 void ufs_qcom_phy_qmp_14nm_power_control(struct ufs_qcom_phy
*phy
, bool val
)
53 writel_relaxed(val
? 0x1 : 0x0, phy
->mmio
+ UFS_PHY_POWER_DOWN_CONTROL
);
55 * Before any transactions involving PHY, ensure PHY knows
56 * that it's analog rail is powered ON (or OFF).
62 void ufs_qcom_phy_qmp_14nm_set_tx_lane_enable(struct ufs_qcom_phy
*phy
, u32 val
)
65 * 14nm PHY does not have TX_LANE_ENABLE register.
66 * Implement this function so as not to propagate error to caller.
70 static inline void ufs_qcom_phy_qmp_14nm_start_serdes(struct ufs_qcom_phy
*phy
)
74 tmp
= readl_relaxed(phy
->mmio
+ UFS_PHY_PHY_START
);
75 tmp
&= ~MASK_SERDES_START
;
76 tmp
|= (1 << OFFSET_SERDES_START
);
77 writel_relaxed(tmp
, phy
->mmio
+ UFS_PHY_PHY_START
);
78 /* Ensure register value is committed */
82 static int ufs_qcom_phy_qmp_14nm_is_pcs_ready(struct ufs_qcom_phy
*phy_common
)
87 err
= readl_poll_timeout(phy_common
->mmio
+ UFS_PHY_PCS_READY_STATUS
,
88 val
, (val
& MASK_PCS_READY
), 10, 1000000);
90 dev_err(phy_common
->dev
, "%s: poll for pcs failed err = %d\n",
95 static const struct phy_ops ufs_qcom_phy_qmp_14nm_phy_ops
= {
96 .power_on
= ufs_qcom_phy_power_on
,
97 .power_off
= ufs_qcom_phy_power_off
,
98 .set_mode
= ufs_qcom_phy_qmp_14nm_set_mode
,
102 static struct ufs_qcom_phy_specific_ops phy_14nm_ops
= {
103 .calibrate
= ufs_qcom_phy_qmp_14nm_phy_calibrate
,
104 .start_serdes
= ufs_qcom_phy_qmp_14nm_start_serdes
,
105 .is_physical_coding_sublayer_ready
= ufs_qcom_phy_qmp_14nm_is_pcs_ready
,
106 .set_tx_lane_enable
= ufs_qcom_phy_qmp_14nm_set_tx_lane_enable
,
107 .power_control
= ufs_qcom_phy_qmp_14nm_power_control
,
110 static int ufs_qcom_phy_qmp_14nm_probe(struct platform_device
*pdev
)
112 struct device
*dev
= &pdev
->dev
;
113 struct phy
*generic_phy
;
114 struct ufs_qcom_phy_qmp_14nm
*phy
;
115 struct ufs_qcom_phy
*phy_common
;
118 phy
= devm_kzalloc(dev
, sizeof(*phy
), GFP_KERNEL
);
123 phy_common
= &phy
->common_cfg
;
125 generic_phy
= ufs_qcom_phy_generic_probe(pdev
, phy_common
,
126 &ufs_qcom_phy_qmp_14nm_phy_ops
, &phy_14nm_ops
);
133 err
= ufs_qcom_phy_init_clks(phy_common
);
137 err
= ufs_qcom_phy_init_vregulators(phy_common
);
141 phy_common
->vdda_phy
.max_uV
= UFS_PHY_VDDA_PHY_UV
;
142 phy_common
->vdda_phy
.min_uV
= UFS_PHY_VDDA_PHY_UV
;
144 ufs_qcom_phy_qmp_14nm_advertise_quirks(phy_common
);
146 phy_set_drvdata(generic_phy
, phy
);
148 strlcpy(phy_common
->name
, UFS_PHY_NAME
, sizeof(phy_common
->name
));
154 static const struct of_device_id ufs_qcom_phy_qmp_14nm_of_match
[] = {
155 {.compatible
= "qcom,ufs-phy-qmp-14nm"},
156 {.compatible
= "qcom,msm8996-ufs-phy-qmp-14nm"},
159 MODULE_DEVICE_TABLE(of
, ufs_qcom_phy_qmp_14nm_of_match
);
161 static struct platform_driver ufs_qcom_phy_qmp_14nm_driver
= {
162 .probe
= ufs_qcom_phy_qmp_14nm_probe
,
164 .of_match_table
= ufs_qcom_phy_qmp_14nm_of_match
,
165 .name
= "ufs_qcom_phy_qmp_14nm",
169 module_platform_driver(ufs_qcom_phy_qmp_14nm_driver
);
171 MODULE_DESCRIPTION("Universal Flash Storage (UFS) QCOM PHY QMP 14nm");
172 MODULE_LICENSE("GPL v2");