drivers/phy/qualcomm/phy-qcom-ufs-qmp-20nm.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2013-2015, Linux Foundation. All rights reserved.
   4  */
   5
   6 #include "phy-qcom-ufs-qmp-20nm.h"
   7
   8 #define UFS_PHY_NAME "ufs_phy_qmp_20nm"
   9
  10 static
  11 int ufs_qcom_phy_qmp_20nm_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy,
  12                                         bool is_rate_B)
  13 {
  14         struct ufs_qcom_phy_calibration *tbl_A, *tbl_B;
  15         int tbl_size_A, tbl_size_B;
  16         u8 major = ufs_qcom_phy->host_ctrl_rev_major;
  17         u16 minor = ufs_qcom_phy->host_ctrl_rev_minor;
  18         u16 step = ufs_qcom_phy->host_ctrl_rev_step;
  19         int err;
  20
  21         if ((major == 0x1) && (minor == 0x002) && (step == 0x0000)) {
  22                 tbl_size_A = ARRAY_SIZE(phy_cal_table_rate_A_1_2_0);
  23                 tbl_A = phy_cal_table_rate_A_1_2_0;
  24         } else if ((major == 0x1) && (minor == 0x003) && (step == 0x0000)) {
  25                 tbl_size_A = ARRAY_SIZE(phy_cal_table_rate_A_1_3_0);
  26                 tbl_A = phy_cal_table_rate_A_1_3_0;
  27         } else {
  28                 dev_err(ufs_qcom_phy->dev, "%s: Unknown UFS-PHY version, no calibration values\n",
  29                         __func__);
  30                 err = -ENODEV;
  31                 goto out;
  32         }
  33
  34         tbl_size_B = ARRAY_SIZE(phy_cal_table_rate_B);
  35         tbl_B = phy_cal_table_rate_B;
  36
  37         err = ufs_qcom_phy_calibrate(ufs_qcom_phy, tbl_A, tbl_size_A,
  38                                                 tbl_B, tbl_size_B, is_rate_B);
  39
  40         if (err)
  41                 dev_err(ufs_qcom_phy->dev, "%s: ufs_qcom_phy_calibrate() failed %d\n",
  42                         __func__, err);
  43
  44 out:
  45         return err;
  46 }
  47
  48 static
  49 void ufs_qcom_phy_qmp_20nm_advertise_quirks(struct ufs_qcom_phy *phy_common)
  50 {
  51         phy_common->quirks =
  52                 UFS_QCOM_PHY_QUIRK_HIBERN8_EXIT_AFTER_PHY_PWR_COLLAPSE;
  53 }
  54
  55 static
  56 int ufs_qcom_phy_qmp_20nm_set_mode(struct phy *generic_phy,
  57                                    enum phy_mode mode, int submode)
  58 {
  59         struct ufs_qcom_phy *phy_common = get_ufs_qcom_phy(generic_phy);
  60
  61         phy_common->mode = PHY_MODE_INVALID;
  62
  63         if (mode > 0)
  64                 phy_common->mode = mode;
  65
  66         return 0;
  67 }
  68
  69 static
  70 void ufs_qcom_phy_qmp_20nm_power_control(struct ufs_qcom_phy *phy, bool val)
  71 {
  72         bool hibern8_exit_after_pwr_collapse = phy->quirks &
  73                 UFS_QCOM_PHY_QUIRK_HIBERN8_EXIT_AFTER_PHY_PWR_COLLAPSE;
  74
  75         if (val) {
  76                 writel_relaxed(0x1, phy->mmio + UFS_PHY_POWER_DOWN_CONTROL);
  77                 /*
  78                  * Before any transactions involving PHY, ensure PHY knows
  79                  * that it's analog rail is powered ON.
  80                  */
  81                 mb();
  82
  83                 if (hibern8_exit_after_pwr_collapse) {
  84                         /*
  85                          * Give atleast 1us delay after restoring PHY analog
  86                          * power.
  87                          */
  88                         usleep_range(1, 2);
  89                         writel_relaxed(0x0A, phy->mmio +
  90                                        QSERDES_COM_SYSCLK_EN_SEL_TXBAND);
  91                         writel_relaxed(0x08, phy->mmio +
  92                                        QSERDES_COM_SYSCLK_EN_SEL_TXBAND);
  93                         /*
  94                          * Make sure workaround is deactivated before proceeding
  95                          * with normal PHY operations.
  96                          */
  97                         mb();
  98                 }
  99         } else {
 100                 if (hibern8_exit_after_pwr_collapse) {
 101                         writel_relaxed(0x0A, phy->mmio +
 102                                        QSERDES_COM_SYSCLK_EN_SEL_TXBAND);
 103                         writel_relaxed(0x02, phy->mmio +
 104                                        QSERDES_COM_SYSCLK_EN_SEL_TXBAND);
 105                         /*
 106                          * Make sure that above workaround is activated before
 107                          * PHY analog power collapse.
 108                          */
 109                         mb();
 110                 }
 111
 112                 writel_relaxed(0x0, phy->mmio + UFS_PHY_POWER_DOWN_CONTROL);
 113                 /*
 114                  * ensure that PHY knows its PHY analog rail is going
 115                  * to be powered down
 116                  */
 117                 mb();
 118         }
 119 }
 120
 121 static
 122 void ufs_qcom_phy_qmp_20nm_set_tx_lane_enable(struct ufs_qcom_phy *phy, u32 val)
 123 {
 124         writel_relaxed(val & UFS_PHY_TX_LANE_ENABLE_MASK,
 125                         phy->mmio + UFS_PHY_TX_LANE_ENABLE);
 126         mb();
 127 }
 128
 129 static inline void ufs_qcom_phy_qmp_20nm_start_serdes(struct ufs_qcom_phy *phy)
 130 {
 131         u32 tmp;
 132
 133         tmp = readl_relaxed(phy->mmio + UFS_PHY_PHY_START);
 134         tmp &= ~MASK_SERDES_START;
 135         tmp |= (1 << OFFSET_SERDES_START);
 136         writel_relaxed(tmp, phy->mmio + UFS_PHY_PHY_START);
 137         mb();
 138 }
 139
 140 static int ufs_qcom_phy_qmp_20nm_is_pcs_ready(struct ufs_qcom_phy *phy_common)
 141 {
 142         int err = 0;
 143         u32 val;
 144
 145         err = readl_poll_timeout(phy_common->mmio + UFS_PHY_PCS_READY_STATUS,
 146                         val, (val & MASK_PCS_READY), 10, 1000000);
 147         if (err)
 148                 dev_err(phy_common->dev, "%s: poll for pcs failed err = %d\n",
 149                         __func__, err);
 150         return err;
 151 }
 152
 153 static const struct phy_ops ufs_qcom_phy_qmp_20nm_phy_ops = {
 154         .power_on       = ufs_qcom_phy_power_on,
 155         .power_off      = ufs_qcom_phy_power_off,
 156         .set_mode       = ufs_qcom_phy_qmp_20nm_set_mode,
 157         .owner          = THIS_MODULE,
 158 };
 159
 160 static struct ufs_qcom_phy_specific_ops phy_20nm_ops = {
 161         .calibrate              = ufs_qcom_phy_qmp_20nm_phy_calibrate,
 162         .start_serdes           = ufs_qcom_phy_qmp_20nm_start_serdes,
 163         .is_physical_coding_sublayer_ready = ufs_qcom_phy_qmp_20nm_is_pcs_ready,
 164         .set_tx_lane_enable     = ufs_qcom_phy_qmp_20nm_set_tx_lane_enable,
 165         .power_control          = ufs_qcom_phy_qmp_20nm_power_control,
 166 };
 167
 168 static int ufs_qcom_phy_qmp_20nm_probe(struct platform_device *pdev)
 169 {
 170         struct device *dev = &pdev->dev;
 171         struct phy *generic_phy;
 172         struct ufs_qcom_phy_qmp_20nm *phy;
 173         struct ufs_qcom_phy *phy_common;
 174         int err = 0;
 175
 176         phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
 177         if (!phy) {
 178                 err = -ENOMEM;
 179                 goto out;
 180         }
 181         phy_common = &phy->common_cfg;
 182
 183         generic_phy = ufs_qcom_phy_generic_probe(pdev, phy_common,
 184                                 &ufs_qcom_phy_qmp_20nm_phy_ops, &phy_20nm_ops);
 185
 186         if (!generic_phy) {
 187                 err = -EIO;
 188                 goto out;
 189         }
 190
 191         err = ufs_qcom_phy_init_clks(phy_common);
 192         if (err)
 193                 goto out;
 194
 195         err = ufs_qcom_phy_init_vregulators(phy_common);
 196         if (err)
 197                 goto out;
 198
 199         ufs_qcom_phy_qmp_20nm_advertise_quirks(phy_common);
 200
 201         phy_set_drvdata(generic_phy, phy);
 202
 203         strlcpy(phy_common->name, UFS_PHY_NAME, sizeof(phy_common->name));
 204
 205 out:
 206         return err;
 207 }
 208
 209 static const struct of_device_id ufs_qcom_phy_qmp_20nm_of_match[] = {
 210         {.compatible = "qcom,ufs-phy-qmp-20nm"},
 211         {},
 212 };
 213 MODULE_DEVICE_TABLE(of, ufs_qcom_phy_qmp_20nm_of_match);
 214
 215 static struct platform_driver ufs_qcom_phy_qmp_20nm_driver = {
 216         .probe = ufs_qcom_phy_qmp_20nm_probe,
 217         .driver = {
 218                 .of_match_table = ufs_qcom_phy_qmp_20nm_of_match,
 219                 .name = "ufs_qcom_phy_qmp_20nm",
 220         },
 221 };
 222
 223 module_platform_driver(ufs_qcom_phy_qmp_20nm_driver);
 224
 225 MODULE_DESCRIPTION("Universal Flash Storage (UFS) QCOM PHY QMP 20nm");
 226 MODULE_LICENSE("GPL v2");