1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
4 * Copyright (C) 2015 Google, Inc.
8 #include <linux/clk/tegra.h>
9 #include <linux/delay.h>
11 #include <linux/mailbox_client.h>
12 #include <linux/module.h>
14 #include <linux/phy/phy.h>
15 #include <linux/platform_device.h>
16 #include <linux/regulator/consumer.h>
17 #include <linux/reset.h>
18 #include <linux/slab.h>
20 #include <soc/tegra/fuse.h>
24 #define FUSE_SKU_CALIB_HS_CURR_LEVEL_PADX_SHIFT(x) \
25 ((x) ? (11 + ((x) - 1) * 6) : 0)
26 #define FUSE_SKU_CALIB_HS_CURR_LEVEL_PAD_MASK 0x3f
27 #define FUSE_SKU_CALIB_HS_TERM_RANGE_ADJ_SHIFT 7
28 #define FUSE_SKU_CALIB_HS_TERM_RANGE_ADJ_MASK 0xf
30 #define FUSE_USB_CALIB_EXT_RPD_CTRL_SHIFT 0
31 #define FUSE_USB_CALIB_EXT_RPD_CTRL_MASK 0x1f
33 #define XUSB_PADCTL_USB2_PAD_MUX 0x004
34 #define XUSB_PADCTL_USB2_PAD_MUX_HSIC_PAD_TRK_SHIFT 16
35 #define XUSB_PADCTL_USB2_PAD_MUX_HSIC_PAD_TRK_MASK 0x3
36 #define XUSB_PADCTL_USB2_PAD_MUX_HSIC_PAD_TRK_XUSB 0x1
37 #define XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_SHIFT 18
38 #define XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_MASK 0x3
39 #define XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_XUSB 0x1
41 #define XUSB_PADCTL_USB2_PORT_CAP 0x008
42 #define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_DISABLED(x) (0x0 << ((x) * 4))
43 #define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_HOST(x) (0x1 << ((x) * 4))
44 #define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_DEVICE(x) (0x2 << ((x) * 4))
45 #define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_OTG(x) (0x3 << ((x) * 4))
46 #define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_MASK(x) (0x3 << ((x) * 4))
48 #define XUSB_PADCTL_SS_PORT_MAP 0x014
49 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(x) (1 << (((x) * 5) + 4))
50 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_SHIFT(x) ((x) * 5)
51 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_MASK(x) (0x7 << ((x) * 5))
52 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(x, v) (((v) & 0x7) << ((x) * 5))
53 #define XUSB_PADCTL_SS_PORT_MAP_PORT_DISABLED 0x7
55 #define XUSB_PADCTL_ELPG_PROGRAM1 0x024
56 #define XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_VCORE_DOWN (1 << 31)
57 #define XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 30)
58 #define XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN (1 << 29)
59 #define XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_VCORE_DOWN(x) (1 << (2 + (x) * 3))
60 #define XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY(x) \
62 #define XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN(x) (1 << ((x) * 3))
64 #define XUSB_PADCTL_USB3_PAD_MUX 0x028
65 #define XUSB_PADCTL_USB3_PAD_MUX_PCIE_IDDQ_DISABLE(x) (1 << (1 + (x)))
66 #define XUSB_PADCTL_USB3_PAD_MUX_SATA_IDDQ_DISABLE(x) (1 << (8 + (x)))
68 #define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADX_CTL0(x) (0x080 + (x) * 0x40)
69 #define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL0_ZIP (1 << 18)
70 #define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL0_ZIN (1 << 22)
72 #define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADX_CTL1(x) (0x084 + (x) * 0x40)
73 #define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_SHIFT 7
74 #define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_MASK 0x3
75 #define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_VAL 0x1
76 #define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_FIX18 (1 << 6)
78 #define XUSB_PADCTL_USB2_OTG_PADX_CTL0(x) (0x088 + (x) * 0x40)
79 #define XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD_ZI (1 << 29)
80 #define XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD2 (1 << 27)
81 #define XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD (1 << 26)
82 #define XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL_SHIFT 0
83 #define XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL_MASK 0x3f
85 #define XUSB_PADCTL_USB2_OTG_PADX_CTL1(x) (0x08c + (x) * 0x40)
86 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_RPD_CTRL_SHIFT 26
87 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_RPD_CTRL_MASK 0x1f
88 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ_SHIFT 3
89 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ_MASK 0xf
90 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR (1 << 2)
91 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DISC_OVRD (1 << 1)
92 #define XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_CHRP_OVRD (1 << 0)
94 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0 0x284
95 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_PD (1 << 11)
96 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_SHIFT 3
97 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_MASK 0x7
98 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_VAL 0x7
99 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_SHIFT 0
100 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_MASK 0x7
101 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_VAL 0x2
103 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1 0x288
104 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_PD_TRK (1 << 26)
105 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_SHIFT 19
106 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_MASK 0x7f
107 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_VAL 0x0a
108 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_SHIFT 12
109 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_MASK 0x7f
110 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_VAL 0x1e
112 #define XUSB_PADCTL_HSIC_PADX_CTL0(x) (0x300 + (x) * 0x20)
113 #define XUSB_PADCTL_HSIC_PAD_CTL0_RPU_STROBE (1 << 18)
114 #define XUSB_PADCTL_HSIC_PAD_CTL0_RPU_DATA1 (1 << 17)
115 #define XUSB_PADCTL_HSIC_PAD_CTL0_RPU_DATA0 (1 << 16)
116 #define XUSB_PADCTL_HSIC_PAD_CTL0_RPD_STROBE (1 << 15)
117 #define XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA1 (1 << 14)
118 #define XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA0 (1 << 13)
119 #define XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_STROBE (1 << 9)
120 #define XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_DATA1 (1 << 8)
121 #define XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_DATA0 (1 << 7)
122 #define XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_STROBE (1 << 6)
123 #define XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA1 (1 << 5)
124 #define XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA0 (1 << 4)
125 #define XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_STROBE (1 << 3)
126 #define XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_DATA1 (1 << 2)
127 #define XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_DATA0 (1 << 1)
129 #define XUSB_PADCTL_HSIC_PADX_CTL1(x) (0x304 + (x) * 0x20)
130 #define XUSB_PADCTL_HSIC_PAD_CTL1_TX_RTUNEP_SHIFT 0
131 #define XUSB_PADCTL_HSIC_PAD_CTL1_TX_RTUNEP_MASK 0xf
133 #define XUSB_PADCTL_HSIC_PADX_CTL2(x) (0x308 + (x) * 0x20)
134 #define XUSB_PADCTL_HSIC_PAD_CTL2_RX_STROBE_TRIM_SHIFT 8
135 #define XUSB_PADCTL_HSIC_PAD_CTL2_RX_STROBE_TRIM_MASK 0xf
136 #define XUSB_PADCTL_HSIC_PAD_CTL2_RX_DATA_TRIM_SHIFT 0
137 #define XUSB_PADCTL_HSIC_PAD_CTL2_RX_DATA_TRIM_MASK 0xff
139 #define XUSB_PADCTL_HSIC_PAD_TRK_CTL 0x340
140 #define XUSB_PADCTL_HSIC_PAD_TRK_CTL_PD_TRK (1 << 19)
141 #define XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_SHIFT 12
142 #define XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_MASK 0x7f
143 #define XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_VAL 0x0a
144 #define XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_SHIFT 5
145 #define XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_MASK 0x7f
146 #define XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_VAL 0x1e
148 #define XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL 0x344
150 #define XUSB_PADCTL_UPHY_PLL_P0_CTL1 0x360
151 #define XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SHIFT 20
152 #define XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_MASK 0xff
153 #define XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_USB_VAL 0x19
154 #define XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SATA_VAL 0x1e
155 #define XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_SHIFT 16
156 #define XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_MASK 0x3
157 #define XUSB_PADCTL_UPHY_PLL_CTL1_LOCKDET_STATUS (1 << 15)
158 #define XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD (1 << 4)
159 #define XUSB_PADCTL_UPHY_PLL_CTL1_ENABLE (1 << 3)
160 #define XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_SHIFT 1
161 #define XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_MASK 0x3
162 #define XUSB_PADCTL_UPHY_PLL_CTL1_IDDQ (1 << 0)
164 #define XUSB_PADCTL_UPHY_PLL_P0_CTL2 0x364
165 #define XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_SHIFT 4
166 #define XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_MASK 0xffffff
167 #define XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_VAL 0x136
168 #define XUSB_PADCTL_UPHY_PLL_CTL2_CAL_OVRD (1 << 2)
169 #define XUSB_PADCTL_UPHY_PLL_CTL2_CAL_DONE (1 << 1)
170 #define XUSB_PADCTL_UPHY_PLL_CTL2_CAL_EN (1 << 0)
172 #define XUSB_PADCTL_UPHY_PLL_P0_CTL4 0x36c
173 #define XUSB_PADCTL_UPHY_PLL_CTL4_XDIGCLK_EN (1 << 19)
174 #define XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_EN (1 << 15)
175 #define XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SHIFT 12
176 #define XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_MASK 0x3
177 #define XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_USB_VAL 0x2
178 #define XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SATA_VAL 0x0
179 #define XUSB_PADCTL_UPHY_PLL_CTL4_REFCLKBUF_EN (1 << 8)
180 #define XUSB_PADCTL_UPHY_PLL_CTL4_REFCLK_SEL_SHIFT 4
181 #define XUSB_PADCTL_UPHY_PLL_CTL4_REFCLK_SEL_MASK 0xf
183 #define XUSB_PADCTL_UPHY_PLL_P0_CTL5 0x370
184 #define XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_SHIFT 16
185 #define XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_MASK 0xff
186 #define XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_VAL 0x2a
188 #define XUSB_PADCTL_UPHY_PLL_P0_CTL8 0x37c
189 #define XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_DONE (1 << 31)
190 #define XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_OVRD (1 << 15)
191 #define XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_CLK_EN (1 << 13)
192 #define XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_EN (1 << 12)
194 #define XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL1(x) (0x460 + (x) * 0x40)
195 #define XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_IDLE_MODE_SHIFT 20
196 #define XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_IDLE_MODE_MASK 0x3
197 #define XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_IDLE_MODE_VAL 0x1
198 #define XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_TERM_EN BIT(18)
199 #define XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_MODE_OVRD BIT(13)
201 #define XUSB_PADCTL_UPHY_PLL_S0_CTL1 0x860
203 #define XUSB_PADCTL_UPHY_PLL_S0_CTL2 0x864
205 #define XUSB_PADCTL_UPHY_PLL_S0_CTL4 0x86c
207 #define XUSB_PADCTL_UPHY_PLL_S0_CTL5 0x870
209 #define XUSB_PADCTL_UPHY_PLL_S0_CTL8 0x87c
211 #define XUSB_PADCTL_UPHY_MISC_PAD_S0_CTL1 0x960
213 #define XUSB_PADCTL_UPHY_USB3_PADX_ECTL1(x) (0xa60 + (x) * 0x40)
214 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_SHIFT 16
215 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_MASK 0x3
216 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_VAL 0x2
218 #define XUSB_PADCTL_UPHY_USB3_PADX_ECTL2(x) (0xa64 + (x) * 0x40)
219 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_SHIFT 0
220 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_MASK 0xffff
221 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_VAL 0x00fc
223 #define XUSB_PADCTL_UPHY_USB3_PADX_ECTL3(x) (0xa68 + (x) * 0x40)
224 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL3_RX_DFE_VAL 0xc0077f1f
226 #define XUSB_PADCTL_UPHY_USB3_PADX_ECTL4(x) (0xa6c + (x) * 0x40)
227 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_SHIFT 16
228 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_MASK 0xffff
229 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_VAL 0x01c7
231 #define XUSB_PADCTL_UPHY_USB3_PADX_ECTL6(x) (0xa74 + (x) * 0x40)
232 #define XUSB_PADCTL_UPHY_USB3_PAD_ECTL6_RX_EQ_CTRL_H_VAL 0xfcf01368
234 #define XUSB_PADCTL_USB2_VBUS_ID 0xc60
235 #define XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_VBUS_ON (1 << 14)
236 #define XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_SHIFT 18
237 #define XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_MASK 0xf
238 #define XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_FLOATING 8
240 struct tegra210_xusb_fuse_calibration
{
241 u32 hs_curr_level
[4];
242 u32 hs_term_range_adj
;
246 struct tegra210_xusb_padctl
{
247 struct tegra_xusb_padctl base
;
249 struct tegra210_xusb_fuse_calibration fuse
;
252 static inline struct tegra210_xusb_padctl
*
253 to_tegra210_xusb_padctl(struct tegra_xusb_padctl
*padctl
)
255 return container_of(padctl
, struct tegra210_xusb_padctl
, base
);
258 /* must be called under padctl->lock */
259 static int tegra210_pex_uphy_enable(struct tegra_xusb_padctl
*padctl
)
261 struct tegra_xusb_pcie_pad
*pcie
= to_pcie_pad(padctl
->pcie
);
262 unsigned long timeout
;
266 if (pcie
->enable
> 0) {
271 err
= clk_prepare_enable(pcie
->pll
);
275 err
= reset_control_deassert(pcie
->rst
);
279 value
= padctl_readl(padctl
, XUSB_PADCTL_UPHY_PLL_P0_CTL2
);
280 value
&= ~(XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_MASK
<<
281 XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_SHIFT
);
282 value
|= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_VAL
<<
283 XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_SHIFT
;
284 padctl_writel(padctl
, value
, XUSB_PADCTL_UPHY_PLL_P0_CTL2
);
286 value
= padctl_readl(padctl
, XUSB_PADCTL_UPHY_PLL_P0_CTL5
);
287 value
&= ~(XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_MASK
<<
288 XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_SHIFT
);
289 value
|= XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_VAL
<<
290 XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_SHIFT
;
291 padctl_writel(padctl
, value
, XUSB_PADCTL_UPHY_PLL_P0_CTL5
);
293 value
= padctl_readl(padctl
, XUSB_PADCTL_UPHY_PLL_P0_CTL1
);
294 value
|= XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD
;
295 padctl_writel(padctl
, value
, XUSB_PADCTL_UPHY_PLL_P0_CTL1
);
297 value
= padctl_readl(padctl
, XUSB_PADCTL_UPHY_PLL_P0_CTL2
);
298 value
|= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_OVRD
;
299 padctl_writel(padctl
, value
, XUSB_PADCTL_UPHY_PLL_P0_CTL2
);
301 value
= padctl_readl(padctl
, XUSB_PADCTL_UPHY_PLL_P0_CTL8
);
302 value
|= XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_OVRD
;
303 padctl_writel(padctl
, value
, XUSB_PADCTL_UPHY_PLL_P0_CTL8
);
305 value
= padctl_readl(padctl
, XUSB_PADCTL_UPHY_PLL_P0_CTL4
);
306 value
&= ~((XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_MASK
<<
307 XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SHIFT
) |
308 (XUSB_PADCTL_UPHY_PLL_CTL4_REFCLK_SEL_MASK
<<
309 XUSB_PADCTL_UPHY_PLL_CTL4_REFCLK_SEL_SHIFT
));
310 value
|= (XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_USB_VAL
<<
311 XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SHIFT
) |
312 XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_EN
;
313 padctl_writel(padctl
, value
, XUSB_PADCTL_UPHY_PLL_P0_CTL4
);
315 value
= padctl_readl(padctl
, XUSB_PADCTL_UPHY_PLL_P0_CTL1
);
316 value
&= ~((XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_MASK
<<
317 XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_SHIFT
) |
318 (XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_MASK
<<
319 XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SHIFT
));
320 value
|= XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_USB_VAL
<<
321 XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SHIFT
;
322 padctl_writel(padctl
, value
, XUSB_PADCTL_UPHY_PLL_P0_CTL1
);
324 value
= padctl_readl(padctl
, XUSB_PADCTL_UPHY_PLL_P0_CTL1
);
325 value
&= ~XUSB_PADCTL_UPHY_PLL_CTL1_IDDQ
;
326 padctl_writel(padctl
, value
, XUSB_PADCTL_UPHY_PLL_P0_CTL1
);
328 value
= padctl_readl(padctl
, XUSB_PADCTL_UPHY_PLL_P0_CTL1
);
329 value
&= ~(XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_MASK
<<
330 XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_SHIFT
);
331 padctl_writel(padctl
, value
, XUSB_PADCTL_UPHY_PLL_P0_CTL1
);
333 usleep_range(10, 20);
335 value
= padctl_readl(padctl
, XUSB_PADCTL_UPHY_PLL_P0_CTL4
);
336 value
|= XUSB_PADCTL_UPHY_PLL_CTL4_REFCLKBUF_EN
;
337 padctl_writel(padctl
, value
, XUSB_PADCTL_UPHY_PLL_P0_CTL4
);
339 value
= padctl_readl(padctl
, XUSB_PADCTL_UPHY_PLL_P0_CTL2
);
340 value
|= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_EN
;
341 padctl_writel(padctl
, value
, XUSB_PADCTL_UPHY_PLL_P0_CTL2
);
343 timeout
= jiffies
+ msecs_to_jiffies(100);
345 while (time_before(jiffies
, timeout
)) {
346 value
= padctl_readl(padctl
, XUSB_PADCTL_UPHY_PLL_P0_CTL2
);
347 if (value
& XUSB_PADCTL_UPHY_PLL_CTL2_CAL_DONE
)
350 usleep_range(10, 20);
353 if (time_after_eq(jiffies
, timeout
)) {
358 value
= padctl_readl(padctl
, XUSB_PADCTL_UPHY_PLL_P0_CTL2
);
359 value
&= ~XUSB_PADCTL_UPHY_PLL_CTL2_CAL_EN
;
360 padctl_writel(padctl
, value
, XUSB_PADCTL_UPHY_PLL_P0_CTL2
);
362 timeout
= jiffies
+ msecs_to_jiffies(100);
364 while (time_before(jiffies
, timeout
)) {
365 value
= padctl_readl(padctl
, XUSB_PADCTL_UPHY_PLL_P0_CTL2
);
366 if (!(value
& XUSB_PADCTL_UPHY_PLL_CTL2_CAL_DONE
))
369 usleep_range(10, 20);
372 if (time_after_eq(jiffies
, timeout
)) {
377 value
= padctl_readl(padctl
, XUSB_PADCTL_UPHY_PLL_P0_CTL1
);
378 value
|= XUSB_PADCTL_UPHY_PLL_CTL1_ENABLE
;
379 padctl_writel(padctl
, value
, XUSB_PADCTL_UPHY_PLL_P0_CTL1
);
381 timeout
= jiffies
+ msecs_to_jiffies(100);
383 while (time_before(jiffies
, timeout
)) {
384 value
= padctl_readl(padctl
, XUSB_PADCTL_UPHY_PLL_P0_CTL1
);
385 if (value
& XUSB_PADCTL_UPHY_PLL_CTL1_LOCKDET_STATUS
)
388 usleep_range(10, 20);
391 if (time_after_eq(jiffies
, timeout
)) {
396 value
= padctl_readl(padctl
, XUSB_PADCTL_UPHY_PLL_P0_CTL8
);
397 value
|= XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_EN
|
398 XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_CLK_EN
;
399 padctl_writel(padctl
, value
, XUSB_PADCTL_UPHY_PLL_P0_CTL8
);
401 timeout
= jiffies
+ msecs_to_jiffies(100);
403 while (time_before(jiffies
, timeout
)) {
404 value
= padctl_readl(padctl
, XUSB_PADCTL_UPHY_PLL_P0_CTL8
);
405 if (value
& XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_DONE
)
408 usleep_range(10, 20);
411 if (time_after_eq(jiffies
, timeout
)) {
416 value
= padctl_readl(padctl
, XUSB_PADCTL_UPHY_PLL_P0_CTL8
);
417 value
&= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_EN
;
418 padctl_writel(padctl
, value
, XUSB_PADCTL_UPHY_PLL_P0_CTL8
);
420 timeout
= jiffies
+ msecs_to_jiffies(100);
422 while (time_before(jiffies
, timeout
)) {
423 value
= padctl_readl(padctl
, XUSB_PADCTL_UPHY_PLL_P0_CTL8
);
424 if (!(value
& XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_DONE
))
427 usleep_range(10, 20);
430 if (time_after_eq(jiffies
, timeout
)) {
435 value
= padctl_readl(padctl
, XUSB_PADCTL_UPHY_PLL_P0_CTL8
);
436 value
&= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_CLK_EN
;
437 padctl_writel(padctl
, value
, XUSB_PADCTL_UPHY_PLL_P0_CTL8
);
439 tegra210_xusb_pll_hw_control_enable();
441 value
= padctl_readl(padctl
, XUSB_PADCTL_UPHY_PLL_P0_CTL1
);
442 value
&= ~XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD
;
443 padctl_writel(padctl
, value
, XUSB_PADCTL_UPHY_PLL_P0_CTL1
);
445 value
= padctl_readl(padctl
, XUSB_PADCTL_UPHY_PLL_P0_CTL2
);
446 value
&= ~XUSB_PADCTL_UPHY_PLL_CTL2_CAL_OVRD
;
447 padctl_writel(padctl
, value
, XUSB_PADCTL_UPHY_PLL_P0_CTL2
);
449 value
= padctl_readl(padctl
, XUSB_PADCTL_UPHY_PLL_P0_CTL8
);
450 value
&= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_OVRD
;
451 padctl_writel(padctl
, value
, XUSB_PADCTL_UPHY_PLL_P0_CTL8
);
453 usleep_range(10, 20);
455 tegra210_xusb_pll_hw_sequence_start();
462 reset_control_assert(pcie
->rst
);
464 clk_disable_unprepare(pcie
->pll
);
468 static void tegra210_pex_uphy_disable(struct tegra_xusb_padctl
*padctl
)
470 struct tegra_xusb_pcie_pad
*pcie
= to_pcie_pad(padctl
->pcie
);
472 mutex_lock(&padctl
->lock
);
474 if (WARN_ON(pcie
->enable
== 0))
477 if (--pcie
->enable
> 0)
480 reset_control_assert(pcie
->rst
);
481 clk_disable_unprepare(pcie
->pll
);
484 mutex_unlock(&padctl
->lock
);
487 /* must be called under padctl->lock */
488 static int tegra210_sata_uphy_enable(struct tegra_xusb_padctl
*padctl
, bool usb
)
490 struct tegra_xusb_sata_pad
*sata
= to_sata_pad(padctl
->sata
);
491 unsigned long timeout
;
495 if (sata
->enable
> 0) {
500 err
= clk_prepare_enable(sata
->pll
);
504 err
= reset_control_deassert(sata
->rst
);
508 value
= padctl_readl(padctl
, XUSB_PADCTL_UPHY_PLL_S0_CTL2
);
509 value
&= ~(XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_MASK
<<
510 XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_SHIFT
);
511 value
|= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_VAL
<<
512 XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_SHIFT
;
513 padctl_writel(padctl
, value
, XUSB_PADCTL_UPHY_PLL_S0_CTL2
);
515 value
= padctl_readl(padctl
, XUSB_PADCTL_UPHY_PLL_S0_CTL5
);
516 value
&= ~(XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_MASK
<<
517 XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_SHIFT
);
518 value
|= XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_VAL
<<
519 XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_SHIFT
;
520 padctl_writel(padctl
, value
, XUSB_PADCTL_UPHY_PLL_S0_CTL5
);
522 value
= padctl_readl(padctl
, XUSB_PADCTL_UPHY_PLL_S0_CTL1
);
523 value
|= XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD
;
524 padctl_writel(padctl
, value
, XUSB_PADCTL_UPHY_PLL_S0_CTL1
);
526 value
= padctl_readl(padctl
, XUSB_PADCTL_UPHY_PLL_S0_CTL2
);
527 value
|= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_OVRD
;
528 padctl_writel(padctl
, value
, XUSB_PADCTL_UPHY_PLL_S0_CTL2
);
530 value
= padctl_readl(padctl
, XUSB_PADCTL_UPHY_PLL_S0_CTL8
);
531 value
|= XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_OVRD
;
532 padctl_writel(padctl
, value
, XUSB_PADCTL_UPHY_PLL_S0_CTL8
);
534 value
= padctl_readl(padctl
, XUSB_PADCTL_UPHY_PLL_S0_CTL4
);
535 value
&= ~((XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_MASK
<<
536 XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SHIFT
) |
537 (XUSB_PADCTL_UPHY_PLL_CTL4_REFCLK_SEL_MASK
<<
538 XUSB_PADCTL_UPHY_PLL_CTL4_REFCLK_SEL_SHIFT
));
539 value
|= XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_EN
;
542 value
|= (XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_USB_VAL
<<
543 XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SHIFT
);
545 value
|= (XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SATA_VAL
<<
546 XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SHIFT
);
548 value
&= ~XUSB_PADCTL_UPHY_PLL_CTL4_XDIGCLK_EN
;
549 padctl_writel(padctl
, value
, XUSB_PADCTL_UPHY_PLL_S0_CTL4
);
551 value
= padctl_readl(padctl
, XUSB_PADCTL_UPHY_PLL_S0_CTL1
);
552 value
&= ~((XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_MASK
<<
553 XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_SHIFT
) |
554 (XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_MASK
<<
555 XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SHIFT
));
558 value
|= XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_USB_VAL
<<
559 XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SHIFT
;
561 value
|= XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SATA_VAL
<<
562 XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SHIFT
;
564 padctl_writel(padctl
, value
, XUSB_PADCTL_UPHY_PLL_S0_CTL1
);
566 value
= padctl_readl(padctl
, XUSB_PADCTL_UPHY_PLL_S0_CTL1
);
567 value
&= ~XUSB_PADCTL_UPHY_PLL_CTL1_IDDQ
;
568 padctl_writel(padctl
, value
, XUSB_PADCTL_UPHY_PLL_S0_CTL1
);
570 value
= padctl_readl(padctl
, XUSB_PADCTL_UPHY_PLL_S0_CTL1
);
571 value
&= ~(XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_MASK
<<
572 XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_SHIFT
);
573 padctl_writel(padctl
, value
, XUSB_PADCTL_UPHY_PLL_S0_CTL1
);
575 usleep_range(10, 20);
577 value
= padctl_readl(padctl
, XUSB_PADCTL_UPHY_PLL_S0_CTL4
);
578 value
|= XUSB_PADCTL_UPHY_PLL_CTL4_REFCLKBUF_EN
;
579 padctl_writel(padctl
, value
, XUSB_PADCTL_UPHY_PLL_S0_CTL4
);
581 value
= padctl_readl(padctl
, XUSB_PADCTL_UPHY_PLL_S0_CTL2
);
582 value
|= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_EN
;
583 padctl_writel(padctl
, value
, XUSB_PADCTL_UPHY_PLL_S0_CTL2
);
585 timeout
= jiffies
+ msecs_to_jiffies(100);
587 while (time_before(jiffies
, timeout
)) {
588 value
= padctl_readl(padctl
, XUSB_PADCTL_UPHY_PLL_S0_CTL2
);
589 if (value
& XUSB_PADCTL_UPHY_PLL_CTL2_CAL_DONE
)
592 usleep_range(10, 20);
595 if (time_after_eq(jiffies
, timeout
)) {
600 value
= padctl_readl(padctl
, XUSB_PADCTL_UPHY_PLL_S0_CTL2
);
601 value
&= ~XUSB_PADCTL_UPHY_PLL_CTL2_CAL_EN
;
602 padctl_writel(padctl
, value
, XUSB_PADCTL_UPHY_PLL_S0_CTL2
);
604 timeout
= jiffies
+ msecs_to_jiffies(100);
606 while (time_before(jiffies
, timeout
)) {
607 value
= padctl_readl(padctl
, XUSB_PADCTL_UPHY_PLL_S0_CTL2
);
608 if (!(value
& XUSB_PADCTL_UPHY_PLL_CTL2_CAL_DONE
))
611 usleep_range(10, 20);
614 if (time_after_eq(jiffies
, timeout
)) {
619 value
= padctl_readl(padctl
, XUSB_PADCTL_UPHY_PLL_S0_CTL1
);
620 value
|= XUSB_PADCTL_UPHY_PLL_CTL1_ENABLE
;
621 padctl_writel(padctl
, value
, XUSB_PADCTL_UPHY_PLL_S0_CTL1
);
623 timeout
= jiffies
+ msecs_to_jiffies(100);
625 while (time_before(jiffies
, timeout
)) {
626 value
= padctl_readl(padctl
, XUSB_PADCTL_UPHY_PLL_S0_CTL1
);
627 if (value
& XUSB_PADCTL_UPHY_PLL_CTL1_LOCKDET_STATUS
)
630 usleep_range(10, 20);
633 if (time_after_eq(jiffies
, timeout
)) {
638 value
= padctl_readl(padctl
, XUSB_PADCTL_UPHY_PLL_S0_CTL8
);
639 value
|= XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_EN
|
640 XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_CLK_EN
;
641 padctl_writel(padctl
, value
, XUSB_PADCTL_UPHY_PLL_S0_CTL8
);
643 timeout
= jiffies
+ msecs_to_jiffies(100);
645 while (time_before(jiffies
, timeout
)) {
646 value
= padctl_readl(padctl
, XUSB_PADCTL_UPHY_PLL_S0_CTL8
);
647 if (value
& XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_DONE
)
650 usleep_range(10, 20);
653 if (time_after_eq(jiffies
, timeout
)) {
658 value
= padctl_readl(padctl
, XUSB_PADCTL_UPHY_PLL_S0_CTL8
);
659 value
&= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_EN
;
660 padctl_writel(padctl
, value
, XUSB_PADCTL_UPHY_PLL_S0_CTL8
);
662 timeout
= jiffies
+ msecs_to_jiffies(100);
664 while (time_before(jiffies
, timeout
)) {
665 value
= padctl_readl(padctl
, XUSB_PADCTL_UPHY_PLL_S0_CTL8
);
666 if (!(value
& XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_DONE
))
669 usleep_range(10, 20);
672 if (time_after_eq(jiffies
, timeout
)) {
677 value
= padctl_readl(padctl
, XUSB_PADCTL_UPHY_PLL_S0_CTL8
);
678 value
&= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_CLK_EN
;
679 padctl_writel(padctl
, value
, XUSB_PADCTL_UPHY_PLL_S0_CTL8
);
681 tegra210_sata_pll_hw_control_enable();
683 value
= padctl_readl(padctl
, XUSB_PADCTL_UPHY_PLL_S0_CTL1
);
684 value
&= ~XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD
;
685 padctl_writel(padctl
, value
, XUSB_PADCTL_UPHY_PLL_S0_CTL1
);
687 value
= padctl_readl(padctl
, XUSB_PADCTL_UPHY_PLL_S0_CTL2
);
688 value
&= ~XUSB_PADCTL_UPHY_PLL_CTL2_CAL_OVRD
;
689 padctl_writel(padctl
, value
, XUSB_PADCTL_UPHY_PLL_S0_CTL2
);
691 value
= padctl_readl(padctl
, XUSB_PADCTL_UPHY_PLL_S0_CTL8
);
692 value
&= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_OVRD
;
693 padctl_writel(padctl
, value
, XUSB_PADCTL_UPHY_PLL_S0_CTL8
);
695 usleep_range(10, 20);
697 tegra210_sata_pll_hw_sequence_start();
704 reset_control_assert(sata
->rst
);
706 clk_disable_unprepare(sata
->pll
);
710 static void tegra210_sata_uphy_disable(struct tegra_xusb_padctl
*padctl
)
712 struct tegra_xusb_sata_pad
*sata
= to_sata_pad(padctl
->sata
);
714 mutex_lock(&padctl
->lock
);
716 if (WARN_ON(sata
->enable
== 0))
719 if (--sata
->enable
> 0)
722 reset_control_assert(sata
->rst
);
723 clk_disable_unprepare(sata
->pll
);
726 mutex_unlock(&padctl
->lock
);
729 static int tegra210_xusb_padctl_enable(struct tegra_xusb_padctl
*padctl
)
733 mutex_lock(&padctl
->lock
);
735 if (padctl
->enable
++ > 0)
738 value
= padctl_readl(padctl
, XUSB_PADCTL_ELPG_PROGRAM1
);
739 value
&= ~XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN
;
740 padctl_writel(padctl
, value
, XUSB_PADCTL_ELPG_PROGRAM1
);
742 usleep_range(100, 200);
744 value
= padctl_readl(padctl
, XUSB_PADCTL_ELPG_PROGRAM1
);
745 value
&= ~XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN_EARLY
;
746 padctl_writel(padctl
, value
, XUSB_PADCTL_ELPG_PROGRAM1
);
748 usleep_range(100, 200);
750 value
= padctl_readl(padctl
, XUSB_PADCTL_ELPG_PROGRAM1
);
751 value
&= ~XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_VCORE_DOWN
;
752 padctl_writel(padctl
, value
, XUSB_PADCTL_ELPG_PROGRAM1
);
755 mutex_unlock(&padctl
->lock
);
759 static int tegra210_xusb_padctl_disable(struct tegra_xusb_padctl
*padctl
)
763 mutex_lock(&padctl
->lock
);
765 if (WARN_ON(padctl
->enable
== 0))
768 if (--padctl
->enable
> 0)
771 value
= padctl_readl(padctl
, XUSB_PADCTL_ELPG_PROGRAM1
);
772 value
|= XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_VCORE_DOWN
;
773 padctl_writel(padctl
, value
, XUSB_PADCTL_ELPG_PROGRAM1
);
775 usleep_range(100, 200);
777 value
= padctl_readl(padctl
, XUSB_PADCTL_ELPG_PROGRAM1
);
778 value
|= XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN_EARLY
;
779 padctl_writel(padctl
, value
, XUSB_PADCTL_ELPG_PROGRAM1
);
781 usleep_range(100, 200);
783 value
= padctl_readl(padctl
, XUSB_PADCTL_ELPG_PROGRAM1
);
784 value
|= XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN
;
785 padctl_writel(padctl
, value
, XUSB_PADCTL_ELPG_PROGRAM1
);
788 mutex_unlock(&padctl
->lock
);
792 static int tegra210_hsic_set_idle(struct tegra_xusb_padctl
*padctl
,
793 unsigned int index
, bool idle
)
797 value
= padctl_readl(padctl
, XUSB_PADCTL_HSIC_PADX_CTL0(index
));
799 value
&= ~(XUSB_PADCTL_HSIC_PAD_CTL0_RPU_DATA0
|
800 XUSB_PADCTL_HSIC_PAD_CTL0_RPU_DATA1
|
801 XUSB_PADCTL_HSIC_PAD_CTL0_RPD_STROBE
);
804 value
|= XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA0
|
805 XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA1
|
806 XUSB_PADCTL_HSIC_PAD_CTL0_RPU_STROBE
;
808 value
&= ~(XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA0
|
809 XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA1
|
810 XUSB_PADCTL_HSIC_PAD_CTL0_RPU_STROBE
);
812 padctl_writel(padctl
, value
, XUSB_PADCTL_HSIC_PADX_CTL0(index
));
817 static int tegra210_usb3_set_lfps_detect(struct tegra_xusb_padctl
*padctl
,
818 unsigned int index
, bool enable
)
820 struct tegra_xusb_port
*port
;
821 struct tegra_xusb_lane
*lane
;
824 port
= tegra_xusb_find_port(padctl
, "usb3", index
);
830 if (lane
->pad
== padctl
->pcie
)
831 offset
= XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL1(lane
->index
);
833 offset
= XUSB_PADCTL_UPHY_MISC_PAD_S0_CTL1
;
835 value
= padctl_readl(padctl
, offset
);
837 value
&= ~((XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_IDLE_MODE_MASK
<<
838 XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_IDLE_MODE_SHIFT
) |
839 XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_TERM_EN
|
840 XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_MODE_OVRD
);
843 value
|= (XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_IDLE_MODE_VAL
<<
844 XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_IDLE_MODE_SHIFT
) |
845 XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_TERM_EN
|
846 XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_MODE_OVRD
;
849 padctl_writel(padctl
, value
, offset
);
854 #define TEGRA210_LANE(_name, _offset, _shift, _mask, _type) \
860 .num_funcs = ARRAY_SIZE(tegra210_##_type##_functions), \
861 .funcs = tegra210_##_type##_functions, \
864 static const char *tegra210_usb2_functions
[] = {
870 static const struct tegra_xusb_lane_soc tegra210_usb2_lanes
[] = {
871 TEGRA210_LANE("usb2-0", 0x004, 0, 0x3, usb2
),
872 TEGRA210_LANE("usb2-1", 0x004, 2, 0x3, usb2
),
873 TEGRA210_LANE("usb2-2", 0x004, 4, 0x3, usb2
),
874 TEGRA210_LANE("usb2-3", 0x004, 6, 0x3, usb2
),
877 static struct tegra_xusb_lane
*
878 tegra210_usb2_lane_probe(struct tegra_xusb_pad
*pad
, struct device_node
*np
,
881 struct tegra_xusb_usb2_lane
*usb2
;
884 usb2
= kzalloc(sizeof(*usb2
), GFP_KERNEL
);
886 return ERR_PTR(-ENOMEM
);
888 INIT_LIST_HEAD(&usb2
->base
.list
);
889 usb2
->base
.soc
= &pad
->soc
->lanes
[index
];
890 usb2
->base
.index
= index
;
891 usb2
->base
.pad
= pad
;
894 err
= tegra_xusb_lane_parse_dt(&usb2
->base
, np
);
903 static void tegra210_usb2_lane_remove(struct tegra_xusb_lane
*lane
)
905 struct tegra_xusb_usb2_lane
*usb2
= to_usb2_lane(lane
);
910 static const struct tegra_xusb_lane_ops tegra210_usb2_lane_ops
= {
911 .probe
= tegra210_usb2_lane_probe
,
912 .remove
= tegra210_usb2_lane_remove
,
915 static int tegra210_usb2_phy_init(struct phy
*phy
)
917 struct tegra_xusb_lane
*lane
= phy_get_drvdata(phy
);
918 struct tegra_xusb_padctl
*padctl
= lane
->pad
->padctl
;
921 value
= padctl_readl(padctl
, XUSB_PADCTL_USB2_PAD_MUX
);
922 value
&= ~(XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_MASK
<<
923 XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_SHIFT
);
924 value
|= XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_XUSB
<<
925 XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_SHIFT
;
926 padctl_writel(padctl
, value
, XUSB_PADCTL_USB2_PAD_MUX
);
928 return tegra210_xusb_padctl_enable(padctl
);
931 static int tegra210_usb2_phy_exit(struct phy
*phy
)
933 struct tegra_xusb_lane
*lane
= phy_get_drvdata(phy
);
935 return tegra210_xusb_padctl_disable(lane
->pad
->padctl
);
938 static int tegra210_usb2_phy_power_on(struct phy
*phy
)
940 struct tegra_xusb_lane
*lane
= phy_get_drvdata(phy
);
941 struct tegra_xusb_usb2_lane
*usb2
= to_usb2_lane(lane
);
942 struct tegra_xusb_usb2_pad
*pad
= to_usb2_pad(lane
->pad
);
943 struct tegra_xusb_padctl
*padctl
= lane
->pad
->padctl
;
944 struct tegra210_xusb_padctl
*priv
;
945 struct tegra_xusb_usb2_port
*port
;
946 unsigned int index
= lane
->index
;
950 port
= tegra_xusb_find_usb2_port(padctl
, index
);
952 dev_err(&phy
->dev
, "no port found for USB2 lane %u\n", index
);
956 priv
= to_tegra210_xusb_padctl(padctl
);
958 if (port
->usb3_port_fake
!= -1) {
959 value
= padctl_readl(padctl
, XUSB_PADCTL_SS_PORT_MAP
);
960 value
&= ~XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_MASK(
961 port
->usb3_port_fake
);
962 value
|= XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(
963 port
->usb3_port_fake
, index
);
964 padctl_writel(padctl
, value
, XUSB_PADCTL_SS_PORT_MAP
);
966 value
= padctl_readl(padctl
, XUSB_PADCTL_ELPG_PROGRAM1
);
967 value
&= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_VCORE_DOWN(
968 port
->usb3_port_fake
);
969 padctl_writel(padctl
, value
, XUSB_PADCTL_ELPG_PROGRAM1
);
971 usleep_range(100, 200);
973 value
= padctl_readl(padctl
, XUSB_PADCTL_ELPG_PROGRAM1
);
974 value
&= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY(
975 port
->usb3_port_fake
);
976 padctl_writel(padctl
, value
, XUSB_PADCTL_ELPG_PROGRAM1
);
978 usleep_range(100, 200);
980 value
= padctl_readl(padctl
, XUSB_PADCTL_ELPG_PROGRAM1
);
981 value
&= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN(
982 port
->usb3_port_fake
);
983 padctl_writel(padctl
, value
, XUSB_PADCTL_ELPG_PROGRAM1
);
986 value
= padctl_readl(padctl
, XUSB_PADCTL_USB2_BIAS_PAD_CTL0
);
987 value
&= ~((XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_MASK
<<
988 XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_SHIFT
) |
989 (XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_MASK
<<
990 XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_SHIFT
));
991 value
|= (XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_VAL
<<
992 XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_SHIFT
);
994 if (tegra_sku_info
.revision
< TEGRA_REVISION_A02
)
996 (XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_VAL
<<
997 XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_SHIFT
);
999 padctl_writel(padctl
, value
, XUSB_PADCTL_USB2_BIAS_PAD_CTL0
);
1001 value
= padctl_readl(padctl
, XUSB_PADCTL_USB2_PORT_CAP
);
1002 value
&= ~XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_MASK(index
);
1003 if (port
->mode
== USB_DR_MODE_UNKNOWN
)
1004 value
|= XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_DISABLED(index
);
1005 else if (port
->mode
== USB_DR_MODE_PERIPHERAL
)
1006 value
|= XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_DEVICE(index
);
1007 else if (port
->mode
== USB_DR_MODE_HOST
)
1008 value
|= XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_HOST(index
);
1009 else if (port
->mode
== USB_DR_MODE_OTG
)
1010 value
|= XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_OTG(index
);
1011 padctl_writel(padctl
, value
, XUSB_PADCTL_USB2_PORT_CAP
);
1013 value
= padctl_readl(padctl
, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index
));
1014 value
&= ~((XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL_MASK
<<
1015 XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL_SHIFT
) |
1016 XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD
|
1017 XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD2
|
1018 XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD_ZI
);
1019 value
|= (priv
->fuse
.hs_curr_level
[index
] +
1020 usb2
->hs_curr_level_offset
) <<
1021 XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL_SHIFT
;
1022 padctl_writel(padctl
, value
, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index
));
1024 value
= padctl_readl(padctl
, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index
));
1025 value
&= ~((XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ_MASK
<<
1026 XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ_SHIFT
) |
1027 (XUSB_PADCTL_USB2_OTG_PAD_CTL1_RPD_CTRL_MASK
<<
1028 XUSB_PADCTL_USB2_OTG_PAD_CTL1_RPD_CTRL_SHIFT
) |
1029 XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR
|
1030 XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_CHRP_OVRD
|
1031 XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DISC_OVRD
);
1032 value
|= (priv
->fuse
.hs_term_range_adj
<<
1033 XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ_SHIFT
) |
1034 (priv
->fuse
.rpd_ctrl
<<
1035 XUSB_PADCTL_USB2_OTG_PAD_CTL1_RPD_CTRL_SHIFT
);
1036 padctl_writel(padctl
, value
, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index
));
1038 value
= padctl_readl(padctl
,
1039 XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADX_CTL1(index
));
1040 value
&= ~(XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_MASK
<<
1041 XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_SHIFT
);
1042 if (port
->mode
== USB_DR_MODE_HOST
)
1043 value
|= XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_FIX18
;
1046 XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_VAL
<<
1047 XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_SHIFT
;
1048 padctl_writel(padctl
, value
,
1049 XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADX_CTL1(index
));
1051 err
= regulator_enable(port
->supply
);
1055 mutex_lock(&padctl
->lock
);
1057 if (pad
->enable
> 0) {
1059 mutex_unlock(&padctl
->lock
);
1063 err
= clk_prepare_enable(pad
->clk
);
1065 goto disable_regulator
;
1067 value
= padctl_readl(padctl
, XUSB_PADCTL_USB2_BIAS_PAD_CTL1
);
1068 value
&= ~((XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_MASK
<<
1069 XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_SHIFT
) |
1070 (XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_MASK
<<
1071 XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_SHIFT
));
1072 value
|= (XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_VAL
<<
1073 XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_SHIFT
) |
1074 (XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_VAL
<<
1075 XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_SHIFT
);
1076 padctl_writel(padctl
, value
, XUSB_PADCTL_USB2_BIAS_PAD_CTL1
);
1078 value
= padctl_readl(padctl
, XUSB_PADCTL_USB2_BIAS_PAD_CTL0
);
1079 value
&= ~XUSB_PADCTL_USB2_BIAS_PAD_CTL0_PD
;
1080 padctl_writel(padctl
, value
, XUSB_PADCTL_USB2_BIAS_PAD_CTL0
);
1084 value
= padctl_readl(padctl
, XUSB_PADCTL_USB2_BIAS_PAD_CTL1
);
1085 value
&= ~XUSB_PADCTL_USB2_BIAS_PAD_CTL1_PD_TRK
;
1086 padctl_writel(padctl
, value
, XUSB_PADCTL_USB2_BIAS_PAD_CTL1
);
1090 clk_disable_unprepare(pad
->clk
);
1093 mutex_unlock(&padctl
->lock
);
1098 regulator_disable(port
->supply
);
1099 mutex_unlock(&padctl
->lock
);
1103 static int tegra210_usb2_phy_power_off(struct phy
*phy
)
1105 struct tegra_xusb_lane
*lane
= phy_get_drvdata(phy
);
1106 struct tegra_xusb_usb2_pad
*pad
= to_usb2_pad(lane
->pad
);
1107 struct tegra_xusb_padctl
*padctl
= lane
->pad
->padctl
;
1108 struct tegra_xusb_usb2_port
*port
;
1111 port
= tegra_xusb_find_usb2_port(padctl
, lane
->index
);
1113 dev_err(&phy
->dev
, "no port found for USB2 lane %u\n",
1118 mutex_lock(&padctl
->lock
);
1120 if (port
->usb3_port_fake
!= -1) {
1121 value
= padctl_readl(padctl
, XUSB_PADCTL_ELPG_PROGRAM1
);
1122 value
|= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY(
1123 port
->usb3_port_fake
);
1124 padctl_writel(padctl
, value
, XUSB_PADCTL_ELPG_PROGRAM1
);
1126 usleep_range(100, 200);
1128 value
= padctl_readl(padctl
, XUSB_PADCTL_ELPG_PROGRAM1
);
1129 value
|= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN(
1130 port
->usb3_port_fake
);
1131 padctl_writel(padctl
, value
, XUSB_PADCTL_ELPG_PROGRAM1
);
1133 usleep_range(250, 350);
1135 value
= padctl_readl(padctl
, XUSB_PADCTL_ELPG_PROGRAM1
);
1136 value
|= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_VCORE_DOWN(
1137 port
->usb3_port_fake
);
1138 padctl_writel(padctl
, value
, XUSB_PADCTL_ELPG_PROGRAM1
);
1140 value
= padctl_readl(padctl
, XUSB_PADCTL_SS_PORT_MAP
);
1141 value
|= XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(port
->usb3_port_fake
,
1142 XUSB_PADCTL_SS_PORT_MAP_PORT_DISABLED
);
1143 padctl_writel(padctl
, value
, XUSB_PADCTL_SS_PORT_MAP
);
1146 if (WARN_ON(pad
->enable
== 0))
1149 if (--pad
->enable
> 0)
1152 value
= padctl_readl(padctl
, XUSB_PADCTL_USB2_BIAS_PAD_CTL0
);
1153 value
|= XUSB_PADCTL_USB2_BIAS_PAD_CTL0_PD
;
1154 padctl_writel(padctl
, value
, XUSB_PADCTL_USB2_BIAS_PAD_CTL0
);
1157 regulator_disable(port
->supply
);
1158 mutex_unlock(&padctl
->lock
);
1162 static const struct phy_ops tegra210_usb2_phy_ops
= {
1163 .init
= tegra210_usb2_phy_init
,
1164 .exit
= tegra210_usb2_phy_exit
,
1165 .power_on
= tegra210_usb2_phy_power_on
,
1166 .power_off
= tegra210_usb2_phy_power_off
,
1167 .owner
= THIS_MODULE
,
1170 static struct tegra_xusb_pad
*
1171 tegra210_usb2_pad_probe(struct tegra_xusb_padctl
*padctl
,
1172 const struct tegra_xusb_pad_soc
*soc
,
1173 struct device_node
*np
)
1175 struct tegra_xusb_usb2_pad
*usb2
;
1176 struct tegra_xusb_pad
*pad
;
1179 usb2
= kzalloc(sizeof(*usb2
), GFP_KERNEL
);
1181 return ERR_PTR(-ENOMEM
);
1184 pad
->ops
= &tegra210_usb2_lane_ops
;
1187 err
= tegra_xusb_pad_init(pad
, padctl
, np
);
1193 usb2
->clk
= devm_clk_get(&pad
->dev
, "trk");
1194 if (IS_ERR(usb2
->clk
)) {
1195 err
= PTR_ERR(usb2
->clk
);
1196 dev_err(&pad
->dev
, "failed to get trk clock: %d\n", err
);
1200 err
= tegra_xusb_pad_register(pad
, &tegra210_usb2_phy_ops
);
1204 dev_set_drvdata(&pad
->dev
, pad
);
1209 device_unregister(&pad
->dev
);
1211 return ERR_PTR(err
);
1214 static void tegra210_usb2_pad_remove(struct tegra_xusb_pad
*pad
)
1216 struct tegra_xusb_usb2_pad
*usb2
= to_usb2_pad(pad
);
1221 static const struct tegra_xusb_pad_ops tegra210_usb2_ops
= {
1222 .probe
= tegra210_usb2_pad_probe
,
1223 .remove
= tegra210_usb2_pad_remove
,
1226 static const struct tegra_xusb_pad_soc tegra210_usb2_pad
= {
1228 .num_lanes
= ARRAY_SIZE(tegra210_usb2_lanes
),
1229 .lanes
= tegra210_usb2_lanes
,
1230 .ops
= &tegra210_usb2_ops
,
1233 static const char *tegra210_hsic_functions
[] = {
1238 static const struct tegra_xusb_lane_soc tegra210_hsic_lanes
[] = {
1239 TEGRA210_LANE("hsic-0", 0x004, 14, 0x1, hsic
),
1242 static struct tegra_xusb_lane
*
1243 tegra210_hsic_lane_probe(struct tegra_xusb_pad
*pad
, struct device_node
*np
,
1246 struct tegra_xusb_hsic_lane
*hsic
;
1249 hsic
= kzalloc(sizeof(*hsic
), GFP_KERNEL
);
1251 return ERR_PTR(-ENOMEM
);
1253 INIT_LIST_HEAD(&hsic
->base
.list
);
1254 hsic
->base
.soc
= &pad
->soc
->lanes
[index
];
1255 hsic
->base
.index
= index
;
1256 hsic
->base
.pad
= pad
;
1259 err
= tegra_xusb_lane_parse_dt(&hsic
->base
, np
);
1262 return ERR_PTR(err
);
1268 static void tegra210_hsic_lane_remove(struct tegra_xusb_lane
*lane
)
1270 struct tegra_xusb_hsic_lane
*hsic
= to_hsic_lane(lane
);
1275 static const struct tegra_xusb_lane_ops tegra210_hsic_lane_ops
= {
1276 .probe
= tegra210_hsic_lane_probe
,
1277 .remove
= tegra210_hsic_lane_remove
,
1280 static int tegra210_hsic_phy_init(struct phy
*phy
)
1282 struct tegra_xusb_lane
*lane
= phy_get_drvdata(phy
);
1283 struct tegra_xusb_padctl
*padctl
= lane
->pad
->padctl
;
1286 value
= padctl_readl(padctl
, XUSB_PADCTL_USB2_PAD_MUX
);
1287 value
&= ~(XUSB_PADCTL_USB2_PAD_MUX_HSIC_PAD_TRK_MASK
<<
1288 XUSB_PADCTL_USB2_PAD_MUX_HSIC_PAD_TRK_SHIFT
);
1289 value
|= XUSB_PADCTL_USB2_PAD_MUX_HSIC_PAD_TRK_XUSB
<<
1290 XUSB_PADCTL_USB2_PAD_MUX_HSIC_PAD_TRK_SHIFT
;
1291 padctl_writel(padctl
, value
, XUSB_PADCTL_USB2_PAD_MUX
);
1293 return tegra210_xusb_padctl_enable(padctl
);
1296 static int tegra210_hsic_phy_exit(struct phy
*phy
)
1298 struct tegra_xusb_lane
*lane
= phy_get_drvdata(phy
);
1300 return tegra210_xusb_padctl_disable(lane
->pad
->padctl
);
1303 static int tegra210_hsic_phy_power_on(struct phy
*phy
)
1305 struct tegra_xusb_lane
*lane
= phy_get_drvdata(phy
);
1306 struct tegra_xusb_hsic_lane
*hsic
= to_hsic_lane(lane
);
1307 struct tegra_xusb_hsic_pad
*pad
= to_hsic_pad(lane
->pad
);
1308 struct tegra_xusb_padctl
*padctl
= lane
->pad
->padctl
;
1309 unsigned int index
= lane
->index
;
1313 err
= regulator_enable(pad
->supply
);
1317 padctl_writel(padctl
, hsic
->strobe_trim
,
1318 XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL
);
1320 value
= padctl_readl(padctl
, XUSB_PADCTL_HSIC_PADX_CTL1(index
));
1321 value
&= ~(XUSB_PADCTL_HSIC_PAD_CTL1_TX_RTUNEP_MASK
<<
1322 XUSB_PADCTL_HSIC_PAD_CTL1_TX_RTUNEP_SHIFT
);
1323 value
|= (hsic
->tx_rtune_p
<<
1324 XUSB_PADCTL_HSIC_PAD_CTL1_TX_RTUNEP_SHIFT
);
1325 padctl_writel(padctl
, value
, XUSB_PADCTL_HSIC_PADX_CTL1(index
));
1327 value
= padctl_readl(padctl
, XUSB_PADCTL_HSIC_PADX_CTL2(index
));
1328 value
&= ~((XUSB_PADCTL_HSIC_PAD_CTL2_RX_STROBE_TRIM_MASK
<<
1329 XUSB_PADCTL_HSIC_PAD_CTL2_RX_STROBE_TRIM_SHIFT
) |
1330 (XUSB_PADCTL_HSIC_PAD_CTL2_RX_DATA_TRIM_MASK
<<
1331 XUSB_PADCTL_HSIC_PAD_CTL2_RX_DATA_TRIM_SHIFT
));
1332 value
|= (hsic
->rx_strobe_trim
<<
1333 XUSB_PADCTL_HSIC_PAD_CTL2_RX_STROBE_TRIM_SHIFT
) |
1334 (hsic
->rx_data_trim
<<
1335 XUSB_PADCTL_HSIC_PAD_CTL2_RX_DATA_TRIM_SHIFT
);
1336 padctl_writel(padctl
, value
, XUSB_PADCTL_HSIC_PADX_CTL2(index
));
1338 value
= padctl_readl(padctl
, XUSB_PADCTL_HSIC_PADX_CTL0(index
));
1339 value
&= ~(XUSB_PADCTL_HSIC_PAD_CTL0_RPU_DATA0
|
1340 XUSB_PADCTL_HSIC_PAD_CTL0_RPU_DATA1
|
1341 XUSB_PADCTL_HSIC_PAD_CTL0_RPU_STROBE
|
1342 XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA0
|
1343 XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA1
|
1344 XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_STROBE
|
1345 XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_DATA0
|
1346 XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_DATA1
|
1347 XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_STROBE
|
1348 XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_DATA0
|
1349 XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_DATA1
|
1350 XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_STROBE
);
1351 value
|= XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA0
|
1352 XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA1
|
1353 XUSB_PADCTL_HSIC_PAD_CTL0_RPD_STROBE
;
1354 padctl_writel(padctl
, value
, XUSB_PADCTL_HSIC_PADX_CTL0(index
));
1356 err
= clk_prepare_enable(pad
->clk
);
1360 value
= padctl_readl(padctl
, XUSB_PADCTL_HSIC_PAD_TRK_CTL
);
1361 value
&= ~((XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_MASK
<<
1362 XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_SHIFT
) |
1363 (XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_MASK
<<
1364 XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_SHIFT
));
1365 value
|= (XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_VAL
<<
1366 XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_SHIFT
) |
1367 (XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_VAL
<<
1368 XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_SHIFT
);
1369 padctl_writel(padctl
, value
, XUSB_PADCTL_HSIC_PAD_TRK_CTL
);
1373 value
= padctl_readl(padctl
, XUSB_PADCTL_HSIC_PAD_TRK_CTL
);
1374 value
&= ~XUSB_PADCTL_HSIC_PAD_TRK_CTL_PD_TRK
;
1375 padctl_writel(padctl
, value
, XUSB_PADCTL_HSIC_PAD_TRK_CTL
);
1379 clk_disable_unprepare(pad
->clk
);
1384 regulator_disable(pad
->supply
);
1388 static int tegra210_hsic_phy_power_off(struct phy
*phy
)
1390 struct tegra_xusb_lane
*lane
= phy_get_drvdata(phy
);
1391 struct tegra_xusb_hsic_pad
*pad
= to_hsic_pad(lane
->pad
);
1392 struct tegra_xusb_padctl
*padctl
= lane
->pad
->padctl
;
1393 unsigned int index
= lane
->index
;
1396 value
= padctl_readl(padctl
, XUSB_PADCTL_HSIC_PADX_CTL0(index
));
1397 value
|= XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA0
|
1398 XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA1
|
1399 XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_STROBE
|
1400 XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_DATA0
|
1401 XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_DATA1
|
1402 XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_STROBE
|
1403 XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_DATA0
|
1404 XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_DATA1
|
1405 XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_STROBE
;
1406 padctl_writel(padctl
, value
, XUSB_PADCTL_HSIC_PADX_CTL1(index
));
1408 regulator_disable(pad
->supply
);
1413 static const struct phy_ops tegra210_hsic_phy_ops
= {
1414 .init
= tegra210_hsic_phy_init
,
1415 .exit
= tegra210_hsic_phy_exit
,
1416 .power_on
= tegra210_hsic_phy_power_on
,
1417 .power_off
= tegra210_hsic_phy_power_off
,
1418 .owner
= THIS_MODULE
,
1421 static struct tegra_xusb_pad
*
1422 tegra210_hsic_pad_probe(struct tegra_xusb_padctl
*padctl
,
1423 const struct tegra_xusb_pad_soc
*soc
,
1424 struct device_node
*np
)
1426 struct tegra_xusb_hsic_pad
*hsic
;
1427 struct tegra_xusb_pad
*pad
;
1430 hsic
= kzalloc(sizeof(*hsic
), GFP_KERNEL
);
1432 return ERR_PTR(-ENOMEM
);
1435 pad
->ops
= &tegra210_hsic_lane_ops
;
1438 err
= tegra_xusb_pad_init(pad
, padctl
, np
);
1444 hsic
->clk
= devm_clk_get(&pad
->dev
, "trk");
1445 if (IS_ERR(hsic
->clk
)) {
1446 err
= PTR_ERR(hsic
->clk
);
1447 dev_err(&pad
->dev
, "failed to get trk clock: %d\n", err
);
1451 err
= tegra_xusb_pad_register(pad
, &tegra210_hsic_phy_ops
);
1455 dev_set_drvdata(&pad
->dev
, pad
);
1460 device_unregister(&pad
->dev
);
1462 return ERR_PTR(err
);
1465 static void tegra210_hsic_pad_remove(struct tegra_xusb_pad
*pad
)
1467 struct tegra_xusb_hsic_pad
*hsic
= to_hsic_pad(pad
);
1472 static const struct tegra_xusb_pad_ops tegra210_hsic_ops
= {
1473 .probe
= tegra210_hsic_pad_probe
,
1474 .remove
= tegra210_hsic_pad_remove
,
1477 static const struct tegra_xusb_pad_soc tegra210_hsic_pad
= {
1479 .num_lanes
= ARRAY_SIZE(tegra210_hsic_lanes
),
1480 .lanes
= tegra210_hsic_lanes
,
1481 .ops
= &tegra210_hsic_ops
,
1484 static const char *tegra210_pcie_functions
[] = {
1491 static const struct tegra_xusb_lane_soc tegra210_pcie_lanes
[] = {
1492 TEGRA210_LANE("pcie-0", 0x028, 12, 0x3, pcie
),
1493 TEGRA210_LANE("pcie-1", 0x028, 14, 0x3, pcie
),
1494 TEGRA210_LANE("pcie-2", 0x028, 16, 0x3, pcie
),
1495 TEGRA210_LANE("pcie-3", 0x028, 18, 0x3, pcie
),
1496 TEGRA210_LANE("pcie-4", 0x028, 20, 0x3, pcie
),
1497 TEGRA210_LANE("pcie-5", 0x028, 22, 0x3, pcie
),
1498 TEGRA210_LANE("pcie-6", 0x028, 24, 0x3, pcie
),
1501 static struct tegra_xusb_lane
*
1502 tegra210_pcie_lane_probe(struct tegra_xusb_pad
*pad
, struct device_node
*np
,
1505 struct tegra_xusb_pcie_lane
*pcie
;
1508 pcie
= kzalloc(sizeof(*pcie
), GFP_KERNEL
);
1510 return ERR_PTR(-ENOMEM
);
1512 INIT_LIST_HEAD(&pcie
->base
.list
);
1513 pcie
->base
.soc
= &pad
->soc
->lanes
[index
];
1514 pcie
->base
.index
= index
;
1515 pcie
->base
.pad
= pad
;
1518 err
= tegra_xusb_lane_parse_dt(&pcie
->base
, np
);
1521 return ERR_PTR(err
);
1527 static void tegra210_pcie_lane_remove(struct tegra_xusb_lane
*lane
)
1529 struct tegra_xusb_pcie_lane
*pcie
= to_pcie_lane(lane
);
1534 static const struct tegra_xusb_lane_ops tegra210_pcie_lane_ops
= {
1535 .probe
= tegra210_pcie_lane_probe
,
1536 .remove
= tegra210_pcie_lane_remove
,
1539 static int tegra210_pcie_phy_init(struct phy
*phy
)
1541 struct tegra_xusb_lane
*lane
= phy_get_drvdata(phy
);
1543 return tegra210_xusb_padctl_enable(lane
->pad
->padctl
);
1546 static int tegra210_pcie_phy_exit(struct phy
*phy
)
1548 struct tegra_xusb_lane
*lane
= phy_get_drvdata(phy
);
1550 return tegra210_xusb_padctl_disable(lane
->pad
->padctl
);
1553 static int tegra210_pcie_phy_power_on(struct phy
*phy
)
1555 struct tegra_xusb_lane
*lane
= phy_get_drvdata(phy
);
1556 struct tegra_xusb_padctl
*padctl
= lane
->pad
->padctl
;
1560 mutex_lock(&padctl
->lock
);
1562 err
= tegra210_pex_uphy_enable(padctl
);
1566 value
= padctl_readl(padctl
, XUSB_PADCTL_USB3_PAD_MUX
);
1567 value
|= XUSB_PADCTL_USB3_PAD_MUX_PCIE_IDDQ_DISABLE(lane
->index
);
1568 padctl_writel(padctl
, value
, XUSB_PADCTL_USB3_PAD_MUX
);
1571 mutex_unlock(&padctl
->lock
);
1575 static int tegra210_pcie_phy_power_off(struct phy
*phy
)
1577 struct tegra_xusb_lane
*lane
= phy_get_drvdata(phy
);
1578 struct tegra_xusb_padctl
*padctl
= lane
->pad
->padctl
;
1581 value
= padctl_readl(padctl
, XUSB_PADCTL_USB3_PAD_MUX
);
1582 value
&= ~XUSB_PADCTL_USB3_PAD_MUX_PCIE_IDDQ_DISABLE(lane
->index
);
1583 padctl_writel(padctl
, value
, XUSB_PADCTL_USB3_PAD_MUX
);
1585 tegra210_pex_uphy_disable(padctl
);
1590 static const struct phy_ops tegra210_pcie_phy_ops
= {
1591 .init
= tegra210_pcie_phy_init
,
1592 .exit
= tegra210_pcie_phy_exit
,
1593 .power_on
= tegra210_pcie_phy_power_on
,
1594 .power_off
= tegra210_pcie_phy_power_off
,
1595 .owner
= THIS_MODULE
,
1598 static struct tegra_xusb_pad
*
1599 tegra210_pcie_pad_probe(struct tegra_xusb_padctl
*padctl
,
1600 const struct tegra_xusb_pad_soc
*soc
,
1601 struct device_node
*np
)
1603 struct tegra_xusb_pcie_pad
*pcie
;
1604 struct tegra_xusb_pad
*pad
;
1607 pcie
= kzalloc(sizeof(*pcie
), GFP_KERNEL
);
1609 return ERR_PTR(-ENOMEM
);
1612 pad
->ops
= &tegra210_pcie_lane_ops
;
1615 err
= tegra_xusb_pad_init(pad
, padctl
, np
);
1621 pcie
->pll
= devm_clk_get(&pad
->dev
, "pll");
1622 if (IS_ERR(pcie
->pll
)) {
1623 err
= PTR_ERR(pcie
->pll
);
1624 dev_err(&pad
->dev
, "failed to get PLL: %d\n", err
);
1628 pcie
->rst
= devm_reset_control_get(&pad
->dev
, "phy");
1629 if (IS_ERR(pcie
->rst
)) {
1630 err
= PTR_ERR(pcie
->rst
);
1631 dev_err(&pad
->dev
, "failed to get PCIe pad reset: %d\n", err
);
1635 err
= tegra_xusb_pad_register(pad
, &tegra210_pcie_phy_ops
);
1639 dev_set_drvdata(&pad
->dev
, pad
);
1644 device_unregister(&pad
->dev
);
1646 return ERR_PTR(err
);
1649 static void tegra210_pcie_pad_remove(struct tegra_xusb_pad
*pad
)
1651 struct tegra_xusb_pcie_pad
*pcie
= to_pcie_pad(pad
);
1656 static const struct tegra_xusb_pad_ops tegra210_pcie_ops
= {
1657 .probe
= tegra210_pcie_pad_probe
,
1658 .remove
= tegra210_pcie_pad_remove
,
1661 static const struct tegra_xusb_pad_soc tegra210_pcie_pad
= {
1663 .num_lanes
= ARRAY_SIZE(tegra210_pcie_lanes
),
1664 .lanes
= tegra210_pcie_lanes
,
1665 .ops
= &tegra210_pcie_ops
,
1668 static const struct tegra_xusb_lane_soc tegra210_sata_lanes
[] = {
1669 TEGRA210_LANE("sata-0", 0x028, 30, 0x3, pcie
),
1672 static struct tegra_xusb_lane
*
1673 tegra210_sata_lane_probe(struct tegra_xusb_pad
*pad
, struct device_node
*np
,
1676 struct tegra_xusb_sata_lane
*sata
;
1679 sata
= kzalloc(sizeof(*sata
), GFP_KERNEL
);
1681 return ERR_PTR(-ENOMEM
);
1683 INIT_LIST_HEAD(&sata
->base
.list
);
1684 sata
->base
.soc
= &pad
->soc
->lanes
[index
];
1685 sata
->base
.index
= index
;
1686 sata
->base
.pad
= pad
;
1689 err
= tegra_xusb_lane_parse_dt(&sata
->base
, np
);
1692 return ERR_PTR(err
);
1698 static void tegra210_sata_lane_remove(struct tegra_xusb_lane
*lane
)
1700 struct tegra_xusb_sata_lane
*sata
= to_sata_lane(lane
);
1705 static const struct tegra_xusb_lane_ops tegra210_sata_lane_ops
= {
1706 .probe
= tegra210_sata_lane_probe
,
1707 .remove
= tegra210_sata_lane_remove
,
1710 static int tegra210_sata_phy_init(struct phy
*phy
)
1712 struct tegra_xusb_lane
*lane
= phy_get_drvdata(phy
);
1714 return tegra210_xusb_padctl_enable(lane
->pad
->padctl
);
1717 static int tegra210_sata_phy_exit(struct phy
*phy
)
1719 struct tegra_xusb_lane
*lane
= phy_get_drvdata(phy
);
1721 return tegra210_xusb_padctl_disable(lane
->pad
->padctl
);
1724 static int tegra210_sata_phy_power_on(struct phy
*phy
)
1726 struct tegra_xusb_lane
*lane
= phy_get_drvdata(phy
);
1727 struct tegra_xusb_padctl
*padctl
= lane
->pad
->padctl
;
1731 mutex_lock(&padctl
->lock
);
1733 err
= tegra210_sata_uphy_enable(padctl
, false);
1737 value
= padctl_readl(padctl
, XUSB_PADCTL_USB3_PAD_MUX
);
1738 value
|= XUSB_PADCTL_USB3_PAD_MUX_SATA_IDDQ_DISABLE(lane
->index
);
1739 padctl_writel(padctl
, value
, XUSB_PADCTL_USB3_PAD_MUX
);
1742 mutex_unlock(&padctl
->lock
);
1746 static int tegra210_sata_phy_power_off(struct phy
*phy
)
1748 struct tegra_xusb_lane
*lane
= phy_get_drvdata(phy
);
1749 struct tegra_xusb_padctl
*padctl
= lane
->pad
->padctl
;
1752 value
= padctl_readl(padctl
, XUSB_PADCTL_USB3_PAD_MUX
);
1753 value
&= ~XUSB_PADCTL_USB3_PAD_MUX_SATA_IDDQ_DISABLE(lane
->index
);
1754 padctl_writel(padctl
, value
, XUSB_PADCTL_USB3_PAD_MUX
);
1756 tegra210_sata_uphy_disable(lane
->pad
->padctl
);
1761 static const struct phy_ops tegra210_sata_phy_ops
= {
1762 .init
= tegra210_sata_phy_init
,
1763 .exit
= tegra210_sata_phy_exit
,
1764 .power_on
= tegra210_sata_phy_power_on
,
1765 .power_off
= tegra210_sata_phy_power_off
,
1766 .owner
= THIS_MODULE
,
1769 static struct tegra_xusb_pad
*
1770 tegra210_sata_pad_probe(struct tegra_xusb_padctl
*padctl
,
1771 const struct tegra_xusb_pad_soc
*soc
,
1772 struct device_node
*np
)
1774 struct tegra_xusb_sata_pad
*sata
;
1775 struct tegra_xusb_pad
*pad
;
1778 sata
= kzalloc(sizeof(*sata
), GFP_KERNEL
);
1780 return ERR_PTR(-ENOMEM
);
1783 pad
->ops
= &tegra210_sata_lane_ops
;
1786 err
= tegra_xusb_pad_init(pad
, padctl
, np
);
1792 sata
->rst
= devm_reset_control_get(&pad
->dev
, "phy");
1793 if (IS_ERR(sata
->rst
)) {
1794 err
= PTR_ERR(sata
->rst
);
1795 dev_err(&pad
->dev
, "failed to get SATA pad reset: %d\n", err
);
1799 err
= tegra_xusb_pad_register(pad
, &tegra210_sata_phy_ops
);
1803 dev_set_drvdata(&pad
->dev
, pad
);
1808 device_unregister(&pad
->dev
);
1810 return ERR_PTR(err
);
1813 static void tegra210_sata_pad_remove(struct tegra_xusb_pad
*pad
)
1815 struct tegra_xusb_sata_pad
*sata
= to_sata_pad(pad
);
1820 static const struct tegra_xusb_pad_ops tegra210_sata_ops
= {
1821 .probe
= tegra210_sata_pad_probe
,
1822 .remove
= tegra210_sata_pad_remove
,
1825 static const struct tegra_xusb_pad_soc tegra210_sata_pad
= {
1827 .num_lanes
= ARRAY_SIZE(tegra210_sata_lanes
),
1828 .lanes
= tegra210_sata_lanes
,
1829 .ops
= &tegra210_sata_ops
,
1832 static const struct tegra_xusb_pad_soc
* const tegra210_pads
[] = {
1839 static int tegra210_usb2_port_enable(struct tegra_xusb_port
*port
)
1844 static void tegra210_usb2_port_disable(struct tegra_xusb_port
*port
)
1848 static struct tegra_xusb_lane
*
1849 tegra210_usb2_port_map(struct tegra_xusb_port
*port
)
1851 return tegra_xusb_find_lane(port
->padctl
, "usb2", port
->index
);
1854 static const struct tegra_xusb_port_ops tegra210_usb2_port_ops
= {
1855 .enable
= tegra210_usb2_port_enable
,
1856 .disable
= tegra210_usb2_port_disable
,
1857 .map
= tegra210_usb2_port_map
,
1860 static int tegra210_hsic_port_enable(struct tegra_xusb_port
*port
)
1865 static void tegra210_hsic_port_disable(struct tegra_xusb_port
*port
)
1869 static struct tegra_xusb_lane
*
1870 tegra210_hsic_port_map(struct tegra_xusb_port
*port
)
1872 return tegra_xusb_find_lane(port
->padctl
, "hsic", port
->index
);
1875 static const struct tegra_xusb_port_ops tegra210_hsic_port_ops
= {
1876 .enable
= tegra210_hsic_port_enable
,
1877 .disable
= tegra210_hsic_port_disable
,
1878 .map
= tegra210_hsic_port_map
,
1881 static int tegra210_usb3_port_enable(struct tegra_xusb_port
*port
)
1883 struct tegra_xusb_usb3_port
*usb3
= to_usb3_port(port
);
1884 struct tegra_xusb_padctl
*padctl
= port
->padctl
;
1885 struct tegra_xusb_lane
*lane
= usb3
->base
.lane
;
1886 unsigned int index
= port
->index
;
1890 value
= padctl_readl(padctl
, XUSB_PADCTL_SS_PORT_MAP
);
1892 if (!usb3
->internal
)
1893 value
&= ~XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(index
);
1895 value
|= XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(index
);
1897 value
&= ~XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_MASK(index
);
1898 value
|= XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(index
, usb3
->port
);
1899 padctl_writel(padctl
, value
, XUSB_PADCTL_SS_PORT_MAP
);
1902 * TODO: move this code into the PCIe/SATA PHY ->power_on() callbacks
1903 * and conditionalize based on mux function? This seems to work, but
1904 * might not be the exact proper sequence.
1906 err
= regulator_enable(usb3
->supply
);
1910 value
= padctl_readl(padctl
, XUSB_PADCTL_UPHY_USB3_PADX_ECTL1(index
));
1911 value
&= ~(XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_MASK
<<
1912 XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_SHIFT
);
1913 value
|= XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_VAL
<<
1914 XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_SHIFT
;
1915 padctl_writel(padctl
, value
, XUSB_PADCTL_UPHY_USB3_PADX_ECTL1(index
));
1917 value
= padctl_readl(padctl
, XUSB_PADCTL_UPHY_USB3_PADX_ECTL2(index
));
1918 value
&= ~(XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_MASK
<<
1919 XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_SHIFT
);
1920 value
|= XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_VAL
<<
1921 XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_SHIFT
;
1922 padctl_writel(padctl
, value
, XUSB_PADCTL_UPHY_USB3_PADX_ECTL2(index
));
1924 padctl_writel(padctl
, XUSB_PADCTL_UPHY_USB3_PAD_ECTL3_RX_DFE_VAL
,
1925 XUSB_PADCTL_UPHY_USB3_PADX_ECTL3(index
));
1927 value
= padctl_readl(padctl
, XUSB_PADCTL_UPHY_USB3_PADX_ECTL4(index
));
1928 value
&= ~(XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_MASK
<<
1929 XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_SHIFT
);
1930 value
|= XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_VAL
<<
1931 XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_SHIFT
;
1932 padctl_writel(padctl
, value
, XUSB_PADCTL_UPHY_USB3_PADX_ECTL4(index
));
1934 padctl_writel(padctl
, XUSB_PADCTL_UPHY_USB3_PAD_ECTL6_RX_EQ_CTRL_H_VAL
,
1935 XUSB_PADCTL_UPHY_USB3_PADX_ECTL6(index
));
1937 if (lane
->pad
== padctl
->sata
)
1938 err
= tegra210_sata_uphy_enable(padctl
, true);
1940 err
= tegra210_pex_uphy_enable(padctl
);
1943 dev_err(&port
->dev
, "%s: failed to enable UPHY: %d\n",
1948 value
= padctl_readl(padctl
, XUSB_PADCTL_ELPG_PROGRAM1
);
1949 value
&= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_VCORE_DOWN(index
);
1950 padctl_writel(padctl
, value
, XUSB_PADCTL_ELPG_PROGRAM1
);
1952 usleep_range(100, 200);
1954 value
= padctl_readl(padctl
, XUSB_PADCTL_ELPG_PROGRAM1
);
1955 value
&= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY(index
);
1956 padctl_writel(padctl
, value
, XUSB_PADCTL_ELPG_PROGRAM1
);
1958 usleep_range(100, 200);
1960 value
= padctl_readl(padctl
, XUSB_PADCTL_ELPG_PROGRAM1
);
1961 value
&= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN(index
);
1962 padctl_writel(padctl
, value
, XUSB_PADCTL_ELPG_PROGRAM1
);
1967 static void tegra210_usb3_port_disable(struct tegra_xusb_port
*port
)
1969 struct tegra_xusb_usb3_port
*usb3
= to_usb3_port(port
);
1970 struct tegra_xusb_padctl
*padctl
= port
->padctl
;
1971 struct tegra_xusb_lane
*lane
= port
->lane
;
1972 unsigned int index
= port
->index
;
1975 value
= padctl_readl(padctl
, XUSB_PADCTL_ELPG_PROGRAM1
);
1976 value
|= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY(index
);
1977 padctl_writel(padctl
, value
, XUSB_PADCTL_ELPG_PROGRAM1
);
1979 usleep_range(100, 200);
1981 value
= padctl_readl(padctl
, XUSB_PADCTL_ELPG_PROGRAM1
);
1982 value
|= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN(index
);
1983 padctl_writel(padctl
, value
, XUSB_PADCTL_ELPG_PROGRAM1
);
1985 usleep_range(250, 350);
1987 value
= padctl_readl(padctl
, XUSB_PADCTL_ELPG_PROGRAM1
);
1988 value
|= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_VCORE_DOWN(index
);
1989 padctl_writel(padctl
, value
, XUSB_PADCTL_ELPG_PROGRAM1
);
1991 if (lane
->pad
== padctl
->sata
)
1992 tegra210_sata_uphy_disable(padctl
);
1994 tegra210_pex_uphy_disable(padctl
);
1996 regulator_disable(usb3
->supply
);
1998 value
= padctl_readl(padctl
, XUSB_PADCTL_SS_PORT_MAP
);
1999 value
&= ~XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_MASK(index
);
2000 value
|= XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(index
, 0x7);
2001 padctl_writel(padctl
, value
, XUSB_PADCTL_SS_PORT_MAP
);
2004 static const struct tegra_xusb_lane_map tegra210_usb3_map
[] = {
2014 static struct tegra_xusb_lane
*
2015 tegra210_usb3_port_map(struct tegra_xusb_port
*port
)
2017 return tegra_xusb_port_find_lane(port
, tegra210_usb3_map
, "usb3-ss");
2020 static const struct tegra_xusb_port_ops tegra210_usb3_port_ops
= {
2021 .enable
= tegra210_usb3_port_enable
,
2022 .disable
= tegra210_usb3_port_disable
,
2023 .map
= tegra210_usb3_port_map
,
2026 static int tegra210_xusb_padctl_vbus_override(struct tegra_xusb_padctl
*padctl
,
2031 dev_dbg(padctl
->dev
, "%s vbus override\n", status
? "set" : "clear");
2033 value
= padctl_readl(padctl
, XUSB_PADCTL_USB2_VBUS_ID
);
2036 value
|= XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_VBUS_ON
;
2037 value
&= ~(XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_MASK
<<
2038 XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_SHIFT
);
2039 value
|= XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_FLOATING
<<
2040 XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_SHIFT
;
2042 value
&= ~XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_VBUS_ON
;
2045 padctl_writel(padctl
, value
, XUSB_PADCTL_USB2_VBUS_ID
);
2050 static int tegra210_utmi_port_reset(struct phy
*phy
)
2052 struct tegra_xusb_padctl
*padctl
;
2053 struct tegra_xusb_lane
*lane
;
2056 lane
= phy_get_drvdata(phy
);
2057 padctl
= lane
->pad
->padctl
;
2059 value
= padctl_readl(padctl
,
2060 XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADX_CTL0(lane
->index
));
2062 if ((value
& XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL0_ZIP
) ||
2063 (value
& XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL0_ZIN
)) {
2064 tegra210_xusb_padctl_vbus_override(padctl
, false);
2065 tegra210_xusb_padctl_vbus_override(padctl
, true);
2073 tegra210_xusb_read_fuse_calibration(struct tegra210_xusb_fuse_calibration
*fuse
)
2079 err
= tegra_fuse_readl(TEGRA_FUSE_SKU_CALIB_0
, &value
);
2083 for (i
= 0; i
< ARRAY_SIZE(fuse
->hs_curr_level
); i
++) {
2084 fuse
->hs_curr_level
[i
] =
2085 (value
>> FUSE_SKU_CALIB_HS_CURR_LEVEL_PADX_SHIFT(i
)) &
2086 FUSE_SKU_CALIB_HS_CURR_LEVEL_PAD_MASK
;
2089 fuse
->hs_term_range_adj
=
2090 (value
>> FUSE_SKU_CALIB_HS_TERM_RANGE_ADJ_SHIFT
) &
2091 FUSE_SKU_CALIB_HS_TERM_RANGE_ADJ_MASK
;
2093 err
= tegra_fuse_readl(TEGRA_FUSE_USB_CALIB_EXT_0
, &value
);
2098 (value
>> FUSE_USB_CALIB_EXT_RPD_CTRL_SHIFT
) &
2099 FUSE_USB_CALIB_EXT_RPD_CTRL_MASK
;
2104 static struct tegra_xusb_padctl
*
2105 tegra210_xusb_padctl_probe(struct device
*dev
,
2106 const struct tegra_xusb_padctl_soc
*soc
)
2108 struct tegra210_xusb_padctl
*padctl
;
2111 padctl
= devm_kzalloc(dev
, sizeof(*padctl
), GFP_KERNEL
);
2113 return ERR_PTR(-ENOMEM
);
2115 padctl
->base
.dev
= dev
;
2116 padctl
->base
.soc
= soc
;
2118 err
= tegra210_xusb_read_fuse_calibration(&padctl
->fuse
);
2120 return ERR_PTR(err
);
2122 return &padctl
->base
;
2125 static void tegra210_xusb_padctl_remove(struct tegra_xusb_padctl
*padctl
)
2129 static const struct tegra_xusb_padctl_ops tegra210_xusb_padctl_ops
= {
2130 .probe
= tegra210_xusb_padctl_probe
,
2131 .remove
= tegra210_xusb_padctl_remove
,
2132 .usb3_set_lfps_detect
= tegra210_usb3_set_lfps_detect
,
2133 .hsic_set_idle
= tegra210_hsic_set_idle
,
2134 .vbus_override
= tegra210_xusb_padctl_vbus_override
,
2135 .utmi_port_reset
= tegra210_utmi_port_reset
,
2138 static const char * const tegra210_xusb_padctl_supply_names
[] = {
2145 const struct tegra_xusb_padctl_soc tegra210_xusb_padctl_soc
= {
2146 .num_pads
= ARRAY_SIZE(tegra210_pads
),
2147 .pads
= tegra210_pads
,
2150 .ops
= &tegra210_usb2_port_ops
,
2154 .ops
= &tegra210_hsic_port_ops
,
2158 .ops
= &tegra210_usb3_port_ops
,
2162 .ops
= &tegra210_xusb_padctl_ops
,
2163 .supply_names
= tegra210_xusb_padctl_supply_names
,
2164 .num_supplies
= ARRAY_SIZE(tegra210_xusb_padctl_supply_names
),
2165 .need_fake_usb3_port
= true,
2167 EXPORT_SYMBOL_GPL(tegra210_xusb_padctl_soc
);
2169 MODULE_AUTHOR("Andrew Bresticker <abrestic@chromium.org>");
2170 MODULE_DESCRIPTION("NVIDIA Tegra 210 XUSB Pad Controller driver");
2171 MODULE_LICENSE("GPL v2");