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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / phy / ti / phy-ti-pipe3.c
bloba87946589eb785ca3762ca6a4c8baa16365e64ad
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * phy-ti-pipe3 - PIPE3 PHY driver.
4 *
5 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
6 * Author: Kishon Vijay Abraham I <kishon@ti.com>
7 */
8
9 #include <linux/module.h>
10 #include <linux/platform_device.h>
11 #include <linux/slab.h>
12 #include <linux/phy/phy.h>
13 #include <linux/of.h>
14 #include <linux/clk.h>
15 #include <linux/err.h>
16 #include <linux/io.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/delay.h>
19 #include <linux/phy/omap_control_phy.h>
20 #include <linux/of_platform.h>
21 #include <linux/mfd/syscon.h>
22 #include <linux/regmap.h>
23
24 #define PLL_STATUS 0x00000004
25 #define PLL_GO 0x00000008
26 #define PLL_CONFIGURATION1 0x0000000C
27 #define PLL_CONFIGURATION2 0x00000010
28 #define PLL_CONFIGURATION3 0x00000014
29 #define PLL_CONFIGURATION4 0x00000020
30
31 #define PLL_REGM_MASK 0x001FFE00
32 #define PLL_REGM_SHIFT 0x9
33 #define PLL_REGM_F_MASK 0x0003FFFF
34 #define PLL_REGM_F_SHIFT 0x0
35 #define PLL_REGN_MASK 0x000001FE
36 #define PLL_REGN_SHIFT 0x1
37 #define PLL_SELFREQDCO_MASK 0x0000000E
38 #define PLL_SELFREQDCO_SHIFT 0x1
39 #define PLL_SD_MASK 0x0003FC00
40 #define PLL_SD_SHIFT 10
41 #define SET_PLL_GO 0x1
42 #define PLL_LDOPWDN BIT(15)
43 #define PLL_TICOPWDN BIT(16)
44 #define PLL_LOCK 0x2
45 #define PLL_IDLE 0x1
46
47 #define SATA_PLL_SOFT_RESET BIT(18)
48
49 #define PIPE3_PHY_PWRCTL_CLK_CMD_MASK GENMASK(21, 14)
50 #define PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT 14
51
52 #define PIPE3_PHY_PWRCTL_CLK_FREQ_MASK GENMASK(31, 22)
53 #define PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT 22
54
55 #define PIPE3_PHY_RX_POWERON (0x1 << PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT)
56 #define PIPE3_PHY_TX_POWERON (0x2 << PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT)
57
58 #define PCIE_PCS_MASK 0xFF0000
59 #define PCIE_PCS_DELAY_COUNT_SHIFT 0x10
60
61 #define PIPE3_PHY_RX_ANA_PROGRAMMABILITY 0x0000000C
62 #define INTERFACE_MASK GENMASK(31, 27)
63 #define INTERFACE_SHIFT 27
64 #define INTERFACE_MODE_USBSS BIT(4)
65 #define INTERFACE_MODE_SATA_1P5 BIT(3)
66 #define INTERFACE_MODE_SATA_3P0 BIT(2)
67 #define INTERFACE_MODE_PCIE BIT(0)
68
69 #define LOSD_MASK GENMASK(17, 14)
70 #define LOSD_SHIFT 14
71 #define MEM_PLLDIV GENMASK(6, 5)
72
73 #define PIPE3_PHY_RX_TRIM 0x0000001C
74 #define MEM_DLL_TRIM_SEL_MASK GENMASK(31, 30)
75 #define MEM_DLL_TRIM_SHIFT 30
76
77 #define PIPE3_PHY_RX_DLL 0x00000024
78 #define MEM_DLL_PHINT_RATE_MASK GENMASK(31, 30)
79 #define MEM_DLL_PHINT_RATE_SHIFT 30
80
81 #define PIPE3_PHY_RX_DIGITAL_MODES 0x00000028
82 #define MEM_HS_RATE_MASK GENMASK(28, 27)
83 #define MEM_HS_RATE_SHIFT 27
84 #define MEM_OVRD_HS_RATE BIT(26)
85 #define MEM_OVRD_HS_RATE_SHIFT 26
86 #define MEM_CDR_FASTLOCK BIT(23)
87 #define MEM_CDR_FASTLOCK_SHIFT 23
88 #define MEM_CDR_LBW_MASK GENMASK(22, 21)
89 #define MEM_CDR_LBW_SHIFT 21
90 #define MEM_CDR_STEPCNT_MASK GENMASK(20, 19)
91 #define MEM_CDR_STEPCNT_SHIFT 19
92 #define MEM_CDR_STL_MASK GENMASK(18, 16)
93 #define MEM_CDR_STL_SHIFT 16
94 #define MEM_CDR_THR_MASK GENMASK(15, 13)
95 #define MEM_CDR_THR_SHIFT 13
96 #define MEM_CDR_THR_MODE BIT(12)
97 #define MEM_CDR_THR_MODE_SHIFT 12
98 #define MEM_CDR_2NDO_SDM_MODE BIT(11)
99 #define MEM_CDR_2NDO_SDM_MODE_SHIFT 11
100
101 #define PIPE3_PHY_RX_EQUALIZER 0x00000038
102 #define MEM_EQLEV_MASK GENMASK(31, 16)
103 #define MEM_EQLEV_SHIFT 16
104 #define MEM_EQFTC_MASK GENMASK(15, 11)
105 #define MEM_EQFTC_SHIFT 11
106 #define MEM_EQCTL_MASK GENMASK(10, 7)
107 #define MEM_EQCTL_SHIFT 7
108 #define MEM_OVRD_EQLEV BIT(2)
109 #define MEM_OVRD_EQLEV_SHIFT 2
110 #define MEM_OVRD_EQFTC BIT(1)
111 #define MEM_OVRD_EQFTC_SHIFT 1
112
113 #define SATA_PHY_RX_IO_AND_A2D_OVERRIDES 0x44
114 #define MEM_CDR_LOS_SOURCE_MASK GENMASK(10, 9)
115 #define MEM_CDR_LOS_SOURCE_SHIFT 9
116
117 /*
118 * This is an Empirical value that works, need to confirm the actual
119 * value required for the PIPE3PHY_PLL_CONFIGURATION2.PLL_IDLE status
120 * to be correctly reflected in the PIPE3PHY_PLL_STATUS register.
121 */
122 #define PLL_IDLE_TIME 100 /* in milliseconds */
123 #define PLL_LOCK_TIME 100 /* in milliseconds */
124
125 enum pipe3_mode { PIPE3_MODE_PCIE = 1,
126 PIPE3_MODE_SATA,
127 PIPE3_MODE_USBSS };
128
129 struct pipe3_dpll_params {
130 u16 m;
131 u8 n;
132 u8 freq:3;
133 u8 sd;
134 u32 mf;
135 };
136
137 struct pipe3_dpll_map {
138 unsigned long rate;
139 struct pipe3_dpll_params params;
140 };
141
142 struct pipe3_settings {
143 u8 ana_interface;
144 u8 ana_losd;
145 u8 dig_fastlock;
146 u8 dig_lbw;
147 u8 dig_stepcnt;
148 u8 dig_stl;
149 u8 dig_thr;
150 u8 dig_thr_mode;
151 u8 dig_2ndo_sdm_mode;
152 u8 dig_hs_rate;
153 u8 dig_ovrd_hs_rate;
154 u8 dll_trim_sel;
155 u8 dll_phint_rate;
156 u8 eq_lev;
157 u8 eq_ftc;
158 u8 eq_ctl;
159 u8 eq_ovrd_lev;
160 u8 eq_ovrd_ftc;
161 };
162
163 struct ti_pipe3 {
164 void __iomem *pll_ctrl_base;
165 void __iomem *phy_rx;
166 void __iomem *phy_tx;
167 struct device *dev;
168 struct device *control_dev;
169 struct clk *wkupclk;
170 struct clk *sys_clk;
171 struct clk *refclk;
172 struct clk *div_clk;
173 struct pipe3_dpll_map *dpll_map;
174 struct regmap *phy_power_syscon; /* ctrl. reg. acces */
175 struct regmap *pcs_syscon; /* ctrl. reg. acces */
176 struct regmap *dpll_reset_syscon; /* ctrl. reg. acces */
177 unsigned int dpll_reset_reg; /* reg. index within syscon */
178 unsigned int power_reg; /* power reg. index within syscon */
179 unsigned int pcie_pcs_reg; /* pcs reg. index in syscon */
180 bool sata_refclk_enabled;
181 enum pipe3_mode mode;
182 struct pipe3_settings settings;
183 };
184
185 static struct pipe3_dpll_map dpll_map_usb[] = {
186 {12000000, {1250, 5, 4, 20, 0} }, /* 12 MHz */
187 {16800000, {3125, 20, 4, 20, 0} }, /* 16.8 MHz */
188 {19200000, {1172, 8, 4, 20, 65537} }, /* 19.2 MHz */
189 {20000000, {1000, 7, 4, 10, 0} }, /* 20 MHz */
190 {26000000, {1250, 12, 4, 20, 0} }, /* 26 MHz */
191 {38400000, {3125, 47, 4, 20, 92843} }, /* 38.4 MHz */
192 { }, /* Terminator */
193 };
194
195 static struct pipe3_dpll_map dpll_map_sata[] = {
196 {12000000, {625, 4, 4, 6, 0} }, /* 12 MHz */
197 {16800000, {625, 6, 4, 7, 0} }, /* 16.8 MHz */
198 {19200000, {625, 7, 4, 6, 0} }, /* 19.2 MHz */
199 {20000000, {750, 9, 4, 6, 0} }, /* 20 MHz */
200 {26000000, {750, 12, 4, 6, 0} }, /* 26 MHz */
201 {38400000, {625, 15, 4, 6, 0} }, /* 38.4 MHz */
202 { }, /* Terminator */
203 };
204
205 struct pipe3_data {
206 enum pipe3_mode mode;
207 struct pipe3_dpll_map *dpll_map;
208 struct pipe3_settings settings;
209 };
210
211 static struct pipe3_data data_usb = {
212 .mode = PIPE3_MODE_USBSS,
213 .dpll_map = dpll_map_usb,
214 .settings = {
215 /* DRA75x TRM Table 26-17 Preferred USB3_PHY_RX SCP Register Settings */
216 .ana_interface = INTERFACE_MODE_USBSS,
217 .ana_losd = 0xa,
218 .dig_fastlock = 1,
219 .dig_lbw = 3,
220 .dig_stepcnt = 0,
221 .dig_stl = 0x3,
222 .dig_thr = 1,
223 .dig_thr_mode = 1,
224 .dig_2ndo_sdm_mode = 0,
225 .dig_hs_rate = 0,
226 .dig_ovrd_hs_rate = 1,
227 .dll_trim_sel = 0x2,
228 .dll_phint_rate = 0x3,
229 .eq_lev = 0,
230 .eq_ftc = 0,
231 .eq_ctl = 0x9,
232 .eq_ovrd_lev = 0,
233 .eq_ovrd_ftc = 0,
234 },
235 };
236
237 static struct pipe3_data data_sata = {
238 .mode = PIPE3_MODE_SATA,
239 .dpll_map = dpll_map_sata,
240 .settings = {
241 /* DRA75x TRM Table 26-9 Preferred SATA_PHY_RX SCP Register Settings */
242 .ana_interface = INTERFACE_MODE_SATA_3P0,
243 .ana_losd = 0x5,
244 .dig_fastlock = 1,
245 .dig_lbw = 3,
246 .dig_stepcnt = 0,
247 .dig_stl = 0x3,
248 .dig_thr = 1,
249 .dig_thr_mode = 1,
250 .dig_2ndo_sdm_mode = 0,
251 .dig_hs_rate = 0, /* Not in TRM preferred settings */
252 .dig_ovrd_hs_rate = 0, /* Not in TRM preferred settings */
253 .dll_trim_sel = 0x1,
254 .dll_phint_rate = 0x2, /* for 1.5 GHz DPLL clock */
255 .eq_lev = 0,
256 .eq_ftc = 0x1f,
257 .eq_ctl = 0,
258 .eq_ovrd_lev = 1,
259 .eq_ovrd_ftc = 1,
260 },
261 };
262
263 static struct pipe3_data data_pcie = {
264 .mode = PIPE3_MODE_PCIE,
265 .settings = {
266 /* DRA75x TRM Table 26-62 Preferred PCIe_PHY_RX SCP Register Settings */
267 .ana_interface = INTERFACE_MODE_PCIE,
268 .ana_losd = 0xa,
269 .dig_fastlock = 1,
270 .dig_lbw = 3,
271 .dig_stepcnt = 0,
272 .dig_stl = 0x3,
273 .dig_thr = 1,
274 .dig_thr_mode = 1,
275 .dig_2ndo_sdm_mode = 0,
276 .dig_hs_rate = 0,
277 .dig_ovrd_hs_rate = 0,
278 .dll_trim_sel = 0x2,
279 .dll_phint_rate = 0x3,
280 .eq_lev = 0,
281 .eq_ftc = 0x1f,
282 .eq_ctl = 1,
283 .eq_ovrd_lev = 0,
284 .eq_ovrd_ftc = 0,
285 },
286 };
287
288 static inline u32 ti_pipe3_readl(void __iomem *addr, unsigned offset)
289 {
290 return __raw_readl(addr + offset);
291 }
292
293 static inline void ti_pipe3_writel(void __iomem *addr, unsigned offset,
294 u32 data)
295 {
296 __raw_writel(data, addr + offset);
297 }
298
299 static struct pipe3_dpll_params *ti_pipe3_get_dpll_params(struct ti_pipe3 *phy)
300 {
301 unsigned long rate;
302 struct pipe3_dpll_map *dpll_map = phy->dpll_map;
303
304 rate = clk_get_rate(phy->sys_clk);
305
306 for (; dpll_map->rate; dpll_map++) {
307 if (rate == dpll_map->rate)
308 return &dpll_map->params;
309 }
310
311 dev_err(phy->dev, "No DPLL configuration for %lu Hz SYS CLK\n", rate);
312
313 return NULL;
314 }
315
316 static int ti_pipe3_enable_clocks(struct ti_pipe3 *phy);
317 static void ti_pipe3_disable_clocks(struct ti_pipe3 *phy);
318
319 static int ti_pipe3_power_off(struct phy *x)
320 {
321 int ret;
322 struct ti_pipe3 *phy = phy_get_drvdata(x);
323
324 if (!phy->phy_power_syscon) {
325 omap_control_phy_power(phy->control_dev, 0);
326 return 0;
327 }
328
329 ret = regmap_update_bits(phy->phy_power_syscon, phy->power_reg,
330 PIPE3_PHY_PWRCTL_CLK_CMD_MASK, 0);
331 return ret;
332 }
333
334 static void ti_pipe3_calibrate(struct ti_pipe3 *phy);
335
336 static int ti_pipe3_power_on(struct phy *x)
337 {
338 u32 val;
339 u32 mask;
340 int ret;
341 unsigned long rate;
342 struct ti_pipe3 *phy = phy_get_drvdata(x);
343 bool rx_pending = false;
344
345 if (!phy->phy_power_syscon) {
346 omap_control_phy_power(phy->control_dev, 1);
347 return 0;
348 }
349
350 rate = clk_get_rate(phy->sys_clk);
351 if (!rate) {
352 dev_err(phy->dev, "Invalid clock rate\n");
353 return -EINVAL;
354 }
355 rate = rate / 1000000;
356 mask = OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK;
357 val = rate << OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT;
358 ret = regmap_update_bits(phy->phy_power_syscon, phy->power_reg,
359 mask, val);
360 /*
361 * For PCIe, TX and RX must be powered on simultaneously.
362 * For USB and SATA, TX must be powered on before RX
363 */
364 mask = OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK;
365 if (phy->mode == PIPE3_MODE_SATA || phy->mode == PIPE3_MODE_USBSS) {
366 val = PIPE3_PHY_TX_POWERON;
367 rx_pending = true;
368 } else {
369 val = PIPE3_PHY_TX_POWERON | PIPE3_PHY_RX_POWERON;
370 }
371
372 regmap_update_bits(phy->phy_power_syscon, phy->power_reg,
373 mask, val);
374
375 if (rx_pending) {
376 val = PIPE3_PHY_TX_POWERON | PIPE3_PHY_RX_POWERON;
377 regmap_update_bits(phy->phy_power_syscon, phy->power_reg,
378 mask, val);
379 }
380
381 if (phy->mode == PIPE3_MODE_PCIE)
382 ti_pipe3_calibrate(phy);
383
384 return 0;
385 }
386
387 static int ti_pipe3_dpll_wait_lock(struct ti_pipe3 *phy)
388 {
389 u32 val;
390 unsigned long timeout;
391
392 timeout = jiffies + msecs_to_jiffies(PLL_LOCK_TIME);
393 do {
394 cpu_relax();
395 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
396 if (val & PLL_LOCK)
397 return 0;
398 } while (!time_after(jiffies, timeout));
399
400 dev_err(phy->dev, "DPLL failed to lock\n");
401 return -EBUSY;
402 }
403
404 static int ti_pipe3_dpll_program(struct ti_pipe3 *phy)
405 {
406 u32 val;
407 struct pipe3_dpll_params *dpll_params;
408
409 dpll_params = ti_pipe3_get_dpll_params(phy);
410 if (!dpll_params)
411 return -EINVAL;
412
413 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
414 val &= ~PLL_REGN_MASK;
415 val |= dpll_params->n << PLL_REGN_SHIFT;
416 ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
417
418 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
419 val &= ~PLL_SELFREQDCO_MASK;
420 val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT;
421 ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
422
423 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
424 val &= ~PLL_REGM_MASK;
425 val |= dpll_params->m << PLL_REGM_SHIFT;
426 ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
427
428 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION4);
429 val &= ~PLL_REGM_F_MASK;
430 val |= dpll_params->mf << PLL_REGM_F_SHIFT;
431 ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION4, val);
432
433 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION3);
434 val &= ~PLL_SD_MASK;
435 val |= dpll_params->sd << PLL_SD_SHIFT;
436 ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION3, val);
437
438 ti_pipe3_writel(phy->pll_ctrl_base, PLL_GO, SET_PLL_GO);
439
440 return ti_pipe3_dpll_wait_lock(phy);
441 }
442
443 static void ti_pipe3_calibrate(struct ti_pipe3 *phy)
444 {
445 u32 val;
446 struct pipe3_settings *s = &phy->settings;
447
448 val = ti_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_ANA_PROGRAMMABILITY);
449 val &= ~(INTERFACE_MASK | LOSD_MASK | MEM_PLLDIV);
450 val |= (s->ana_interface << INTERFACE_SHIFT | s->ana_losd << LOSD_SHIFT);
451 ti_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_ANA_PROGRAMMABILITY, val);
452
453 val = ti_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_DIGITAL_MODES);
454 val &= ~(MEM_HS_RATE_MASK | MEM_OVRD_HS_RATE | MEM_CDR_FASTLOCK |
455 MEM_CDR_LBW_MASK | MEM_CDR_STEPCNT_MASK | MEM_CDR_STL_MASK |
456 MEM_CDR_THR_MASK | MEM_CDR_THR_MODE | MEM_CDR_2NDO_SDM_MODE);
457 val |= s->dig_hs_rate << MEM_HS_RATE_SHIFT |
458 s->dig_ovrd_hs_rate << MEM_OVRD_HS_RATE_SHIFT |
459 s->dig_fastlock << MEM_CDR_FASTLOCK_SHIFT |
460 s->dig_lbw << MEM_CDR_LBW_SHIFT |
461 s->dig_stepcnt << MEM_CDR_STEPCNT_SHIFT |
462 s->dig_stl << MEM_CDR_STL_SHIFT |
463 s->dig_thr << MEM_CDR_THR_SHIFT |
464 s->dig_thr_mode << MEM_CDR_THR_MODE_SHIFT |
465 s->dig_2ndo_sdm_mode << MEM_CDR_2NDO_SDM_MODE_SHIFT;
466 ti_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_DIGITAL_MODES, val);
467
468 val = ti_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_TRIM);
469 val &= ~MEM_DLL_TRIM_SEL_MASK;
470 val |= s->dll_trim_sel << MEM_DLL_TRIM_SHIFT;
471 ti_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_TRIM, val);
472
473 val = ti_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_DLL);
474 val &= ~MEM_DLL_PHINT_RATE_MASK;
475 val |= s->dll_phint_rate << MEM_DLL_PHINT_RATE_SHIFT;
476 ti_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_DLL, val);
477
478 val = ti_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_EQUALIZER);
479 val &= ~(MEM_EQLEV_MASK | MEM_EQFTC_MASK | MEM_EQCTL_MASK |
480 MEM_OVRD_EQLEV | MEM_OVRD_EQFTC);
481 val |= s->eq_lev << MEM_EQLEV_SHIFT |
482 s->eq_ftc << MEM_EQFTC_SHIFT |
483 s->eq_ctl << MEM_EQCTL_SHIFT |
484 s->eq_ovrd_lev << MEM_OVRD_EQLEV_SHIFT |
485 s->eq_ovrd_ftc << MEM_OVRD_EQFTC_SHIFT;
486 ti_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_EQUALIZER, val);
487
488 if (phy->mode == PIPE3_MODE_SATA) {
489 val = ti_pipe3_readl(phy->phy_rx,
490 SATA_PHY_RX_IO_AND_A2D_OVERRIDES);
491 val &= ~MEM_CDR_LOS_SOURCE_MASK;
492 ti_pipe3_writel(phy->phy_rx, SATA_PHY_RX_IO_AND_A2D_OVERRIDES,
493 val);
494 }
495 }
496
497 static int ti_pipe3_init(struct phy *x)
498 {
499 struct ti_pipe3 *phy = phy_get_drvdata(x);
500 u32 val;
501 int ret = 0;
502
503 ti_pipe3_enable_clocks(phy);
504 /*
505 * Set pcie_pcs register to 0x96 for proper functioning of phy
506 * as recommended in AM572x TRM SPRUHZ6, section 18.5.2.2, table
507 * 18-1804.
508 */
509 if (phy->mode == PIPE3_MODE_PCIE) {
510 if (!phy->pcs_syscon) {
511 omap_control_pcie_pcs(phy->control_dev, 0x96);
512 return 0;
513 }
514
515 val = 0x96 << OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT;
516 ret = regmap_update_bits(phy->pcs_syscon, phy->pcie_pcs_reg,
517 PCIE_PCS_MASK, val);
518 return ret;
519 }
520
521 /* Bring it out of IDLE if it is IDLE */
522 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
523 if (val & PLL_IDLE) {
524 val &= ~PLL_IDLE;
525 ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
526 ret = ti_pipe3_dpll_wait_lock(phy);
527 }
528
529 /* SATA has issues if re-programmed when locked */
530 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
531 if ((val & PLL_LOCK) && phy->mode == PIPE3_MODE_SATA)
532 return ret;
533
534 /* Program the DPLL */
535 ret = ti_pipe3_dpll_program(phy);
536 if (ret) {
537 ti_pipe3_disable_clocks(phy);
538 return -EINVAL;
539 }
540
541 ti_pipe3_calibrate(phy);
542
543 return ret;
544 }
545
546 static int ti_pipe3_exit(struct phy *x)
547 {
548 struct ti_pipe3 *phy = phy_get_drvdata(x);
549 u32 val;
550 unsigned long timeout;
551
552 /* If dpll_reset_syscon is not present we wont power down SATA DPLL
553 * due to Errata i783
554 */
555 if (phy->mode == PIPE3_MODE_SATA && !phy->dpll_reset_syscon)
556 return 0;
557
558 /* PCIe doesn't have internal DPLL */
559 if (phy->mode != PIPE3_MODE_PCIE) {
560 /* Put DPLL in IDLE mode */
561 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
562 val |= PLL_IDLE;
563 ti_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
564
565 /* wait for LDO and Oscillator to power down */
566 timeout = jiffies + msecs_to_jiffies(PLL_IDLE_TIME);
567 do {
568 cpu_relax();
569 val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
570 if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN))
571 break;
572 } while (!time_after(jiffies, timeout));
573
574 if (!(val & PLL_TICOPWDN) || !(val & PLL_LDOPWDN)) {
575 dev_err(phy->dev, "Failed to power down: PLL_STATUS 0x%x\n",
576 val);
577 return -EBUSY;
578 }
579 }
580
581 /* i783: SATA needs control bit toggle after PLL unlock */
582 if (phy->mode == PIPE3_MODE_SATA) {
583 regmap_update_bits(phy->dpll_reset_syscon, phy->dpll_reset_reg,
584 SATA_PLL_SOFT_RESET, SATA_PLL_SOFT_RESET);
585 regmap_update_bits(phy->dpll_reset_syscon, phy->dpll_reset_reg,
586 SATA_PLL_SOFT_RESET, 0);
587 }
588
589 ti_pipe3_disable_clocks(phy);
590
591 return 0;
592 }
593 static const struct phy_ops ops = {
594 .init = ti_pipe3_init,
595 .exit = ti_pipe3_exit,
596 .power_on = ti_pipe3_power_on,
597 .power_off = ti_pipe3_power_off,
598 .owner = THIS_MODULE,
599 };
600
601 static const struct of_device_id ti_pipe3_id_table[];
602
603 static int ti_pipe3_get_clk(struct ti_pipe3 *phy)
604 {
605 struct clk *clk;
606 struct device *dev = phy->dev;
607
608 phy->refclk = devm_clk_get(dev, "refclk");
609 if (IS_ERR(phy->refclk)) {
610 dev_err(dev, "unable to get refclk\n");
611 /* older DTBs have missing refclk in SATA PHY
612 * so don't bail out in case of SATA PHY.
613 */
614 if (phy->mode != PIPE3_MODE_SATA)
615 return PTR_ERR(phy->refclk);
616 }
617
618 if (phy->mode != PIPE3_MODE_SATA) {
619 phy->wkupclk = devm_clk_get(dev, "wkupclk");
620 if (IS_ERR(phy->wkupclk)) {
621 dev_err(dev, "unable to get wkupclk\n");
622 return PTR_ERR(phy->wkupclk);
623 }
624 } else {
625 phy->wkupclk = ERR_PTR(-ENODEV);
626 }
627
628 if (phy->mode != PIPE3_MODE_PCIE || phy->phy_power_syscon) {
629 phy->sys_clk = devm_clk_get(dev, "sysclk");
630 if (IS_ERR(phy->sys_clk)) {
631 dev_err(dev, "unable to get sysclk\n");
632 return -EINVAL;
633 }
634 }
635
636 if (phy->mode == PIPE3_MODE_PCIE) {
637 clk = devm_clk_get(dev, "dpll_ref");
638 if (IS_ERR(clk)) {
639 dev_err(dev, "unable to get dpll ref clk\n");
640 return PTR_ERR(clk);
641 }
642 clk_set_rate(clk, 1500000000);
643
644 clk = devm_clk_get(dev, "dpll_ref_m2");
645 if (IS_ERR(clk)) {
646 dev_err(dev, "unable to get dpll ref m2 clk\n");
647 return PTR_ERR(clk);
648 }
649 clk_set_rate(clk, 100000000);
650
651 clk = devm_clk_get(dev, "phy-div");
652 if (IS_ERR(clk)) {
653 dev_err(dev, "unable to get phy-div clk\n");
654 return PTR_ERR(clk);
655 }
656 clk_set_rate(clk, 100000000);
657
658 phy->div_clk = devm_clk_get(dev, "div-clk");
659 if (IS_ERR(phy->div_clk)) {
660 dev_err(dev, "unable to get div-clk\n");
661 return PTR_ERR(phy->div_clk);
662 }
663 } else {
664 phy->div_clk = ERR_PTR(-ENODEV);
665 }
666
667 return 0;
668 }
669
670 static int ti_pipe3_get_sysctrl(struct ti_pipe3 *phy)
671 {
672 struct device *dev = phy->dev;
673 struct device_node *node = dev->of_node;
674 struct device_node *control_node;
675 struct platform_device *control_pdev;
676
677 phy->phy_power_syscon = syscon_regmap_lookup_by_phandle(node,
678 "syscon-phy-power");
679 if (IS_ERR(phy->phy_power_syscon)) {
680 dev_dbg(dev,
681 "can't get syscon-phy-power, using control device\n");
682 phy->phy_power_syscon = NULL;
683 } else {
684 if (of_property_read_u32_index(node,
685 "syscon-phy-power", 1,
686 &phy->power_reg)) {
687 dev_err(dev, "couldn't get power reg. offset\n");
688 return -EINVAL;
689 }
690 }
691
692 if (!phy->phy_power_syscon) {
693 control_node = of_parse_phandle(node, "ctrl-module", 0);
694 if (!control_node) {
695 dev_err(dev, "Failed to get control device phandle\n");
696 return -EINVAL;
697 }
698
699 control_pdev = of_find_device_by_node(control_node);
700 if (!control_pdev) {
701 dev_err(dev, "Failed to get control device\n");
702 return -EINVAL;
703 }
704
705 phy->control_dev = &control_pdev->dev;
706 }
707
708 if (phy->mode == PIPE3_MODE_PCIE) {
709 phy->pcs_syscon = syscon_regmap_lookup_by_phandle(node,
710 "syscon-pcs");
711 if (IS_ERR(phy->pcs_syscon)) {
712 dev_dbg(dev,
713 "can't get syscon-pcs, using omap control\n");
714 phy->pcs_syscon = NULL;
715 } else {
716 if (of_property_read_u32_index(node,
717 "syscon-pcs", 1,
718 &phy->pcie_pcs_reg)) {
719 dev_err(dev,
720 "couldn't get pcie pcs reg. offset\n");
721 return -EINVAL;
722 }
723 }
724 }
725
726 if (phy->mode == PIPE3_MODE_SATA) {
727 phy->dpll_reset_syscon = syscon_regmap_lookup_by_phandle(node,
728 "syscon-pllreset");
729 if (IS_ERR(phy->dpll_reset_syscon)) {
730 dev_info(dev,
731 "can't get syscon-pllreset, sata dpll won't idle\n");
732 phy->dpll_reset_syscon = NULL;
733 } else {
734 if (of_property_read_u32_index(node,
735 "syscon-pllreset", 1,
736 &phy->dpll_reset_reg)) {
737 dev_err(dev,
738 "couldn't get pllreset reg. offset\n");
739 return -EINVAL;
740 }
741 }
742 }
743
744 return 0;
745 }
746
747 static int ti_pipe3_get_tx_rx_base(struct ti_pipe3 *phy)
748 {
749 struct resource *res;
750 struct device *dev = phy->dev;
751 struct platform_device *pdev = to_platform_device(dev);
752
753 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
754 "phy_rx");
755 phy->phy_rx = devm_ioremap_resource(dev, res);
756 if (IS_ERR(phy->phy_rx))
757 return PTR_ERR(phy->phy_rx);
758
759 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
760 "phy_tx");
761 phy->phy_tx = devm_ioremap_resource(dev, res);
762
763 return PTR_ERR_OR_ZERO(phy->phy_tx);
764 }
765
766 static int ti_pipe3_get_pll_base(struct ti_pipe3 *phy)
767 {
768 struct resource *res;
769 struct device *dev = phy->dev;
770 struct platform_device *pdev = to_platform_device(dev);
771
772 if (phy->mode == PIPE3_MODE_PCIE)
773 return 0;
774
775 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
776 "pll_ctrl");
777 phy->pll_ctrl_base = devm_ioremap_resource(dev, res);
778 return PTR_ERR_OR_ZERO(phy->pll_ctrl_base);
779 }
780
781 static int ti_pipe3_probe(struct platform_device *pdev)
782 {
783 struct ti_pipe3 *phy;
784 struct phy *generic_phy;
785 struct phy_provider *phy_provider;
786 struct device *dev = &pdev->dev;
787 int ret;
788 const struct of_device_id *match;
789 struct pipe3_data *data;
790
791 phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
792 if (!phy)
793 return -ENOMEM;
794
795 match = of_match_device(ti_pipe3_id_table, dev);
796 if (!match)
797 return -EINVAL;
798
799 data = (struct pipe3_data *)match->data;
800 if (!data) {
801 dev_err(dev, "no driver data\n");
802 return -EINVAL;
803 }
804
805 phy->dev = dev;
806 phy->mode = data->mode;
807 phy->dpll_map = data->dpll_map;
808 phy->settings = data->settings;
809
810 ret = ti_pipe3_get_pll_base(phy);
811 if (ret)
812 return ret;
813
814 ret = ti_pipe3_get_tx_rx_base(phy);
815 if (ret)
816 return ret;
817
818 ret = ti_pipe3_get_sysctrl(phy);
819 if (ret)
820 return ret;
821
822 ret = ti_pipe3_get_clk(phy);
823 if (ret)
824 return ret;
825
826 platform_set_drvdata(pdev, phy);
827 pm_runtime_enable(dev);
828
829 /*
830 * Prevent auto-disable of refclk for SATA PHY due to Errata i783
831 */
832 if (phy->mode == PIPE3_MODE_SATA) {
833 if (!IS_ERR(phy->refclk)) {
834 clk_prepare_enable(phy->refclk);
835 phy->sata_refclk_enabled = true;
836 }
837 }
838
839 generic_phy = devm_phy_create(dev, NULL, &ops);
840 if (IS_ERR(generic_phy))
841 return PTR_ERR(generic_phy);
842
843 phy_set_drvdata(generic_phy, phy);
844
845 ti_pipe3_power_off(generic_phy);
846
847 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
848 return PTR_ERR_OR_ZERO(phy_provider);
849 }
850
851 static int ti_pipe3_remove(struct platform_device *pdev)
852 {
853 struct ti_pipe3 *phy = platform_get_drvdata(pdev);
854
855 if (phy->mode == PIPE3_MODE_SATA) {
856 clk_disable_unprepare(phy->refclk);
857 phy->sata_refclk_enabled = false;
858 }
859 pm_runtime_disable(&pdev->dev);
860
861 return 0;
862 }
863
864 static int ti_pipe3_enable_clocks(struct ti_pipe3 *phy)
865 {
866 int ret = 0;
867
868 if (!IS_ERR(phy->refclk)) {
869 ret = clk_prepare_enable(phy->refclk);
870 if (ret) {
871 dev_err(phy->dev, "Failed to enable refclk %d\n", ret);
872 return ret;
873 }
874 }
875
876 if (!IS_ERR(phy->wkupclk)) {
877 ret = clk_prepare_enable(phy->wkupclk);
878 if (ret) {
879 dev_err(phy->dev, "Failed to enable wkupclk %d\n", ret);
880 goto disable_refclk;
881 }
882 }
883
884 if (!IS_ERR(phy->div_clk)) {
885 ret = clk_prepare_enable(phy->div_clk);
886 if (ret) {
887 dev_err(phy->dev, "Failed to enable div_clk %d\n", ret);
888 goto disable_wkupclk;
889 }
890 }
891
892 return 0;
893
894 disable_wkupclk:
895 if (!IS_ERR(phy->wkupclk))
896 clk_disable_unprepare(phy->wkupclk);
897
898 disable_refclk:
899 if (!IS_ERR(phy->refclk))
900 clk_disable_unprepare(phy->refclk);
901
902 return ret;
903 }
904
905 static void ti_pipe3_disable_clocks(struct ti_pipe3 *phy)
906 {
907 if (!IS_ERR(phy->wkupclk))
908 clk_disable_unprepare(phy->wkupclk);
909 if (!IS_ERR(phy->refclk))
910 clk_disable_unprepare(phy->refclk);
911 if (!IS_ERR(phy->div_clk))
912 clk_disable_unprepare(phy->div_clk);
913 }
914
915 static const struct of_device_id ti_pipe3_id_table[] = {
916 {
917 .compatible = "ti,phy-usb3",
918 .data = &data_usb,
919 },
920 {
921 .compatible = "ti,omap-usb3",
922 .data = &data_usb,
923 },
924 {
925 .compatible = "ti,phy-pipe3-sata",
926 .data = &data_sata,
927 },
928 {
929 .compatible = "ti,phy-pipe3-pcie",
930 .data = &data_pcie,
931 },
932 {}
933 };
934 MODULE_DEVICE_TABLE(of, ti_pipe3_id_table);
935
936 static struct platform_driver ti_pipe3_driver = {
937 .probe = ti_pipe3_probe,
938 .remove = ti_pipe3_remove,
939 .driver = {
940 .name = "ti-pipe3",
941 .of_match_table = ti_pipe3_id_table,
942 },
943 };
944
945 module_platform_driver(ti_pipe3_driver);
946
947 MODULE_ALIAS("platform:ti_pipe3");
948 MODULE_AUTHOR("Texas Instruments Inc.");
949 MODULE_DESCRIPTION("TI PIPE3 phy driver");
950 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support