drivers/pinctrl/freescale/pinctrl-imx.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * IMX pinmux core definitions
   4  *
   5  * Copyright (C) 2012 Freescale Semiconductor, Inc.
   6  * Copyright (C) 2012 Linaro Ltd.
   7  *
   8  * Author: Dong Aisheng <dong.aisheng@linaro.org>
   9  */
  10
  11 #ifndef __DRIVERS_PINCTRL_IMX_H
  12 #define __DRIVERS_PINCTRL_IMX_H
  13
  14 #include <linux/pinctrl/pinconf-generic.h>
  15 #include <linux/pinctrl/pinmux.h>
  16
  17 struct platform_device;
  18
  19 extern struct pinmux_ops imx_pmx_ops;
  20 extern const struct dev_pm_ops imx_pinctrl_pm_ops;
  21
  22 /**
  23  * struct imx_pin_mmio - MMIO pin configurations
  24  * @mux_mode: the mux mode for this pin.
  25  * @input_reg: the select input register offset for this pin if any
  26  *      0 if no select input setting needed.
  27  * @input_val: the select input value for this pin.
  28  * @configs: the config for this pin.
  29  */
  30 struct imx_pin_mmio {
  31         unsigned int mux_mode;
  32         u16 input_reg;
  33         unsigned int input_val;
  34         unsigned long config;
  35 };
  36
  37 /**
  38  * struct imx_pin_scu - SCU pin configurations
  39  * @mux: the mux mode for this pin.
  40  * @configs: the config for this pin.
  41  */
  42 struct imx_pin_scu {
  43         unsigned int mux_mode;
  44         unsigned long config;
  45 };
  46
  47 /**
  48  * struct imx_pin - describes a single i.MX pin
  49  * @pin: the pin_id of this pin
  50  * @conf: config type of this pin, either mmio or scu
  51  */
  52 struct imx_pin {
  53         unsigned int pin;
  54         union {
  55                 struct imx_pin_mmio mmio;
  56                 struct imx_pin_scu scu;
  57         } conf;
  58 };
  59
  60 /**
  61  * struct imx_pin_reg - describe a pin reg map
  62  * @mux_reg: mux register offset
  63  * @conf_reg: config register offset
  64  */
  65 struct imx_pin_reg {
  66         s16 mux_reg;
  67         s16 conf_reg;
  68 };
  69
  70 /* decode a generic config into raw register value */
  71 struct imx_cfg_params_decode {
  72         enum pin_config_param param;
  73         u32 mask;
  74         u8 shift;
  75         bool invert;
  76 };
  77
  78 struct imx_pinctrl_soc_info {
  79         const struct pinctrl_pin_desc *pins;
  80         unsigned int npins;
  81         unsigned int flags;
  82         const char *gpr_compatible;
  83
  84         /* MUX_MODE shift and mask in case SHARE_MUX_CONF_REG */
  85         unsigned int mux_mask;
  86         u8 mux_shift;
  87
  88         /* generic pinconf */
  89         bool generic_pinconf;
  90         const struct pinconf_generic_params *custom_params;
  91         unsigned int num_custom_params;
  92         const struct imx_cfg_params_decode *decodes;
  93         unsigned int num_decodes;
  94         void (*fixup)(unsigned long *configs, unsigned int num_configs,
  95                       u32 *raw_config);
  96
  97         int (*gpio_set_direction)(struct pinctrl_dev *pctldev,
  98                                   struct pinctrl_gpio_range *range,
  99                                   unsigned offset,
 100                                   bool input);
 101 };
 102
 103 /**
 104  * @dev: a pointer back to containing device
 105  * @base: the offset to the controller in virtual memory
 106  */
 107 struct imx_pinctrl {
 108         struct device *dev;
 109         struct pinctrl_dev *pctl;
 110         void __iomem *base;
 111         void __iomem *input_sel_base;
 112         const struct imx_pinctrl_soc_info *info;
 113         struct imx_pin_reg *pin_regs;
 114         unsigned int group_index;
 115         struct mutex mutex;
 116 };
 117
 118 #define IMX_CFG_PARAMS_DECODE(p, m, o) \
 119         { .param = p, .mask = m, .shift = o, .invert = false, }
 120
 121 #define IMX_CFG_PARAMS_DECODE_INVERT(p, m, o) \
 122         { .param = p, .mask = m, .shift = o, .invert = true, }
 123
 124 #define SHARE_MUX_CONF_REG      BIT(0)
 125 #define ZERO_OFFSET_VALID       BIT(1)
 126 #define IMX_USE_SCU             BIT(2)
 127
 128 #define NO_MUX          0x0
 129 #define NO_PAD          0x0
 130
 131 #define IMX_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin)
 132
 133 #define PAD_CTL_MASK(len)       ((1 << len) - 1)
 134 #define IMX_MUX_MASK    0x7
 135 #define IOMUXC_CONFIG_SION      (0x1 << 4)
 136
 137 int imx_pinctrl_probe(struct platform_device *pdev,
 138                         const struct imx_pinctrl_soc_info *info);
 139
 140 #ifdef CONFIG_PINCTRL_IMX_SCU
 141 #define BM_PAD_CTL_GP_ENABLE            BIT(30)
 142 #define BM_PAD_CTL_IFMUX_ENABLE         BIT(31)
 143 #define BP_PAD_CTL_IFMUX                27
 144
 145 int imx_pinctrl_sc_ipc_init(struct platform_device *pdev);
 146 int imx_pinconf_get_scu(struct pinctrl_dev *pctldev, unsigned pin_id,
 147                         unsigned long *config);
 148 int imx_pinconf_set_scu(struct pinctrl_dev *pctldev, unsigned pin_id,
 149                         unsigned long *configs, unsigned num_configs);
 150 void imx_pinctrl_parse_pin_scu(struct imx_pinctrl *ipctl,
 151                                unsigned int *pin_id, struct imx_pin *pin,
 152                                const __be32 **list_p);
 153 #else
 154 static inline int imx_pinconf_get_scu(struct pinctrl_dev *pctldev,
 155                                       unsigned pin_id, unsigned long *config)
 156 {
 157         return -EINVAL;
 158 }
 159 static inline int imx_pinconf_set_scu(struct pinctrl_dev *pctldev,
 160                                       unsigned pin_id, unsigned long *configs,
 161                                       unsigned num_configs)
 162 {
 163         return -EINVAL;
 164 }
 165 static inline void imx_pinctrl_parse_pin_scu(struct imx_pinctrl *ipctl,
 166                                             unsigned int *pin_id,
 167                                             struct imx_pin *pin,
 168                                             const __be32 **list_p)
 169 {
 170 }
 171 #endif
 172 #endif /* __DRIVERS_PINCTRL_IMX_H */