1 // SPDX-License-Identifier: GPL-2.0+
3 // imx50 pinctrl driver based on imx pinmux core
5 // Copyright (C) 2013 Greg Ungerer <gerg@uclinux.org>
6 // Copyright (C) 2012 Freescale Semiconductor, Inc.
7 // Copyright (C) 2012 Linaro, Inc.
10 #include <linux/init.h>
13 #include <linux/of_device.h>
14 #include <linux/pinctrl/pinctrl.h>
16 #include "pinctrl-imx.h"
19 MX50_PAD_RESERVE0
= 0,
20 MX50_PAD_RESERVE1
= 1,
21 MX50_PAD_RESERVE2
= 2,
22 MX50_PAD_RESERVE3
= 3,
23 MX50_PAD_RESERVE4
= 4,
24 MX50_PAD_RESERVE5
= 5,
25 MX50_PAD_RESERVE6
= 6,
26 MX50_PAD_RESERVE7
= 7,
27 MX50_PAD_KEY_COL0
= 8,
28 MX50_PAD_KEY_ROW0
= 9,
29 MX50_PAD_KEY_COL1
= 10,
30 MX50_PAD_KEY_ROW1
= 11,
31 MX50_PAD_KEY_COL2
= 12,
32 MX50_PAD_KEY_ROW2
= 13,
33 MX50_PAD_KEY_COL3
= 14,
34 MX50_PAD_KEY_ROW3
= 15,
35 MX50_PAD_I2C1_SCL
= 16,
36 MX50_PAD_I2C1_SDA
= 17,
37 MX50_PAD_I2C2_SCL
= 18,
38 MX50_PAD_I2C2_SDA
= 19,
39 MX50_PAD_I2C3_SCL
= 20,
40 MX50_PAD_I2C3_SDA
= 21,
46 MX50_PAD_SSI_TXFS
= 27,
47 MX50_PAD_SSI_TXC
= 28,
48 MX50_PAD_SSI_TXD
= 29,
49 MX50_PAD_SSI_RXD
= 30,
50 MX50_PAD_SSI_RXF
= 31,
51 MX50_PAD_SSI_RXC
= 32,
52 MX50_PAD_UART1_TXD
= 33,
53 MX50_PAD_UART1_RXD
= 34,
54 MX50_PAD_UART1_CTS
= 35,
55 MX50_PAD_UART1_RTS
= 36,
56 MX50_PAD_UART2_TXD
= 37,
57 MX50_PAD_UART2_RXD
= 38,
58 MX50_PAD_UART2_CTS
= 39,
59 MX50_PAD_UART2_RTS
= 40,
60 MX50_PAD_UART3_TXD
= 41,
61 MX50_PAD_UART3_RXD
= 42,
62 MX50_PAD_UART4_TXD
= 43,
63 MX50_PAD_UART4_RXD
= 44,
64 MX50_PAD_CSPI_CLK
= 45,
65 MX50_PAD_CSPI_MOSI
= 46,
66 MX50_PAD_CSPI_MISO
= 47,
67 MX50_PAD_CSPI_SS0
= 48,
68 MX50_PAD_ECSPI1_CLK
= 49,
69 MX50_PAD_ECSPI1_MOSI
= 50,
70 MX50_PAD_ECSPI1_MISO
= 51,
71 MX50_PAD_ECSPI1_SS0
= 52,
72 MX50_PAD_ECSPI2_CLK
= 53,
73 MX50_PAD_ECSPI2_MOSI
= 54,
74 MX50_PAD_ECSPI2_MISO
= 55,
75 MX50_PAD_ECSPI2_SS0
= 56,
76 MX50_PAD_SD1_CLK
= 57,
77 MX50_PAD_SD1_CMD
= 58,
82 MX50_PAD_SD2_CLK
= 63,
83 MX50_PAD_SD2_CMD
= 64,
94 MX50_PAD_DISP_D0
= 75,
95 MX50_PAD_DISP_D1
= 76,
96 MX50_PAD_DISP_D2
= 77,
97 MX50_PAD_DISP_D3
= 78,
98 MX50_PAD_DISP_D4
= 79,
99 MX50_PAD_DISP_D5
= 80,
100 MX50_PAD_DISP_D6
= 81,
101 MX50_PAD_DISP_D7
= 82,
102 MX50_PAD_DISP_WR
= 83,
103 MX50_PAD_DISP_RD
= 84,
104 MX50_PAD_DISP_RS
= 85,
105 MX50_PAD_DISP_CS
= 86,
106 MX50_PAD_DISP_BUSY
= 87,
107 MX50_PAD_DISP_RESET
= 88,
108 MX50_PAD_SD3_CLK
= 89,
109 MX50_PAD_SD3_CMD
= 90,
110 MX50_PAD_SD3_D0
= 91,
111 MX50_PAD_SD3_D1
= 92,
112 MX50_PAD_SD3_D2
= 93,
113 MX50_PAD_SD3_D3
= 94,
114 MX50_PAD_SD3_D4
= 95,
115 MX50_PAD_SD3_D5
= 96,
116 MX50_PAD_SD3_D6
= 97,
117 MX50_PAD_SD3_D7
= 98,
118 MX50_PAD_SD3_WP
= 99,
119 MX50_PAD_DISP_D8
= 100,
120 MX50_PAD_DISP_D9
= 101,
121 MX50_PAD_DISP_D10
= 102,
122 MX50_PAD_DISP_D11
= 103,
123 MX50_PAD_DISP_D12
= 104,
124 MX50_PAD_DISP_D13
= 105,
125 MX50_PAD_DISP_D14
= 106,
126 MX50_PAD_DISP_D15
= 107,
127 MX50_PAD_EPDC_D0
= 108,
128 MX50_PAD_EPDC_D1
= 109,
129 MX50_PAD_EPDC_D2
= 110,
130 MX50_PAD_EPDC_D3
= 111,
131 MX50_PAD_EPDC_D4
= 112,
132 MX50_PAD_EPDC_D5
= 113,
133 MX50_PAD_EPDC_D6
= 114,
134 MX50_PAD_EPDC_D7
= 115,
135 MX50_PAD_EPDC_D8
= 116,
136 MX50_PAD_EPDC_D9
= 117,
137 MX50_PAD_EPDC_D10
= 118,
138 MX50_PAD_EPDC_D11
= 119,
139 MX50_PAD_EPDC_D12
= 120,
140 MX50_PAD_EPDC_D13
= 121,
141 MX50_PAD_EPDC_D14
= 122,
142 MX50_PAD_EPDC_D15
= 123,
143 MX50_PAD_EPDC_GDCLK
= 124,
144 MX50_PAD_EPDC_GDSP
= 125,
145 MX50_PAD_EPDC_GDOE
= 126,
146 MX50_PAD_EPDC_GDRL
= 127,
147 MX50_PAD_EPDC_SDCLK
= 128,
148 MX50_PAD_EPDC_SDOEZ
= 129,
149 MX50_PAD_EPDC_SDOED
= 130,
150 MX50_PAD_EPDC_SDOE
= 131,
151 MX50_PAD_EPDC_SDLE
= 132,
152 MX50_PAD_EPDC_SDCLKN
= 133,
153 MX50_PAD_EPDC_SDSHR
= 134,
154 MX50_PAD_EPDC_PWRCOM
= 135,
155 MX50_PAD_EPDC_PWRSTAT
= 136,
156 MX50_PAD_EPDC_PWRCTRL0
= 137,
157 MX50_PAD_EPDC_PWRCTRL1
= 138,
158 MX50_PAD_EPDC_PWRCTRL2
= 139,
159 MX50_PAD_EPDC_PWRCTRL3
= 140,
160 MX50_PAD_EPDC_VCOM0
= 141,
161 MX50_PAD_EPDC_VCOM1
= 142,
162 MX50_PAD_EPDC_BDR0
= 143,
163 MX50_PAD_EPDC_BDR1
= 144,
164 MX50_PAD_EPDC_SDCE0
= 145,
165 MX50_PAD_EPDC_SDCE1
= 146,
166 MX50_PAD_EPDC_SDCE2
= 147,
167 MX50_PAD_EPDC_SDCE3
= 148,
168 MX50_PAD_EPDC_SDCE4
= 149,
169 MX50_PAD_EPDC_SDCE5
= 150,
170 MX50_PAD_EIM_DA0
= 151,
171 MX50_PAD_EIM_DA1
= 152,
172 MX50_PAD_EIM_DA2
= 153,
173 MX50_PAD_EIM_DA3
= 154,
174 MX50_PAD_EIM_DA4
= 155,
175 MX50_PAD_EIM_DA5
= 156,
176 MX50_PAD_EIM_DA6
= 157,
177 MX50_PAD_EIM_DA7
= 158,
178 MX50_PAD_EIM_DA8
= 159,
179 MX50_PAD_EIM_DA9
= 160,
180 MX50_PAD_EIM_DA10
= 161,
181 MX50_PAD_EIM_DA11
= 162,
182 MX50_PAD_EIM_DA12
= 163,
183 MX50_PAD_EIM_DA13
= 164,
184 MX50_PAD_EIM_DA14
= 165,
185 MX50_PAD_EIM_DA15
= 166,
186 MX50_PAD_EIM_CS2
= 167,
187 MX50_PAD_EIM_CS1
= 168,
188 MX50_PAD_EIM_CS0
= 169,
189 MX50_PAD_EIM_EB0
= 170,
190 MX50_PAD_EIM_EB1
= 171,
191 MX50_PAD_EIM_WAIT
= 172,
192 MX50_PAD_EIM_BCLK
= 173,
193 MX50_PAD_EIM_RDY
= 174,
194 MX50_PAD_EIM_OE
= 175,
195 MX50_PAD_EIM_RW
= 176,
196 MX50_PAD_EIM_LBA
= 177,
197 MX50_PAD_EIM_CRE
= 178,
200 /* Pad names for the pinmux subsystem */
201 static const struct pinctrl_pin_desc imx50_pinctrl_pads
[] = {
202 IMX_PINCTRL_PIN(MX50_PAD_RESERVE0
),
203 IMX_PINCTRL_PIN(MX50_PAD_RESERVE1
),
204 IMX_PINCTRL_PIN(MX50_PAD_RESERVE2
),
205 IMX_PINCTRL_PIN(MX50_PAD_RESERVE3
),
206 IMX_PINCTRL_PIN(MX50_PAD_RESERVE4
),
207 IMX_PINCTRL_PIN(MX50_PAD_RESERVE5
),
208 IMX_PINCTRL_PIN(MX50_PAD_RESERVE6
),
209 IMX_PINCTRL_PIN(MX50_PAD_RESERVE7
),
210 IMX_PINCTRL_PIN(MX50_PAD_KEY_COL0
),
211 IMX_PINCTRL_PIN(MX50_PAD_KEY_ROW0
),
212 IMX_PINCTRL_PIN(MX50_PAD_KEY_COL1
),
213 IMX_PINCTRL_PIN(MX50_PAD_KEY_ROW1
),
214 IMX_PINCTRL_PIN(MX50_PAD_KEY_COL2
),
215 IMX_PINCTRL_PIN(MX50_PAD_KEY_ROW2
),
216 IMX_PINCTRL_PIN(MX50_PAD_KEY_COL3
),
217 IMX_PINCTRL_PIN(MX50_PAD_KEY_ROW3
),
218 IMX_PINCTRL_PIN(MX50_PAD_I2C1_SCL
),
219 IMX_PINCTRL_PIN(MX50_PAD_I2C1_SDA
),
220 IMX_PINCTRL_PIN(MX50_PAD_I2C2_SCL
),
221 IMX_PINCTRL_PIN(MX50_PAD_I2C2_SDA
),
222 IMX_PINCTRL_PIN(MX50_PAD_I2C3_SCL
),
223 IMX_PINCTRL_PIN(MX50_PAD_I2C3_SDA
),
224 IMX_PINCTRL_PIN(MX50_PAD_PWM1
),
225 IMX_PINCTRL_PIN(MX50_PAD_PWM2
),
226 IMX_PINCTRL_PIN(MX50_PAD_0WIRE
),
227 IMX_PINCTRL_PIN(MX50_PAD_EPITO
),
228 IMX_PINCTRL_PIN(MX50_PAD_WDOG
),
229 IMX_PINCTRL_PIN(MX50_PAD_SSI_TXFS
),
230 IMX_PINCTRL_PIN(MX50_PAD_SSI_TXC
),
231 IMX_PINCTRL_PIN(MX50_PAD_SSI_TXD
),
232 IMX_PINCTRL_PIN(MX50_PAD_SSI_RXD
),
233 IMX_PINCTRL_PIN(MX50_PAD_SSI_RXF
),
234 IMX_PINCTRL_PIN(MX50_PAD_SSI_RXC
),
235 IMX_PINCTRL_PIN(MX50_PAD_UART1_TXD
),
236 IMX_PINCTRL_PIN(MX50_PAD_UART1_RXD
),
237 IMX_PINCTRL_PIN(MX50_PAD_UART1_CTS
),
238 IMX_PINCTRL_PIN(MX50_PAD_UART1_RTS
),
239 IMX_PINCTRL_PIN(MX50_PAD_UART2_TXD
),
240 IMX_PINCTRL_PIN(MX50_PAD_UART2_RXD
),
241 IMX_PINCTRL_PIN(MX50_PAD_UART2_CTS
),
242 IMX_PINCTRL_PIN(MX50_PAD_UART2_RTS
),
243 IMX_PINCTRL_PIN(MX50_PAD_UART3_TXD
),
244 IMX_PINCTRL_PIN(MX50_PAD_UART3_RXD
),
245 IMX_PINCTRL_PIN(MX50_PAD_UART4_TXD
),
246 IMX_PINCTRL_PIN(MX50_PAD_UART4_RXD
),
247 IMX_PINCTRL_PIN(MX50_PAD_CSPI_CLK
),
248 IMX_PINCTRL_PIN(MX50_PAD_CSPI_MOSI
),
249 IMX_PINCTRL_PIN(MX50_PAD_CSPI_MISO
),
250 IMX_PINCTRL_PIN(MX50_PAD_CSPI_SS0
),
251 IMX_PINCTRL_PIN(MX50_PAD_ECSPI1_CLK
),
252 IMX_PINCTRL_PIN(MX50_PAD_ECSPI1_MOSI
),
253 IMX_PINCTRL_PIN(MX50_PAD_ECSPI1_MISO
),
254 IMX_PINCTRL_PIN(MX50_PAD_ECSPI1_SS0
),
255 IMX_PINCTRL_PIN(MX50_PAD_ECSPI2_CLK
),
256 IMX_PINCTRL_PIN(MX50_PAD_ECSPI2_MOSI
),
257 IMX_PINCTRL_PIN(MX50_PAD_ECSPI2_MISO
),
258 IMX_PINCTRL_PIN(MX50_PAD_ECSPI2_SS0
),
259 IMX_PINCTRL_PIN(MX50_PAD_SD1_CLK
),
260 IMX_PINCTRL_PIN(MX50_PAD_SD1_CMD
),
261 IMX_PINCTRL_PIN(MX50_PAD_SD1_D0
),
262 IMX_PINCTRL_PIN(MX50_PAD_SD1_D1
),
263 IMX_PINCTRL_PIN(MX50_PAD_SD1_D2
),
264 IMX_PINCTRL_PIN(MX50_PAD_SD1_D3
),
265 IMX_PINCTRL_PIN(MX50_PAD_SD2_CLK
),
266 IMX_PINCTRL_PIN(MX50_PAD_SD2_CMD
),
267 IMX_PINCTRL_PIN(MX50_PAD_SD2_D0
),
268 IMX_PINCTRL_PIN(MX50_PAD_SD2_D1
),
269 IMX_PINCTRL_PIN(MX50_PAD_SD2_D2
),
270 IMX_PINCTRL_PIN(MX50_PAD_SD2_D3
),
271 IMX_PINCTRL_PIN(MX50_PAD_SD2_D4
),
272 IMX_PINCTRL_PIN(MX50_PAD_SD2_D5
),
273 IMX_PINCTRL_PIN(MX50_PAD_SD2_D6
),
274 IMX_PINCTRL_PIN(MX50_PAD_SD2_D7
),
275 IMX_PINCTRL_PIN(MX50_PAD_SD2_WP
),
276 IMX_PINCTRL_PIN(MX50_PAD_SD2_CD
),
277 IMX_PINCTRL_PIN(MX50_PAD_DISP_D0
),
278 IMX_PINCTRL_PIN(MX50_PAD_DISP_D1
),
279 IMX_PINCTRL_PIN(MX50_PAD_DISP_D2
),
280 IMX_PINCTRL_PIN(MX50_PAD_DISP_D3
),
281 IMX_PINCTRL_PIN(MX50_PAD_DISP_D4
),
282 IMX_PINCTRL_PIN(MX50_PAD_DISP_D5
),
283 IMX_PINCTRL_PIN(MX50_PAD_DISP_D6
),
284 IMX_PINCTRL_PIN(MX50_PAD_DISP_D7
),
285 IMX_PINCTRL_PIN(MX50_PAD_DISP_WR
),
286 IMX_PINCTRL_PIN(MX50_PAD_DISP_RD
),
287 IMX_PINCTRL_PIN(MX50_PAD_DISP_RS
),
288 IMX_PINCTRL_PIN(MX50_PAD_DISP_CS
),
289 IMX_PINCTRL_PIN(MX50_PAD_DISP_BUSY
),
290 IMX_PINCTRL_PIN(MX50_PAD_DISP_RESET
),
291 IMX_PINCTRL_PIN(MX50_PAD_SD3_CLK
),
292 IMX_PINCTRL_PIN(MX50_PAD_SD3_CMD
),
293 IMX_PINCTRL_PIN(MX50_PAD_SD3_D0
),
294 IMX_PINCTRL_PIN(MX50_PAD_SD3_D1
),
295 IMX_PINCTRL_PIN(MX50_PAD_SD3_D2
),
296 IMX_PINCTRL_PIN(MX50_PAD_SD3_D3
),
297 IMX_PINCTRL_PIN(MX50_PAD_SD3_D4
),
298 IMX_PINCTRL_PIN(MX50_PAD_SD3_D5
),
299 IMX_PINCTRL_PIN(MX50_PAD_SD3_D6
),
300 IMX_PINCTRL_PIN(MX50_PAD_SD3_D7
),
301 IMX_PINCTRL_PIN(MX50_PAD_SD3_WP
),
302 IMX_PINCTRL_PIN(MX50_PAD_DISP_D8
),
303 IMX_PINCTRL_PIN(MX50_PAD_DISP_D9
),
304 IMX_PINCTRL_PIN(MX50_PAD_DISP_D10
),
305 IMX_PINCTRL_PIN(MX50_PAD_DISP_D11
),
306 IMX_PINCTRL_PIN(MX50_PAD_DISP_D12
),
307 IMX_PINCTRL_PIN(MX50_PAD_DISP_D13
),
308 IMX_PINCTRL_PIN(MX50_PAD_DISP_D14
),
309 IMX_PINCTRL_PIN(MX50_PAD_DISP_D15
),
310 IMX_PINCTRL_PIN(MX50_PAD_EPDC_D0
),
311 IMX_PINCTRL_PIN(MX50_PAD_EPDC_D1
),
312 IMX_PINCTRL_PIN(MX50_PAD_EPDC_D2
),
313 IMX_PINCTRL_PIN(MX50_PAD_EPDC_D3
),
314 IMX_PINCTRL_PIN(MX50_PAD_EPDC_D4
),
315 IMX_PINCTRL_PIN(MX50_PAD_EPDC_D5
),
316 IMX_PINCTRL_PIN(MX50_PAD_EPDC_D6
),
317 IMX_PINCTRL_PIN(MX50_PAD_EPDC_D7
),
318 IMX_PINCTRL_PIN(MX50_PAD_EPDC_D8
),
319 IMX_PINCTRL_PIN(MX50_PAD_EPDC_D9
),
320 IMX_PINCTRL_PIN(MX50_PAD_EPDC_D10
),
321 IMX_PINCTRL_PIN(MX50_PAD_EPDC_D11
),
322 IMX_PINCTRL_PIN(MX50_PAD_EPDC_D12
),
323 IMX_PINCTRL_PIN(MX50_PAD_EPDC_D13
),
324 IMX_PINCTRL_PIN(MX50_PAD_EPDC_D14
),
325 IMX_PINCTRL_PIN(MX50_PAD_EPDC_D15
),
326 IMX_PINCTRL_PIN(MX50_PAD_EPDC_GDCLK
),
327 IMX_PINCTRL_PIN(MX50_PAD_EPDC_GDSP
),
328 IMX_PINCTRL_PIN(MX50_PAD_EPDC_GDOE
),
329 IMX_PINCTRL_PIN(MX50_PAD_EPDC_GDRL
),
330 IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCLK
),
331 IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDOEZ
),
332 IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDOED
),
333 IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDOE
),
334 IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDLE
),
335 IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCLKN
),
336 IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDSHR
),
337 IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCOM
),
338 IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRSTAT
),
339 IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCTRL0
),
340 IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCTRL1
),
341 IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCTRL2
),
342 IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCTRL3
),
343 IMX_PINCTRL_PIN(MX50_PAD_EPDC_VCOM0
),
344 IMX_PINCTRL_PIN(MX50_PAD_EPDC_VCOM1
),
345 IMX_PINCTRL_PIN(MX50_PAD_EPDC_BDR0
),
346 IMX_PINCTRL_PIN(MX50_PAD_EPDC_BDR1
),
347 IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE0
),
348 IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE1
),
349 IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE2
),
350 IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE3
),
351 IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE4
),
352 IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE5
),
353 IMX_PINCTRL_PIN(MX50_PAD_EIM_DA0
),
354 IMX_PINCTRL_PIN(MX50_PAD_EIM_DA1
),
355 IMX_PINCTRL_PIN(MX50_PAD_EIM_DA2
),
356 IMX_PINCTRL_PIN(MX50_PAD_EIM_DA3
),
357 IMX_PINCTRL_PIN(MX50_PAD_EIM_DA4
),
358 IMX_PINCTRL_PIN(MX50_PAD_EIM_DA5
),
359 IMX_PINCTRL_PIN(MX50_PAD_EIM_DA6
),
360 IMX_PINCTRL_PIN(MX50_PAD_EIM_DA7
),
361 IMX_PINCTRL_PIN(MX50_PAD_EIM_DA8
),
362 IMX_PINCTRL_PIN(MX50_PAD_EIM_DA9
),
363 IMX_PINCTRL_PIN(MX50_PAD_EIM_DA10
),
364 IMX_PINCTRL_PIN(MX50_PAD_EIM_DA11
),
365 IMX_PINCTRL_PIN(MX50_PAD_EIM_DA12
),
366 IMX_PINCTRL_PIN(MX50_PAD_EIM_DA13
),
367 IMX_PINCTRL_PIN(MX50_PAD_EIM_DA14
),
368 IMX_PINCTRL_PIN(MX50_PAD_EIM_DA15
),
369 IMX_PINCTRL_PIN(MX50_PAD_EIM_CS2
),
370 IMX_PINCTRL_PIN(MX50_PAD_EIM_CS1
),
371 IMX_PINCTRL_PIN(MX50_PAD_EIM_CS0
),
372 IMX_PINCTRL_PIN(MX50_PAD_EIM_EB0
),
373 IMX_PINCTRL_PIN(MX50_PAD_EIM_EB1
),
374 IMX_PINCTRL_PIN(MX50_PAD_EIM_WAIT
),
375 IMX_PINCTRL_PIN(MX50_PAD_EIM_BCLK
),
376 IMX_PINCTRL_PIN(MX50_PAD_EIM_RDY
),
377 IMX_PINCTRL_PIN(MX50_PAD_EIM_OE
),
378 IMX_PINCTRL_PIN(MX50_PAD_EIM_RW
),
379 IMX_PINCTRL_PIN(MX50_PAD_EIM_LBA
),
380 IMX_PINCTRL_PIN(MX50_PAD_EIM_CRE
),
383 static const struct imx_pinctrl_soc_info imx50_pinctrl_info
= {
384 .pins
= imx50_pinctrl_pads
,
385 .npins
= ARRAY_SIZE(imx50_pinctrl_pads
),
386 .gpr_compatible
= "fsl,imx50-iomuxc-gpr",
389 static const struct of_device_id imx50_pinctrl_of_match
[] = {
390 { .compatible
= "fsl,imx50-iomuxc", },
394 static int imx50_pinctrl_probe(struct platform_device
*pdev
)
396 return imx_pinctrl_probe(pdev
, &imx50_pinctrl_info
);
399 static struct platform_driver imx50_pinctrl_driver
= {
401 .name
= "imx50-pinctrl",
402 .of_match_table
= of_match_ptr(imx50_pinctrl_of_match
),
404 .probe
= imx50_pinctrl_probe
,
407 static int __init
imx50_pinctrl_init(void)
409 return platform_driver_register(&imx50_pinctrl_driver
);
411 arch_initcall(imx50_pinctrl_init
);
