1 # SPDX-License-Identifier: GPL-2.0
2 # Intel pin control drivers
4 if (X86 || COMPILE_TEST)
6 config PINCTRL_BAYTRAIL
7 bool "Intel Baytrail GPIO pin control"
10 select GPIOLIB_IRQCHIP
13 select GENERIC_PINCONF
15 driver for memory mapped GPIO functionality on Intel Baytrail
16 platforms. Supports 3 banks with 102, 28 and 44 gpios.
17 Most pins are usually muxed to some other functionality by firmware,
18 so only a small amount is available for gpio use.
20 Requires ACPI device enumeration code to set up a platform device.
22 config PINCTRL_CHERRYVIEW
23 tristate "Intel Cherryview/Braswell pinctrl and GPIO driver"
27 select GENERIC_PINCONF
29 select GPIOLIB_IRQCHIP
31 Cherryview/Braswell pinctrl driver provides an interface that
32 allows configuring of SoC pins and using them as GPIOs.
34 config PINCTRL_LYNXPOINT
35 tristate "Intel Lynxpoint pinctrl and GPIO driver"
39 select GENERIC_PINCONF
41 select GPIOLIB_IRQCHIP
43 Lynxpoint is the PCH of Intel Haswell. This pinctrl driver
44 provides an interface that allows configuring of PCH pins and
47 config PINCTRL_MERRIFIELD
48 tristate "Intel Merrifield pinctrl driver"
49 depends on X86_INTEL_MID
52 select GENERIC_PINCONF
54 Merrifield Family-Level Interface Shim (FLIS) driver provides an
55 interface that allows configuring of SoC pins and using them as
62 select GENERIC_PINCONF
64 select GPIOLIB_IRQCHIP
66 config PINCTRL_BROXTON
67 tristate "Intel Broxton pinctrl and GPIO driver"
71 Broxton pinctrl driver provides an interface that allows
72 configuring of SoC pins and using them as GPIOs.
74 config PINCTRL_CANNONLAKE
75 tristate "Intel Cannon Lake PCH pinctrl and GPIO driver"
79 This pinctrl driver provides an interface that allows configuring
80 of Intel Cannon Lake PCH pins and using them as GPIOs.
82 config PINCTRL_CEDARFORK
83 tristate "Intel Cedar Fork pinctrl and GPIO driver"
87 This pinctrl driver provides an interface that allows configuring
88 of Intel Cedar Fork PCH pins and using them as GPIOs.
90 config PINCTRL_DENVERTON
91 tristate "Intel Denverton pinctrl and GPIO driver"
95 This pinctrl driver provides an interface that allows configuring
96 of Intel Denverton SoC pins and using them as GPIOs.
98 config PINCTRL_GEMINILAKE
99 tristate "Intel Gemini Lake SoC pinctrl and GPIO driver"
103 This pinctrl driver provides an interface that allows configuring
104 of Intel Gemini Lake SoC pins and using them as GPIOs.
106 config PINCTRL_ICELAKE
107 tristate "Intel Ice Lake PCH pinctrl and GPIO driver"
111 This pinctrl driver provides an interface that allows configuring
112 of Intel Ice Lake PCH pins and using them as GPIOs.
114 config PINCTRL_LEWISBURG
115 tristate "Intel Lewisburg pinctrl and GPIO driver"
119 This pinctrl driver provides an interface that allows configuring
120 of Intel Lewisburg pins and using them as GPIOs.
122 config PINCTRL_SUNRISEPOINT
123 tristate "Intel Sunrisepoint pinctrl and GPIO driver"
127 Sunrisepoint is the PCH of Intel Skylake. This pinctrl driver
128 provides an interface that allows configuring of PCH pins and
131 config PINCTRL_TIGERLAKE
132 tristate "Intel Tiger Lake pinctrl and GPIO driver"
136 This pinctrl driver provides an interface that allows configuring
137 of Intel Tiger Lake PCH pins and using them as GPIOs.