drivers/pinctrl/intel/pinctrl-tigerlake.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Intel Tiger Lake PCH pinctrl/GPIO driver
   4  *
   5  * Copyright (C) 2019 - 2020, Intel Corporation
   6  * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
   7  *          Mika Westerberg <mika.westerberg@linux.intel.com>
   8  */
   9
  10 #include <linux/mod_devicetable.h>
  11 #include <linux/module.h>
  12 #include <linux/platform_device.h>
  13
  14 #include <linux/pinctrl/pinctrl.h>
  15
  16 #include "pinctrl-intel.h"
  17
  18 #define TGL_PAD_OWN     0x020
  19 #define TGL_PADCFGLOCK  0x080
  20 #define TGL_HOSTSW_OWN  0x0b0
  21 #define TGL_GPI_IS      0x100
  22 #define TGL_GPI_IE      0x120
  23
  24 #define TGL_NO_GPIO     -1
  25
  26 #define TGL_GPP(r, s, e, g)                             \
  27         {                                               \
  28                 .reg_num = (r),                         \
  29                 .base = (s),                            \
  30                 .size = ((e) - (s) + 1),                \
  31                 .gpio_base = (g),                       \
  32         }
  33
  34 #define TGL_COMMUNITY(b, s, e, g)                       \
  35         {                                               \
  36                 .barno = (b),                           \
  37                 .padown_offset = TGL_PAD_OWN,           \
  38                 .padcfglock_offset = TGL_PADCFGLOCK,    \
  39                 .hostown_offset = TGL_HOSTSW_OWN,       \
  40                 .is_offset = TGL_GPI_IS,                \
  41                 .ie_offset = TGL_GPI_IE,                \
  42                 .pin_base = (s),                        \
  43                 .npins = ((e) - (s) + 1),               \
  44                 .gpps = (g),                            \
  45                 .ngpps = ARRAY_SIZE(g),                 \
  46         }
  47
  48 /* Tiger Lake-LP */
  49 static const struct pinctrl_pin_desc tgllp_pins[] = {
  50         /* GPP_B */
  51         PINCTRL_PIN(0, "CORE_VID_0"),
  52         PINCTRL_PIN(1, "CORE_VID_1"),
  53         PINCTRL_PIN(2, "VRALERTB"),
  54         PINCTRL_PIN(3, "CPU_GP_2"),
  55         PINCTRL_PIN(4, "CPU_GP_3"),
  56         PINCTRL_PIN(5, "ISH_I2C0_SDA"),
  57         PINCTRL_PIN(6, "ISH_I2C0_SCL"),
  58         PINCTRL_PIN(7, "ISH_I2C1_SDA"),
  59         PINCTRL_PIN(8, "ISH_I2C1_SCL"),
  60         PINCTRL_PIN(9, "I2C5_SDA"),
  61         PINCTRL_PIN(10, "I2C5_SCL"),
  62         PINCTRL_PIN(11, "PMCALERTB"),
  63         PINCTRL_PIN(12, "SLP_S0B"),
  64         PINCTRL_PIN(13, "PLTRSTB"),
  65         PINCTRL_PIN(14, "SPKR"),
  66         PINCTRL_PIN(15, "GSPI0_CS0B"),
  67         PINCTRL_PIN(16, "GSPI0_CLK"),
  68         PINCTRL_PIN(17, "GSPI0_MISO"),
  69         PINCTRL_PIN(18, "GSPI0_MOSI"),
  70         PINCTRL_PIN(19, "GSPI1_CS0B"),
  71         PINCTRL_PIN(20, "GSPI1_CLK"),
  72         PINCTRL_PIN(21, "GSPI1_MISO"),
  73         PINCTRL_PIN(22, "GSPI1_MOSI"),
  74         PINCTRL_PIN(23, "SML1ALERTB"),
  75         PINCTRL_PIN(24, "GSPI0_CLK_LOOPBK"),
  76         PINCTRL_PIN(25, "GSPI1_CLK_LOOPBK"),
  77         /* GPP_T */
  78         PINCTRL_PIN(26, "I2C6_SDA"),
  79         PINCTRL_PIN(27, "I2C6_SCL"),
  80         PINCTRL_PIN(28, "I2C7_SDA"),
  81         PINCTRL_PIN(29, "I2C7_SCL"),
  82         PINCTRL_PIN(30, "UART4_RXD"),
  83         PINCTRL_PIN(31, "UART4_TXD"),
  84         PINCTRL_PIN(32, "UART4_RTSB"),
  85         PINCTRL_PIN(33, "UART4_CTSB"),
  86         PINCTRL_PIN(34, "UART5_RXD"),
  87         PINCTRL_PIN(35, "UART5_TXD"),
  88         PINCTRL_PIN(36, "UART5_RTSB"),
  89         PINCTRL_PIN(37, "UART5_CTSB"),
  90         PINCTRL_PIN(38, "UART6_RXD"),
  91         PINCTRL_PIN(39, "UART6_TXD"),
  92         PINCTRL_PIN(40, "UART6_RTSB"),
  93         PINCTRL_PIN(41, "UART6_CTSB"),
  94         /* GPP_A */
  95         PINCTRL_PIN(42, "ESPI_IO_0"),
  96         PINCTRL_PIN(43, "ESPI_IO_1"),
  97         PINCTRL_PIN(44, "ESPI_IO_2"),
  98         PINCTRL_PIN(45, "ESPI_IO_3"),
  99         PINCTRL_PIN(46, "ESPI_CSB"),
 100         PINCTRL_PIN(47, "ESPI_CLK"),
 101         PINCTRL_PIN(48, "ESPI_RESETB"),
 102         PINCTRL_PIN(49, "I2S2_SCLK"),
 103         PINCTRL_PIN(50, "I2S2_SFRM"),
 104         PINCTRL_PIN(51, "I2S2_TXD"),
 105         PINCTRL_PIN(52, "I2S2_RXD"),
 106         PINCTRL_PIN(53, "PMC_I2C_SDA"),
 107         PINCTRL_PIN(54, "SATAXPCIE_1"),
 108         PINCTRL_PIN(55, "PMC_I2C_SCL"),
 109         PINCTRL_PIN(56, "USB2_OCB_1"),
 110         PINCTRL_PIN(57, "USB2_OCB_2"),
 111         PINCTRL_PIN(58, "USB2_OCB_3"),
 112         PINCTRL_PIN(59, "DDSP_HPD_C"),
 113         PINCTRL_PIN(60, "DDSP_HPD_B"),
 114         PINCTRL_PIN(61, "DDSP_HPD_1"),
 115         PINCTRL_PIN(62, "DDSP_HPD_2"),
 116         PINCTRL_PIN(63, "GPPC_A_21"),
 117         PINCTRL_PIN(64, "GPPC_A_22"),
 118         PINCTRL_PIN(65, "I2S1_SCLK"),
 119         PINCTRL_PIN(66, "ESPI_CLK_LOOPBK"),
 120         /* GPP_S */
 121         PINCTRL_PIN(67, "SNDW0_CLK"),
 122         PINCTRL_PIN(68, "SNDW0_DATA"),
 123         PINCTRL_PIN(69, "SNDW1_CLK"),
 124         PINCTRL_PIN(70, "SNDW1_DATA"),
 125         PINCTRL_PIN(71, "SNDW2_CLK"),
 126         PINCTRL_PIN(72, "SNDW2_DATA"),
 127         PINCTRL_PIN(73, "SNDW3_CLK"),
 128         PINCTRL_PIN(74, "SNDW3_DATA"),
 129         /* GPP_H */
 130         PINCTRL_PIN(75, "GPPC_H_0"),
 131         PINCTRL_PIN(76, "GPPC_H_1"),
 132         PINCTRL_PIN(77, "GPPC_H_2"),
 133         PINCTRL_PIN(78, "SX_EXIT_HOLDOFFB"),
 134         PINCTRL_PIN(79, "I2C2_SDA"),
 135         PINCTRL_PIN(80, "I2C2_SCL"),
 136         PINCTRL_PIN(81, "I2C3_SDA"),
 137         PINCTRL_PIN(82, "I2C3_SCL"),
 138         PINCTRL_PIN(83, "I2C4_SDA"),
 139         PINCTRL_PIN(84, "I2C4_SCL"),
 140         PINCTRL_PIN(85, "SRCCLKREQB_4"),
 141         PINCTRL_PIN(86, "SRCCLKREQB_5"),
 142         PINCTRL_PIN(87, "M2_SKT2_CFG_0"),
 143         PINCTRL_PIN(88, "M2_SKT2_CFG_1"),
 144         PINCTRL_PIN(89, "M2_SKT2_CFG_2"),
 145         PINCTRL_PIN(90, "M2_SKT2_CFG_3"),
 146         PINCTRL_PIN(91, "DDPB_CTRLCLK"),
 147         PINCTRL_PIN(92, "DDPB_CTRLDATA"),
 148         PINCTRL_PIN(93, "CPU_C10_GATEB"),
 149         PINCTRL_PIN(94, "TIME_SYNC_0"),
 150         PINCTRL_PIN(95, "IMGCLKOUT_1"),
 151         PINCTRL_PIN(96, "IMGCLKOUT_2"),
 152         PINCTRL_PIN(97, "IMGCLKOUT_3"),
 153         PINCTRL_PIN(98, "IMGCLKOUT_4"),
 154         /* GPP_D */
 155         PINCTRL_PIN(99, "ISH_GP_0"),
 156         PINCTRL_PIN(100, "ISH_GP_1"),
 157         PINCTRL_PIN(101, "ISH_GP_2"),
 158         PINCTRL_PIN(102, "ISH_GP_3"),
 159         PINCTRL_PIN(103, "IMGCLKOUT_0"),
 160         PINCTRL_PIN(104, "SRCCLKREQB_0"),
 161         PINCTRL_PIN(105, "SRCCLKREQB_1"),
 162         PINCTRL_PIN(106, "SRCCLKREQB_2"),
 163         PINCTRL_PIN(107, "SRCCLKREQB_3"),
 164         PINCTRL_PIN(108, "ISH_SPI_CSB"),
 165         PINCTRL_PIN(109, "ISH_SPI_CLK"),
 166         PINCTRL_PIN(110, "ISH_SPI_MISO"),
 167         PINCTRL_PIN(111, "ISH_SPI_MOSI"),
 168         PINCTRL_PIN(112, "ISH_UART0_RXD"),
 169         PINCTRL_PIN(113, "ISH_UART0_TXD"),
 170         PINCTRL_PIN(114, "ISH_UART0_RTSB"),
 171         PINCTRL_PIN(115, "ISH_UART0_CTSB"),
 172         PINCTRL_PIN(116, "ISH_GP_4"),
 173         PINCTRL_PIN(117, "ISH_GP_5"),
 174         PINCTRL_PIN(118, "I2S_MCLK1_OUT"),
 175         PINCTRL_PIN(119, "GSPI2_CLK_LOOPBK"),
 176         /* GPP_U */
 177         PINCTRL_PIN(120, "UART3_RXD"),
 178         PINCTRL_PIN(121, "UART3_TXD"),
 179         PINCTRL_PIN(122, "UART3_RTSB"),
 180         PINCTRL_PIN(123, "UART3_CTSB"),
 181         PINCTRL_PIN(124, "GSPI3_CS0B"),
 182         PINCTRL_PIN(125, "GSPI3_CLK"),
 183         PINCTRL_PIN(126, "GSPI3_MISO"),
 184         PINCTRL_PIN(127, "GSPI3_MOSI"),
 185         PINCTRL_PIN(128, "GSPI4_CS0B"),
 186         PINCTRL_PIN(129, "GSPI4_CLK"),
 187         PINCTRL_PIN(130, "GSPI4_MISO"),
 188         PINCTRL_PIN(131, "GSPI4_MOSI"),
 189         PINCTRL_PIN(132, "GSPI5_CS0B"),
 190         PINCTRL_PIN(133, "GSPI5_CLK"),
 191         PINCTRL_PIN(134, "GSPI5_MISO"),
 192         PINCTRL_PIN(135, "GSPI5_MOSI"),
 193         PINCTRL_PIN(136, "GSPI6_CS0B"),
 194         PINCTRL_PIN(137, "GSPI6_CLK"),
 195         PINCTRL_PIN(138, "GSPI6_MISO"),
 196         PINCTRL_PIN(139, "GSPI6_MOSI"),
 197         PINCTRL_PIN(140, "GSPI3_CLK_LOOPBK"),
 198         PINCTRL_PIN(141, "GSPI4_CLK_LOOPBK"),
 199         PINCTRL_PIN(142, "GSPI5_CLK_LOOPBK"),
 200         PINCTRL_PIN(143, "GSPI6_CLK_LOOPBK"),
 201         /* vGPIO */
 202         PINCTRL_PIN(144, "CNV_BTEN"),
 203         PINCTRL_PIN(145, "CNV_BT_HOST_WAKEB"),
 204         PINCTRL_PIN(146, "CNV_BT_IF_SELECT"),
 205         PINCTRL_PIN(147, "vCNV_BT_UART_TXD"),
 206         PINCTRL_PIN(148, "vCNV_BT_UART_RXD"),
 207         PINCTRL_PIN(149, "vCNV_BT_UART_CTS_B"),
 208         PINCTRL_PIN(150, "vCNV_BT_UART_RTS_B"),
 209         PINCTRL_PIN(151, "vCNV_MFUART1_TXD"),
 210         PINCTRL_PIN(152, "vCNV_MFUART1_RXD"),
 211         PINCTRL_PIN(153, "vCNV_MFUART1_CTS_B"),
 212         PINCTRL_PIN(154, "vCNV_MFUART1_RTS_B"),
 213         PINCTRL_PIN(155, "vUART0_TXD"),
 214         PINCTRL_PIN(156, "vUART0_RXD"),
 215         PINCTRL_PIN(157, "vUART0_CTS_B"),
 216         PINCTRL_PIN(158, "vUART0_RTS_B"),
 217         PINCTRL_PIN(159, "vISH_UART0_TXD"),
 218         PINCTRL_PIN(160, "vISH_UART0_RXD"),
 219         PINCTRL_PIN(161, "vISH_UART0_CTS_B"),
 220         PINCTRL_PIN(162, "vISH_UART0_RTS_B"),
 221         PINCTRL_PIN(163, "vCNV_BT_I2S_BCLK"),
 222         PINCTRL_PIN(164, "vCNV_BT_I2S_WS_SYNC"),
 223         PINCTRL_PIN(165, "vCNV_BT_I2S_SDO"),
 224         PINCTRL_PIN(166, "vCNV_BT_I2S_SDI"),
 225         PINCTRL_PIN(167, "vI2S2_SCLK"),
 226         PINCTRL_PIN(168, "vI2S2_SFRM"),
 227         PINCTRL_PIN(169, "vI2S2_TXD"),
 228         PINCTRL_PIN(170, "vI2S2_RXD"),
 229         /* GPP_C */
 230         PINCTRL_PIN(171, "SMBCLK"),
 231         PINCTRL_PIN(172, "SMBDATA"),
 232         PINCTRL_PIN(173, "SMBALERTB"),
 233         PINCTRL_PIN(174, "SML0CLK"),
 234         PINCTRL_PIN(175, "SML0DATA"),
 235         PINCTRL_PIN(176, "SML0ALERTB"),
 236         PINCTRL_PIN(177, "SML1CLK"),
 237         PINCTRL_PIN(178, "SML1DATA"),
 238         PINCTRL_PIN(179, "UART0_RXD"),
 239         PINCTRL_PIN(180, "UART0_TXD"),
 240         PINCTRL_PIN(181, "UART0_RTSB"),
 241         PINCTRL_PIN(182, "UART0_CTSB"),
 242         PINCTRL_PIN(183, "UART1_RXD"),
 243         PINCTRL_PIN(184, "UART1_TXD"),
 244         PINCTRL_PIN(185, "UART1_RTSB"),
 245         PINCTRL_PIN(186, "UART1_CTSB"),
 246         PINCTRL_PIN(187, "I2C0_SDA"),
 247         PINCTRL_PIN(188, "I2C0_SCL"),
 248         PINCTRL_PIN(189, "I2C1_SDA"),
 249         PINCTRL_PIN(190, "I2C1_SCL"),
 250         PINCTRL_PIN(191, "UART2_RXD"),
 251         PINCTRL_PIN(192, "UART2_TXD"),
 252         PINCTRL_PIN(193, "UART2_RTSB"),
 253         PINCTRL_PIN(194, "UART2_CTSB"),
 254         /* GPP_F */
 255         PINCTRL_PIN(195, "CNV_BRI_DT"),
 256         PINCTRL_PIN(196, "CNV_BRI_RSP"),
 257         PINCTRL_PIN(197, "CNV_RGI_DT"),
 258         PINCTRL_PIN(198, "CNV_RGI_RSP"),
 259         PINCTRL_PIN(199, "CNV_RF_RESET_B"),
 260         PINCTRL_PIN(200, "GPPC_F_5"),
 261         PINCTRL_PIN(201, "CNV_PA_BLANKING"),
 262         PINCTRL_PIN(202, "GPPC_F_7"),
 263         PINCTRL_PIN(203, "I2S_MCLK2_INOUT"),
 264         PINCTRL_PIN(204, "BOOTMPC"),
 265         PINCTRL_PIN(205, "GPPC_F_10"),
 266         PINCTRL_PIN(206, "GPPC_F_11"),
 267         PINCTRL_PIN(207, "GSXDOUT"),
 268         PINCTRL_PIN(208, "GSXSLOAD"),
 269         PINCTRL_PIN(209, "GSXDIN"),
 270         PINCTRL_PIN(210, "GSXSRESETB"),
 271         PINCTRL_PIN(211, "GSXCLK"),
 272         PINCTRL_PIN(212, "GMII_MDC"),
 273         PINCTRL_PIN(213, "GMII_MDIO"),
 274         PINCTRL_PIN(214, "SRCCLKREQB_6"),
 275         PINCTRL_PIN(215, "EXT_PWR_GATEB"),
 276         PINCTRL_PIN(216, "EXT_PWR_GATE2B"),
 277         PINCTRL_PIN(217, "VNN_CTRL"),
 278         PINCTRL_PIN(218, "V1P05_CTRL"),
 279         PINCTRL_PIN(219, "GPPF_CLK_LOOPBACK"),
 280         /* HVCMOS */
 281         PINCTRL_PIN(220, "L_BKLTEN"),
 282         PINCTRL_PIN(221, "L_BKLTCTL"),
 283         PINCTRL_PIN(222, "L_VDDEN"),
 284         PINCTRL_PIN(223, "SYS_PWROK"),
 285         PINCTRL_PIN(224, "SYS_RESETB"),
 286         PINCTRL_PIN(225, "MLK_RSTB"),
 287         /* GPP_E */
 288         PINCTRL_PIN(226, "SATAXPCIE_0"),
 289         PINCTRL_PIN(227, "SPI1_IO_2"),
 290         PINCTRL_PIN(228, "SPI1_IO_3"),
 291         PINCTRL_PIN(229, "CPU_GP_0"),
 292         PINCTRL_PIN(230, "SATA_DEVSLP_0"),
 293         PINCTRL_PIN(231, "SATA_DEVSLP_1"),
 294         PINCTRL_PIN(232, "GPPC_E_6"),
 295         PINCTRL_PIN(233, "CPU_GP_1"),
 296         PINCTRL_PIN(234, "SPI1_CS1B"),
 297         PINCTRL_PIN(235, "USB2_OCB_0"),
 298         PINCTRL_PIN(236, "SPI1_CSB"),
 299         PINCTRL_PIN(237, "SPI1_CLK"),
 300         PINCTRL_PIN(238, "SPI1_MISO_IO_1"),
 301         PINCTRL_PIN(239, "SPI1_MOSI_IO_0"),
 302         PINCTRL_PIN(240, "DDSP_HPD_A"),
 303         PINCTRL_PIN(241, "ISH_GP_6"),
 304         PINCTRL_PIN(242, "ISH_GP_7"),
 305         PINCTRL_PIN(243, "GPPC_E_17"),
 306         PINCTRL_PIN(244, "DDP1_CTRLCLK"),
 307         PINCTRL_PIN(245, "DDP1_CTRLDATA"),
 308         PINCTRL_PIN(246, "DDP2_CTRLCLK"),
 309         PINCTRL_PIN(247, "DDP2_CTRLDATA"),
 310         PINCTRL_PIN(248, "DDPA_CTRLCLK"),
 311         PINCTRL_PIN(249, "DDPA_CTRLDATA"),
 312         PINCTRL_PIN(250, "SPI1_CLK_LOOPBK"),
 313         /* JTAG */
 314         PINCTRL_PIN(251, "JTAG_TDO"),
 315         PINCTRL_PIN(252, "JTAGX"),
 316         PINCTRL_PIN(253, "PRDYB"),
 317         PINCTRL_PIN(254, "PREQB"),
 318         PINCTRL_PIN(255, "CPU_TRSTB"),
 319         PINCTRL_PIN(256, "JTAG_TDI"),
 320         PINCTRL_PIN(257, "JTAG_TMS"),
 321         PINCTRL_PIN(258, "JTAG_TCK"),
 322         PINCTRL_PIN(259, "DBG_PMODE"),
 323         /* GPP_R */
 324         PINCTRL_PIN(260, "HDA_BCLK"),
 325         PINCTRL_PIN(261, "HDA_SYNC"),
 326         PINCTRL_PIN(262, "HDA_SDO"),
 327         PINCTRL_PIN(263, "HDA_SDI_0"),
 328         PINCTRL_PIN(264, "HDA_RSTB"),
 329         PINCTRL_PIN(265, "HDA_SDI_1"),
 330         PINCTRL_PIN(266, "GPP_R_6"),
 331         PINCTRL_PIN(267, "GPP_R_7"),
 332         /* SPI */
 333         PINCTRL_PIN(268, "SPI0_IO_2"),
 334         PINCTRL_PIN(269, "SPI0_IO_3"),
 335         PINCTRL_PIN(270, "SPI0_MOSI_IO_0"),
 336         PINCTRL_PIN(271, "SPI0_MISO_IO_1"),
 337         PINCTRL_PIN(272, "SPI0_TPM_CSB"),
 338         PINCTRL_PIN(273, "SPI0_FLASH_0_CSB"),
 339         PINCTRL_PIN(274, "SPI0_FLASH_1_CSB"),
 340         PINCTRL_PIN(275, "SPI0_CLK"),
 341         PINCTRL_PIN(276, "SPI0_CLK_LOOPBK"),
 342 };
 343
 344 static const struct intel_padgroup tgllp_community0_gpps[] = {
 345         TGL_GPP(0, 0, 25, 0),                   /* GPP_B */
 346         TGL_GPP(1, 26, 41, 32),                 /* GPP_T */
 347         TGL_GPP(2, 42, 66, 64),                 /* GPP_A */
 348 };
 349
 350 static const struct intel_padgroup tgllp_community1_gpps[] = {
 351         TGL_GPP(0, 67, 74, 96),                 /* GPP_S */
 352         TGL_GPP(1, 75, 98, 128),                /* GPP_H */
 353         TGL_GPP(2, 99, 119, 160),               /* GPP_D */
 354         TGL_GPP(3, 120, 143, 192),              /* GPP_U */
 355         TGL_GPP(4, 144, 170, 224),              /* vGPIO */
 356 };
 357
 358 static const struct intel_padgroup tgllp_community4_gpps[] = {
 359         TGL_GPP(0, 171, 194, 256),              /* GPP_C */
 360         TGL_GPP(1, 195, 219, 288),              /* GPP_F */
 361         TGL_GPP(2, 220, 225, TGL_NO_GPIO),      /* HVCMOS */
 362         TGL_GPP(3, 226, 250, 320),              /* GPP_E */
 363         TGL_GPP(4, 251, 259, TGL_NO_GPIO),      /* JTAG */
 364 };
 365
 366 static const struct intel_padgroup tgllp_community5_gpps[] = {
 367         TGL_GPP(0, 260, 267, 352),              /* GPP_R */
 368         TGL_GPP(1, 268, 276, TGL_NO_GPIO),      /* SPI */
 369 };
 370
 371 static const struct intel_community tgllp_communities[] = {
 372         TGL_COMMUNITY(0, 0, 66, tgllp_community0_gpps),
 373         TGL_COMMUNITY(1, 67, 170, tgllp_community1_gpps),
 374         TGL_COMMUNITY(2, 171, 259, tgllp_community4_gpps),
 375         TGL_COMMUNITY(3, 260, 276, tgllp_community5_gpps),
 376 };
 377
 378 static const struct intel_pinctrl_soc_data tgllp_soc_data = {
 379         .pins = tgllp_pins,
 380         .npins = ARRAY_SIZE(tgllp_pins),
 381         .communities = tgllp_communities,
 382         .ncommunities = ARRAY_SIZE(tgllp_communities),
 383 };
 384
 385 static const struct acpi_device_id tgl_pinctrl_acpi_match[] = {
 386         { "INT34C5", (kernel_ulong_t)&tgllp_soc_data },
 387         { }
 388 };
 389 MODULE_DEVICE_TABLE(acpi, tgl_pinctrl_acpi_match);
 390
 391 static INTEL_PINCTRL_PM_OPS(tgl_pinctrl_pm_ops);
 392
 393 static struct platform_driver tgl_pinctrl_driver = {
 394         .probe = intel_pinctrl_probe_by_hid,
 395         .driver = {
 396                 .name = "tigerlake-pinctrl",
 397                 .acpi_match_table = tgl_pinctrl_acpi_match,
 398                 .pm = &tgl_pinctrl_pm_ops,
 399         },
 400 };
 401
 402 module_platform_driver(tgl_pinctrl_driver);
 403
 404 MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
 405 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
 406 MODULE_DESCRIPTION("Intel Tiger Lake PCH pinctrl/GPIO driver");
 407 MODULE_LICENSE("GPL v2");