drivers/pinctrl/mediatek/mtk-eint.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 // Copyright (c) 2014-2018 MediaTek Inc.
   3
   4 /*
   5  * Library for MediaTek External Interrupt Support
   6  *
   7  * Author: Maoguang Meng <maoguang.meng@mediatek.com>
   8  *         Sean Wang <sean.wang@mediatek.com>
   9  *
  10  */
  11
  12 #include <linux/delay.h>
  13 #include <linux/err.h>
  14 #include <linux/gpio/driver.h>
  15 #include <linux/io.h>
  16 #include <linux/irqchip/chained_irq.h>
  17 #include <linux/irqdomain.h>
  18 #include <linux/of_irq.h>
  19 #include <linux/platform_device.h>
  20
  21 #include "mtk-eint.h"
  22
  23 #define MTK_EINT_EDGE_SENSITIVE           0
  24 #define MTK_EINT_LEVEL_SENSITIVE          1
  25 #define MTK_EINT_DBNC_SET_DBNC_BITS       4
  26 #define MTK_EINT_DBNC_RST_BIT             (0x1 << 1)
  27 #define MTK_EINT_DBNC_SET_EN              (0x1 << 0)
  28
  29 static const struct mtk_eint_regs mtk_generic_eint_regs = {
  30         .stat      = 0x000,
  31         .ack       = 0x040,
  32         .mask      = 0x080,
  33         .mask_set  = 0x0c0,
  34         .mask_clr  = 0x100,
  35         .sens      = 0x140,
  36         .sens_set  = 0x180,
  37         .sens_clr  = 0x1c0,
  38         .soft      = 0x200,
  39         .soft_set  = 0x240,
  40         .soft_clr  = 0x280,
  41         .pol       = 0x300,
  42         .pol_set   = 0x340,
  43         .pol_clr   = 0x380,
  44         .dom_en    = 0x400,
  45         .dbnc_ctrl = 0x500,
  46         .dbnc_set  = 0x600,
  47         .dbnc_clr  = 0x700,
  48 };
  49
  50 static void __iomem *mtk_eint_get_offset(struct mtk_eint *eint,
  51                                          unsigned int eint_num,
  52                                          unsigned int offset)
  53 {
  54         unsigned int eint_base = 0;
  55         void __iomem *reg;
  56
  57         if (eint_num >= eint->hw->ap_num)
  58                 eint_base = eint->hw->ap_num;
  59
  60         reg = eint->base + offset + ((eint_num - eint_base) / 32) * 4;
  61
  62         return reg;
  63 }
  64
  65 static unsigned int mtk_eint_can_en_debounce(struct mtk_eint *eint,
  66                                              unsigned int eint_num)
  67 {
  68         unsigned int sens;
  69         unsigned int bit = BIT(eint_num % 32);
  70         void __iomem *reg = mtk_eint_get_offset(eint, eint_num,
  71                                                 eint->regs->sens);
  72
  73         if (readl(reg) & bit)
  74                 sens = MTK_EINT_LEVEL_SENSITIVE;
  75         else
  76                 sens = MTK_EINT_EDGE_SENSITIVE;
  77
  78         if (eint_num < eint->hw->db_cnt && sens != MTK_EINT_EDGE_SENSITIVE)
  79                 return 1;
  80         else
  81                 return 0;
  82 }
  83
  84 static int mtk_eint_flip_edge(struct mtk_eint *eint, int hwirq)
  85 {
  86         int start_level, curr_level;
  87         unsigned int reg_offset;
  88         u32 mask = BIT(hwirq & 0x1f);
  89         u32 port = (hwirq >> 5) & eint->hw->port_mask;
  90         void __iomem *reg = eint->base + (port << 2);
  91
  92         curr_level = eint->gpio_xlate->get_gpio_state(eint->pctl, hwirq);
  93
  94         do {
  95                 start_level = curr_level;
  96                 if (start_level)
  97                         reg_offset = eint->regs->pol_clr;
  98                 else
  99                         reg_offset = eint->regs->pol_set;
 100                 writel(mask, reg + reg_offset);
 101
 102                 curr_level = eint->gpio_xlate->get_gpio_state(eint->pctl,
 103                                                               hwirq);
 104         } while (start_level != curr_level);
 105
 106         return start_level;
 107 }
 108
 109 static void mtk_eint_mask(struct irq_data *d)
 110 {
 111         struct mtk_eint *eint = irq_data_get_irq_chip_data(d);
 112         u32 mask = BIT(d->hwirq & 0x1f);
 113         void __iomem *reg = mtk_eint_get_offset(eint, d->hwirq,
 114                                                 eint->regs->mask_set);
 115
 116         eint->cur_mask[d->hwirq >> 5] &= ~mask;
 117
 118         writel(mask, reg);
 119 }
 120
 121 static void mtk_eint_unmask(struct irq_data *d)
 122 {
 123         struct mtk_eint *eint = irq_data_get_irq_chip_data(d);
 124         u32 mask = BIT(d->hwirq & 0x1f);
 125         void __iomem *reg = mtk_eint_get_offset(eint, d->hwirq,
 126                                                 eint->regs->mask_clr);
 127
 128         eint->cur_mask[d->hwirq >> 5] |= mask;
 129
 130         writel(mask, reg);
 131
 132         if (eint->dual_edge[d->hwirq])
 133                 mtk_eint_flip_edge(eint, d->hwirq);
 134 }
 135
 136 static unsigned int mtk_eint_get_mask(struct mtk_eint *eint,
 137                                       unsigned int eint_num)
 138 {
 139         unsigned int bit = BIT(eint_num % 32);
 140         void __iomem *reg = mtk_eint_get_offset(eint, eint_num,
 141                                                 eint->regs->mask);
 142
 143         return !!(readl(reg) & bit);
 144 }
 145
 146 static void mtk_eint_ack(struct irq_data *d)
 147 {
 148         struct mtk_eint *eint = irq_data_get_irq_chip_data(d);
 149         u32 mask = BIT(d->hwirq & 0x1f);
 150         void __iomem *reg = mtk_eint_get_offset(eint, d->hwirq,
 151                                                 eint->regs->ack);
 152
 153         writel(mask, reg);
 154 }
 155
 156 static int mtk_eint_set_type(struct irq_data *d, unsigned int type)
 157 {
 158         struct mtk_eint *eint = irq_data_get_irq_chip_data(d);
 159         u32 mask = BIT(d->hwirq & 0x1f);
 160         void __iomem *reg;
 161
 162         if (((type & IRQ_TYPE_EDGE_BOTH) && (type & IRQ_TYPE_LEVEL_MASK)) ||
 163             ((type & IRQ_TYPE_LEVEL_MASK) == IRQ_TYPE_LEVEL_MASK)) {
 164                 dev_err(eint->dev,
 165                         "Can't configure IRQ%d (EINT%lu) for type 0x%X\n",
 166                         d->irq, d->hwirq, type);
 167                 return -EINVAL;
 168         }
 169
 170         if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
 171                 eint->dual_edge[d->hwirq] = 1;
 172         else
 173                 eint->dual_edge[d->hwirq] = 0;
 174
 175         if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING)) {
 176                 reg = mtk_eint_get_offset(eint, d->hwirq, eint->regs->pol_clr);
 177                 writel(mask, reg);
 178         } else {
 179                 reg = mtk_eint_get_offset(eint, d->hwirq, eint->regs->pol_set);
 180                 writel(mask, reg);
 181         }
 182
 183         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
 184                 reg = mtk_eint_get_offset(eint, d->hwirq, eint->regs->sens_clr);
 185                 writel(mask, reg);
 186         } else {
 187                 reg = mtk_eint_get_offset(eint, d->hwirq, eint->regs->sens_set);
 188                 writel(mask, reg);
 189         }
 190
 191         if (eint->dual_edge[d->hwirq])
 192                 mtk_eint_flip_edge(eint, d->hwirq);
 193
 194         return 0;
 195 }
 196
 197 static int mtk_eint_irq_set_wake(struct irq_data *d, unsigned int on)
 198 {
 199         struct mtk_eint *eint = irq_data_get_irq_chip_data(d);
 200         int shift = d->hwirq & 0x1f;
 201         int reg = d->hwirq >> 5;
 202
 203         if (on)
 204                 eint->wake_mask[reg] |= BIT(shift);
 205         else
 206                 eint->wake_mask[reg] &= ~BIT(shift);
 207
 208         return 0;
 209 }
 210
 211 static void mtk_eint_chip_write_mask(const struct mtk_eint *eint,
 212                                      void __iomem *base, u32 *buf)
 213 {
 214         int port;
 215         void __iomem *reg;
 216
 217         for (port = 0; port < eint->hw->ports; port++) {
 218                 reg = base + (port << 2);
 219                 writel_relaxed(~buf[port], reg + eint->regs->mask_set);
 220                 writel_relaxed(buf[port], reg + eint->regs->mask_clr);
 221         }
 222 }
 223
 224 static int mtk_eint_irq_request_resources(struct irq_data *d)
 225 {
 226         struct mtk_eint *eint = irq_data_get_irq_chip_data(d);
 227         struct gpio_chip *gpio_c;
 228         unsigned int gpio_n;
 229         int err;
 230
 231         err = eint->gpio_xlate->get_gpio_n(eint->pctl, d->hwirq,
 232                                            &gpio_n, &gpio_c);
 233         if (err < 0) {
 234                 dev_err(eint->dev, "Can not find pin\n");
 235                 return err;
 236         }
 237
 238         err = gpiochip_lock_as_irq(gpio_c, gpio_n);
 239         if (err < 0) {
 240                 dev_err(eint->dev, "unable to lock HW IRQ %lu for IRQ\n",
 241                         irqd_to_hwirq(d));
 242                 return err;
 243         }
 244
 245         err = eint->gpio_xlate->set_gpio_as_eint(eint->pctl, d->hwirq);
 246         if (err < 0) {
 247                 dev_err(eint->dev, "Can not eint mode\n");
 248                 return err;
 249         }
 250
 251         return 0;
 252 }
 253
 254 static void mtk_eint_irq_release_resources(struct irq_data *d)
 255 {
 256         struct mtk_eint *eint = irq_data_get_irq_chip_data(d);
 257         struct gpio_chip *gpio_c;
 258         unsigned int gpio_n;
 259
 260         eint->gpio_xlate->get_gpio_n(eint->pctl, d->hwirq, &gpio_n,
 261                                      &gpio_c);
 262
 263         gpiochip_unlock_as_irq(gpio_c, gpio_n);
 264 }
 265
 266 static struct irq_chip mtk_eint_irq_chip = {
 267         .name = "mt-eint",
 268         .irq_disable = mtk_eint_mask,
 269         .irq_mask = mtk_eint_mask,
 270         .irq_unmask = mtk_eint_unmask,
 271         .irq_ack = mtk_eint_ack,
 272         .irq_set_type = mtk_eint_set_type,
 273         .irq_set_wake = mtk_eint_irq_set_wake,
 274         .irq_request_resources = mtk_eint_irq_request_resources,
 275         .irq_release_resources = mtk_eint_irq_release_resources,
 276 };
 277
 278 static unsigned int mtk_eint_hw_init(struct mtk_eint *eint)
 279 {
 280         void __iomem *reg = eint->base + eint->regs->dom_en;
 281         unsigned int i;
 282
 283         for (i = 0; i < eint->hw->ap_num; i += 32) {
 284                 writel(0xffffffff, reg);
 285                 reg += 4;
 286         }
 287
 288         return 0;
 289 }
 290
 291 static inline void
 292 mtk_eint_debounce_process(struct mtk_eint *eint, int index)
 293 {
 294         unsigned int rst, ctrl_offset;
 295         unsigned int bit, dbnc;
 296
 297         ctrl_offset = (index / 4) * 4 + eint->regs->dbnc_ctrl;
 298         dbnc = readl(eint->base + ctrl_offset);
 299         bit = MTK_EINT_DBNC_SET_EN << ((index % 4) * 8);
 300         if ((bit & dbnc) > 0) {
 301                 ctrl_offset = (index / 4) * 4 + eint->regs->dbnc_set;
 302                 rst = MTK_EINT_DBNC_RST_BIT << ((index % 4) * 8);
 303                 writel(rst, eint->base + ctrl_offset);
 304         }
 305 }
 306
 307 static void mtk_eint_irq_handler(struct irq_desc *desc)
 308 {
 309         struct irq_chip *chip = irq_desc_get_chip(desc);
 310         struct mtk_eint *eint = irq_desc_get_handler_data(desc);
 311         unsigned int status, eint_num;
 312         int offset, mask_offset, index, virq;
 313         void __iomem *reg =  mtk_eint_get_offset(eint, 0, eint->regs->stat);
 314         int dual_edge, start_level, curr_level;
 315
 316         chained_irq_enter(chip, desc);
 317         for (eint_num = 0; eint_num < eint->hw->ap_num; eint_num += 32,
 318              reg += 4) {
 319                 status = readl(reg);
 320                 while (status) {
 321                         offset = __ffs(status);
 322                         mask_offset = eint_num >> 5;
 323                         index = eint_num + offset;
 324                         virq = irq_find_mapping(eint->domain, index);
 325                         status &= ~BIT(offset);
 326
 327                         /*
 328                          * If we get an interrupt on pin that was only required
 329                          * for wake (but no real interrupt requested), mask the
 330                          * interrupt (as would mtk_eint_resume do anyway later
 331                          * in the resume sequence).
 332                          */
 333                         if (eint->wake_mask[mask_offset] & BIT(offset) &&
 334                             !(eint->cur_mask[mask_offset] & BIT(offset))) {
 335                                 writel_relaxed(BIT(offset), reg -
 336                                         eint->regs->stat +
 337                                         eint->regs->mask_set);
 338                         }
 339
 340                         dual_edge = eint->dual_edge[index];
 341                         if (dual_edge) {
 342                                 /*
 343                                  * Clear soft-irq in case we raised it last
 344                                  * time.
 345                                  */
 346                                 writel(BIT(offset), reg - eint->regs->stat +
 347                                        eint->regs->soft_clr);
 348
 349                                 start_level =
 350                                 eint->gpio_xlate->get_gpio_state(eint->pctl,
 351                                                                  index);
 352                         }
 353
 354                         generic_handle_irq(virq);
 355
 356                         if (dual_edge) {
 357                                 curr_level = mtk_eint_flip_edge(eint, index);
 358
 359                                 /*
 360                                  * If level changed, we might lost one edge
 361                                  * interrupt, raised it through soft-irq.
 362                                  */
 363                                 if (start_level != curr_level)
 364                                         writel(BIT(offset), reg -
 365                                                eint->regs->stat +
 366                                                eint->regs->soft_set);
 367                         }
 368
 369                         if (index < eint->hw->db_cnt)
 370                                 mtk_eint_debounce_process(eint, index);
 371                 }
 372         }
 373         chained_irq_exit(chip, desc);
 374 }
 375
 376 int mtk_eint_do_suspend(struct mtk_eint *eint)
 377 {
 378         mtk_eint_chip_write_mask(eint, eint->base, eint->wake_mask);
 379
 380         return 0;
 381 }
 382
 383 int mtk_eint_do_resume(struct mtk_eint *eint)
 384 {
 385         mtk_eint_chip_write_mask(eint, eint->base, eint->cur_mask);
 386
 387         return 0;
 388 }
 389
 390 int mtk_eint_set_debounce(struct mtk_eint *eint, unsigned long eint_num,
 391                           unsigned int debounce)
 392 {
 393         int virq, eint_offset;
 394         unsigned int set_offset, bit, clr_bit, clr_offset, rst, i, unmask,
 395                      dbnc;
 396         static const unsigned int debounce_time[] = {500, 1000, 16000, 32000,
 397                                                      64000, 128000, 256000};
 398         struct irq_data *d;
 399
 400         virq = irq_find_mapping(eint->domain, eint_num);
 401         eint_offset = (eint_num % 4) * 8;
 402         d = irq_get_irq_data(virq);
 403
 404         set_offset = (eint_num / 4) * 4 + eint->regs->dbnc_set;
 405         clr_offset = (eint_num / 4) * 4 + eint->regs->dbnc_clr;
 406
 407         if (!mtk_eint_can_en_debounce(eint, eint_num))
 408                 return -EINVAL;
 409
 410         dbnc = ARRAY_SIZE(debounce_time);
 411         for (i = 0; i < ARRAY_SIZE(debounce_time); i++) {
 412                 if (debounce <= debounce_time[i]) {
 413                         dbnc = i;
 414                         break;
 415                 }
 416         }
 417
 418         if (!mtk_eint_get_mask(eint, eint_num)) {
 419                 mtk_eint_mask(d);
 420                 unmask = 1;
 421         } else {
 422                 unmask = 0;
 423         }
 424
 425         clr_bit = 0xff << eint_offset;
 426         writel(clr_bit, eint->base + clr_offset);
 427
 428         bit = ((dbnc << MTK_EINT_DBNC_SET_DBNC_BITS) | MTK_EINT_DBNC_SET_EN) <<
 429                 eint_offset;
 430         rst = MTK_EINT_DBNC_RST_BIT << eint_offset;
 431         writel(rst | bit, eint->base + set_offset);
 432
 433         /*
 434          * Delay a while (more than 2T) to wait for hw debounce counter reset
 435          * work correctly.
 436          */
 437         udelay(1);
 438         if (unmask == 1)
 439                 mtk_eint_unmask(d);
 440
 441         return 0;
 442 }
 443
 444 int mtk_eint_find_irq(struct mtk_eint *eint, unsigned long eint_n)
 445 {
 446         int irq;
 447
 448         irq = irq_find_mapping(eint->domain, eint_n);
 449         if (!irq)
 450                 return -EINVAL;
 451
 452         return irq;
 453 }
 454
 455 int mtk_eint_do_init(struct mtk_eint *eint)
 456 {
 457         int i;
 458
 459         /* If clients don't assign a specific regs, let's use generic one */
 460         if (!eint->regs)
 461                 eint->regs = &mtk_generic_eint_regs;
 462
 463         eint->wake_mask = devm_kcalloc(eint->dev, eint->hw->ports,
 464                                        sizeof(*eint->wake_mask), GFP_KERNEL);
 465         if (!eint->wake_mask)
 466                 return -ENOMEM;
 467
 468         eint->cur_mask = devm_kcalloc(eint->dev, eint->hw->ports,
 469                                       sizeof(*eint->cur_mask), GFP_KERNEL);
 470         if (!eint->cur_mask)
 471                 return -ENOMEM;
 472
 473         eint->dual_edge = devm_kcalloc(eint->dev, eint->hw->ap_num,
 474                                        sizeof(int), GFP_KERNEL);
 475         if (!eint->dual_edge)
 476                 return -ENOMEM;
 477
 478         eint->domain = irq_domain_add_linear(eint->dev->of_node,
 479                                              eint->hw->ap_num,
 480                                              &irq_domain_simple_ops, NULL);
 481         if (!eint->domain)
 482                 return -ENOMEM;
 483
 484         mtk_eint_hw_init(eint);
 485         for (i = 0; i < eint->hw->ap_num; i++) {
 486                 int virq = irq_create_mapping(eint->domain, i);
 487
 488                 irq_set_chip_and_handler(virq, &mtk_eint_irq_chip,
 489                                          handle_level_irq);
 490                 irq_set_chip_data(virq, eint);
 491         }
 492
 493         irq_set_chained_handler_and_data(eint->irq, mtk_eint_irq_handler,
 494                                          eint);
 495
 496         return 0;
 497 }