drivers/pinctrl/mediatek/pinctrl-mt8135.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2014 MediaTek Inc.
   4  * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com>
   5  */
   6
   7 #include <linux/init.h>
   8 #include <linux/platform_device.h>
   9 #include <linux/of.h>
  10 #include <linux/of_device.h>
  11 #include <linux/pinctrl/pinctrl.h>
  12 #include <linux/regmap.h>
  13 #include <dt-bindings/pinctrl/mt65xx.h>
  14
  15 #include "pinctrl-mtk-common.h"
  16 #include "pinctrl-mtk-mt8135.h"
  17
  18 #define DRV_BASE1                               0x500
  19 #define DRV_BASE2                               0x510
  20 #define PUPD_BASE1                              0x400
  21 #define PUPD_BASE2                              0x450
  22 #define R0_BASE1                                0x4d0
  23 #define R1_BASE1                                0x200
  24 #define R1_BASE2                                0x250
  25
  26 struct mtk_spec_pull_set {
  27         unsigned char pin;
  28         unsigned char pupd_bit;
  29         unsigned short pupd_offset;
  30         unsigned short r0_offset;
  31         unsigned short r1_offset;
  32         unsigned char r0_bit;
  33         unsigned char r1_bit;
  34 };
  35
  36 #define SPEC_PULL(_pin, _pupd_offset, _pupd_bit, _r0_offset, \
  37         _r0_bit, _r1_offset, _r1_bit)   \
  38         {       \
  39                 .pin = _pin,    \
  40                 .pupd_offset = _pupd_offset,    \
  41                 .pupd_bit = _pupd_bit,  \
  42                 .r0_offset = _r0_offset, \
  43                 .r0_bit = _r0_bit, \
  44                 .r1_offset = _r1_offset, \
  45                 .r1_bit = _r1_bit, \
  46         }
  47
  48 static const struct mtk_drv_group_desc mt8135_drv_grp[] =  {
  49         /* E8E4E2 2/4/6/8/10/12/14/16 */
  50         MTK_DRV_GRP(2, 16, 0, 2, 2),
  51         /* E8E4  4/8/12/16 */
  52         MTK_DRV_GRP(4, 16, 1, 2, 4),
  53         /* E4E2  2/4/6/8 */
  54         MTK_DRV_GRP(2, 8, 0, 1, 2),
  55         /* E16E8E4 4/8/12/16/20/24/28/32 */
  56         MTK_DRV_GRP(4, 32, 0, 2, 4)
  57 };
  58
  59 static const struct mtk_pin_drv_grp mt8135_pin_drv[] = {
  60         MTK_PIN_DRV_GRP(0, DRV_BASE1, 0, 0),
  61         MTK_PIN_DRV_GRP(1, DRV_BASE1, 0, 0),
  62         MTK_PIN_DRV_GRP(2, DRV_BASE1, 0, 0),
  63         MTK_PIN_DRV_GRP(3, DRV_BASE1, 0, 0),
  64         MTK_PIN_DRV_GRP(4, DRV_BASE1, 4, 0),
  65         MTK_PIN_DRV_GRP(5, DRV_BASE1, 8, 0),
  66         MTK_PIN_DRV_GRP(6, DRV_BASE1, 0, 0),
  67         MTK_PIN_DRV_GRP(7, DRV_BASE1, 0, 0),
  68         MTK_PIN_DRV_GRP(8, DRV_BASE1, 0, 0),
  69         MTK_PIN_DRV_GRP(9, DRV_BASE1, 0, 0),
  70
  71         MTK_PIN_DRV_GRP(10, DRV_BASE1, 12, 1),
  72         MTK_PIN_DRV_GRP(11, DRV_BASE1, 12, 1),
  73         MTK_PIN_DRV_GRP(12, DRV_BASE1, 12, 1),
  74         MTK_PIN_DRV_GRP(13, DRV_BASE1, 12, 1),
  75         MTK_PIN_DRV_GRP(14, DRV_BASE1, 12, 1),
  76         MTK_PIN_DRV_GRP(15, DRV_BASE1, 12, 1),
  77         MTK_PIN_DRV_GRP(16, DRV_BASE1, 12, 1),
  78         MTK_PIN_DRV_GRP(17, DRV_BASE1, 16, 1),
  79         MTK_PIN_DRV_GRP(18, DRV_BASE1, 16, 1),
  80         MTK_PIN_DRV_GRP(19, DRV_BASE1, 16, 1),
  81         MTK_PIN_DRV_GRP(20, DRV_BASE1, 16, 1),
  82         MTK_PIN_DRV_GRP(21, DRV_BASE1, 16, 1),
  83         MTK_PIN_DRV_GRP(22, DRV_BASE1, 16, 1),
  84         MTK_PIN_DRV_GRP(23, DRV_BASE1, 16, 1),
  85         MTK_PIN_DRV_GRP(24, DRV_BASE1, 16, 1),
  86         MTK_PIN_DRV_GRP(33, DRV_BASE1, 24, 1),
  87         MTK_PIN_DRV_GRP(34, DRV_BASE2, 12, 2),
  88         MTK_PIN_DRV_GRP(37, DRV_BASE2, 20, 1),
  89         MTK_PIN_DRV_GRP(38, DRV_BASE2, 20, 1),
  90         MTK_PIN_DRV_GRP(39, DRV_BASE2, 20, 1),
  91         MTK_PIN_DRV_GRP(40, DRV_BASE2, 24, 1),
  92         MTK_PIN_DRV_GRP(41, DRV_BASE2, 24, 1),
  93         MTK_PIN_DRV_GRP(42, DRV_BASE2, 24, 1),
  94         MTK_PIN_DRV_GRP(43, DRV_BASE2, 28, 1),
  95         MTK_PIN_DRV_GRP(44, DRV_BASE2, 28, 1),
  96         MTK_PIN_DRV_GRP(45, DRV_BASE2, 28, 1),
  97         MTK_PIN_DRV_GRP(46, DRV_BASE2, 28, 1),
  98         MTK_PIN_DRV_GRP(47, DRV_BASE2, 28, 1),
  99
 100         MTK_PIN_DRV_GRP(49, DRV_BASE2+0x10, 0, 1),
 101         MTK_PIN_DRV_GRP(50, DRV_BASE2+0x10, 4, 1),
 102         MTK_PIN_DRV_GRP(51, DRV_BASE2+0x10, 8, 1),
 103         MTK_PIN_DRV_GRP(52, DRV_BASE2+0x10, 12, 2),
 104         MTK_PIN_DRV_GRP(53, DRV_BASE2+0x10, 16, 1),
 105         MTK_PIN_DRV_GRP(54, DRV_BASE2+0x10, 20, 1),
 106         MTK_PIN_DRV_GRP(55, DRV_BASE2+0x10, 24, 1),
 107         MTK_PIN_DRV_GRP(56, DRV_BASE2+0x10, 28, 1),
 108
 109         MTK_PIN_DRV_GRP(57, DRV_BASE2+0x20, 0, 1),
 110         MTK_PIN_DRV_GRP(58, DRV_BASE2+0x20, 0, 1),
 111         MTK_PIN_DRV_GRP(59, DRV_BASE2+0x20, 0, 1),
 112         MTK_PIN_DRV_GRP(60, DRV_BASE2+0x20, 0, 1),
 113         MTK_PIN_DRV_GRP(61, DRV_BASE2+0x20, 0, 1),
 114         MTK_PIN_DRV_GRP(62, DRV_BASE2+0x20, 0, 1),
 115         MTK_PIN_DRV_GRP(63, DRV_BASE2+0x20, 4, 1),
 116         MTK_PIN_DRV_GRP(64, DRV_BASE2+0x20, 8, 1),
 117         MTK_PIN_DRV_GRP(65, DRV_BASE2+0x20, 12, 1),
 118         MTK_PIN_DRV_GRP(66, DRV_BASE2+0x20, 16, 1),
 119         MTK_PIN_DRV_GRP(67, DRV_BASE2+0x20, 20, 1),
 120         MTK_PIN_DRV_GRP(68, DRV_BASE2+0x20, 24, 1),
 121         MTK_PIN_DRV_GRP(69, DRV_BASE2+0x20, 28, 1),
 122
 123         MTK_PIN_DRV_GRP(70, DRV_BASE2+0x30, 0, 1),
 124         MTK_PIN_DRV_GRP(71, DRV_BASE2+0x30, 4, 1),
 125         MTK_PIN_DRV_GRP(72, DRV_BASE2+0x30, 8, 1),
 126         MTK_PIN_DRV_GRP(73, DRV_BASE2+0x30, 12, 1),
 127         MTK_PIN_DRV_GRP(74, DRV_BASE2+0x30, 16, 1),
 128         MTK_PIN_DRV_GRP(75, DRV_BASE2+0x30, 20, 1),
 129         MTK_PIN_DRV_GRP(76, DRV_BASE2+0x30, 24, 1),
 130         MTK_PIN_DRV_GRP(77, DRV_BASE2+0x30, 28, 3),
 131         MTK_PIN_DRV_GRP(78, DRV_BASE2+0x30, 28, 3),
 132
 133         MTK_PIN_DRV_GRP(79, DRV_BASE2+0x40, 0, 3),
 134         MTK_PIN_DRV_GRP(80, DRV_BASE2+0x40, 4, 3),
 135
 136         MTK_PIN_DRV_GRP(81, DRV_BASE2+0x30, 28, 3),
 137         MTK_PIN_DRV_GRP(82, DRV_BASE2+0x30, 28, 3),
 138
 139         MTK_PIN_DRV_GRP(83, DRV_BASE2+0x40, 8, 3),
 140         MTK_PIN_DRV_GRP(84, DRV_BASE2+0x40, 8, 3),
 141         MTK_PIN_DRV_GRP(85, DRV_BASE2+0x40, 12, 3),
 142         MTK_PIN_DRV_GRP(86, DRV_BASE2+0x40, 16, 3),
 143         MTK_PIN_DRV_GRP(87, DRV_BASE2+0x40, 8, 3),
 144         MTK_PIN_DRV_GRP(88, DRV_BASE2+0x40, 8, 3),
 145
 146         MTK_PIN_DRV_GRP(89, DRV_BASE2+0x50, 12, 0),
 147         MTK_PIN_DRV_GRP(90, DRV_BASE2+0x50, 12, 0),
 148         MTK_PIN_DRV_GRP(91, DRV_BASE2+0x50, 12, 0),
 149         MTK_PIN_DRV_GRP(92, DRV_BASE2+0x50, 12, 0),
 150         MTK_PIN_DRV_GRP(93, DRV_BASE2+0x50, 12, 0),
 151         MTK_PIN_DRV_GRP(94, DRV_BASE2+0x50, 12, 0),
 152         MTK_PIN_DRV_GRP(95, DRV_BASE2+0x50, 12, 0),
 153
 154         MTK_PIN_DRV_GRP(96, DRV_BASE1+0xb0, 28, 0),
 155
 156         MTK_PIN_DRV_GRP(97, DRV_BASE2+0x50, 12, 0),
 157         MTK_PIN_DRV_GRP(98, DRV_BASE2+0x50, 16, 0),
 158         MTK_PIN_DRV_GRP(99, DRV_BASE2+0x50, 20, 1),
 159         MTK_PIN_DRV_GRP(102, DRV_BASE2+0x50, 24, 1),
 160         MTK_PIN_DRV_GRP(103, DRV_BASE2+0x50, 28, 1),
 161
 162
 163         MTK_PIN_DRV_GRP(104, DRV_BASE2+0x60, 0, 1),
 164         MTK_PIN_DRV_GRP(105, DRV_BASE2+0x60, 4, 1),
 165         MTK_PIN_DRV_GRP(106, DRV_BASE2+0x60, 4, 1),
 166         MTK_PIN_DRV_GRP(107, DRV_BASE2+0x60, 4, 1),
 167         MTK_PIN_DRV_GRP(108, DRV_BASE2+0x60, 4, 1),
 168         MTK_PIN_DRV_GRP(109, DRV_BASE2+0x60, 8, 2),
 169         MTK_PIN_DRV_GRP(110, DRV_BASE2+0x60, 12, 2),
 170         MTK_PIN_DRV_GRP(111, DRV_BASE2+0x60, 16, 2),
 171         MTK_PIN_DRV_GRP(112, DRV_BASE2+0x60, 20, 2),
 172         MTK_PIN_DRV_GRP(113, DRV_BASE2+0x60, 24, 2),
 173         MTK_PIN_DRV_GRP(114, DRV_BASE2+0x60, 28, 2),
 174
 175         MTK_PIN_DRV_GRP(115, DRV_BASE2+0x70, 0, 2),
 176         MTK_PIN_DRV_GRP(116, DRV_BASE2+0x70, 4, 2),
 177         MTK_PIN_DRV_GRP(117, DRV_BASE2+0x70, 8, 2),
 178         MTK_PIN_DRV_GRP(118, DRV_BASE2+0x70, 12, 2),
 179         MTK_PIN_DRV_GRP(119, DRV_BASE2+0x70, 16, 2),
 180         MTK_PIN_DRV_GRP(120, DRV_BASE2+0x70, 20, 2),
 181
 182         MTK_PIN_DRV_GRP(181, DRV_BASE1+0xa0, 12, 1),
 183         MTK_PIN_DRV_GRP(182, DRV_BASE1+0xa0, 16, 1),
 184         MTK_PIN_DRV_GRP(183, DRV_BASE1+0xa0, 20, 1),
 185         MTK_PIN_DRV_GRP(184, DRV_BASE1+0xa0, 24, 1),
 186         MTK_PIN_DRV_GRP(185, DRV_BASE1+0xa0, 28, 1),
 187
 188         MTK_PIN_DRV_GRP(186, DRV_BASE1+0xb0, 0, 2),
 189         MTK_PIN_DRV_GRP(187, DRV_BASE1+0xb0, 0, 2),
 190         MTK_PIN_DRV_GRP(188, DRV_BASE1+0xb0, 0, 2),
 191         MTK_PIN_DRV_GRP(189, DRV_BASE1+0xb0, 0, 2),
 192         MTK_PIN_DRV_GRP(190, DRV_BASE1+0xb0, 4, 1),
 193         MTK_PIN_DRV_GRP(191, DRV_BASE1+0xb0, 8, 1),
 194         MTK_PIN_DRV_GRP(192, DRV_BASE1+0xb0, 12, 1),
 195
 196         MTK_PIN_DRV_GRP(197, DRV_BASE1+0xb0, 16, 0),
 197         MTK_PIN_DRV_GRP(198, DRV_BASE1+0xb0, 16, 0),
 198         MTK_PIN_DRV_GRP(199, DRV_BASE1+0xb0, 20, 0),
 199         MTK_PIN_DRV_GRP(200, DRV_BASE1+0xb0, 24, 0),
 200         MTK_PIN_DRV_GRP(201, DRV_BASE1+0xb0, 16, 0),
 201         MTK_PIN_DRV_GRP(202, DRV_BASE1+0xb0, 16, 0)
 202 };
 203
 204 static const struct mtk_spec_pull_set spec_pupd[] = {
 205         SPEC_PULL(0, PUPD_BASE1, 0, R0_BASE1, 9, R1_BASE1, 0),
 206         SPEC_PULL(1, PUPD_BASE1, 1, R0_BASE1, 8, R1_BASE1, 1),
 207         SPEC_PULL(2, PUPD_BASE1, 2, R0_BASE1, 7, R1_BASE1, 2),
 208         SPEC_PULL(3, PUPD_BASE1, 3, R0_BASE1, 6, R1_BASE1, 3),
 209         SPEC_PULL(4, PUPD_BASE1, 4, R0_BASE1, 1, R1_BASE1, 4),
 210         SPEC_PULL(5, PUPD_BASE1, 5, R0_BASE1, 0, R1_BASE1, 5),
 211         SPEC_PULL(6, PUPD_BASE1, 6, R0_BASE1, 5, R1_BASE1, 6),
 212         SPEC_PULL(7, PUPD_BASE1, 7, R0_BASE1, 4, R1_BASE1, 7),
 213         SPEC_PULL(8, PUPD_BASE1, 8, R0_BASE1, 3, R1_BASE1, 8),
 214         SPEC_PULL(9, PUPD_BASE1, 9, R0_BASE1, 2, R1_BASE1, 9),
 215         SPEC_PULL(89, PUPD_BASE2, 9, R0_BASE1, 18, R1_BASE2, 9),
 216         SPEC_PULL(90, PUPD_BASE2, 10, R0_BASE1, 19, R1_BASE2, 10),
 217         SPEC_PULL(91, PUPD_BASE2, 11, R0_BASE1, 23, R1_BASE2, 11),
 218         SPEC_PULL(92, PUPD_BASE2, 12, R0_BASE1, 24, R1_BASE2, 12),
 219         SPEC_PULL(93, PUPD_BASE2, 13, R0_BASE1, 25, R1_BASE2, 13),
 220         SPEC_PULL(94, PUPD_BASE2, 14, R0_BASE1, 22, R1_BASE2, 14),
 221         SPEC_PULL(95, PUPD_BASE2, 15, R0_BASE1, 20, R1_BASE2, 15),
 222         SPEC_PULL(96, PUPD_BASE2+0x10, 0, R0_BASE1, 16, R1_BASE2+0x10, 0),
 223         SPEC_PULL(97, PUPD_BASE2+0x10, 1, R0_BASE1, 21, R1_BASE2+0x10, 1),
 224         SPEC_PULL(98, PUPD_BASE2+0x10, 2, R0_BASE1, 17, R1_BASE2+0x10, 2),
 225         SPEC_PULL(197, PUPD_BASE1+0xc0, 5, R0_BASE1, 13, R1_BASE2+0xc0, 5),
 226         SPEC_PULL(198, PUPD_BASE2+0xc0, 6, R0_BASE1, 14, R1_BASE2+0xc0, 6),
 227         SPEC_PULL(199, PUPD_BASE2+0xc0, 7, R0_BASE1, 11, R1_BASE2+0xc0, 7),
 228         SPEC_PULL(200, PUPD_BASE2+0xc0, 8, R0_BASE1, 10, R1_BASE2+0xc0, 8),
 229         SPEC_PULL(201, PUPD_BASE2+0xc0, 9, R0_BASE1, 13, R1_BASE2+0xc0, 9),
 230         SPEC_PULL(202, PUPD_BASE2+0xc0, 10, R0_BASE1, 12, R1_BASE2+0xc0, 10)
 231 };
 232
 233 static int spec_pull_set(struct regmap *regmap, unsigned int pin,
 234                 unsigned char align, bool isup, unsigned int r1r0)
 235 {
 236         unsigned int i;
 237         unsigned int reg_pupd, reg_set_r0, reg_set_r1;
 238         unsigned int reg_rst_r0, reg_rst_r1;
 239         bool find = false;
 240
 241         for (i = 0; i < ARRAY_SIZE(spec_pupd); i++) {
 242                 if (pin == spec_pupd[i].pin) {
 243                         find = true;
 244                         break;
 245                 }
 246         }
 247
 248         if (!find)
 249                 return -EINVAL;
 250
 251         if (isup)
 252                 reg_pupd = spec_pupd[i].pupd_offset + align;
 253         else
 254                 reg_pupd = spec_pupd[i].pupd_offset + (align << 1);
 255
 256         regmap_write(regmap, reg_pupd, spec_pupd[i].pupd_bit);
 257
 258         reg_set_r0 = spec_pupd[i].r0_offset + align;
 259         reg_rst_r0 = spec_pupd[i].r0_offset + (align << 1);
 260         reg_set_r1 = spec_pupd[i].r1_offset + align;
 261         reg_rst_r1 = spec_pupd[i].r1_offset + (align << 1);
 262
 263         switch (r1r0) {
 264         case MTK_PUPD_SET_R1R0_00:
 265                 regmap_write(regmap, reg_rst_r0, spec_pupd[i].r0_bit);
 266                 regmap_write(regmap, reg_rst_r1, spec_pupd[i].r1_bit);
 267                 break;
 268         case MTK_PUPD_SET_R1R0_01:
 269                 regmap_write(regmap, reg_set_r0, spec_pupd[i].r0_bit);
 270                 regmap_write(regmap, reg_rst_r1, spec_pupd[i].r1_bit);
 271                 break;
 272         case MTK_PUPD_SET_R1R0_10:
 273                 regmap_write(regmap, reg_rst_r0, spec_pupd[i].r0_bit);
 274                 regmap_write(regmap, reg_set_r1, spec_pupd[i].r1_bit);
 275                 break;
 276         case MTK_PUPD_SET_R1R0_11:
 277                 regmap_write(regmap, reg_set_r0, spec_pupd[i].r0_bit);
 278                 regmap_write(regmap, reg_set_r1, spec_pupd[i].r1_bit);
 279                 break;
 280         default:
 281                 return -EINVAL;
 282         }
 283
 284         return 0;
 285 }
 286
 287 static const struct mtk_pinctrl_devdata mt8135_pinctrl_data = {
 288         .pins = mtk_pins_mt8135,
 289         .npins = ARRAY_SIZE(mtk_pins_mt8135),
 290         .grp_desc = mt8135_drv_grp,
 291         .n_grp_cls = ARRAY_SIZE(mt8135_drv_grp),
 292         .pin_drv_grp = mt8135_pin_drv,
 293         .n_pin_drv_grps = ARRAY_SIZE(mt8135_pin_drv),
 294         .spec_pull_set = spec_pull_set,
 295         .dir_offset = 0x0000,
 296         .ies_offset = 0x0100,
 297         .pullen_offset = 0x0200,
 298         .smt_offset = 0x0300,
 299         .pullsel_offset = 0x0400,
 300         .dout_offset = 0x0800,
 301         .din_offset = 0x0A00,
 302         .pinmux_offset = 0x0C00,
 303         .type1_start = 34,
 304         .type1_end = 149,
 305         .port_shf = 4,
 306         .port_mask = 0xf,
 307         .port_align = 4,
 308         .eint_hw = {
 309                 .port_mask = 7,
 310                 .ports     = 6,
 311                 .ap_num    = 192,
 312                 .db_cnt    = 16,
 313         },
 314 };
 315
 316 static int mt8135_pinctrl_probe(struct platform_device *pdev)
 317 {
 318         return mtk_pctrl_init(pdev, &mt8135_pinctrl_data, NULL);
 319 }
 320
 321 static const struct of_device_id mt8135_pctrl_match[] = {
 322         {
 323                 .compatible = "mediatek,mt8135-pinctrl",
 324         },
 325         { }
 326 };
 327
 328 static struct platform_driver mtk_pinctrl_driver = {
 329         .probe = mt8135_pinctrl_probe,
 330         .driver = {
 331                 .name = "mediatek-mt8135-pinctrl",
 332                 .of_match_table = mt8135_pctrl_match,
 333         },
 334 };
 335
 336 static int __init mtk_pinctrl_init(void)
 337 {
 338         return platform_driver_register(&mtk_pinctrl_driver);
 339 }
 340 arch_initcall(mtk_pinctrl_init);