?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / pinctrl / mediatek / pinctrl-paris.c
blob923264d0e9ef2c595b93d559bc04fb209e736045
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * MediaTek Pinctrl Paris Driver, which implement the vendor per-pin
4 * bindings for MediaTek SoC.
5 *
6 * Copyright (C) 2018 MediaTek Inc.
7 * Author: Sean Wang <sean.wang@mediatek.com>
8 * Zhiyong Tao <zhiyong.tao@mediatek.com>
9 * Hongzhou.Yang <hongzhou.yang@mediatek.com>
10 */
11
12 #include <linux/gpio/driver.h>
13 #include <dt-bindings/pinctrl/mt65xx.h>
14 #include "pinctrl-paris.h"
15
16 #define PINCTRL_PINCTRL_DEV KBUILD_MODNAME
17
18 /* Custom pinconf parameters */
19 #define MTK_PIN_CONFIG_TDSEL (PIN_CONFIG_END + 1)
20 #define MTK_PIN_CONFIG_RDSEL (PIN_CONFIG_END + 2)
21 #define MTK_PIN_CONFIG_PU_ADV (PIN_CONFIG_END + 3)
22 #define MTK_PIN_CONFIG_PD_ADV (PIN_CONFIG_END + 4)
23 #define MTK_PIN_CONFIG_DRV_ADV (PIN_CONFIG_END + 5)
24
25 static const struct pinconf_generic_params mtk_custom_bindings[] = {
26 {"mediatek,tdsel", MTK_PIN_CONFIG_TDSEL, 0},
27 {"mediatek,rdsel", MTK_PIN_CONFIG_RDSEL, 0},
28 {"mediatek,pull-up-adv", MTK_PIN_CONFIG_PU_ADV, 1},
29 {"mediatek,pull-down-adv", MTK_PIN_CONFIG_PD_ADV, 1},
30 {"mediatek,drive-strength-adv", MTK_PIN_CONFIG_DRV_ADV, 2},
31 };
32
33 #ifdef CONFIG_DEBUG_FS
34 static const struct pin_config_item mtk_conf_items[] = {
35 PCONFDUMP(MTK_PIN_CONFIG_TDSEL, "tdsel", NULL, true),
36 PCONFDUMP(MTK_PIN_CONFIG_RDSEL, "rdsel", NULL, true),
37 PCONFDUMP(MTK_PIN_CONFIG_PU_ADV, "pu-adv", NULL, true),
38 PCONFDUMP(MTK_PIN_CONFIG_PD_ADV, "pd-adv", NULL, true),
39 PCONFDUMP(MTK_PIN_CONFIG_DRV_ADV, "drive-strength-adv", NULL, true),
40 };
41 #endif
42
43 static const char * const mtk_gpio_functions[] = {
44 "func0", "func1", "func2", "func3",
45 "func4", "func5", "func6", "func7",
46 "func8", "func9", "func10", "func11",
47 "func12", "func13", "func14", "func15",
48 };
49
50 static int mtk_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev,
51 struct pinctrl_gpio_range *range,
52 unsigned int pin)
53 {
54 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
55 const struct mtk_pin_desc *desc;
56
57 desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
58
59 return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE,
60 hw->soc->gpio_m);
61 }
62
63 static int mtk_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
64 struct pinctrl_gpio_range *range,
65 unsigned int pin, bool input)
66 {
67 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
68 const struct mtk_pin_desc *desc;
69
70 desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
71
72 /* hardware would take 0 as input direction */
73 return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, !input);
74 }
75
76 static int mtk_pinconf_get(struct pinctrl_dev *pctldev,
77 unsigned int pin, unsigned long *config)
78 {
79 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
80 u32 param = pinconf_to_config_param(*config);
81 int val, val2, err, reg, ret = 1;
82 const struct mtk_pin_desc *desc;
83
84 desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
85
86 switch (param) {
87 case PIN_CONFIG_BIAS_DISABLE:
88 if (hw->soc->bias_disable_get) {
89 err = hw->soc->bias_disable_get(hw, desc, &ret);
90 if (err)
91 return err;
92 } else {
93 return -ENOTSUPP;
94 }
95 break;
96 case PIN_CONFIG_BIAS_PULL_UP:
97 if (hw->soc->bias_get) {
98 err = hw->soc->bias_get(hw, desc, 1, &ret);
99 if (err)
100 return err;
101 } else {
102 return -ENOTSUPP;
103 }
104 break;
105 case PIN_CONFIG_BIAS_PULL_DOWN:
106 if (hw->soc->bias_get) {
107 err = hw->soc->bias_get(hw, desc, 0, &ret);
108 if (err)
109 return err;
110 } else {
111 return -ENOTSUPP;
112 }
113 break;
114 case PIN_CONFIG_SLEW_RATE:
115 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_SR, &val);
116 if (err)
117 return err;
118
119 if (!val)
120 return -EINVAL;
121
122 break;
123 case PIN_CONFIG_INPUT_ENABLE:
124 case PIN_CONFIG_OUTPUT_ENABLE:
125 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &val);
126 if (err)
127 return err;
128
129 /* HW takes input mode as zero; output mode as non-zero */
130 if ((val && param == PIN_CONFIG_INPUT_ENABLE) ||
131 (!val && param == PIN_CONFIG_OUTPUT_ENABLE))
132 return -EINVAL;
133
134 break;
135 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
136 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &val);
137 if (err)
138 return err;
139
140 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_SMT, &val2);
141 if (err)
142 return err;
143
144 if (val || !val2)
145 return -EINVAL;
146
147 break;
148 case PIN_CONFIG_DRIVE_STRENGTH:
149 if (hw->soc->drive_get) {
150 err = hw->soc->drive_get(hw, desc, &ret);
151 if (err)
152 return err;
153 } else {
154 err = -ENOTSUPP;
155 }
156 break;
157 case MTK_PIN_CONFIG_TDSEL:
158 case MTK_PIN_CONFIG_RDSEL:
159 reg = (param == MTK_PIN_CONFIG_TDSEL) ?
160 PINCTRL_PIN_REG_TDSEL : PINCTRL_PIN_REG_RDSEL;
161
162 err = mtk_hw_get_value(hw, desc, reg, &val);
163 if (err)
164 return err;
165
166 ret = val;
167
168 break;
169 case MTK_PIN_CONFIG_PU_ADV:
170 case MTK_PIN_CONFIG_PD_ADV:
171 if (hw->soc->adv_pull_get) {
172 bool pullup;
173
174 pullup = param == MTK_PIN_CONFIG_PU_ADV;
175 err = hw->soc->adv_pull_get(hw, desc, pullup, &ret);
176 if (err)
177 return err;
178 } else {
179 return -ENOTSUPP;
180 }
181 break;
182 case MTK_PIN_CONFIG_DRV_ADV:
183 if (hw->soc->adv_drive_get) {
184 err = hw->soc->adv_drive_get(hw, desc, &ret);
185 if (err)
186 return err;
187 } else {
188 return -ENOTSUPP;
189 }
190 break;
191 default:
192 return -ENOTSUPP;
193 }
194
195 *config = pinconf_to_config_packed(param, ret);
196
197 return 0;
198 }
199
200 static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
201 enum pin_config_param param,
202 enum pin_config_param arg)
203 {
204 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
205 const struct mtk_pin_desc *desc;
206 int err = 0;
207 u32 reg;
208
209 desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
210
211 switch ((u32)param) {
212 case PIN_CONFIG_BIAS_DISABLE:
213 if (hw->soc->bias_disable_set) {
214 err = hw->soc->bias_disable_set(hw, desc);
215 if (err)
216 return err;
217 } else {
218 return -ENOTSUPP;
219 }
220 break;
221 case PIN_CONFIG_BIAS_PULL_UP:
222 if (hw->soc->bias_set) {
223 err = hw->soc->bias_set(hw, desc, 1);
224 if (err)
225 return err;
226 } else {
227 return -ENOTSUPP;
228 }
229 break;
230 case PIN_CONFIG_BIAS_PULL_DOWN:
231 if (hw->soc->bias_set) {
232 err = hw->soc->bias_set(hw, desc, 0);
233 if (err)
234 return err;
235 } else {
236 return -ENOTSUPP;
237 }
238 break;
239 case PIN_CONFIG_OUTPUT_ENABLE:
240 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT,
241 MTK_DISABLE);
242 if (err)
243 goto err;
244
245 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
246 MTK_OUTPUT);
247 if (err)
248 goto err;
249 break;
250 case PIN_CONFIG_INPUT_ENABLE:
251 if (hw->soc->ies_present) {
252 mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_IES,
253 MTK_ENABLE);
254 }
255
256 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
257 MTK_INPUT);
258 if (err)
259 goto err;
260 break;
261 case PIN_CONFIG_SLEW_RATE:
262 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SR,
263 arg);
264 if (err)
265 goto err;
266
267 break;
268 case PIN_CONFIG_OUTPUT:
269 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
270 MTK_OUTPUT);
271 if (err)
272 goto err;
273
274 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO,
275 arg);
276 if (err)
277 goto err;
278 break;
279 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
280 /* arg = 1: Input mode & SMT enable ;
281 * arg = 0: Output mode & SMT disable
282 */
283 arg = arg ? 2 : 1;
284 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
285 arg & 1);
286 if (err)
287 goto err;
288
289 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT,
290 !!(arg & 2));
291 if (err)
292 goto err;
293 break;
294 case PIN_CONFIG_DRIVE_STRENGTH:
295 if (hw->soc->drive_set) {
296 err = hw->soc->drive_set(hw, desc, arg);
297 if (err)
298 return err;
299 } else {
300 return -ENOTSUPP;
301 }
302 break;
303 case MTK_PIN_CONFIG_TDSEL:
304 case MTK_PIN_CONFIG_RDSEL:
305 reg = (param == MTK_PIN_CONFIG_TDSEL) ?
306 PINCTRL_PIN_REG_TDSEL : PINCTRL_PIN_REG_RDSEL;
307
308 err = mtk_hw_set_value(hw, desc, reg, arg);
309 if (err)
310 goto err;
311 break;
312 case MTK_PIN_CONFIG_PU_ADV:
313 case MTK_PIN_CONFIG_PD_ADV:
314 if (hw->soc->adv_pull_set) {
315 bool pullup;
316
317 pullup = param == MTK_PIN_CONFIG_PU_ADV;
318 err = hw->soc->adv_pull_set(hw, desc, pullup,
319 arg);
320 if (err)
321 return err;
322 } else {
323 return -ENOTSUPP;
324 }
325 break;
326 case MTK_PIN_CONFIG_DRV_ADV:
327 if (hw->soc->adv_drive_set) {
328 err = hw->soc->adv_drive_set(hw, desc, arg);
329 if (err)
330 return err;
331 } else {
332 return -ENOTSUPP;
333 }
334 break;
335 default:
336 err = -ENOTSUPP;
337 }
338
339 err:
340 return err;
341 }
342
343 static struct mtk_pinctrl_group *
344 mtk_pctrl_find_group_by_pin(struct mtk_pinctrl *hw, u32 pin)
345 {
346 int i;
347
348 for (i = 0; i < hw->soc->ngrps; i++) {
349 struct mtk_pinctrl_group *grp = hw->groups + i;
350
351 if (grp->pin == pin)
352 return grp;
353 }
354
355 return NULL;
356 }
357
358 static const struct mtk_func_desc *
359 mtk_pctrl_find_function_by_pin(struct mtk_pinctrl *hw, u32 pin_num, u32 fnum)
360 {
361 const struct mtk_pin_desc *pin = hw->soc->pins + pin_num;
362 const struct mtk_func_desc *func = pin->funcs;
363
364 while (func && func->name) {
365 if (func->muxval == fnum)
366 return func;
367 func++;
368 }
369
370 return NULL;
371 }
372
373 static bool mtk_pctrl_is_function_valid(struct mtk_pinctrl *hw, u32 pin_num,
374 u32 fnum)
375 {
376 int i;
377
378 for (i = 0; i < hw->soc->npins; i++) {
379 const struct mtk_pin_desc *pin = hw->soc->pins + i;
380
381 if (pin->number == pin_num) {
382 const struct mtk_func_desc *func = pin->funcs;
383
384 while (func && func->name) {
385 if (func->muxval == fnum)
386 return true;
387 func++;
388 }
389
390 break;
391 }
392 }
393
394 return false;
395 }
396
397 static int mtk_pctrl_dt_node_to_map_func(struct mtk_pinctrl *pctl,
398 u32 pin, u32 fnum,
399 struct mtk_pinctrl_group *grp,
400 struct pinctrl_map **map,
401 unsigned *reserved_maps,
402 unsigned *num_maps)
403 {
404 bool ret;
405
406 if (*num_maps == *reserved_maps)
407 return -ENOSPC;
408
409 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
410 (*map)[*num_maps].data.mux.group = grp->name;
411
412 ret = mtk_pctrl_is_function_valid(pctl, pin, fnum);
413 if (!ret) {
414 dev_err(pctl->dev, "invalid function %d on pin %d .\n",
415 fnum, pin);
416 return -EINVAL;
417 }
418
419 (*map)[*num_maps].data.mux.function = mtk_gpio_functions[fnum];
420 (*num_maps)++;
421
422 return 0;
423 }
424
425 static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
426 struct device_node *node,
427 struct pinctrl_map **map,
428 unsigned *reserved_maps,
429 unsigned *num_maps)
430 {
431 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
432 int num_pins, num_funcs, maps_per_pin, i, err;
433 struct mtk_pinctrl_group *grp;
434 unsigned int num_configs;
435 bool has_config = false;
436 unsigned long *configs;
437 u32 pinfunc, pin, func;
438 struct property *pins;
439 unsigned reserve = 0;
440
441 pins = of_find_property(node, "pinmux", NULL);
442 if (!pins) {
443 dev_err(hw->dev, "missing pins property in node %pOFn .\n",
444 node);
445 return -EINVAL;
446 }
447
448 err = pinconf_generic_parse_dt_config(node, pctldev, &configs,
449 &num_configs);
450 if (err)
451 return err;
452
453 if (num_configs)
454 has_config = true;
455
456 num_pins = pins->length / sizeof(u32);
457 num_funcs = num_pins;
458 maps_per_pin = 0;
459 if (num_funcs)
460 maps_per_pin++;
461 if (has_config && num_pins >= 1)
462 maps_per_pin++;
463
464 if (!num_pins || !maps_per_pin) {
465 err = -EINVAL;
466 goto exit;
467 }
468
469 reserve = num_pins * maps_per_pin;
470
471 err = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, num_maps,
472 reserve);
473 if (err < 0)
474 goto exit;
475
476 for (i = 0; i < num_pins; i++) {
477 err = of_property_read_u32_index(node, "pinmux", i, &pinfunc);
478 if (err)
479 goto exit;
480
481 pin = MTK_GET_PIN_NO(pinfunc);
482 func = MTK_GET_PIN_FUNC(pinfunc);
483
484 if (pin >= hw->soc->npins ||
485 func >= ARRAY_SIZE(mtk_gpio_functions)) {
486 dev_err(hw->dev, "invalid pins value.\n");
487 err = -EINVAL;
488 goto exit;
489 }
490
491 grp = mtk_pctrl_find_group_by_pin(hw, pin);
492 if (!grp) {
493 dev_err(hw->dev, "unable to match pin %d to group\n",
494 pin);
495 err = -EINVAL;
496 goto exit;
497 }
498
499 err = mtk_pctrl_dt_node_to_map_func(hw, pin, func, grp, map,
500 reserved_maps, num_maps);
501 if (err < 0)
502 goto exit;
503
504 if (has_config) {
505 err = pinctrl_utils_add_map_configs(pctldev, map,
506 reserved_maps,
507 num_maps,
508 grp->name,
509 configs,
510 num_configs,
511 PIN_MAP_TYPE_CONFIGS_GROUP);
512 if (err < 0)
513 goto exit;
514 }
515 }
516
517 err = 0;
518
519 exit:
520 kfree(configs);
521 return err;
522 }
523
524 static int mtk_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
525 struct device_node *np_config,
526 struct pinctrl_map **map,
527 unsigned *num_maps)
528 {
529 struct device_node *np;
530 unsigned reserved_maps;
531 int ret;
532
533 *map = NULL;
534 *num_maps = 0;
535 reserved_maps = 0;
536
537 for_each_child_of_node(np_config, np) {
538 ret = mtk_pctrl_dt_subnode_to_map(pctldev, np, map,
539 &reserved_maps,
540 num_maps);
541 if (ret < 0) {
542 pinctrl_utils_free_map(pctldev, *map, *num_maps);
543 of_node_put(np);
544 return ret;
545 }
546 }
547
548 return 0;
549 }
550
551 static int mtk_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
552 {
553 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
554
555 return hw->soc->ngrps;
556 }
557
558 static const char *mtk_pctrl_get_group_name(struct pinctrl_dev *pctldev,
559 unsigned group)
560 {
561 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
562
563 return hw->groups[group].name;
564 }
565
566 static int mtk_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
567 unsigned group, const unsigned **pins,
568 unsigned *num_pins)
569 {
570 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
571
572 *pins = (unsigned *)&hw->groups[group].pin;
573 *num_pins = 1;
574
575 return 0;
576 }
577
578 static const struct pinctrl_ops mtk_pctlops = {
579 .dt_node_to_map = mtk_pctrl_dt_node_to_map,
580 .dt_free_map = pinctrl_utils_free_map,
581 .get_groups_count = mtk_pctrl_get_groups_count,
582 .get_group_name = mtk_pctrl_get_group_name,
583 .get_group_pins = mtk_pctrl_get_group_pins,
584 };
585
586 static int mtk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
587 {
588 return ARRAY_SIZE(mtk_gpio_functions);
589 }
590
591 static const char *mtk_pmx_get_func_name(struct pinctrl_dev *pctldev,
592 unsigned selector)
593 {
594 return mtk_gpio_functions[selector];
595 }
596
597 static int mtk_pmx_get_func_groups(struct pinctrl_dev *pctldev,
598 unsigned function,
599 const char * const **groups,
600 unsigned * const num_groups)
601 {
602 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
603
604 *groups = hw->grp_names;
605 *num_groups = hw->soc->ngrps;
606
607 return 0;
608 }
609
610 static int mtk_pmx_set_mux(struct pinctrl_dev *pctldev,
611 unsigned function,
612 unsigned group)
613 {
614 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
615 struct mtk_pinctrl_group *grp = hw->groups + group;
616 const struct mtk_func_desc *desc_func;
617 const struct mtk_pin_desc *desc;
618 bool ret;
619
620 ret = mtk_pctrl_is_function_valid(hw, grp->pin, function);
621 if (!ret) {
622 dev_err(hw->dev, "invalid function %d on group %d .\n",
623 function, group);
624 return -EINVAL;
625 }
626
627 desc_func = mtk_pctrl_find_function_by_pin(hw, grp->pin, function);
628 if (!desc_func)
629 return -EINVAL;
630
631 desc = (const struct mtk_pin_desc *)&hw->soc->pins[grp->pin];
632 mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE, desc_func->muxval);
633
634 return 0;
635 }
636
637 static const struct pinmux_ops mtk_pmxops = {
638 .get_functions_count = mtk_pmx_get_funcs_cnt,
639 .get_function_name = mtk_pmx_get_func_name,
640 .get_function_groups = mtk_pmx_get_func_groups,
641 .set_mux = mtk_pmx_set_mux,
642 .gpio_set_direction = mtk_pinmux_gpio_set_direction,
643 .gpio_request_enable = mtk_pinmux_gpio_request_enable,
644 };
645
646 static int mtk_pconf_group_get(struct pinctrl_dev *pctldev, unsigned group,
647 unsigned long *config)
648 {
649 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
650
651 *config = hw->groups[group].config;
652
653 return 0;
654 }
655
656 static int mtk_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
657 unsigned long *configs, unsigned num_configs)
658 {
659 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
660 struct mtk_pinctrl_group *grp = &hw->groups[group];
661 int i, ret;
662
663 for (i = 0; i < num_configs; i++) {
664 ret = mtk_pinconf_set(pctldev, grp->pin,
665 pinconf_to_config_param(configs[i]),
666 pinconf_to_config_argument(configs[i]));
667 if (ret < 0)
668 return ret;
669
670 grp->config = configs[i];
671 }
672
673 return 0;
674 }
675
676 static const struct pinconf_ops mtk_confops = {
677 .pin_config_get = mtk_pinconf_get,
678 .pin_config_group_get = mtk_pconf_group_get,
679 .pin_config_group_set = mtk_pconf_group_set,
680 };
681
682 static struct pinctrl_desc mtk_desc = {
683 .name = PINCTRL_PINCTRL_DEV,
684 .pctlops = &mtk_pctlops,
685 .pmxops = &mtk_pmxops,
686 .confops = &mtk_confops,
687 .owner = THIS_MODULE,
688 };
689
690 static int mtk_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio)
691 {
692 struct mtk_pinctrl *hw = gpiochip_get_data(chip);
693 const struct mtk_pin_desc *desc;
694 int value, err;
695
696 desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
697
698 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &value);
699 if (err)
700 return err;
701
702 return !value;
703 }
704
705 static int mtk_gpio_get(struct gpio_chip *chip, unsigned int gpio)
706 {
707 struct mtk_pinctrl *hw = gpiochip_get_data(chip);
708 const struct mtk_pin_desc *desc;
709 int value, err;
710
711 desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
712
713 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DI, &value);
714 if (err)
715 return err;
716
717 return !!value;
718 }
719
720 static void mtk_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value)
721 {
722 struct mtk_pinctrl *hw = gpiochip_get_data(chip);
723 const struct mtk_pin_desc *desc;
724
725 desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
726
727 mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO, !!value);
728 }
729
730 static int mtk_gpio_direction_input(struct gpio_chip *chip, unsigned int gpio)
731 {
732 return pinctrl_gpio_direction_input(chip->base + gpio);
733 }
734
735 static int mtk_gpio_direction_output(struct gpio_chip *chip, unsigned int gpio,
736 int value)
737 {
738 mtk_gpio_set(chip, gpio, value);
739
740 return pinctrl_gpio_direction_output(chip->base + gpio);
741 }
742
743 static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
744 {
745 struct mtk_pinctrl *hw = gpiochip_get_data(chip);
746 const struct mtk_pin_desc *desc;
747
748 if (!hw->eint)
749 return -ENOTSUPP;
750
751 desc = (const struct mtk_pin_desc *)&hw->soc->pins[offset];
752
753 if (desc->eint.eint_n == EINT_NA)
754 return -ENOTSUPP;
755
756 return mtk_eint_find_irq(hw->eint, desc->eint.eint_n);
757 }
758
759 static int mtk_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
760 unsigned long config)
761 {
762 struct mtk_pinctrl *hw = gpiochip_get_data(chip);
763 const struct mtk_pin_desc *desc;
764 u32 debounce;
765
766 desc = (const struct mtk_pin_desc *)&hw->soc->pins[offset];
767
768 if (!hw->eint ||
769 pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE ||
770 desc->eint.eint_n == EINT_NA)
771 return -ENOTSUPP;
772
773 debounce = pinconf_to_config_argument(config);
774
775 return mtk_eint_set_debounce(hw->eint, desc->eint.eint_n, debounce);
776 }
777
778 static int mtk_build_gpiochip(struct mtk_pinctrl *hw, struct device_node *np)
779 {
780 struct gpio_chip *chip = &hw->chip;
781 int ret;
782
783 chip->label = PINCTRL_PINCTRL_DEV;
784 chip->parent = hw->dev;
785 chip->request = gpiochip_generic_request;
786 chip->free = gpiochip_generic_free;
787 chip->get_direction = mtk_gpio_get_direction;
788 chip->direction_input = mtk_gpio_direction_input;
789 chip->direction_output = mtk_gpio_direction_output;
790 chip->get = mtk_gpio_get;
791 chip->set = mtk_gpio_set;
792 chip->to_irq = mtk_gpio_to_irq,
793 chip->set_config = mtk_gpio_set_config,
794 chip->base = -1;
795 chip->ngpio = hw->soc->npins;
796 chip->of_node = np;
797 chip->of_gpio_n_cells = 2;
798
799 ret = gpiochip_add_data(chip, hw);
800 if (ret < 0)
801 return ret;
802
803 return 0;
804 }
805
806 static int mtk_pctrl_build_state(struct platform_device *pdev)
807 {
808 struct mtk_pinctrl *hw = platform_get_drvdata(pdev);
809 int i;
810
811 /* Allocate groups */
812 hw->groups = devm_kmalloc_array(&pdev->dev, hw->soc->ngrps,
813 sizeof(*hw->groups), GFP_KERNEL);
814 if (!hw->groups)
815 return -ENOMEM;
816
817 /* We assume that one pin is one group, use pin name as group name. */
818 hw->grp_names = devm_kmalloc_array(&pdev->dev, hw->soc->ngrps,
819 sizeof(*hw->grp_names), GFP_KERNEL);
820 if (!hw->grp_names)
821 return -ENOMEM;
822
823 for (i = 0; i < hw->soc->npins; i++) {
824 const struct mtk_pin_desc *pin = hw->soc->pins + i;
825 struct mtk_pinctrl_group *group = hw->groups + i;
826
827 group->name = pin->name;
828 group->pin = pin->number;
829
830 hw->grp_names[i] = pin->name;
831 }
832
833 return 0;
834 }
835
836 int mtk_paris_pinctrl_probe(struct platform_device *pdev,
837 const struct mtk_pin_soc *soc)
838 {
839 struct pinctrl_pin_desc *pins;
840 struct mtk_pinctrl *hw;
841 struct resource *res;
842 int err, i;
843
844 hw = devm_kzalloc(&pdev->dev, sizeof(*hw), GFP_KERNEL);
845 if (!hw)
846 return -ENOMEM;
847
848 platform_set_drvdata(pdev, hw);
849 hw->soc = soc;
850 hw->dev = &pdev->dev;
851
852 if (!hw->soc->nbase_names) {
853 dev_err(&pdev->dev,
854 "SoC should be assigned at least one register base\n");
855 return -EINVAL;
856 }
857
858 hw->base = devm_kmalloc_array(&pdev->dev, hw->soc->nbase_names,
859 sizeof(*hw->base), GFP_KERNEL);
860 if (!hw->base)
861 return -ENOMEM;
862
863 for (i = 0; i < hw->soc->nbase_names; i++) {
864 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
865 hw->soc->base_names[i]);
866 if (!res) {
867 dev_err(&pdev->dev, "missing IO resource\n");
868 return -ENXIO;
869 }
870
871 hw->base[i] = devm_ioremap_resource(&pdev->dev, res);
872 if (IS_ERR(hw->base[i]))
873 return PTR_ERR(hw->base[i]);
874 }
875
876 hw->nbase = hw->soc->nbase_names;
877
878 err = mtk_pctrl_build_state(pdev);
879 if (err) {
880 dev_err(&pdev->dev, "build state failed: %d\n", err);
881 return -EINVAL;
882 }
883
884 /* Copy from internal struct mtk_pin_desc to register to the core */
885 pins = devm_kmalloc_array(&pdev->dev, hw->soc->npins, sizeof(*pins),
886 GFP_KERNEL);
887 if (!pins)
888 return -ENOMEM;
889
890 for (i = 0; i < hw->soc->npins; i++) {
891 pins[i].number = hw->soc->pins[i].number;
892 pins[i].name = hw->soc->pins[i].name;
893 }
894
895 /* Setup pins descriptions per SoC types */
896 mtk_desc.pins = (const struct pinctrl_pin_desc *)pins;
897 mtk_desc.npins = hw->soc->npins;
898 mtk_desc.num_custom_params = ARRAY_SIZE(mtk_custom_bindings);
899 mtk_desc.custom_params = mtk_custom_bindings;
900 #ifdef CONFIG_DEBUG_FS
901 mtk_desc.custom_conf_items = mtk_conf_items;
902 #endif
903
904 err = devm_pinctrl_register_and_init(&pdev->dev, &mtk_desc, hw,
905 &hw->pctrl);
906 if (err)
907 return err;
908
909 err = pinctrl_enable(hw->pctrl);
910 if (err)
911 return err;
912
913 err = mtk_build_eint(hw, pdev);
914 if (err)
915 dev_warn(&pdev->dev,
916 "Failed to add EINT, but pinctrl still can work\n");
917
918 /* Build gpiochip should be after pinctrl_enable is done */
919 err = mtk_build_gpiochip(hw, pdev->dev.of_node);
920 if (err) {
921 dev_err(&pdev->dev, "Failed to add gpio_chip\n");
922 return err;
923 }
924
925 platform_set_drvdata(pdev, hw);
926
927 return 0;
928 }
929
930 static int mtk_paris_pinctrl_suspend(struct device *device)
931 {
932 struct mtk_pinctrl *pctl = dev_get_drvdata(device);
933
934 return mtk_eint_do_suspend(pctl->eint);
935 }
936
937 static int mtk_paris_pinctrl_resume(struct device *device)
938 {
939 struct mtk_pinctrl *pctl = dev_get_drvdata(device);
940
941 return mtk_eint_do_resume(pctl->eint);
942 }
943
944 const struct dev_pm_ops mtk_paris_pinctrl_pm_ops = {
945 .suspend_noirq = mtk_paris_pinctrl_suspend,
946 .resume_noirq = mtk_paris_pinctrl_resume,
947 };
Linux with added FPC-III support