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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / pinctrl / mvebu / pinctrl-armada-37xx.c
blob243fba2541750d508a029231f57822410c40b83d
1 /*
2 * Marvell 37xx SoC pinctrl driver
3 *
4 * Copyright (C) 2017 Marvell
5 *
6 * Gregory CLEMENT <gregory.clement@free-electrons.com>
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2 or later. This program is licensed "as is"
10 * without any warranty of any kind, whether express or implied.
11 */
12
13 #include <linux/gpio/driver.h>
14 #include <linux/mfd/syscon.h>
15 #include <linux/of.h>
16 #include <linux/of_address.h>
17 #include <linux/of_device.h>
18 #include <linux/pinctrl/pinconf-generic.h>
19 #include <linux/pinctrl/pinconf.h>
20 #include <linux/pinctrl/pinctrl.h>
21 #include <linux/pinctrl/pinmux.h>
22 #include <linux/platform_device.h>
23 #include <linux/regmap.h>
24 #include <linux/slab.h>
25
26 #include "../pinctrl-utils.h"
27
28 #define OUTPUT_EN 0x0
29 #define INPUT_VAL 0x10
30 #define OUTPUT_VAL 0x18
31 #define OUTPUT_CTL 0x20
32 #define SELECTION 0x30
33
34 #define IRQ_EN 0x0
35 #define IRQ_POL 0x08
36 #define IRQ_STATUS 0x10
37 #define IRQ_WKUP 0x18
38
39 #define NB_FUNCS 3
40 #define GPIO_PER_REG 32
41
42 /**
43 * struct armada_37xx_pin_group: represents group of pins of a pinmux function.
44 * The pins of a pinmux groups are composed of one or two groups of contiguous
45 * pins.
46 * @name: Name of the pin group, used to lookup the group.
47 * @start_pins: Index of the first pin of the main range of pins belonging to
48 * the group
49 * @npins: Number of pins included in the first range
50 * @reg_mask: Bit mask matching the group in the selection register
51 * @extra_pins: Index of the first pin of the optional second range of pins
52 * belonging to the group
53 * @npins: Number of pins included in the second optional range
54 * @funcs: A list of pinmux functions that can be selected for this group.
55 * @pins: List of the pins included in the group
56 */
57 struct armada_37xx_pin_group {
58 const char *name;
59 unsigned int start_pin;
60 unsigned int npins;
61 u32 reg_mask;
62 u32 val[NB_FUNCS];
63 unsigned int extra_pin;
64 unsigned int extra_npins;
65 const char *funcs[NB_FUNCS];
66 unsigned int *pins;
67 };
68
69 struct armada_37xx_pin_data {
70 u8 nr_pins;
71 char *name;
72 struct armada_37xx_pin_group *groups;
73 int ngroups;
74 };
75
76 struct armada_37xx_pmx_func {
77 const char *name;
78 const char **groups;
79 unsigned int ngroups;
80 };
81
82 struct armada_37xx_pm_state {
83 u32 out_en_l;
84 u32 out_en_h;
85 u32 out_val_l;
86 u32 out_val_h;
87 u32 irq_en_l;
88 u32 irq_en_h;
89 u32 irq_pol_l;
90 u32 irq_pol_h;
91 u32 selection;
92 };
93
94 struct armada_37xx_pinctrl {
95 struct regmap *regmap;
96 void __iomem *base;
97 const struct armada_37xx_pin_data *data;
98 struct device *dev;
99 struct gpio_chip gpio_chip;
100 struct irq_chip irq_chip;
101 spinlock_t irq_lock;
102 struct pinctrl_desc pctl;
103 struct pinctrl_dev *pctl_dev;
104 struct armada_37xx_pin_group *groups;
105 unsigned int ngroups;
106 struct armada_37xx_pmx_func *funcs;
107 unsigned int nfuncs;
108 struct armada_37xx_pm_state pm;
109 };
110
111 #define PIN_GRP(_name, _start, _nr, _mask, _func1, _func2) \
112 { \
113 .name = _name, \
114 .start_pin = _start, \
115 .npins = _nr, \
116 .reg_mask = _mask, \
117 .val = {0, _mask}, \
118 .funcs = {_func1, _func2} \
119 }
120
121 #define PIN_GRP_GPIO(_name, _start, _nr, _mask, _func1) \
122 { \
123 .name = _name, \
124 .start_pin = _start, \
125 .npins = _nr, \
126 .reg_mask = _mask, \
127 .val = {0, _mask}, \
128 .funcs = {_func1, "gpio"} \
129 }
130
131 #define PIN_GRP_GPIO_2(_name, _start, _nr, _mask, _val1, _val2, _func1) \
132 { \
133 .name = _name, \
134 .start_pin = _start, \
135 .npins = _nr, \
136 .reg_mask = _mask, \
137 .val = {_val1, _val2}, \
138 .funcs = {_func1, "gpio"} \
139 }
140
141 #define PIN_GRP_GPIO_3(_name, _start, _nr, _mask, _v1, _v2, _v3, _f1, _f2) \
142 { \
143 .name = _name, \
144 .start_pin = _start, \
145 .npins = _nr, \
146 .reg_mask = _mask, \
147 .val = {_v1, _v2, _v3}, \
148 .funcs = {_f1, _f2, "gpio"} \
149 }
150
151 #define PIN_GRP_EXTRA(_name, _start, _nr, _mask, _v1, _v2, _start2, _nr2, \
152 _f1, _f2) \
153 { \
154 .name = _name, \
155 .start_pin = _start, \
156 .npins = _nr, \
157 .reg_mask = _mask, \
158 .val = {_v1, _v2}, \
159 .extra_pin = _start2, \
160 .extra_npins = _nr2, \
161 .funcs = {_f1, _f2} \
162 }
163
164 static struct armada_37xx_pin_group armada_37xx_nb_groups[] = {
165 PIN_GRP_GPIO("jtag", 20, 5, BIT(0), "jtag"),
166 PIN_GRP_GPIO("sdio0", 8, 3, BIT(1), "sdio"),
167 PIN_GRP_GPIO("emmc_nb", 27, 9, BIT(2), "emmc"),
168 PIN_GRP_GPIO("pwm0", 11, 1, BIT(3), "pwm"),
169 PIN_GRP_GPIO("pwm1", 12, 1, BIT(4), "pwm"),
170 PIN_GRP_GPIO("pwm2", 13, 1, BIT(5), "pwm"),
171 PIN_GRP_GPIO("pwm3", 14, 1, BIT(6), "pwm"),
172 PIN_GRP_GPIO("pmic1", 7, 1, BIT(7), "pmic"),
173 PIN_GRP_GPIO("pmic0", 6, 1, BIT(8), "pmic"),
174 PIN_GRP_GPIO("i2c2", 2, 2, BIT(9), "i2c"),
175 PIN_GRP_GPIO("i2c1", 0, 2, BIT(10), "i2c"),
176 PIN_GRP_GPIO("spi_cs1", 17, 1, BIT(12), "spi"),
177 PIN_GRP_GPIO_2("spi_cs2", 18, 1, BIT(13) | BIT(19), 0, BIT(13), "spi"),
178 PIN_GRP_GPIO_2("spi_cs3", 19, 1, BIT(14) | BIT(19), 0, BIT(14), "spi"),
179 PIN_GRP_GPIO("onewire", 4, 1, BIT(16), "onewire"),
180 PIN_GRP_GPIO("uart1", 25, 2, BIT(17), "uart"),
181 PIN_GRP_GPIO("spi_quad", 15, 2, BIT(18), "spi"),
182 PIN_GRP_EXTRA("uart2", 9, 2, BIT(1) | BIT(13) | BIT(14) | BIT(19),
183 BIT(1) | BIT(13) | BIT(14), BIT(1) | BIT(19),
184 18, 2, "gpio", "uart"),
185 PIN_GRP_GPIO_2("led0_od", 11, 1, BIT(20), BIT(20), 0, "led"),
186 PIN_GRP_GPIO_2("led1_od", 12, 1, BIT(21), BIT(21), 0, "led"),
187 PIN_GRP_GPIO_2("led2_od", 13, 1, BIT(22), BIT(22), 0, "led"),
188 PIN_GRP_GPIO_2("led3_od", 14, 1, BIT(23), BIT(23), 0, "led"),
189
190 };
191
192 static struct armada_37xx_pin_group armada_37xx_sb_groups[] = {
193 PIN_GRP_GPIO("usb32_drvvbus0", 0, 1, BIT(0), "drvbus"),
194 PIN_GRP_GPIO("usb2_drvvbus1", 1, 1, BIT(1), "drvbus"),
195 PIN_GRP_GPIO("sdio_sb", 24, 6, BIT(2), "sdio"),
196 PIN_GRP_GPIO("rgmii", 6, 12, BIT(3), "mii"),
197 PIN_GRP_GPIO("smi", 18, 2, BIT(4), "smi"),
198 PIN_GRP_GPIO("pcie1", 3, 1, BIT(5), "pcie"),
199 PIN_GRP_GPIO("pcie1_clkreq", 4, 1, BIT(9), "pcie"),
200 PIN_GRP_GPIO("pcie1_wakeup", 5, 1, BIT(10), "pcie"),
201 PIN_GRP_GPIO("ptp", 20, 3, BIT(11) | BIT(12) | BIT(13), "ptp"),
202 PIN_GRP("ptp_clk", 21, 1, BIT(6), "ptp", "mii"),
203 PIN_GRP("ptp_trig", 22, 1, BIT(7), "ptp", "mii"),
204 PIN_GRP_GPIO_3("mii_col", 23, 1, BIT(8) | BIT(14), 0, BIT(8), BIT(14),
205 "mii", "mii_err"),
206 };
207
208 static const struct armada_37xx_pin_data armada_37xx_pin_nb = {
209 .nr_pins = 36,
210 .name = "GPIO1",
211 .groups = armada_37xx_nb_groups,
212 .ngroups = ARRAY_SIZE(armada_37xx_nb_groups),
213 };
214
215 static const struct armada_37xx_pin_data armada_37xx_pin_sb = {
216 .nr_pins = 30,
217 .name = "GPIO2",
218 .groups = armada_37xx_sb_groups,
219 .ngroups = ARRAY_SIZE(armada_37xx_sb_groups),
220 };
221
222 static inline void armada_37xx_update_reg(unsigned int *reg,
223 unsigned int *offset)
224 {
225 /* We never have more than 2 registers */
226 if (*offset >= GPIO_PER_REG) {
227 *offset -= GPIO_PER_REG;
228 *reg += sizeof(u32);
229 }
230 }
231
232 static struct armada_37xx_pin_group *armada_37xx_find_next_grp_by_pin(
233 struct armada_37xx_pinctrl *info, int pin, int *grp)
234 {
235 while (*grp < info->ngroups) {
236 struct armada_37xx_pin_group *group = &info->groups[*grp];
237 int j;
238
239 *grp = *grp + 1;
240 for (j = 0; j < (group->npins + group->extra_npins); j++)
241 if (group->pins[j] == pin)
242 return group;
243 }
244 return NULL;
245 }
246
247 static int armada_37xx_pin_config_group_get(struct pinctrl_dev *pctldev,
248 unsigned int selector, unsigned long *config)
249 {
250 return -ENOTSUPP;
251 }
252
253 static int armada_37xx_pin_config_group_set(struct pinctrl_dev *pctldev,
254 unsigned int selector, unsigned long *configs,
255 unsigned int num_configs)
256 {
257 return -ENOTSUPP;
258 }
259
260 static const struct pinconf_ops armada_37xx_pinconf_ops = {
261 .is_generic = true,
262 .pin_config_group_get = armada_37xx_pin_config_group_get,
263 .pin_config_group_set = armada_37xx_pin_config_group_set,
264 };
265
266 static int armada_37xx_get_groups_count(struct pinctrl_dev *pctldev)
267 {
268 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
269
270 return info->ngroups;
271 }
272
273 static const char *armada_37xx_get_group_name(struct pinctrl_dev *pctldev,
274 unsigned int group)
275 {
276 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
277
278 return info->groups[group].name;
279 }
280
281 static int armada_37xx_get_group_pins(struct pinctrl_dev *pctldev,
282 unsigned int selector,
283 const unsigned int **pins,
284 unsigned int *npins)
285 {
286 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
287
288 if (selector >= info->ngroups)
289 return -EINVAL;
290
291 *pins = info->groups[selector].pins;
292 *npins = info->groups[selector].npins +
293 info->groups[selector].extra_npins;
294
295 return 0;
296 }
297
298 static const struct pinctrl_ops armada_37xx_pctrl_ops = {
299 .get_groups_count = armada_37xx_get_groups_count,
300 .get_group_name = armada_37xx_get_group_name,
301 .get_group_pins = armada_37xx_get_group_pins,
302 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
303 .dt_free_map = pinctrl_utils_free_map,
304 };
305
306 /*
307 * Pinmux_ops handling
308 */
309
310 static int armada_37xx_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
311 {
312 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
313
314 return info->nfuncs;
315 }
316
317 static const char *armada_37xx_pmx_get_func_name(struct pinctrl_dev *pctldev,
318 unsigned int selector)
319 {
320 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
321
322 return info->funcs[selector].name;
323 }
324
325 static int armada_37xx_pmx_get_groups(struct pinctrl_dev *pctldev,
326 unsigned int selector,
327 const char * const **groups,
328 unsigned int * const num_groups)
329 {
330 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
331
332 *groups = info->funcs[selector].groups;
333 *num_groups = info->funcs[selector].ngroups;
334
335 return 0;
336 }
337
338 static int armada_37xx_pmx_set_by_name(struct pinctrl_dev *pctldev,
339 const char *name,
340 struct armada_37xx_pin_group *grp)
341 {
342 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
343 unsigned int reg = SELECTION;
344 unsigned int mask = grp->reg_mask;
345 int func, val;
346
347 dev_dbg(info->dev, "enable function %s group %s\n",
348 name, grp->name);
349
350 func = match_string(grp->funcs, NB_FUNCS, name);
351 if (func < 0)
352 return -ENOTSUPP;
353
354 val = grp->val[func];
355
356 regmap_update_bits(info->regmap, reg, mask, val);
357
358 return 0;
359 }
360
361 static int armada_37xx_pmx_set(struct pinctrl_dev *pctldev,
362 unsigned int selector,
363 unsigned int group)
364 {
365
366 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
367 struct armada_37xx_pin_group *grp = &info->groups[group];
368 const char *name = info->funcs[selector].name;
369
370 return armada_37xx_pmx_set_by_name(pctldev, name, grp);
371 }
372
373 static inline void armada_37xx_irq_update_reg(unsigned int *reg,
374 struct irq_data *d)
375 {
376 int offset = irqd_to_hwirq(d);
377
378 armada_37xx_update_reg(reg, &offset);
379 }
380
381 static int armada_37xx_gpio_direction_input(struct gpio_chip *chip,
382 unsigned int offset)
383 {
384 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
385 unsigned int reg = OUTPUT_EN;
386 unsigned int mask;
387
388 armada_37xx_update_reg(&reg, &offset);
389 mask = BIT(offset);
390
391 return regmap_update_bits(info->regmap, reg, mask, 0);
392 }
393
394 static int armada_37xx_gpio_get_direction(struct gpio_chip *chip,
395 unsigned int offset)
396 {
397 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
398 unsigned int reg = OUTPUT_EN;
399 unsigned int val, mask;
400
401 armada_37xx_update_reg(&reg, &offset);
402 mask = BIT(offset);
403 regmap_read(info->regmap, reg, &val);
404
405 return !(val & mask);
406 }
407
408 static int armada_37xx_gpio_direction_output(struct gpio_chip *chip,
409 unsigned int offset, int value)
410 {
411 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
412 unsigned int reg = OUTPUT_EN;
413 unsigned int mask, val, ret;
414
415 armada_37xx_update_reg(&reg, &offset);
416 mask = BIT(offset);
417
418 ret = regmap_update_bits(info->regmap, reg, mask, mask);
419
420 if (ret)
421 return ret;
422
423 reg = OUTPUT_VAL;
424 val = value ? mask : 0;
425 regmap_update_bits(info->regmap, reg, mask, val);
426
427 return 0;
428 }
429
430 static int armada_37xx_gpio_get(struct gpio_chip *chip, unsigned int offset)
431 {
432 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
433 unsigned int reg = INPUT_VAL;
434 unsigned int val, mask;
435
436 armada_37xx_update_reg(&reg, &offset);
437 mask = BIT(offset);
438
439 regmap_read(info->regmap, reg, &val);
440
441 return (val & mask) != 0;
442 }
443
444 static void armada_37xx_gpio_set(struct gpio_chip *chip, unsigned int offset,
445 int value)
446 {
447 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
448 unsigned int reg = OUTPUT_VAL;
449 unsigned int mask, val;
450
451 armada_37xx_update_reg(&reg, &offset);
452 mask = BIT(offset);
453 val = value ? mask : 0;
454
455 regmap_update_bits(info->regmap, reg, mask, val);
456 }
457
458 static int armada_37xx_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
459 struct pinctrl_gpio_range *range,
460 unsigned int offset, bool input)
461 {
462 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
463 struct gpio_chip *chip = range->gc;
464
465 dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
466 offset, range->name, offset, input ? "input" : "output");
467
468 if (input)
469 armada_37xx_gpio_direction_input(chip, offset);
470 else
471 armada_37xx_gpio_direction_output(chip, offset, 0);
472
473 return 0;
474 }
475
476 static int armada_37xx_gpio_request_enable(struct pinctrl_dev *pctldev,
477 struct pinctrl_gpio_range *range,
478 unsigned int offset)
479 {
480 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
481 struct armada_37xx_pin_group *group;
482 int grp = 0;
483
484 dev_dbg(info->dev, "requesting gpio %d\n", offset);
485
486 while ((group = armada_37xx_find_next_grp_by_pin(info, offset, &grp)))
487 armada_37xx_pmx_set_by_name(pctldev, "gpio", group);
488
489 return 0;
490 }
491
492 static const struct pinmux_ops armada_37xx_pmx_ops = {
493 .get_functions_count = armada_37xx_pmx_get_funcs_count,
494 .get_function_name = armada_37xx_pmx_get_func_name,
495 .get_function_groups = armada_37xx_pmx_get_groups,
496 .set_mux = armada_37xx_pmx_set,
497 .gpio_request_enable = armada_37xx_gpio_request_enable,
498 .gpio_set_direction = armada_37xx_pmx_gpio_set_direction,
499 };
500
501 static const struct gpio_chip armada_37xx_gpiolib_chip = {
502 .request = gpiochip_generic_request,
503 .free = gpiochip_generic_free,
504 .set = armada_37xx_gpio_set,
505 .get = armada_37xx_gpio_get,
506 .get_direction = armada_37xx_gpio_get_direction,
507 .direction_input = armada_37xx_gpio_direction_input,
508 .direction_output = armada_37xx_gpio_direction_output,
509 .owner = THIS_MODULE,
510 };
511
512 static void armada_37xx_irq_ack(struct irq_data *d)
513 {
514 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
515 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
516 u32 reg = IRQ_STATUS;
517 unsigned long flags;
518
519 armada_37xx_irq_update_reg(&reg, d);
520 spin_lock_irqsave(&info->irq_lock, flags);
521 writel(d->mask, info->base + reg);
522 spin_unlock_irqrestore(&info->irq_lock, flags);
523 }
524
525 static void armada_37xx_irq_mask(struct irq_data *d)
526 {
527 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
528 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
529 u32 val, reg = IRQ_EN;
530 unsigned long flags;
531
532 armada_37xx_irq_update_reg(&reg, d);
533 spin_lock_irqsave(&info->irq_lock, flags);
534 val = readl(info->base + reg);
535 writel(val & ~d->mask, info->base + reg);
536 spin_unlock_irqrestore(&info->irq_lock, flags);
537 }
538
539 static void armada_37xx_irq_unmask(struct irq_data *d)
540 {
541 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
542 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
543 u32 val, reg = IRQ_EN;
544 unsigned long flags;
545
546 armada_37xx_irq_update_reg(&reg, d);
547 spin_lock_irqsave(&info->irq_lock, flags);
548 val = readl(info->base + reg);
549 writel(val | d->mask, info->base + reg);
550 spin_unlock_irqrestore(&info->irq_lock, flags);
551 }
552
553 static int armada_37xx_irq_set_wake(struct irq_data *d, unsigned int on)
554 {
555 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
556 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
557 u32 val, reg = IRQ_WKUP;
558 unsigned long flags;
559
560 armada_37xx_irq_update_reg(&reg, d);
561 spin_lock_irqsave(&info->irq_lock, flags);
562 val = readl(info->base + reg);
563 if (on)
564 val |= (BIT(d->hwirq % GPIO_PER_REG));
565 else
566 val &= ~(BIT(d->hwirq % GPIO_PER_REG));
567 writel(val, info->base + reg);
568 spin_unlock_irqrestore(&info->irq_lock, flags);
569
570 return 0;
571 }
572
573 static int armada_37xx_irq_set_type(struct irq_data *d, unsigned int type)
574 {
575 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
576 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip);
577 u32 val, reg = IRQ_POL;
578 unsigned long flags;
579
580 spin_lock_irqsave(&info->irq_lock, flags);
581 armada_37xx_irq_update_reg(&reg, d);
582 val = readl(info->base + reg);
583 switch (type) {
584 case IRQ_TYPE_EDGE_RISING:
585 val &= ~(BIT(d->hwirq % GPIO_PER_REG));
586 break;
587 case IRQ_TYPE_EDGE_FALLING:
588 val |= (BIT(d->hwirq % GPIO_PER_REG));
589 break;
590 case IRQ_TYPE_EDGE_BOTH: {
591 u32 in_val, in_reg = INPUT_VAL;
592
593 armada_37xx_irq_update_reg(&in_reg, d);
594 regmap_read(info->regmap, in_reg, &in_val);
595
596 /* Set initial polarity based on current input level. */
597 if (in_val & BIT(d->hwirq % GPIO_PER_REG))
598 val |= BIT(d->hwirq % GPIO_PER_REG); /* falling */
599 else
600 val &= ~(BIT(d->hwirq % GPIO_PER_REG)); /* rising */
601 break;
602 }
603 default:
604 spin_unlock_irqrestore(&info->irq_lock, flags);
605 return -EINVAL;
606 }
607 writel(val, info->base + reg);
608 spin_unlock_irqrestore(&info->irq_lock, flags);
609
610 return 0;
611 }
612
613 static int armada_37xx_edge_both_irq_swap_pol(struct armada_37xx_pinctrl *info,
614 u32 pin_idx)
615 {
616 u32 reg_idx = pin_idx / GPIO_PER_REG;
617 u32 bit_num = pin_idx % GPIO_PER_REG;
618 u32 p, l, ret;
619 unsigned long flags;
620
621 regmap_read(info->regmap, INPUT_VAL + 4*reg_idx, &l);
622
623 spin_lock_irqsave(&info->irq_lock, flags);
624 p = readl(info->base + IRQ_POL + 4 * reg_idx);
625 if ((p ^ l) & (1 << bit_num)) {
626 /*
627 * For the gpios which are used for both-edge irqs, when their
628 * interrupts happen, their input levels are changed,
629 * yet their interrupt polarities are kept in old values, we
630 * should synchronize their interrupt polarities; for example,
631 * at first a gpio's input level is low and its interrupt
632 * polarity control is "Detect rising edge", then the gpio has
633 * a interrupt , its level turns to high, we should change its
634 * polarity control to "Detect falling edge" correspondingly.
635 */
636 p ^= 1 << bit_num;
637 writel(p, info->base + IRQ_POL + 4 * reg_idx);
638 ret = 0;
639 } else {
640 /* Spurious irq */
641 ret = -1;
642 }
643
644 spin_unlock_irqrestore(&info->irq_lock, flags);
645 return ret;
646 }
647
648 static void armada_37xx_irq_handler(struct irq_desc *desc)
649 {
650 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
651 struct irq_chip *chip = irq_desc_get_chip(desc);
652 struct armada_37xx_pinctrl *info = gpiochip_get_data(gc);
653 struct irq_domain *d = gc->irq.domain;
654 int i;
655
656 chained_irq_enter(chip, desc);
657 for (i = 0; i <= d->revmap_size / GPIO_PER_REG; i++) {
658 u32 status;
659 unsigned long flags;
660
661 spin_lock_irqsave(&info->irq_lock, flags);
662 status = readl_relaxed(info->base + IRQ_STATUS + 4 * i);
663 /* Manage only the interrupt that was enabled */
664 status &= readl_relaxed(info->base + IRQ_EN + 4 * i);
665 spin_unlock_irqrestore(&info->irq_lock, flags);
666 while (status) {
667 u32 hwirq = ffs(status) - 1;
668 u32 virq = irq_find_mapping(d, hwirq +
669 i * GPIO_PER_REG);
670 u32 t = irq_get_trigger_type(virq);
671
672 if ((t & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
673 /* Swap polarity (race with GPIO line) */
674 if (armada_37xx_edge_both_irq_swap_pol(info,
675 hwirq + i * GPIO_PER_REG)) {
676 /*
677 * For spurious irq, which gpio level
678 * is not as expected after incoming
679 * edge, just ack the gpio irq.
680 */
681 writel(1 << hwirq,
682 info->base +
683 IRQ_STATUS + 4 * i);
684 goto update_status;
685 }
686 }
687
688 generic_handle_irq(virq);
689
690 update_status:
691 /* Update status in case a new IRQ appears */
692 spin_lock_irqsave(&info->irq_lock, flags);
693 status = readl_relaxed(info->base +
694 IRQ_STATUS + 4 * i);
695 /* Manage only the interrupt that was enabled */
696 status &= readl_relaxed(info->base + IRQ_EN + 4 * i);
697 spin_unlock_irqrestore(&info->irq_lock, flags);
698 }
699 }
700 chained_irq_exit(chip, desc);
701 }
702
703 static unsigned int armada_37xx_irq_startup(struct irq_data *d)
704 {
705 /*
706 * The mask field is a "precomputed bitmask for accessing the
707 * chip registers" which was introduced for the generic
708 * irqchip framework. As we don't use this framework, we can
709 * reuse this field for our own usage.
710 */
711 d->mask = BIT(d->hwirq % GPIO_PER_REG);
712
713 armada_37xx_irq_unmask(d);
714
715 return 0;
716 }
717
718 static int armada_37xx_irqchip_register(struct platform_device *pdev,
719 struct armada_37xx_pinctrl *info)
720 {
721 struct device_node *np = info->dev->of_node;
722 struct gpio_chip *gc = &info->gpio_chip;
723 struct irq_chip *irqchip = &info->irq_chip;
724 struct gpio_irq_chip *girq = &gc->irq;
725 struct device *dev = &pdev->dev;
726 struct resource res;
727 int ret = -ENODEV, i, nr_irq_parent;
728
729 /* Check if we have at least one gpio-controller child node */
730 for_each_child_of_node(info->dev->of_node, np) {
731 if (of_property_read_bool(np, "gpio-controller")) {
732 ret = 0;
733 break;
734 }
735 }
736 if (ret) {
737 dev_err(dev, "no gpio-controller child node\n");
738 return ret;
739 }
740
741 nr_irq_parent = platform_irq_count(pdev);
742 if (nr_irq_parent < 0) {
743 if (nr_irq_parent != -EPROBE_DEFER)
744 dev_err(dev, "Couldn't determine irq count: %pe\n",
745 ERR_PTR(nr_irq_parent));
746 return nr_irq_parent;
747 }
748
749 spin_lock_init(&info->irq_lock);
750
751 if (!nr_irq_parent) {
752 dev_err(dev, "invalid or no IRQ\n");
753 return 0;
754 }
755
756 if (of_address_to_resource(info->dev->of_node, 1, &res)) {
757 dev_err(dev, "cannot find IO resource\n");
758 return -ENOENT;
759 }
760
761 info->base = devm_ioremap_resource(info->dev, &res);
762 if (IS_ERR(info->base))
763 return PTR_ERR(info->base);
764
765 irqchip->irq_ack = armada_37xx_irq_ack;
766 irqchip->irq_mask = armada_37xx_irq_mask;
767 irqchip->irq_unmask = armada_37xx_irq_unmask;
768 irqchip->irq_set_wake = armada_37xx_irq_set_wake;
769 irqchip->irq_set_type = armada_37xx_irq_set_type;
770 irqchip->irq_startup = armada_37xx_irq_startup;
771 irqchip->name = info->data->name;
772 girq->chip = irqchip;
773 girq->parent_handler = armada_37xx_irq_handler;
774 /*
775 * Many interrupts are connected to the parent interrupt
776 * controller. But we do not take advantage of this and use
777 * the chained irq with all of them.
778 */
779 girq->num_parents = nr_irq_parent;
780 girq->parents = devm_kcalloc(&pdev->dev, nr_irq_parent,
781 sizeof(*girq->parents), GFP_KERNEL);
782 if (!girq->parents)
783 return -ENOMEM;
784 for (i = 0; i < nr_irq_parent; i++) {
785 int irq = platform_get_irq(pdev, i);
786
787 if (irq < 0)
788 continue;
789 girq->parents[i] = irq;
790 }
791 girq->default_type = IRQ_TYPE_NONE;
792 girq->handler = handle_edge_irq;
793
794 return 0;
795 }
796
797 static int armada_37xx_gpiochip_register(struct platform_device *pdev,
798 struct armada_37xx_pinctrl *info)
799 {
800 struct device_node *np;
801 struct gpio_chip *gc;
802 int ret = -ENODEV;
803
804 for_each_child_of_node(info->dev->of_node, np) {
805 if (of_find_property(np, "gpio-controller", NULL)) {
806 ret = 0;
807 break;
808 }
809 }
810 if (ret)
811 return ret;
812
813 info->gpio_chip = armada_37xx_gpiolib_chip;
814
815 gc = &info->gpio_chip;
816 gc->ngpio = info->data->nr_pins;
817 gc->parent = &pdev->dev;
818 gc->base = -1;
819 gc->of_node = np;
820 gc->label = info->data->name;
821
822 ret = armada_37xx_irqchip_register(pdev, info);
823 if (ret)
824 return ret;
825 ret = devm_gpiochip_add_data(&pdev->dev, gc, info);
826 if (ret)
827 return ret;
828
829 return 0;
830 }
831
832 /**
833 * armada_37xx_add_function() - Add a new function to the list
834 * @funcs: array of function to add the new one
835 * @funcsize: size of the remaining space for the function
836 * @name: name of the function to add
837 *
838 * If it is a new function then create it by adding its name else
839 * increment the number of group associated to this function.
840 */
841 static int armada_37xx_add_function(struct armada_37xx_pmx_func *funcs,
842 int *funcsize, const char *name)
843 {
844 int i = 0;
845
846 if (*funcsize <= 0)
847 return -EOVERFLOW;
848
849 while (funcs->ngroups) {
850 /* function already there */
851 if (strcmp(funcs->name, name) == 0) {
852 funcs->ngroups++;
853
854 return -EEXIST;
855 }
856 funcs++;
857 i++;
858 }
859
860 /* append new unique function */
861 funcs->name = name;
862 funcs->ngroups = 1;
863 (*funcsize)--;
864
865 return 0;
866 }
867
868 /**
869 * armada_37xx_fill_group() - complete the group array
870 * @info: info driver instance
871 *
872 * Based on the data available from the armada_37xx_pin_group array
873 * completes the last member of the struct for each function: the list
874 * of the groups associated to this function.
875 *
876 */
877 static int armada_37xx_fill_group(struct armada_37xx_pinctrl *info)
878 {
879 int n, num = 0, funcsize = info->data->nr_pins;
880
881 for (n = 0; n < info->ngroups; n++) {
882 struct armada_37xx_pin_group *grp = &info->groups[n];
883 int i, j, f;
884
885 grp->pins = devm_kcalloc(info->dev,
886 grp->npins + grp->extra_npins,
887 sizeof(*grp->pins),
888 GFP_KERNEL);
889 if (!grp->pins)
890 return -ENOMEM;
891
892 for (i = 0; i < grp->npins; i++)
893 grp->pins[i] = grp->start_pin + i;
894
895 for (j = 0; j < grp->extra_npins; j++)
896 grp->pins[i+j] = grp->extra_pin + j;
897
898 for (f = 0; (f < NB_FUNCS) && grp->funcs[f]; f++) {
899 int ret;
900 /* check for unique functions and count groups */
901 ret = armada_37xx_add_function(info->funcs, &funcsize,
902 grp->funcs[f]);
903 if (ret == -EOVERFLOW)
904 dev_err(info->dev,
905 "More functions than pins(%d)\n",
906 info->data->nr_pins);
907 if (ret < 0)
908 continue;
909 num++;
910 }
911 }
912
913 info->nfuncs = num;
914
915 return 0;
916 }
917
918 /**
919 * armada_37xx_fill_funcs() - complete the funcs array
920 * @info: info driver instance
921 *
922 * Based on the data available from the armada_37xx_pin_group array
923 * completes the last two member of the struct for each group:
924 * - the list of the pins included in the group
925 * - the list of pinmux functions that can be selected for this group
926 *
927 */
928 static int armada_37xx_fill_func(struct armada_37xx_pinctrl *info)
929 {
930 struct armada_37xx_pmx_func *funcs = info->funcs;
931 int n;
932
933 for (n = 0; n < info->nfuncs; n++) {
934 const char *name = funcs[n].name;
935 const char **groups;
936 int g;
937
938 funcs[n].groups = devm_kcalloc(info->dev,
939 funcs[n].ngroups,
940 sizeof(*(funcs[n].groups)),
941 GFP_KERNEL);
942 if (!funcs[n].groups)
943 return -ENOMEM;
944
945 groups = funcs[n].groups;
946
947 for (g = 0; g < info->ngroups; g++) {
948 struct armada_37xx_pin_group *gp = &info->groups[g];
949 int f;
950
951 f = match_string(gp->funcs, NB_FUNCS, name);
952 if (f < 0)
953 continue;
954
955 *groups = gp->name;
956 groups++;
957 }
958 }
959 return 0;
960 }
961
962 static int armada_37xx_pinctrl_register(struct platform_device *pdev,
963 struct armada_37xx_pinctrl *info)
964 {
965 const struct armada_37xx_pin_data *pin_data = info->data;
966 struct pinctrl_desc *ctrldesc = &info->pctl;
967 struct pinctrl_pin_desc *pindesc, *pdesc;
968 int pin, ret;
969
970 info->groups = pin_data->groups;
971 info->ngroups = pin_data->ngroups;
972
973 ctrldesc->name = "armada_37xx-pinctrl";
974 ctrldesc->owner = THIS_MODULE;
975 ctrldesc->pctlops = &armada_37xx_pctrl_ops;
976 ctrldesc->pmxops = &armada_37xx_pmx_ops;
977 ctrldesc->confops = &armada_37xx_pinconf_ops;
978
979 pindesc = devm_kcalloc(&pdev->dev,
980 pin_data->nr_pins, sizeof(*pindesc),
981 GFP_KERNEL);
982 if (!pindesc)
983 return -ENOMEM;
984
985 ctrldesc->pins = pindesc;
986 ctrldesc->npins = pin_data->nr_pins;
987
988 pdesc = pindesc;
989 for (pin = 0; pin < pin_data->nr_pins; pin++) {
990 pdesc->number = pin;
991 pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
992 pin_data->name, pin);
993 pdesc++;
994 }
995
996 /*
997 * we allocate functions for number of pins and hope there are
998 * fewer unique functions than pins available
999 */
1000 info->funcs = devm_kcalloc(&pdev->dev,
1001 pin_data->nr_pins,
1002 sizeof(struct armada_37xx_pmx_func),
1003 GFP_KERNEL);
1004 if (!info->funcs)
1005 return -ENOMEM;
1006
1007
1008 ret = armada_37xx_fill_group(info);
1009 if (ret)
1010 return ret;
1011
1012 ret = armada_37xx_fill_func(info);
1013 if (ret)
1014 return ret;
1015
1016 info->pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc, info);
1017 if (IS_ERR(info->pctl_dev)) {
1018 dev_err(&pdev->dev, "could not register pinctrl driver\n");
1019 return PTR_ERR(info->pctl_dev);
1020 }
1021
1022 return 0;
1023 }
1024
1025 #if defined(CONFIG_PM)
1026 static int armada_3700_pinctrl_suspend(struct device *dev)
1027 {
1028 struct armada_37xx_pinctrl *info = dev_get_drvdata(dev);
1029
1030 /* Save GPIO state */
1031 regmap_read(info->regmap, OUTPUT_EN, &info->pm.out_en_l);
1032 regmap_read(info->regmap, OUTPUT_EN + sizeof(u32), &info->pm.out_en_h);
1033 regmap_read(info->regmap, OUTPUT_VAL, &info->pm.out_val_l);
1034 regmap_read(info->regmap, OUTPUT_VAL + sizeof(u32),
1035 &info->pm.out_val_h);
1036
1037 info->pm.irq_en_l = readl(info->base + IRQ_EN);
1038 info->pm.irq_en_h = readl(info->base + IRQ_EN + sizeof(u32));
1039 info->pm.irq_pol_l = readl(info->base + IRQ_POL);
1040 info->pm.irq_pol_h = readl(info->base + IRQ_POL + sizeof(u32));
1041
1042 /* Save pinctrl state */
1043 regmap_read(info->regmap, SELECTION, &info->pm.selection);
1044
1045 return 0;
1046 }
1047
1048 static int armada_3700_pinctrl_resume(struct device *dev)
1049 {
1050 struct armada_37xx_pinctrl *info = dev_get_drvdata(dev);
1051 struct gpio_chip *gc;
1052 struct irq_domain *d;
1053 int i;
1054
1055 /* Restore GPIO state */
1056 regmap_write(info->regmap, OUTPUT_EN, info->pm.out_en_l);
1057 regmap_write(info->regmap, OUTPUT_EN + sizeof(u32),
1058 info->pm.out_en_h);
1059 regmap_write(info->regmap, OUTPUT_VAL, info->pm.out_val_l);
1060 regmap_write(info->regmap, OUTPUT_VAL + sizeof(u32),
1061 info->pm.out_val_h);
1062
1063 /*
1064 * Input levels may change during suspend, which is not monitored at
1065 * that time. GPIOs used for both-edge IRQs may not be synchronized
1066 * anymore with their polarities (rising/falling edge) and must be
1067 * re-configured manually.
1068 */
1069 gc = &info->gpio_chip;
1070 d = gc->irq.domain;
1071 for (i = 0; i < gc->ngpio; i++) {
1072 u32 irq_bit = BIT(i % GPIO_PER_REG);
1073 u32 mask, *irq_pol, input_reg, virq, type, level;
1074
1075 if (i < GPIO_PER_REG) {
1076 mask = info->pm.irq_en_l;
1077 irq_pol = &info->pm.irq_pol_l;
1078 input_reg = INPUT_VAL;
1079 } else {
1080 mask = info->pm.irq_en_h;
1081 irq_pol = &info->pm.irq_pol_h;
1082 input_reg = INPUT_VAL + sizeof(u32);
1083 }
1084
1085 if (!(mask & irq_bit))
1086 continue;
1087
1088 virq = irq_find_mapping(d, i);
1089 type = irq_get_trigger_type(virq);
1090
1091 /*
1092 * Synchronize level and polarity for both-edge irqs:
1093 * - a high input level expects a falling edge,
1094 * - a low input level exepects a rising edge.
1095 */
1096 if ((type & IRQ_TYPE_SENSE_MASK) ==
1097 IRQ_TYPE_EDGE_BOTH) {
1098 regmap_read(info->regmap, input_reg, &level);
1099 if ((*irq_pol ^ level) & irq_bit)
1100 *irq_pol ^= irq_bit;
1101 }
1102 }
1103
1104 writel(info->pm.irq_en_l, info->base + IRQ_EN);
1105 writel(info->pm.irq_en_h, info->base + IRQ_EN + sizeof(u32));
1106 writel(info->pm.irq_pol_l, info->base + IRQ_POL);
1107 writel(info->pm.irq_pol_h, info->base + IRQ_POL + sizeof(u32));
1108
1109 /* Restore pinctrl state */
1110 regmap_write(info->regmap, SELECTION, info->pm.selection);
1111
1112 return 0;
1113 }
1114
1115 /*
1116 * Since pinctrl is an infrastructure module, its resume should be issued prior
1117 * to other IO drivers.
1118 */
1119 static const struct dev_pm_ops armada_3700_pinctrl_pm_ops = {
1120 .suspend_noirq = armada_3700_pinctrl_suspend,
1121 .resume_noirq = armada_3700_pinctrl_resume,
1122 };
1123
1124 #define PINCTRL_ARMADA_37XX_DEV_PM_OPS (&armada_3700_pinctrl_pm_ops)
1125 #else
1126 #define PINCTRL_ARMADA_37XX_DEV_PM_OPS NULL
1127 #endif /* CONFIG_PM */
1128
1129 static const struct of_device_id armada_37xx_pinctrl_of_match[] = {
1130 {
1131 .compatible = "marvell,armada3710-sb-pinctrl",
1132 .data = &armada_37xx_pin_sb,
1133 },
1134 {
1135 .compatible = "marvell,armada3710-nb-pinctrl",
1136 .data = &armada_37xx_pin_nb,
1137 },
1138 { },
1139 };
1140
1141 static int __init armada_37xx_pinctrl_probe(struct platform_device *pdev)
1142 {
1143 struct armada_37xx_pinctrl *info;
1144 struct device *dev = &pdev->dev;
1145 struct device_node *np = dev->of_node;
1146 struct regmap *regmap;
1147 int ret;
1148
1149 info = devm_kzalloc(dev, sizeof(struct armada_37xx_pinctrl),
1150 GFP_KERNEL);
1151 if (!info)
1152 return -ENOMEM;
1153
1154 info->dev = dev;
1155
1156 regmap = syscon_node_to_regmap(np);
1157 if (IS_ERR(regmap)) {
1158 dev_err(&pdev->dev, "cannot get regmap\n");
1159 return PTR_ERR(regmap);
1160 }
1161 info->regmap = regmap;
1162
1163 info->data = of_device_get_match_data(dev);
1164
1165 ret = armada_37xx_pinctrl_register(pdev, info);
1166 if (ret)
1167 return ret;
1168
1169 ret = armada_37xx_gpiochip_register(pdev, info);
1170 if (ret)
1171 return ret;
1172
1173 platform_set_drvdata(pdev, info);
1174
1175 return 0;
1176 }
1177
1178 static struct platform_driver armada_37xx_pinctrl_driver = {
1179 .driver = {
1180 .name = "armada-37xx-pinctrl",
1181 .of_match_table = armada_37xx_pinctrl_of_match,
1182 .pm = PINCTRL_ARMADA_37XX_DEV_PM_OPS,
1183 },
1184 };
1185
1186 builtin_platform_driver_probe(armada_37xx_pinctrl_driver,
1187 armada_37xx_pinctrl_probe);
Linux with added FPC-III support