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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / pinctrl / nomadik / pinctrl-nomadik.c
blob95f864dfdef4978e445cf7a689e054ac6c410b5e
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Generic GPIO driver for logic cells found in the Nomadik SoC
4 *
5 * Copyright (C) 2008,2009 STMicroelectronics
6 * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it>
7 * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com>
8 * Copyright (C) 2011-2013 Linus Walleij <linus.walleij@linaro.org>
9 */
10 #include <linux/kernel.h>
11 #include <linux/init.h>
12 #include <linux/device.h>
13 #include <linux/platform_device.h>
14 #include <linux/io.h>
15 #include <linux/clk.h>
16 #include <linux/err.h>
17 #include <linux/gpio/driver.h>
18 #include <linux/spinlock.h>
19 #include <linux/interrupt.h>
20 #include <linux/slab.h>
21 #include <linux/of_device.h>
22 #include <linux/of_address.h>
23 #include <linux/bitops.h>
24 #include <linux/pinctrl/machine.h>
25 #include <linux/pinctrl/pinctrl.h>
26 #include <linux/pinctrl/pinmux.h>
27 #include <linux/pinctrl/pinconf.h>
28 /* Since we request GPIOs from ourself */
29 #include <linux/pinctrl/consumer.h>
30 #include "pinctrl-nomadik.h"
31 #include "../core.h"
32 #include "../pinctrl-utils.h"
33
34 /*
35 * The GPIO module in the Nomadik family of Systems-on-Chip is an
36 * AMBA device, managing 32 pins and alternate functions. The logic block
37 * is currently used in the Nomadik and ux500.
38 *
39 * Symbols in this file are called "nmk_gpio" for "nomadik gpio"
40 */
41
42 /*
43 * pin configurations are represented by 32-bit integers:
44 *
45 * bit 0.. 8 - Pin Number (512 Pins Maximum)
46 * bit 9..10 - Alternate Function Selection
47 * bit 11..12 - Pull up/down state
48 * bit 13 - Sleep mode behaviour
49 * bit 14 - Direction
50 * bit 15 - Value (if output)
51 * bit 16..18 - SLPM pull up/down state
52 * bit 19..20 - SLPM direction
53 * bit 21..22 - SLPM Value (if output)
54 * bit 23..25 - PDIS value (if input)
55 * bit 26 - Gpio mode
56 * bit 27 - Sleep mode
57 *
58 * to facilitate the definition, the following macros are provided
59 *
60 * PIN_CFG_DEFAULT - default config (0):
61 * pull up/down = disabled
62 * sleep mode = input/wakeup
63 * direction = input
64 * value = low
65 * SLPM direction = same as normal
66 * SLPM pull = same as normal
67 * SLPM value = same as normal
68 *
69 * PIN_CFG - default config with alternate function
70 */
71
72 typedef unsigned long pin_cfg_t;
73
74 #define PIN_NUM_MASK 0x1ff
75 #define PIN_NUM(x) ((x) & PIN_NUM_MASK)
76
77 #define PIN_ALT_SHIFT 9
78 #define PIN_ALT_MASK (0x3 << PIN_ALT_SHIFT)
79 #define PIN_ALT(x) (((x) & PIN_ALT_MASK) >> PIN_ALT_SHIFT)
80 #define PIN_GPIO (NMK_GPIO_ALT_GPIO << PIN_ALT_SHIFT)
81 #define PIN_ALT_A (NMK_GPIO_ALT_A << PIN_ALT_SHIFT)
82 #define PIN_ALT_B (NMK_GPIO_ALT_B << PIN_ALT_SHIFT)
83 #define PIN_ALT_C (NMK_GPIO_ALT_C << PIN_ALT_SHIFT)
84
85 #define PIN_PULL_SHIFT 11
86 #define PIN_PULL_MASK (0x3 << PIN_PULL_SHIFT)
87 #define PIN_PULL(x) (((x) & PIN_PULL_MASK) >> PIN_PULL_SHIFT)
88 #define PIN_PULL_NONE (NMK_GPIO_PULL_NONE << PIN_PULL_SHIFT)
89 #define PIN_PULL_UP (NMK_GPIO_PULL_UP << PIN_PULL_SHIFT)
90 #define PIN_PULL_DOWN (NMK_GPIO_PULL_DOWN << PIN_PULL_SHIFT)
91
92 #define PIN_SLPM_SHIFT 13
93 #define PIN_SLPM_MASK (0x1 << PIN_SLPM_SHIFT)
94 #define PIN_SLPM(x) (((x) & PIN_SLPM_MASK) >> PIN_SLPM_SHIFT)
95 #define PIN_SLPM_MAKE_INPUT (NMK_GPIO_SLPM_INPUT << PIN_SLPM_SHIFT)
96 #define PIN_SLPM_NOCHANGE (NMK_GPIO_SLPM_NOCHANGE << PIN_SLPM_SHIFT)
97 /* These two replace the above in DB8500v2+ */
98 #define PIN_SLPM_WAKEUP_ENABLE (NMK_GPIO_SLPM_WAKEUP_ENABLE << PIN_SLPM_SHIFT)
99 #define PIN_SLPM_WAKEUP_DISABLE (NMK_GPIO_SLPM_WAKEUP_DISABLE << PIN_SLPM_SHIFT)
100 #define PIN_SLPM_USE_MUX_SETTINGS_IN_SLEEP PIN_SLPM_WAKEUP_DISABLE
101
102 #define PIN_SLPM_GPIO PIN_SLPM_WAKEUP_ENABLE /* In SLPM, pin is a gpio */
103 #define PIN_SLPM_ALTFUNC PIN_SLPM_WAKEUP_DISABLE /* In SLPM, pin is altfunc */
104
105 #define PIN_DIR_SHIFT 14
106 #define PIN_DIR_MASK (0x1 << PIN_DIR_SHIFT)
107 #define PIN_DIR(x) (((x) & PIN_DIR_MASK) >> PIN_DIR_SHIFT)
108 #define PIN_DIR_INPUT (0 << PIN_DIR_SHIFT)
109 #define PIN_DIR_OUTPUT (1 << PIN_DIR_SHIFT)
110
111 #define PIN_VAL_SHIFT 15
112 #define PIN_VAL_MASK (0x1 << PIN_VAL_SHIFT)
113 #define PIN_VAL(x) (((x) & PIN_VAL_MASK) >> PIN_VAL_SHIFT)
114 #define PIN_VAL_LOW (0 << PIN_VAL_SHIFT)
115 #define PIN_VAL_HIGH (1 << PIN_VAL_SHIFT)
116
117 #define PIN_SLPM_PULL_SHIFT 16
118 #define PIN_SLPM_PULL_MASK (0x7 << PIN_SLPM_PULL_SHIFT)
119 #define PIN_SLPM_PULL(x) \
120 (((x) & PIN_SLPM_PULL_MASK) >> PIN_SLPM_PULL_SHIFT)
121 #define PIN_SLPM_PULL_NONE \
122 ((1 + NMK_GPIO_PULL_NONE) << PIN_SLPM_PULL_SHIFT)
123 #define PIN_SLPM_PULL_UP \
124 ((1 + NMK_GPIO_PULL_UP) << PIN_SLPM_PULL_SHIFT)
125 #define PIN_SLPM_PULL_DOWN \
126 ((1 + NMK_GPIO_PULL_DOWN) << PIN_SLPM_PULL_SHIFT)
127
128 #define PIN_SLPM_DIR_SHIFT 19
129 #define PIN_SLPM_DIR_MASK (0x3 << PIN_SLPM_DIR_SHIFT)
130 #define PIN_SLPM_DIR(x) \
131 (((x) & PIN_SLPM_DIR_MASK) >> PIN_SLPM_DIR_SHIFT)
132 #define PIN_SLPM_DIR_INPUT ((1 + 0) << PIN_SLPM_DIR_SHIFT)
133 #define PIN_SLPM_DIR_OUTPUT ((1 + 1) << PIN_SLPM_DIR_SHIFT)
134
135 #define PIN_SLPM_VAL_SHIFT 21
136 #define PIN_SLPM_VAL_MASK (0x3 << PIN_SLPM_VAL_SHIFT)
137 #define PIN_SLPM_VAL(x) \
138 (((x) & PIN_SLPM_VAL_MASK) >> PIN_SLPM_VAL_SHIFT)
139 #define PIN_SLPM_VAL_LOW ((1 + 0) << PIN_SLPM_VAL_SHIFT)
140 #define PIN_SLPM_VAL_HIGH ((1 + 1) << PIN_SLPM_VAL_SHIFT)
141
142 #define PIN_SLPM_PDIS_SHIFT 23
143 #define PIN_SLPM_PDIS_MASK (0x3 << PIN_SLPM_PDIS_SHIFT)
144 #define PIN_SLPM_PDIS(x) \
145 (((x) & PIN_SLPM_PDIS_MASK) >> PIN_SLPM_PDIS_SHIFT)
146 #define PIN_SLPM_PDIS_NO_CHANGE (0 << PIN_SLPM_PDIS_SHIFT)
147 #define PIN_SLPM_PDIS_DISABLED (1 << PIN_SLPM_PDIS_SHIFT)
148 #define PIN_SLPM_PDIS_ENABLED (2 << PIN_SLPM_PDIS_SHIFT)
149
150 #define PIN_LOWEMI_SHIFT 25
151 #define PIN_LOWEMI_MASK (0x1 << PIN_LOWEMI_SHIFT)
152 #define PIN_LOWEMI(x) (((x) & PIN_LOWEMI_MASK) >> PIN_LOWEMI_SHIFT)
153 #define PIN_LOWEMI_DISABLED (0 << PIN_LOWEMI_SHIFT)
154 #define PIN_LOWEMI_ENABLED (1 << PIN_LOWEMI_SHIFT)
155
156 #define PIN_GPIOMODE_SHIFT 26
157 #define PIN_GPIOMODE_MASK (0x1 << PIN_GPIOMODE_SHIFT)
158 #define PIN_GPIOMODE(x) (((x) & PIN_GPIOMODE_MASK) >> PIN_GPIOMODE_SHIFT)
159 #define PIN_GPIOMODE_DISABLED (0 << PIN_GPIOMODE_SHIFT)
160 #define PIN_GPIOMODE_ENABLED (1 << PIN_GPIOMODE_SHIFT)
161
162 #define PIN_SLEEPMODE_SHIFT 27
163 #define PIN_SLEEPMODE_MASK (0x1 << PIN_SLEEPMODE_SHIFT)
164 #define PIN_SLEEPMODE(x) (((x) & PIN_SLEEPMODE_MASK) >> PIN_SLEEPMODE_SHIFT)
165 #define PIN_SLEEPMODE_DISABLED (0 << PIN_SLEEPMODE_SHIFT)
166 #define PIN_SLEEPMODE_ENABLED (1 << PIN_SLEEPMODE_SHIFT)
167
168
169 /* Shortcuts. Use these instead of separate DIR, PULL, and VAL. */
170 #define PIN_INPUT_PULLDOWN (PIN_DIR_INPUT | PIN_PULL_DOWN)
171 #define PIN_INPUT_PULLUP (PIN_DIR_INPUT | PIN_PULL_UP)
172 #define PIN_INPUT_NOPULL (PIN_DIR_INPUT | PIN_PULL_NONE)
173 #define PIN_OUTPUT_LOW (PIN_DIR_OUTPUT | PIN_VAL_LOW)
174 #define PIN_OUTPUT_HIGH (PIN_DIR_OUTPUT | PIN_VAL_HIGH)
175
176 #define PIN_SLPM_INPUT_PULLDOWN (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_DOWN)
177 #define PIN_SLPM_INPUT_PULLUP (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_UP)
178 #define PIN_SLPM_INPUT_NOPULL (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_NONE)
179 #define PIN_SLPM_OUTPUT_LOW (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_LOW)
180 #define PIN_SLPM_OUTPUT_HIGH (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_HIGH)
181
182 #define PIN_CFG_DEFAULT (0)
183
184 #define PIN_CFG(num, alt) \
185 (PIN_CFG_DEFAULT |\
186 (PIN_NUM(num) | PIN_##alt))
187
188 #define PIN_CFG_INPUT(num, alt, pull) \
189 (PIN_CFG_DEFAULT |\
190 (PIN_NUM(num) | PIN_##alt | PIN_INPUT_##pull))
191
192 #define PIN_CFG_OUTPUT(num, alt, val) \
193 (PIN_CFG_DEFAULT |\
194 (PIN_NUM(num) | PIN_##alt | PIN_OUTPUT_##val))
195
196 /*
197 * "nmk_gpio" and "NMK_GPIO" stand for "Nomadik GPIO", leaving
198 * the "gpio" namespace for generic and cross-machine functions
199 */
200
201 #define GPIO_BLOCK_SHIFT 5
202 #define NMK_GPIO_PER_CHIP (1 << GPIO_BLOCK_SHIFT)
203 #define NMK_MAX_BANKS DIV_ROUND_UP(512, NMK_GPIO_PER_CHIP)
204
205 /* Register in the logic block */
206 #define NMK_GPIO_DAT 0x00
207 #define NMK_GPIO_DATS 0x04
208 #define NMK_GPIO_DATC 0x08
209 #define NMK_GPIO_PDIS 0x0c
210 #define NMK_GPIO_DIR 0x10
211 #define NMK_GPIO_DIRS 0x14
212 #define NMK_GPIO_DIRC 0x18
213 #define NMK_GPIO_SLPC 0x1c
214 #define NMK_GPIO_AFSLA 0x20
215 #define NMK_GPIO_AFSLB 0x24
216 #define NMK_GPIO_LOWEMI 0x28
217
218 #define NMK_GPIO_RIMSC 0x40
219 #define NMK_GPIO_FIMSC 0x44
220 #define NMK_GPIO_IS 0x48
221 #define NMK_GPIO_IC 0x4c
222 #define NMK_GPIO_RWIMSC 0x50
223 #define NMK_GPIO_FWIMSC 0x54
224 #define NMK_GPIO_WKS 0x58
225 /* These appear in DB8540 and later ASICs */
226 #define NMK_GPIO_EDGELEVEL 0x5C
227 #define NMK_GPIO_LEVEL 0x60
228
229
230 /* Pull up/down values */
231 enum nmk_gpio_pull {
232 NMK_GPIO_PULL_NONE,
233 NMK_GPIO_PULL_UP,
234 NMK_GPIO_PULL_DOWN,
235 };
236
237 /* Sleep mode */
238 enum nmk_gpio_slpm {
239 NMK_GPIO_SLPM_INPUT,
240 NMK_GPIO_SLPM_WAKEUP_ENABLE = NMK_GPIO_SLPM_INPUT,
241 NMK_GPIO_SLPM_NOCHANGE,
242 NMK_GPIO_SLPM_WAKEUP_DISABLE = NMK_GPIO_SLPM_NOCHANGE,
243 };
244
245 struct nmk_gpio_chip {
246 struct gpio_chip chip;
247 struct irq_chip irqchip;
248 void __iomem *addr;
249 struct clk *clk;
250 unsigned int bank;
251 void (*set_ioforce)(bool enable);
252 spinlock_t lock;
253 bool sleepmode;
254 /* Keep track of configured edges */
255 u32 edge_rising;
256 u32 edge_falling;
257 u32 real_wake;
258 u32 rwimsc;
259 u32 fwimsc;
260 u32 rimsc;
261 u32 fimsc;
262 u32 pull_up;
263 u32 lowemi;
264 };
265
266 /**
267 * struct nmk_pinctrl - state container for the Nomadik pin controller
268 * @dev: containing device pointer
269 * @pctl: corresponding pin controller device
270 * @soc: SoC data for this specific chip
271 * @prcm_base: PRCM register range virtual base
272 */
273 struct nmk_pinctrl {
274 struct device *dev;
275 struct pinctrl_dev *pctl;
276 const struct nmk_pinctrl_soc_data *soc;
277 void __iomem *prcm_base;
278 };
279
280 static struct nmk_gpio_chip *nmk_gpio_chips[NMK_MAX_BANKS];
281
282 static DEFINE_SPINLOCK(nmk_gpio_slpm_lock);
283
284 #define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips)
285
286 static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip,
287 unsigned offset, int gpio_mode)
288 {
289 u32 afunc, bfunc;
290
291 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~BIT(offset);
292 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~BIT(offset);
293 if (gpio_mode & NMK_GPIO_ALT_A)
294 afunc |= BIT(offset);
295 if (gpio_mode & NMK_GPIO_ALT_B)
296 bfunc |= BIT(offset);
297 writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA);
298 writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB);
299 }
300
301 static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip,
302 unsigned offset, enum nmk_gpio_slpm mode)
303 {
304 u32 slpm;
305
306 slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC);
307 if (mode == NMK_GPIO_SLPM_NOCHANGE)
308 slpm |= BIT(offset);
309 else
310 slpm &= ~BIT(offset);
311 writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC);
312 }
313
314 static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip,
315 unsigned offset, enum nmk_gpio_pull pull)
316 {
317 u32 pdis;
318
319 pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS);
320 if (pull == NMK_GPIO_PULL_NONE) {
321 pdis |= BIT(offset);
322 nmk_chip->pull_up &= ~BIT(offset);
323 } else {
324 pdis &= ~BIT(offset);
325 }
326
327 writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS);
328
329 if (pull == NMK_GPIO_PULL_UP) {
330 nmk_chip->pull_up |= BIT(offset);
331 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATS);
332 } else if (pull == NMK_GPIO_PULL_DOWN) {
333 nmk_chip->pull_up &= ~BIT(offset);
334 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATC);
335 }
336 }
337
338 static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip *nmk_chip,
339 unsigned offset, bool lowemi)
340 {
341 bool enabled = nmk_chip->lowemi & BIT(offset);
342
343 if (lowemi == enabled)
344 return;
345
346 if (lowemi)
347 nmk_chip->lowemi |= BIT(offset);
348 else
349 nmk_chip->lowemi &= ~BIT(offset);
350
351 writel_relaxed(nmk_chip->lowemi,
352 nmk_chip->addr + NMK_GPIO_LOWEMI);
353 }
354
355 static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip,
356 unsigned offset)
357 {
358 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRC);
359 }
360
361 static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip,
362 unsigned offset, int val)
363 {
364 if (val)
365 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATS);
366 else
367 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATC);
368 }
369
370 static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip,
371 unsigned offset, int val)
372 {
373 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRS);
374 __nmk_gpio_set_output(nmk_chip, offset, val);
375 }
376
377 static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip,
378 unsigned offset, int gpio_mode,
379 bool glitch)
380 {
381 u32 rwimsc = nmk_chip->rwimsc;
382 u32 fwimsc = nmk_chip->fwimsc;
383
384 if (glitch && nmk_chip->set_ioforce) {
385 u32 bit = BIT(offset);
386
387 /* Prevent spurious wakeups */
388 writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC);
389 writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC);
390
391 nmk_chip->set_ioforce(true);
392 }
393
394 __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode);
395
396 if (glitch && nmk_chip->set_ioforce) {
397 nmk_chip->set_ioforce(false);
398
399 writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC);
400 writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC);
401 }
402 }
403
404 static void
405 nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset)
406 {
407 u32 falling = nmk_chip->fimsc & BIT(offset);
408 u32 rising = nmk_chip->rimsc & BIT(offset);
409 int gpio = nmk_chip->chip.base + offset;
410 int irq = irq_find_mapping(nmk_chip->chip.irq.domain, offset);
411 struct irq_data *d = irq_get_irq_data(irq);
412
413 if (!rising && !falling)
414 return;
415
416 if (!d || !irqd_irq_disabled(d))
417 return;
418
419 if (rising) {
420 nmk_chip->rimsc &= ~BIT(offset);
421 writel_relaxed(nmk_chip->rimsc,
422 nmk_chip->addr + NMK_GPIO_RIMSC);
423 }
424
425 if (falling) {
426 nmk_chip->fimsc &= ~BIT(offset);
427 writel_relaxed(nmk_chip->fimsc,
428 nmk_chip->addr + NMK_GPIO_FIMSC);
429 }
430
431 dev_dbg(nmk_chip->chip.parent, "%d: clearing interrupt mask\n", gpio);
432 }
433
434 static void nmk_write_masked(void __iomem *reg, u32 mask, u32 value)
435 {
436 u32 val;
437
438 val = readl(reg);
439 val = ((val & ~mask) | (value & mask));
440 writel(val, reg);
441 }
442
443 static void nmk_prcm_altcx_set_mode(struct nmk_pinctrl *npct,
444 unsigned offset, unsigned alt_num)
445 {
446 int i;
447 u16 reg;
448 u8 bit;
449 u8 alt_index;
450 const struct prcm_gpiocr_altcx_pin_desc *pin_desc;
451 const u16 *gpiocr_regs;
452
453 if (!npct->prcm_base)
454 return;
455
456 if (alt_num > PRCM_IDX_GPIOCR_ALTC_MAX) {
457 dev_err(npct->dev, "PRCM GPIOCR: alternate-C%i is invalid\n",
458 alt_num);
459 return;
460 }
461
462 for (i = 0 ; i < npct->soc->npins_altcx ; i++) {
463 if (npct->soc->altcx_pins[i].pin == offset)
464 break;
465 }
466 if (i == npct->soc->npins_altcx) {
467 dev_dbg(npct->dev, "PRCM GPIOCR: pin %i is not found\n",
468 offset);
469 return;
470 }
471
472 pin_desc = npct->soc->altcx_pins + i;
473 gpiocr_regs = npct->soc->prcm_gpiocr_registers;
474
475 /*
476 * If alt_num is NULL, just clear current ALTCx selection
477 * to make sure we come back to a pure ALTC selection
478 */
479 if (!alt_num) {
480 for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) {
481 if (pin_desc->altcx[i].used == true) {
482 reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
483 bit = pin_desc->altcx[i].control_bit;
484 if (readl(npct->prcm_base + reg) & BIT(bit)) {
485 nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0);
486 dev_dbg(npct->dev,
487 "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n",
488 offset, i+1);
489 }
490 }
491 }
492 return;
493 }
494
495 alt_index = alt_num - 1;
496 if (pin_desc->altcx[alt_index].used == false) {
497 dev_warn(npct->dev,
498 "PRCM GPIOCR: pin %i: alternate-C%i does not exist\n",
499 offset, alt_num);
500 return;
501 }
502
503 /*
504 * Check if any other ALTCx functions are activated on this pin
505 * and disable it first.
506 */
507 for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) {
508 if (i == alt_index)
509 continue;
510 if (pin_desc->altcx[i].used == true) {
511 reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
512 bit = pin_desc->altcx[i].control_bit;
513 if (readl(npct->prcm_base + reg) & BIT(bit)) {
514 nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0);
515 dev_dbg(npct->dev,
516 "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n",
517 offset, i+1);
518 }
519 }
520 }
521
522 reg = gpiocr_regs[pin_desc->altcx[alt_index].reg_index];
523 bit = pin_desc->altcx[alt_index].control_bit;
524 dev_dbg(npct->dev, "PRCM GPIOCR: pin %i: alternate-C%i has been selected\n",
525 offset, alt_index+1);
526 nmk_write_masked(npct->prcm_base + reg, BIT(bit), BIT(bit));
527 }
528
529 /*
530 * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
531 * - Save SLPM registers
532 * - Set SLPM=0 for the IOs you want to switch and others to 1
533 * - Configure the GPIO registers for the IOs that are being switched
534 * - Set IOFORCE=1
535 * - Modify the AFLSA/B registers for the IOs that are being switched
536 * - Set IOFORCE=0
537 * - Restore SLPM registers
538 * - Any spurious wake up event during switch sequence to be ignored and
539 * cleared
540 */
541 static void nmk_gpio_glitch_slpm_init(unsigned int *slpm)
542 {
543 int i;
544
545 for (i = 0; i < NUM_BANKS; i++) {
546 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
547 unsigned int temp = slpm[i];
548
549 if (!chip)
550 break;
551
552 clk_enable(chip->clk);
553
554 slpm[i] = readl(chip->addr + NMK_GPIO_SLPC);
555 writel(temp, chip->addr + NMK_GPIO_SLPC);
556 }
557 }
558
559 static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm)
560 {
561 int i;
562
563 for (i = 0; i < NUM_BANKS; i++) {
564 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
565
566 if (!chip)
567 break;
568
569 writel(slpm[i], chip->addr + NMK_GPIO_SLPC);
570
571 clk_disable(chip->clk);
572 }
573 }
574
575 static int __maybe_unused nmk_prcm_gpiocr_get_mode(struct pinctrl_dev *pctldev, int gpio)
576 {
577 int i;
578 u16 reg;
579 u8 bit;
580 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
581 const struct prcm_gpiocr_altcx_pin_desc *pin_desc;
582 const u16 *gpiocr_regs;
583
584 if (!npct->prcm_base)
585 return NMK_GPIO_ALT_C;
586
587 for (i = 0; i < npct->soc->npins_altcx; i++) {
588 if (npct->soc->altcx_pins[i].pin == gpio)
589 break;
590 }
591 if (i == npct->soc->npins_altcx)
592 return NMK_GPIO_ALT_C;
593
594 pin_desc = npct->soc->altcx_pins + i;
595 gpiocr_regs = npct->soc->prcm_gpiocr_registers;
596 for (i = 0; i < PRCM_IDX_GPIOCR_ALTC_MAX; i++) {
597 if (pin_desc->altcx[i].used == true) {
598 reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
599 bit = pin_desc->altcx[i].control_bit;
600 if (readl(npct->prcm_base + reg) & BIT(bit))
601 return NMK_GPIO_ALT_C+i+1;
602 }
603 }
604 return NMK_GPIO_ALT_C;
605 }
606
607 /* IRQ functions */
608
609 static void nmk_gpio_irq_ack(struct irq_data *d)
610 {
611 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
612 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
613
614 clk_enable(nmk_chip->clk);
615 writel(BIT(d->hwirq), nmk_chip->addr + NMK_GPIO_IC);
616 clk_disable(nmk_chip->clk);
617 }
618
619 enum nmk_gpio_irq_type {
620 NORMAL,
621 WAKE,
622 };
623
624 static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip,
625 int offset, enum nmk_gpio_irq_type which,
626 bool enable)
627 {
628 u32 *rimscval;
629 u32 *fimscval;
630 u32 rimscreg;
631 u32 fimscreg;
632
633 if (which == NORMAL) {
634 rimscreg = NMK_GPIO_RIMSC;
635 fimscreg = NMK_GPIO_FIMSC;
636 rimscval = &nmk_chip->rimsc;
637 fimscval = &nmk_chip->fimsc;
638 } else {
639 rimscreg = NMK_GPIO_RWIMSC;
640 fimscreg = NMK_GPIO_FWIMSC;
641 rimscval = &nmk_chip->rwimsc;
642 fimscval = &nmk_chip->fwimsc;
643 }
644
645 /* we must individually set/clear the two edges */
646 if (nmk_chip->edge_rising & BIT(offset)) {
647 if (enable)
648 *rimscval |= BIT(offset);
649 else
650 *rimscval &= ~BIT(offset);
651 writel(*rimscval, nmk_chip->addr + rimscreg);
652 }
653 if (nmk_chip->edge_falling & BIT(offset)) {
654 if (enable)
655 *fimscval |= BIT(offset);
656 else
657 *fimscval &= ~BIT(offset);
658 writel(*fimscval, nmk_chip->addr + fimscreg);
659 }
660 }
661
662 static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip,
663 int offset, bool on)
664 {
665 /*
666 * Ensure WAKEUP_ENABLE is on. No need to disable it if wakeup is
667 * disabled, since setting SLPM to 1 increases power consumption, and
668 * wakeup is anyhow controlled by the RIMSC and FIMSC registers.
669 */
670 if (nmk_chip->sleepmode && on) {
671 __nmk_gpio_set_slpm(nmk_chip, offset,
672 NMK_GPIO_SLPM_WAKEUP_ENABLE);
673 }
674
675 __nmk_gpio_irq_modify(nmk_chip, offset, WAKE, on);
676 }
677
678 static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable)
679 {
680 struct nmk_gpio_chip *nmk_chip;
681 unsigned long flags;
682
683 nmk_chip = irq_data_get_irq_chip_data(d);
684 if (!nmk_chip)
685 return -EINVAL;
686
687 clk_enable(nmk_chip->clk);
688 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
689 spin_lock(&nmk_chip->lock);
690
691 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, enable);
692
693 if (!(nmk_chip->real_wake & BIT(d->hwirq)))
694 __nmk_gpio_set_wake(nmk_chip, d->hwirq, enable);
695
696 spin_unlock(&nmk_chip->lock);
697 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
698 clk_disable(nmk_chip->clk);
699
700 return 0;
701 }
702
703 static void nmk_gpio_irq_mask(struct irq_data *d)
704 {
705 nmk_gpio_irq_maskunmask(d, false);
706 }
707
708 static void nmk_gpio_irq_unmask(struct irq_data *d)
709 {
710 nmk_gpio_irq_maskunmask(d, true);
711 }
712
713 static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
714 {
715 struct nmk_gpio_chip *nmk_chip;
716 unsigned long flags;
717
718 nmk_chip = irq_data_get_irq_chip_data(d);
719 if (!nmk_chip)
720 return -EINVAL;
721
722 clk_enable(nmk_chip->clk);
723 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
724 spin_lock(&nmk_chip->lock);
725
726 if (irqd_irq_disabled(d))
727 __nmk_gpio_set_wake(nmk_chip, d->hwirq, on);
728
729 if (on)
730 nmk_chip->real_wake |= BIT(d->hwirq);
731 else
732 nmk_chip->real_wake &= ~BIT(d->hwirq);
733
734 spin_unlock(&nmk_chip->lock);
735 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
736 clk_disable(nmk_chip->clk);
737
738 return 0;
739 }
740
741 static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type)
742 {
743 bool enabled = !irqd_irq_disabled(d);
744 bool wake = irqd_is_wakeup_set(d);
745 struct nmk_gpio_chip *nmk_chip;
746 unsigned long flags;
747
748 nmk_chip = irq_data_get_irq_chip_data(d);
749 if (!nmk_chip)
750 return -EINVAL;
751 if (type & IRQ_TYPE_LEVEL_HIGH)
752 return -EINVAL;
753 if (type & IRQ_TYPE_LEVEL_LOW)
754 return -EINVAL;
755
756 clk_enable(nmk_chip->clk);
757 spin_lock_irqsave(&nmk_chip->lock, flags);
758
759 if (enabled)
760 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, false);
761
762 if (enabled || wake)
763 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, false);
764
765 nmk_chip->edge_rising &= ~BIT(d->hwirq);
766 if (type & IRQ_TYPE_EDGE_RISING)
767 nmk_chip->edge_rising |= BIT(d->hwirq);
768
769 nmk_chip->edge_falling &= ~BIT(d->hwirq);
770 if (type & IRQ_TYPE_EDGE_FALLING)
771 nmk_chip->edge_falling |= BIT(d->hwirq);
772
773 if (enabled)
774 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, true);
775
776 if (enabled || wake)
777 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, true);
778
779 spin_unlock_irqrestore(&nmk_chip->lock, flags);
780 clk_disable(nmk_chip->clk);
781
782 return 0;
783 }
784
785 static unsigned int nmk_gpio_irq_startup(struct irq_data *d)
786 {
787 struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);
788
789 clk_enable(nmk_chip->clk);
790 nmk_gpio_irq_unmask(d);
791 return 0;
792 }
793
794 static void nmk_gpio_irq_shutdown(struct irq_data *d)
795 {
796 struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);
797
798 nmk_gpio_irq_mask(d);
799 clk_disable(nmk_chip->clk);
800 }
801
802 static void nmk_gpio_irq_handler(struct irq_desc *desc)
803 {
804 struct irq_chip *host_chip = irq_desc_get_chip(desc);
805 struct gpio_chip *chip = irq_desc_get_handler_data(desc);
806 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
807 u32 status;
808
809 chained_irq_enter(host_chip, desc);
810
811 clk_enable(nmk_chip->clk);
812 status = readl(nmk_chip->addr + NMK_GPIO_IS);
813 clk_disable(nmk_chip->clk);
814
815 while (status) {
816 int bit = __ffs(status);
817
818 generic_handle_irq(irq_find_mapping(chip->irq.domain, bit));
819 status &= ~BIT(bit);
820 }
821
822 chained_irq_exit(host_chip, desc);
823 }
824
825 /* I/O Functions */
826
827 static int nmk_gpio_get_dir(struct gpio_chip *chip, unsigned offset)
828 {
829 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
830 int dir;
831
832 clk_enable(nmk_chip->clk);
833
834 dir = !(readl(nmk_chip->addr + NMK_GPIO_DIR) & BIT(offset));
835
836 clk_disable(nmk_chip->clk);
837
838 return dir;
839 }
840
841 static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset)
842 {
843 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
844
845 clk_enable(nmk_chip->clk);
846
847 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRC);
848
849 clk_disable(nmk_chip->clk);
850
851 return 0;
852 }
853
854 static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset)
855 {
856 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
857 int value;
858
859 clk_enable(nmk_chip->clk);
860
861 value = !!(readl(nmk_chip->addr + NMK_GPIO_DAT) & BIT(offset));
862
863 clk_disable(nmk_chip->clk);
864
865 return value;
866 }
867
868 static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset,
869 int val)
870 {
871 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
872
873 clk_enable(nmk_chip->clk);
874
875 __nmk_gpio_set_output(nmk_chip, offset, val);
876
877 clk_disable(nmk_chip->clk);
878 }
879
880 static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset,
881 int val)
882 {
883 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
884
885 clk_enable(nmk_chip->clk);
886
887 __nmk_gpio_make_output(nmk_chip, offset, val);
888
889 clk_disable(nmk_chip->clk);
890
891 return 0;
892 }
893
894 #ifdef CONFIG_DEBUG_FS
895 static int nmk_gpio_get_mode(struct nmk_gpio_chip *nmk_chip, int offset)
896 {
897 u32 afunc, bfunc;
898
899 clk_enable(nmk_chip->clk);
900
901 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & BIT(offset);
902 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & BIT(offset);
903
904 clk_disable(nmk_chip->clk);
905
906 return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0);
907 }
908
909 #include <linux/seq_file.h>
910
911 static void nmk_gpio_dbg_show_one(struct seq_file *s,
912 struct pinctrl_dev *pctldev, struct gpio_chip *chip,
913 unsigned offset, unsigned gpio)
914 {
915 const char *label = gpiochip_is_requested(chip, offset);
916 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
917 int mode;
918 bool is_out;
919 bool data_out;
920 bool pull;
921 const char *modes[] = {
922 [NMK_GPIO_ALT_GPIO] = "gpio",
923 [NMK_GPIO_ALT_A] = "altA",
924 [NMK_GPIO_ALT_B] = "altB",
925 [NMK_GPIO_ALT_C] = "altC",
926 [NMK_GPIO_ALT_C+1] = "altC1",
927 [NMK_GPIO_ALT_C+2] = "altC2",
928 [NMK_GPIO_ALT_C+3] = "altC3",
929 [NMK_GPIO_ALT_C+4] = "altC4",
930 };
931 const char *pulls[] = {
932 "none ",
933 "pull down",
934 "pull up ",
935 };
936
937 clk_enable(nmk_chip->clk);
938 is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & BIT(offset));
939 pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & BIT(offset));
940 data_out = !!(readl(nmk_chip->addr + NMK_GPIO_DAT) & BIT(offset));
941 mode = nmk_gpio_get_mode(nmk_chip, offset);
942 if ((mode == NMK_GPIO_ALT_C) && pctldev)
943 mode = nmk_prcm_gpiocr_get_mode(pctldev, gpio);
944
945 if (is_out) {
946 seq_printf(s, " gpio-%-3d (%-20.20s) out %s %s",
947 gpio,
948 label ?: "(none)",
949 data_out ? "hi" : "lo",
950 (mode < 0) ? "unknown" : modes[mode]);
951 } else {
952 int irq = chip->to_irq(chip, offset);
953 struct irq_desc *desc = irq_to_desc(irq);
954 int pullidx = 0;
955 int val;
956
957 if (pull)
958 pullidx = data_out ? 2 : 1;
959
960 seq_printf(s, " gpio-%-3d (%-20.20s) in %s %s",
961 gpio,
962 label ?: "(none)",
963 pulls[pullidx],
964 (mode < 0) ? "unknown" : modes[mode]);
965
966 val = nmk_gpio_get_input(chip, offset);
967 seq_printf(s, " VAL %d", val);
968
969 /*
970 * This races with request_irq(), set_irq_type(),
971 * and set_irq_wake() ... but those are "rare".
972 */
973 if (irq > 0 && desc && desc->action) {
974 char *trigger;
975
976 if (nmk_chip->edge_rising & BIT(offset))
977 trigger = "edge-rising";
978 else if (nmk_chip->edge_falling & BIT(offset))
979 trigger = "edge-falling";
980 else
981 trigger = "edge-undefined";
982
983 seq_printf(s, " irq-%d %s%s",
984 irq, trigger,
985 irqd_is_wakeup_set(&desc->irq_data)
986 ? " wakeup" : "");
987 }
988 }
989 clk_disable(nmk_chip->clk);
990 }
991
992 static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
993 {
994 unsigned i;
995 unsigned gpio = chip->base;
996
997 for (i = 0; i < chip->ngpio; i++, gpio++) {
998 nmk_gpio_dbg_show_one(s, NULL, chip, i, gpio);
999 seq_printf(s, "\n");
1000 }
1001 }
1002
1003 #else
1004 static inline void nmk_gpio_dbg_show_one(struct seq_file *s,
1005 struct pinctrl_dev *pctldev,
1006 struct gpio_chip *chip,
1007 unsigned offset, unsigned gpio)
1008 {
1009 }
1010 #define nmk_gpio_dbg_show NULL
1011 #endif
1012
1013 /*
1014 * We will allocate memory for the state container using devm* allocators
1015 * binding to the first device reaching this point, it doesn't matter if
1016 * it is the pin controller or GPIO driver. However we need to use the right
1017 * platform device when looking up resources so pay attention to pdev.
1018 */
1019 static struct nmk_gpio_chip *nmk_gpio_populate_chip(struct device_node *np,
1020 struct platform_device *pdev)
1021 {
1022 struct nmk_gpio_chip *nmk_chip;
1023 struct platform_device *gpio_pdev;
1024 struct gpio_chip *chip;
1025 struct resource *res;
1026 struct clk *clk;
1027 void __iomem *base;
1028 u32 id;
1029
1030 gpio_pdev = of_find_device_by_node(np);
1031 if (!gpio_pdev) {
1032 pr_err("populate \"%pOFn\": device not found\n", np);
1033 return ERR_PTR(-ENODEV);
1034 }
1035 if (of_property_read_u32(np, "gpio-bank", &id)) {
1036 dev_err(&pdev->dev, "populate: gpio-bank property not found\n");
1037 platform_device_put(gpio_pdev);
1038 return ERR_PTR(-EINVAL);
1039 }
1040
1041 /* Already populated? */
1042 nmk_chip = nmk_gpio_chips[id];
1043 if (nmk_chip) {
1044 platform_device_put(gpio_pdev);
1045 return nmk_chip;
1046 }
1047
1048 nmk_chip = devm_kzalloc(&pdev->dev, sizeof(*nmk_chip), GFP_KERNEL);
1049 if (!nmk_chip) {
1050 platform_device_put(gpio_pdev);
1051 return ERR_PTR(-ENOMEM);
1052 }
1053
1054 nmk_chip->bank = id;
1055 chip = &nmk_chip->chip;
1056 chip->base = id * NMK_GPIO_PER_CHIP;
1057 chip->ngpio = NMK_GPIO_PER_CHIP;
1058 chip->label = dev_name(&gpio_pdev->dev);
1059 chip->parent = &gpio_pdev->dev;
1060
1061 res = platform_get_resource(gpio_pdev, IORESOURCE_MEM, 0);
1062 base = devm_ioremap_resource(&pdev->dev, res);
1063 if (IS_ERR(base)) {
1064 platform_device_put(gpio_pdev);
1065 return ERR_CAST(base);
1066 }
1067 nmk_chip->addr = base;
1068
1069 clk = clk_get(&gpio_pdev->dev, NULL);
1070 if (IS_ERR(clk)) {
1071 platform_device_put(gpio_pdev);
1072 return (void *) clk;
1073 }
1074 clk_prepare(clk);
1075 nmk_chip->clk = clk;
1076
1077 BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips));
1078 nmk_gpio_chips[id] = nmk_chip;
1079 return nmk_chip;
1080 }
1081
1082 static int nmk_gpio_probe(struct platform_device *dev)
1083 {
1084 struct device_node *np = dev->dev.of_node;
1085 struct nmk_gpio_chip *nmk_chip;
1086 struct gpio_chip *chip;
1087 struct gpio_irq_chip *girq;
1088 struct irq_chip *irqchip;
1089 bool supports_sleepmode;
1090 int irq;
1091 int ret;
1092
1093 nmk_chip = nmk_gpio_populate_chip(np, dev);
1094 if (IS_ERR(nmk_chip)) {
1095 dev_err(&dev->dev, "could not populate nmk chip struct\n");
1096 return PTR_ERR(nmk_chip);
1097 }
1098
1099 supports_sleepmode =
1100 of_property_read_bool(np, "st,supports-sleepmode");
1101
1102 /* Correct platform device ID */
1103 dev->id = nmk_chip->bank;
1104
1105 irq = platform_get_irq(dev, 0);
1106 if (irq < 0)
1107 return irq;
1108
1109 /*
1110 * The virt address in nmk_chip->addr is in the nomadik register space,
1111 * so we can simply convert the resource address, without remapping
1112 */
1113 nmk_chip->sleepmode = supports_sleepmode;
1114 spin_lock_init(&nmk_chip->lock);
1115
1116 chip = &nmk_chip->chip;
1117 chip->request = gpiochip_generic_request;
1118 chip->free = gpiochip_generic_free;
1119 chip->get_direction = nmk_gpio_get_dir;
1120 chip->direction_input = nmk_gpio_make_input;
1121 chip->get = nmk_gpio_get_input;
1122 chip->direction_output = nmk_gpio_make_output;
1123 chip->set = nmk_gpio_set_output;
1124 chip->dbg_show = nmk_gpio_dbg_show;
1125 chip->can_sleep = false;
1126 chip->owner = THIS_MODULE;
1127
1128 irqchip = &nmk_chip->irqchip;
1129 irqchip->irq_ack = nmk_gpio_irq_ack;
1130 irqchip->irq_mask = nmk_gpio_irq_mask;
1131 irqchip->irq_unmask = nmk_gpio_irq_unmask;
1132 irqchip->irq_set_type = nmk_gpio_irq_set_type;
1133 irqchip->irq_set_wake = nmk_gpio_irq_set_wake;
1134 irqchip->irq_startup = nmk_gpio_irq_startup;
1135 irqchip->irq_shutdown = nmk_gpio_irq_shutdown;
1136 irqchip->flags = IRQCHIP_MASK_ON_SUSPEND;
1137 irqchip->name = kasprintf(GFP_KERNEL, "nmk%u-%u-%u",
1138 dev->id,
1139 chip->base,
1140 chip->base + chip->ngpio - 1);
1141
1142 girq = &chip->irq;
1143 girq->chip = irqchip;
1144 girq->parent_handler = nmk_gpio_irq_handler;
1145 girq->num_parents = 1;
1146 girq->parents = devm_kcalloc(&dev->dev, 1,
1147 sizeof(*girq->parents),
1148 GFP_KERNEL);
1149 if (!girq->parents)
1150 return -ENOMEM;
1151 girq->parents[0] = irq;
1152 girq->default_type = IRQ_TYPE_NONE;
1153 girq->handler = handle_edge_irq;
1154
1155 clk_enable(nmk_chip->clk);
1156 nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI);
1157 clk_disable(nmk_chip->clk);
1158 chip->of_node = np;
1159
1160 ret = gpiochip_add_data(chip, nmk_chip);
1161 if (ret)
1162 return ret;
1163
1164 platform_set_drvdata(dev, nmk_chip);
1165
1166 dev_info(&dev->dev, "chip registered\n");
1167
1168 return 0;
1169 }
1170
1171 static int nmk_get_groups_cnt(struct pinctrl_dev *pctldev)
1172 {
1173 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1174
1175 return npct->soc->ngroups;
1176 }
1177
1178 static const char *nmk_get_group_name(struct pinctrl_dev *pctldev,
1179 unsigned selector)
1180 {
1181 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1182
1183 return npct->soc->groups[selector].name;
1184 }
1185
1186 static int nmk_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
1187 const unsigned **pins,
1188 unsigned *num_pins)
1189 {
1190 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1191
1192 *pins = npct->soc->groups[selector].pins;
1193 *num_pins = npct->soc->groups[selector].npins;
1194 return 0;
1195 }
1196
1197 static struct nmk_gpio_chip *find_nmk_gpio_from_pin(unsigned pin)
1198 {
1199 int i;
1200 struct nmk_gpio_chip *nmk_gpio;
1201
1202 for(i = 0; i < NMK_MAX_BANKS; i++) {
1203 nmk_gpio = nmk_gpio_chips[i];
1204 if (!nmk_gpio)
1205 continue;
1206 if (pin >= nmk_gpio->chip.base &&
1207 pin < nmk_gpio->chip.base + nmk_gpio->chip.ngpio)
1208 return nmk_gpio;
1209 }
1210 return NULL;
1211 }
1212
1213 static struct gpio_chip *find_gc_from_pin(unsigned pin)
1214 {
1215 struct nmk_gpio_chip *nmk_gpio = find_nmk_gpio_from_pin(pin);
1216
1217 if (nmk_gpio)
1218 return &nmk_gpio->chip;
1219 return NULL;
1220 }
1221
1222 static void nmk_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
1223 unsigned offset)
1224 {
1225 struct gpio_chip *chip = find_gc_from_pin(offset);
1226
1227 if (!chip) {
1228 seq_printf(s, "invalid pin offset");
1229 return;
1230 }
1231 nmk_gpio_dbg_show_one(s, pctldev, chip, offset - chip->base, offset);
1232 }
1233
1234 static int nmk_dt_add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps,
1235 unsigned *num_maps, const char *group,
1236 const char *function)
1237 {
1238 if (*num_maps == *reserved_maps)
1239 return -ENOSPC;
1240
1241 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
1242 (*map)[*num_maps].data.mux.group = group;
1243 (*map)[*num_maps].data.mux.function = function;
1244 (*num_maps)++;
1245
1246 return 0;
1247 }
1248
1249 static int nmk_dt_add_map_configs(struct pinctrl_map **map,
1250 unsigned *reserved_maps,
1251 unsigned *num_maps, const char *group,
1252 unsigned long *configs, unsigned num_configs)
1253 {
1254 unsigned long *dup_configs;
1255
1256 if (*num_maps == *reserved_maps)
1257 return -ENOSPC;
1258
1259 dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs),
1260 GFP_KERNEL);
1261 if (!dup_configs)
1262 return -ENOMEM;
1263
1264 (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_PIN;
1265
1266 (*map)[*num_maps].data.configs.group_or_pin = group;
1267 (*map)[*num_maps].data.configs.configs = dup_configs;
1268 (*map)[*num_maps].data.configs.num_configs = num_configs;
1269 (*num_maps)++;
1270
1271 return 0;
1272 }
1273
1274 #define NMK_CONFIG_PIN(x, y) { .property = x, .config = y, }
1275 #define NMK_CONFIG_PIN_ARRAY(x, y) { .property = x, .choice = y, \
1276 .size = ARRAY_SIZE(y), }
1277
1278 static const unsigned long nmk_pin_input_modes[] = {
1279 PIN_INPUT_NOPULL,
1280 PIN_INPUT_PULLUP,
1281 PIN_INPUT_PULLDOWN,
1282 };
1283
1284 static const unsigned long nmk_pin_output_modes[] = {
1285 PIN_OUTPUT_LOW,
1286 PIN_OUTPUT_HIGH,
1287 PIN_DIR_OUTPUT,
1288 };
1289
1290 static const unsigned long nmk_pin_sleep_modes[] = {
1291 PIN_SLEEPMODE_DISABLED,
1292 PIN_SLEEPMODE_ENABLED,
1293 };
1294
1295 static const unsigned long nmk_pin_sleep_input_modes[] = {
1296 PIN_SLPM_INPUT_NOPULL,
1297 PIN_SLPM_INPUT_PULLUP,
1298 PIN_SLPM_INPUT_PULLDOWN,
1299 PIN_SLPM_DIR_INPUT,
1300 };
1301
1302 static const unsigned long nmk_pin_sleep_output_modes[] = {
1303 PIN_SLPM_OUTPUT_LOW,
1304 PIN_SLPM_OUTPUT_HIGH,
1305 PIN_SLPM_DIR_OUTPUT,
1306 };
1307
1308 static const unsigned long nmk_pin_sleep_wakeup_modes[] = {
1309 PIN_SLPM_WAKEUP_DISABLE,
1310 PIN_SLPM_WAKEUP_ENABLE,
1311 };
1312
1313 static const unsigned long nmk_pin_gpio_modes[] = {
1314 PIN_GPIOMODE_DISABLED,
1315 PIN_GPIOMODE_ENABLED,
1316 };
1317
1318 static const unsigned long nmk_pin_sleep_pdis_modes[] = {
1319 PIN_SLPM_PDIS_DISABLED,
1320 PIN_SLPM_PDIS_ENABLED,
1321 };
1322
1323 struct nmk_cfg_param {
1324 const char *property;
1325 unsigned long config;
1326 const unsigned long *choice;
1327 int size;
1328 };
1329
1330 static const struct nmk_cfg_param nmk_cfg_params[] = {
1331 NMK_CONFIG_PIN_ARRAY("ste,input", nmk_pin_input_modes),
1332 NMK_CONFIG_PIN_ARRAY("ste,output", nmk_pin_output_modes),
1333 NMK_CONFIG_PIN_ARRAY("ste,sleep", nmk_pin_sleep_modes),
1334 NMK_CONFIG_PIN_ARRAY("ste,sleep-input", nmk_pin_sleep_input_modes),
1335 NMK_CONFIG_PIN_ARRAY("ste,sleep-output", nmk_pin_sleep_output_modes),
1336 NMK_CONFIG_PIN_ARRAY("ste,sleep-wakeup", nmk_pin_sleep_wakeup_modes),
1337 NMK_CONFIG_PIN_ARRAY("ste,gpio", nmk_pin_gpio_modes),
1338 NMK_CONFIG_PIN_ARRAY("ste,sleep-pull-disable", nmk_pin_sleep_pdis_modes),
1339 };
1340
1341 static int nmk_dt_pin_config(int index, int val, unsigned long *config)
1342 {
1343 int ret = 0;
1344
1345 if (nmk_cfg_params[index].choice == NULL)
1346 *config = nmk_cfg_params[index].config;
1347 else {
1348 /* test if out of range */
1349 if (val < nmk_cfg_params[index].size) {
1350 *config = nmk_cfg_params[index].config |
1351 nmk_cfg_params[index].choice[val];
1352 }
1353 }
1354 return ret;
1355 }
1356
1357 static const char *nmk_find_pin_name(struct pinctrl_dev *pctldev, const char *pin_name)
1358 {
1359 int i, pin_number;
1360 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1361
1362 if (sscanf((char *)pin_name, "GPIO%d", &pin_number) == 1)
1363 for (i = 0; i < npct->soc->npins; i++)
1364 if (npct->soc->pins[i].number == pin_number)
1365 return npct->soc->pins[i].name;
1366 return NULL;
1367 }
1368
1369 static bool nmk_pinctrl_dt_get_config(struct device_node *np,
1370 unsigned long *configs)
1371 {
1372 bool has_config = 0;
1373 unsigned long cfg = 0;
1374 int i, val, ret;
1375
1376 for (i = 0; i < ARRAY_SIZE(nmk_cfg_params); i++) {
1377 ret = of_property_read_u32(np,
1378 nmk_cfg_params[i].property, &val);
1379 if (ret != -EINVAL) {
1380 if (nmk_dt_pin_config(i, val, &cfg) == 0) {
1381 *configs |= cfg;
1382 has_config = 1;
1383 }
1384 }
1385 }
1386
1387 return has_config;
1388 }
1389
1390 static int nmk_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
1391 struct device_node *np,
1392 struct pinctrl_map **map,
1393 unsigned *reserved_maps,
1394 unsigned *num_maps)
1395 {
1396 int ret;
1397 const char *function = NULL;
1398 unsigned long configs = 0;
1399 bool has_config = 0;
1400 struct property *prop;
1401 struct device_node *np_config;
1402
1403 ret = of_property_read_string(np, "function", &function);
1404 if (ret >= 0) {
1405 const char *group;
1406
1407 ret = of_property_count_strings(np, "groups");
1408 if (ret < 0)
1409 goto exit;
1410
1411 ret = pinctrl_utils_reserve_map(pctldev, map,
1412 reserved_maps,
1413 num_maps, ret);
1414 if (ret < 0)
1415 goto exit;
1416
1417 of_property_for_each_string(np, "groups", prop, group) {
1418 ret = nmk_dt_add_map_mux(map, reserved_maps, num_maps,
1419 group, function);
1420 if (ret < 0)
1421 goto exit;
1422 }
1423 }
1424
1425 has_config = nmk_pinctrl_dt_get_config(np, &configs);
1426 np_config = of_parse_phandle(np, "ste,config", 0);
1427 if (np_config)
1428 has_config |= nmk_pinctrl_dt_get_config(np_config, &configs);
1429 if (has_config) {
1430 const char *gpio_name;
1431 const char *pin;
1432
1433 ret = of_property_count_strings(np, "pins");
1434 if (ret < 0)
1435 goto exit;
1436 ret = pinctrl_utils_reserve_map(pctldev, map,
1437 reserved_maps,
1438 num_maps, ret);
1439 if (ret < 0)
1440 goto exit;
1441
1442 of_property_for_each_string(np, "pins", prop, pin) {
1443 gpio_name = nmk_find_pin_name(pctldev, pin);
1444
1445 ret = nmk_dt_add_map_configs(map, reserved_maps,
1446 num_maps,
1447 gpio_name, &configs, 1);
1448 if (ret < 0)
1449 goto exit;
1450 }
1451 }
1452
1453 exit:
1454 return ret;
1455 }
1456
1457 static int nmk_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
1458 struct device_node *np_config,
1459 struct pinctrl_map **map, unsigned *num_maps)
1460 {
1461 unsigned reserved_maps;
1462 struct device_node *np;
1463 int ret;
1464
1465 reserved_maps = 0;
1466 *map = NULL;
1467 *num_maps = 0;
1468
1469 for_each_child_of_node(np_config, np) {
1470 ret = nmk_pinctrl_dt_subnode_to_map(pctldev, np, map,
1471 &reserved_maps, num_maps);
1472 if (ret < 0) {
1473 pinctrl_utils_free_map(pctldev, *map, *num_maps);
1474 of_node_put(np);
1475 return ret;
1476 }
1477 }
1478
1479 return 0;
1480 }
1481
1482 static const struct pinctrl_ops nmk_pinctrl_ops = {
1483 .get_groups_count = nmk_get_groups_cnt,
1484 .get_group_name = nmk_get_group_name,
1485 .get_group_pins = nmk_get_group_pins,
1486 .pin_dbg_show = nmk_pin_dbg_show,
1487 .dt_node_to_map = nmk_pinctrl_dt_node_to_map,
1488 .dt_free_map = pinctrl_utils_free_map,
1489 };
1490
1491 static int nmk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
1492 {
1493 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1494
1495 return npct->soc->nfunctions;
1496 }
1497
1498 static const char *nmk_pmx_get_func_name(struct pinctrl_dev *pctldev,
1499 unsigned function)
1500 {
1501 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1502
1503 return npct->soc->functions[function].name;
1504 }
1505
1506 static int nmk_pmx_get_func_groups(struct pinctrl_dev *pctldev,
1507 unsigned function,
1508 const char * const **groups,
1509 unsigned * const num_groups)
1510 {
1511 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1512
1513 *groups = npct->soc->functions[function].groups;
1514 *num_groups = npct->soc->functions[function].ngroups;
1515
1516 return 0;
1517 }
1518
1519 static int nmk_pmx_set(struct pinctrl_dev *pctldev, unsigned function,
1520 unsigned group)
1521 {
1522 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1523 const struct nmk_pingroup *g;
1524 static unsigned int slpm[NUM_BANKS];
1525 unsigned long flags = 0;
1526 bool glitch;
1527 int ret = -EINVAL;
1528 int i;
1529
1530 g = &npct->soc->groups[group];
1531
1532 if (g->altsetting < 0)
1533 return -EINVAL;
1534
1535 dev_dbg(npct->dev, "enable group %s, %u pins\n", g->name, g->npins);
1536
1537 /*
1538 * If we're setting altfunc C by setting both AFSLA and AFSLB to 1,
1539 * we may pass through an undesired state. In this case we take
1540 * some extra care.
1541 *
1542 * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
1543 * - Save SLPM registers (since we have a shadow register in the
1544 * nmk_chip we're using that as backup)
1545 * - Set SLPM=0 for the IOs you want to switch and others to 1
1546 * - Configure the GPIO registers for the IOs that are being switched
1547 * - Set IOFORCE=1
1548 * - Modify the AFLSA/B registers for the IOs that are being switched
1549 * - Set IOFORCE=0
1550 * - Restore SLPM registers
1551 * - Any spurious wake up event during switch sequence to be ignored
1552 * and cleared
1553 *
1554 * We REALLY need to save ALL slpm registers, because the external
1555 * IOFORCE will switch *all* ports to their sleepmode setting to as
1556 * to avoid glitches. (Not just one port!)
1557 */
1558 glitch = ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C);
1559
1560 if (glitch) {
1561 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
1562
1563 /* Initially don't put any pins to sleep when switching */
1564 memset(slpm, 0xff, sizeof(slpm));
1565
1566 /*
1567 * Then mask the pins that need to be sleeping now when we're
1568 * switching to the ALT C function.
1569 */
1570 for (i = 0; i < g->npins; i++)
1571 slpm[g->pins[i] / NMK_GPIO_PER_CHIP] &= ~BIT(g->pins[i]);
1572 nmk_gpio_glitch_slpm_init(slpm);
1573 }
1574
1575 for (i = 0; i < g->npins; i++) {
1576 struct nmk_gpio_chip *nmk_chip;
1577 unsigned bit;
1578
1579 nmk_chip = find_nmk_gpio_from_pin(g->pins[i]);
1580 if (!nmk_chip) {
1581 dev_err(npct->dev,
1582 "invalid pin offset %d in group %s at index %d\n",
1583 g->pins[i], g->name, i);
1584 goto out_glitch;
1585 }
1586 dev_dbg(npct->dev, "setting pin %d to altsetting %d\n", g->pins[i], g->altsetting);
1587
1588 clk_enable(nmk_chip->clk);
1589 bit = g->pins[i] % NMK_GPIO_PER_CHIP;
1590 /*
1591 * If the pin is switching to altfunc, and there was an
1592 * interrupt installed on it which has been lazy disabled,
1593 * actually mask the interrupt to prevent spurious interrupts
1594 * that would occur while the pin is under control of the
1595 * peripheral. Only SKE does this.
1596 */
1597 nmk_gpio_disable_lazy_irq(nmk_chip, bit);
1598
1599 __nmk_gpio_set_mode_safe(nmk_chip, bit,
1600 (g->altsetting & NMK_GPIO_ALT_C), glitch);
1601 clk_disable(nmk_chip->clk);
1602
1603 /*
1604 * Call PRCM GPIOCR config function in case ALTC
1605 * has been selected:
1606 * - If selection is a ALTCx, some bits in PRCM GPIOCR registers
1607 * must be set.
1608 * - If selection is pure ALTC and previous selection was ALTCx,
1609 * then some bits in PRCM GPIOCR registers must be cleared.
1610 */
1611 if ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C)
1612 nmk_prcm_altcx_set_mode(npct, g->pins[i],
1613 g->altsetting >> NMK_GPIO_ALT_CX_SHIFT);
1614 }
1615
1616 /* When all pins are successfully reconfigured we get here */
1617 ret = 0;
1618
1619 out_glitch:
1620 if (glitch) {
1621 nmk_gpio_glitch_slpm_restore(slpm);
1622 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
1623 }
1624
1625 return ret;
1626 }
1627
1628 static int nmk_gpio_request_enable(struct pinctrl_dev *pctldev,
1629 struct pinctrl_gpio_range *range,
1630 unsigned offset)
1631 {
1632 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1633 struct nmk_gpio_chip *nmk_chip;
1634 struct gpio_chip *chip;
1635 unsigned bit;
1636
1637 if (!range) {
1638 dev_err(npct->dev, "invalid range\n");
1639 return -EINVAL;
1640 }
1641 if (!range->gc) {
1642 dev_err(npct->dev, "missing GPIO chip in range\n");
1643 return -EINVAL;
1644 }
1645 chip = range->gc;
1646 nmk_chip = gpiochip_get_data(chip);
1647
1648 dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset);
1649
1650 clk_enable(nmk_chip->clk);
1651 bit = offset % NMK_GPIO_PER_CHIP;
1652 /* There is no glitch when converting any pin to GPIO */
1653 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
1654 clk_disable(nmk_chip->clk);
1655
1656 return 0;
1657 }
1658
1659 static void nmk_gpio_disable_free(struct pinctrl_dev *pctldev,
1660 struct pinctrl_gpio_range *range,
1661 unsigned offset)
1662 {
1663 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1664
1665 dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset);
1666 /* Set the pin to some default state, GPIO is usually default */
1667 }
1668
1669 static const struct pinmux_ops nmk_pinmux_ops = {
1670 .get_functions_count = nmk_pmx_get_funcs_cnt,
1671 .get_function_name = nmk_pmx_get_func_name,
1672 .get_function_groups = nmk_pmx_get_func_groups,
1673 .set_mux = nmk_pmx_set,
1674 .gpio_request_enable = nmk_gpio_request_enable,
1675 .gpio_disable_free = nmk_gpio_disable_free,
1676 .strict = true,
1677 };
1678
1679 static int nmk_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin,
1680 unsigned long *config)
1681 {
1682 /* Not implemented */
1683 return -EINVAL;
1684 }
1685
1686 static int nmk_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin,
1687 unsigned long *configs, unsigned num_configs)
1688 {
1689 static const char *pullnames[] = {
1690 [NMK_GPIO_PULL_NONE] = "none",
1691 [NMK_GPIO_PULL_UP] = "up",
1692 [NMK_GPIO_PULL_DOWN] = "down",
1693 [3] /* illegal */ = "??"
1694 };
1695 static const char *slpmnames[] = {
1696 [NMK_GPIO_SLPM_INPUT] = "input/wakeup",
1697 [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup",
1698 };
1699 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1700 struct nmk_gpio_chip *nmk_chip;
1701 unsigned bit;
1702 pin_cfg_t cfg;
1703 int pull, slpm, output, val, i;
1704 bool lowemi, gpiomode, sleep;
1705
1706 nmk_chip = find_nmk_gpio_from_pin(pin);
1707 if (!nmk_chip) {
1708 dev_err(npct->dev,
1709 "invalid pin offset %d\n", pin);
1710 return -EINVAL;
1711 }
1712
1713 for (i = 0; i < num_configs; i++) {
1714 /*
1715 * The pin config contains pin number and altfunction fields,
1716 * here we just ignore that part. It's being handled by the
1717 * framework and pinmux callback respectively.
1718 */
1719 cfg = (pin_cfg_t) configs[i];
1720 pull = PIN_PULL(cfg);
1721 slpm = PIN_SLPM(cfg);
1722 output = PIN_DIR(cfg);
1723 val = PIN_VAL(cfg);
1724 lowemi = PIN_LOWEMI(cfg);
1725 gpiomode = PIN_GPIOMODE(cfg);
1726 sleep = PIN_SLEEPMODE(cfg);
1727
1728 if (sleep) {
1729 int slpm_pull = PIN_SLPM_PULL(cfg);
1730 int slpm_output = PIN_SLPM_DIR(cfg);
1731 int slpm_val = PIN_SLPM_VAL(cfg);
1732
1733 /* All pins go into GPIO mode at sleep */
1734 gpiomode = true;
1735
1736 /*
1737 * The SLPM_* values are normal values + 1 to allow zero
1738 * to mean "same as normal".
1739 */
1740 if (slpm_pull)
1741 pull = slpm_pull - 1;
1742 if (slpm_output)
1743 output = slpm_output - 1;
1744 if (slpm_val)
1745 val = slpm_val - 1;
1746
1747 dev_dbg(nmk_chip->chip.parent,
1748 "pin %d: sleep pull %s, dir %s, val %s\n",
1749 pin,
1750 slpm_pull ? pullnames[pull] : "same",
1751 slpm_output ? (output ? "output" : "input")
1752 : "same",
1753 slpm_val ? (val ? "high" : "low") : "same");
1754 }
1755
1756 dev_dbg(nmk_chip->chip.parent,
1757 "pin %d [%#lx]: pull %s, slpm %s (%s%s), lowemi %s\n",
1758 pin, cfg, pullnames[pull], slpmnames[slpm],
1759 output ? "output " : "input",
1760 output ? (val ? "high" : "low") : "",
1761 lowemi ? "on" : "off");
1762
1763 clk_enable(nmk_chip->clk);
1764 bit = pin % NMK_GPIO_PER_CHIP;
1765 if (gpiomode)
1766 /* No glitch when going to GPIO mode */
1767 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
1768 if (output)
1769 __nmk_gpio_make_output(nmk_chip, bit, val);
1770 else {
1771 __nmk_gpio_make_input(nmk_chip, bit);
1772 __nmk_gpio_set_pull(nmk_chip, bit, pull);
1773 }
1774 /* TODO: isn't this only applicable on output pins? */
1775 __nmk_gpio_set_lowemi(nmk_chip, bit, lowemi);
1776
1777 __nmk_gpio_set_slpm(nmk_chip, bit, slpm);
1778 clk_disable(nmk_chip->clk);
1779 } /* for each config */
1780
1781 return 0;
1782 }
1783
1784 static const struct pinconf_ops nmk_pinconf_ops = {
1785 .pin_config_get = nmk_pin_config_get,
1786 .pin_config_set = nmk_pin_config_set,
1787 };
1788
1789 static struct pinctrl_desc nmk_pinctrl_desc = {
1790 .name = "pinctrl-nomadik",
1791 .pctlops = &nmk_pinctrl_ops,
1792 .pmxops = &nmk_pinmux_ops,
1793 .confops = &nmk_pinconf_ops,
1794 .owner = THIS_MODULE,
1795 };
1796
1797 static const struct of_device_id nmk_pinctrl_match[] = {
1798 {
1799 .compatible = "stericsson,stn8815-pinctrl",
1800 .data = (void *)PINCTRL_NMK_STN8815,
1801 },
1802 {
1803 .compatible = "stericsson,db8500-pinctrl",
1804 .data = (void *)PINCTRL_NMK_DB8500,
1805 },
1806 {
1807 .compatible = "stericsson,db8540-pinctrl",
1808 .data = (void *)PINCTRL_NMK_DB8540,
1809 },
1810 {},
1811 };
1812
1813 #ifdef CONFIG_PM_SLEEP
1814 static int nmk_pinctrl_suspend(struct device *dev)
1815 {
1816 struct nmk_pinctrl *npct;
1817
1818 npct = dev_get_drvdata(dev);
1819 if (!npct)
1820 return -EINVAL;
1821
1822 return pinctrl_force_sleep(npct->pctl);
1823 }
1824
1825 static int nmk_pinctrl_resume(struct device *dev)
1826 {
1827 struct nmk_pinctrl *npct;
1828
1829 npct = dev_get_drvdata(dev);
1830 if (!npct)
1831 return -EINVAL;
1832
1833 return pinctrl_force_default(npct->pctl);
1834 }
1835 #endif
1836
1837 static int nmk_pinctrl_probe(struct platform_device *pdev)
1838 {
1839 const struct of_device_id *match;
1840 struct device_node *np = pdev->dev.of_node;
1841 struct device_node *prcm_np;
1842 struct nmk_pinctrl *npct;
1843 unsigned int version = 0;
1844 int i;
1845
1846 npct = devm_kzalloc(&pdev->dev, sizeof(*npct), GFP_KERNEL);
1847 if (!npct)
1848 return -ENOMEM;
1849
1850 match = of_match_device(nmk_pinctrl_match, &pdev->dev);
1851 if (!match)
1852 return -ENODEV;
1853 version = (unsigned int) match->data;
1854
1855 /* Poke in other ASIC variants here */
1856 if (version == PINCTRL_NMK_STN8815)
1857 nmk_pinctrl_stn8815_init(&npct->soc);
1858 if (version == PINCTRL_NMK_DB8500)
1859 nmk_pinctrl_db8500_init(&npct->soc);
1860 if (version == PINCTRL_NMK_DB8540)
1861 nmk_pinctrl_db8540_init(&npct->soc);
1862
1863 /*
1864 * Since we depend on the GPIO chips to provide clock and register base
1865 * for the pin control operations, make sure that we have these
1866 * populated before we continue. Follow the phandles to instantiate
1867 * them. The GPIO portion of the actual hardware may be probed before
1868 * or after this point: it shouldn't matter as the APIs are orthogonal.
1869 */
1870 for (i = 0; i < NMK_MAX_BANKS; i++) {
1871 struct device_node *gpio_np;
1872 struct nmk_gpio_chip *nmk_chip;
1873
1874 gpio_np = of_parse_phandle(np, "nomadik-gpio-chips", i);
1875 if (gpio_np) {
1876 dev_info(&pdev->dev,
1877 "populate NMK GPIO %d \"%pOFn\"\n",
1878 i, gpio_np);
1879 nmk_chip = nmk_gpio_populate_chip(gpio_np, pdev);
1880 if (IS_ERR(nmk_chip))
1881 dev_err(&pdev->dev,
1882 "could not populate nmk chip struct "
1883 "- continue anyway\n");
1884 of_node_put(gpio_np);
1885 }
1886 }
1887
1888 prcm_np = of_parse_phandle(np, "prcm", 0);
1889 if (prcm_np)
1890 npct->prcm_base = of_iomap(prcm_np, 0);
1891 if (!npct->prcm_base) {
1892 if (version == PINCTRL_NMK_STN8815) {
1893 dev_info(&pdev->dev,
1894 "No PRCM base, "
1895 "assuming no ALT-Cx control is available\n");
1896 } else {
1897 dev_err(&pdev->dev, "missing PRCM base address\n");
1898 return -EINVAL;
1899 }
1900 }
1901
1902 nmk_pinctrl_desc.pins = npct->soc->pins;
1903 nmk_pinctrl_desc.npins = npct->soc->npins;
1904 npct->dev = &pdev->dev;
1905
1906 npct->pctl = devm_pinctrl_register(&pdev->dev, &nmk_pinctrl_desc, npct);
1907 if (IS_ERR(npct->pctl)) {
1908 dev_err(&pdev->dev, "could not register Nomadik pinctrl driver\n");
1909 return PTR_ERR(npct->pctl);
1910 }
1911
1912 platform_set_drvdata(pdev, npct);
1913 dev_info(&pdev->dev, "initialized Nomadik pin control driver\n");
1914
1915 return 0;
1916 }
1917
1918 static const struct of_device_id nmk_gpio_match[] = {
1919 { .compatible = "st,nomadik-gpio", },
1920 {}
1921 };
1922
1923 static struct platform_driver nmk_gpio_driver = {
1924 .driver = {
1925 .name = "gpio",
1926 .of_match_table = nmk_gpio_match,
1927 },
1928 .probe = nmk_gpio_probe,
1929 };
1930
1931 static SIMPLE_DEV_PM_OPS(nmk_pinctrl_pm_ops,
1932 nmk_pinctrl_suspend,
1933 nmk_pinctrl_resume);
1934
1935 static struct platform_driver nmk_pinctrl_driver = {
1936 .driver = {
1937 .name = "pinctrl-nomadik",
1938 .of_match_table = nmk_pinctrl_match,
1939 .pm = &nmk_pinctrl_pm_ops,
1940 },
1941 .probe = nmk_pinctrl_probe,
1942 };
1943
1944 static int __init nmk_gpio_init(void)
1945 {
1946 return platform_driver_register(&nmk_gpio_driver);
1947 }
1948 subsys_initcall(nmk_gpio_init);
1949
1950 static int __init nmk_pinctrl_init(void)
1951 {
1952 return platform_driver_register(&nmk_pinctrl_driver);
1953 }
1954 core_initcall(nmk_pinctrl_init);
Linux with added FPC-III support