treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / pinctrl / sh-pfc / core.c
blob82209116955b153a55b8966aec5db50ea37f1304
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Pin Control and GPIO driver for SuperH Pin Function Controller.
5 * Authors: Magnus Damm, Paul Mundt, Laurent Pinchart
7 * Copyright (C) 2008 Magnus Damm
8 * Copyright (C) 2009 - 2012 Paul Mundt
9 */
11 #define DRV_NAME "sh-pfc"
13 #include <linux/bitops.h>
14 #include <linux/err.h>
15 #include <linux/errno.h>
16 #include <linux/io.h>
17 #include <linux/ioport.h>
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/of.h>
21 #include <linux/of_device.h>
22 #include <linux/pinctrl/machine.h>
23 #include <linux/platform_device.h>
24 #include <linux/psci.h>
25 #include <linux/slab.h>
26 #include <linux/sys_soc.h>
28 #include "core.h"
30 static int sh_pfc_map_resources(struct sh_pfc *pfc,
31 struct platform_device *pdev)
33 struct sh_pfc_window *windows;
34 unsigned int *irqs = NULL;
35 unsigned int num_windows;
36 struct resource *res;
37 unsigned int i;
38 int num_irqs;
40 /* Count the MEM and IRQ resources. */
41 for (num_windows = 0;; num_windows++) {
42 res = platform_get_resource(pdev, IORESOURCE_MEM, num_windows);
43 if (!res)
44 break;
46 if (num_windows == 0)
47 return -EINVAL;
49 num_irqs = platform_irq_count(pdev);
50 if (num_irqs < 0)
51 return num_irqs;
53 /* Allocate memory windows and IRQs arrays. */
54 windows = devm_kcalloc(pfc->dev, num_windows, sizeof(*windows),
55 GFP_KERNEL);
56 if (windows == NULL)
57 return -ENOMEM;
59 pfc->num_windows = num_windows;
60 pfc->windows = windows;
62 if (num_irqs) {
63 irqs = devm_kcalloc(pfc->dev, num_irqs, sizeof(*irqs),
64 GFP_KERNEL);
65 if (irqs == NULL)
66 return -ENOMEM;
68 pfc->num_irqs = num_irqs;
69 pfc->irqs = irqs;
72 /* Fill them. */
73 for (i = 0; i < num_windows; i++) {
74 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
75 windows->phys = res->start;
76 windows->size = resource_size(res);
77 windows->virt = devm_ioremap_resource(pfc->dev, res);
78 if (IS_ERR(windows->virt))
79 return -ENOMEM;
80 windows++;
82 for (i = 0; i < num_irqs; i++)
83 *irqs++ = platform_get_irq(pdev, i);
85 return 0;
88 static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc, u32 reg)
90 struct sh_pfc_window *window;
91 phys_addr_t address = reg;
92 unsigned int i;
94 /* scan through physical windows and convert address */
95 for (i = 0; i < pfc->num_windows; i++) {
96 window = pfc->windows + i;
98 if (address < window->phys)
99 continue;
101 if (address >= (window->phys + window->size))
102 continue;
104 return window->virt + (address - window->phys);
107 BUG();
108 return NULL;
111 int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
113 unsigned int offset;
114 unsigned int i;
116 for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) {
117 const struct sh_pfc_pin_range *range = &pfc->ranges[i];
119 if (pin <= range->end)
120 return pin >= range->start
121 ? offset + pin - range->start : -1;
123 offset += range->end - range->start + 1;
126 return -EINVAL;
129 static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r)
131 if (enum_id < r->begin)
132 return 0;
134 if (enum_id > r->end)
135 return 0;
137 return 1;
140 u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width)
142 switch (reg_width) {
143 case 8:
144 return ioread8(mapped_reg);
145 case 16:
146 return ioread16(mapped_reg);
147 case 32:
148 return ioread32(mapped_reg);
151 BUG();
152 return 0;
155 void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width,
156 u32 data)
158 switch (reg_width) {
159 case 8:
160 iowrite8(data, mapped_reg);
161 return;
162 case 16:
163 iowrite16(data, mapped_reg);
164 return;
165 case 32:
166 iowrite32(data, mapped_reg);
167 return;
170 BUG();
173 u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg)
175 return sh_pfc_read_raw_reg(sh_pfc_phys_to_virt(pfc, reg), 32);
178 void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data)
180 if (pfc->info->unlock_reg)
181 sh_pfc_write_raw_reg(
182 sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32,
183 ~data);
185 sh_pfc_write_raw_reg(sh_pfc_phys_to_virt(pfc, reg), 32, data);
188 static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
189 const struct pinmux_cfg_reg *crp,
190 unsigned int in_pos,
191 void __iomem **mapped_regp, u32 *maskp,
192 unsigned int *posp)
194 unsigned int k;
196 *mapped_regp = sh_pfc_phys_to_virt(pfc, crp->reg);
198 if (crp->field_width) {
199 *maskp = (1 << crp->field_width) - 1;
200 *posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
201 } else {
202 *maskp = (1 << crp->var_field_width[in_pos]) - 1;
203 *posp = crp->reg_width;
204 for (k = 0; k <= in_pos; k++)
205 *posp -= crp->var_field_width[k];
209 static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
210 const struct pinmux_cfg_reg *crp,
211 unsigned int field, u32 value)
213 void __iomem *mapped_reg;
214 unsigned int pos;
215 u32 mask, data;
217 sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
219 dev_dbg(pfc->dev, "write_reg addr = %x, value = 0x%x, field = %u, "
220 "r_width = %u, f_width = %u\n",
221 crp->reg, value, field, crp->reg_width, hweight32(mask));
223 mask = ~(mask << pos);
224 value = value << pos;
226 data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width);
227 data &= mask;
228 data |= value;
230 if (pfc->info->unlock_reg)
231 sh_pfc_write_raw_reg(
232 sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32,
233 ~data);
235 sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
238 static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,
239 const struct pinmux_cfg_reg **crp,
240 unsigned int *fieldp, u32 *valuep)
242 unsigned int k = 0;
244 while (1) {
245 const struct pinmux_cfg_reg *config_reg =
246 pfc->info->cfg_regs + k;
247 unsigned int r_width = config_reg->reg_width;
248 unsigned int f_width = config_reg->field_width;
249 unsigned int curr_width;
250 unsigned int bit_pos;
251 unsigned int pos = 0;
252 unsigned int m = 0;
254 if (!r_width)
255 break;
257 for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
258 u32 ncomb;
259 u32 n;
261 if (f_width)
262 curr_width = f_width;
263 else
264 curr_width = config_reg->var_field_width[m];
266 ncomb = 1 << curr_width;
267 for (n = 0; n < ncomb; n++) {
268 if (config_reg->enum_ids[pos + n] == enum_id) {
269 *crp = config_reg;
270 *fieldp = m;
271 *valuep = n;
272 return 0;
275 pos += ncomb;
276 m++;
278 k++;
281 return -EINVAL;
284 static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos,
285 u16 *enum_idp)
287 const u16 *data = pfc->info->pinmux_data;
288 unsigned int k;
290 if (pos) {
291 *enum_idp = data[pos + 1];
292 return pos + 1;
295 for (k = 0; k < pfc->info->pinmux_data_size; k++) {
296 if (data[k] == mark) {
297 *enum_idp = data[k + 1];
298 return k + 1;
302 dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n",
303 mark);
304 return -EINVAL;
307 int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
309 const struct pinmux_range *range;
310 int pos = 0;
312 switch (pinmux_type) {
313 case PINMUX_TYPE_GPIO:
314 case PINMUX_TYPE_FUNCTION:
315 range = NULL;
316 break;
318 case PINMUX_TYPE_OUTPUT:
319 range = &pfc->info->output;
320 break;
322 case PINMUX_TYPE_INPUT:
323 range = &pfc->info->input;
324 break;
326 default:
327 return -EINVAL;
330 /* Iterate over all the configuration fields we need to update. */
331 while (1) {
332 const struct pinmux_cfg_reg *cr;
333 unsigned int field;
334 u16 enum_id;
335 u32 value;
336 int in_range;
337 int ret;
339 pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
340 if (pos < 0)
341 return pos;
343 if (!enum_id)
344 break;
346 /* Check if the configuration field selects a function. If it
347 * doesn't, skip the field if it's not applicable to the
348 * requested pinmux type.
350 in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
351 if (!in_range) {
352 if (pinmux_type == PINMUX_TYPE_FUNCTION) {
353 /* Functions are allowed to modify all
354 * fields.
356 in_range = 1;
357 } else if (pinmux_type != PINMUX_TYPE_GPIO) {
358 /* Input/output types can only modify fields
359 * that correspond to their respective ranges.
361 in_range = sh_pfc_enum_in_range(enum_id, range);
364 * special case pass through for fixed
365 * input-only or output-only pins without
366 * function enum register association.
368 if (in_range && enum_id == range->force)
369 continue;
371 /* GPIOs are only allowed to modify function fields. */
374 if (!in_range)
375 continue;
377 ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value);
378 if (ret < 0)
379 return ret;
381 sh_pfc_write_config_reg(pfc, cr, field, value);
384 return 0;
387 const struct pinmux_bias_reg *
388 sh_pfc_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
389 unsigned int *bit)
391 unsigned int i, j;
393 for (i = 0; pfc->info->bias_regs[i].puen; i++) {
394 for (j = 0; j < ARRAY_SIZE(pfc->info->bias_regs[i].pins); j++) {
395 if (pfc->info->bias_regs[i].pins[j] == pin) {
396 *bit = j;
397 return &pfc->info->bias_regs[i];
402 WARN_ONCE(1, "Pin %u is not in bias info list\n", pin);
404 return NULL;
407 static int sh_pfc_init_ranges(struct sh_pfc *pfc)
409 struct sh_pfc_pin_range *range;
410 unsigned int nr_ranges;
411 unsigned int i;
413 if (pfc->info->pins[0].pin == (u16)-1) {
414 /* Pin number -1 denotes that the SoC doesn't report pin numbers
415 * in its pin arrays yet. Consider the pin numbers range as
416 * continuous and allocate a single range.
418 pfc->nr_ranges = 1;
419 pfc->ranges = devm_kzalloc(pfc->dev, sizeof(*pfc->ranges),
420 GFP_KERNEL);
421 if (pfc->ranges == NULL)
422 return -ENOMEM;
424 pfc->ranges->start = 0;
425 pfc->ranges->end = pfc->info->nr_pins - 1;
426 pfc->nr_gpio_pins = pfc->info->nr_pins;
428 return 0;
431 /* Count, allocate and fill the ranges. The PFC SoC data pins array must
432 * be sorted by pin numbers, and pins without a GPIO port must come
433 * last.
435 for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) {
436 if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1)
437 nr_ranges++;
440 pfc->nr_ranges = nr_ranges;
441 pfc->ranges = devm_kcalloc(pfc->dev, nr_ranges, sizeof(*pfc->ranges),
442 GFP_KERNEL);
443 if (pfc->ranges == NULL)
444 return -ENOMEM;
446 range = pfc->ranges;
447 range->start = pfc->info->pins[0].pin;
449 for (i = 1; i < pfc->info->nr_pins; ++i) {
450 if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1)
451 continue;
453 range->end = pfc->info->pins[i-1].pin;
454 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
455 pfc->nr_gpio_pins = range->end + 1;
457 range++;
458 range->start = pfc->info->pins[i].pin;
461 range->end = pfc->info->pins[i-1].pin;
462 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
463 pfc->nr_gpio_pins = range->end + 1;
465 return 0;
468 #ifdef CONFIG_OF
469 static const struct of_device_id sh_pfc_of_table[] = {
470 #ifdef CONFIG_PINCTRL_PFC_EMEV2
472 .compatible = "renesas,pfc-emev2",
473 .data = &emev2_pinmux_info,
475 #endif
476 #ifdef CONFIG_PINCTRL_PFC_R8A73A4
478 .compatible = "renesas,pfc-r8a73a4",
479 .data = &r8a73a4_pinmux_info,
481 #endif
482 #ifdef CONFIG_PINCTRL_PFC_R8A7740
484 .compatible = "renesas,pfc-r8a7740",
485 .data = &r8a7740_pinmux_info,
487 #endif
488 #ifdef CONFIG_PINCTRL_PFC_R8A7743
490 .compatible = "renesas,pfc-r8a7743",
491 .data = &r8a7743_pinmux_info,
493 #endif
494 #ifdef CONFIG_PINCTRL_PFC_R8A7744
496 .compatible = "renesas,pfc-r8a7744",
497 .data = &r8a7744_pinmux_info,
499 #endif
500 #ifdef CONFIG_PINCTRL_PFC_R8A7745
502 .compatible = "renesas,pfc-r8a7745",
503 .data = &r8a7745_pinmux_info,
505 #endif
506 #ifdef CONFIG_PINCTRL_PFC_R8A77470
508 .compatible = "renesas,pfc-r8a77470",
509 .data = &r8a77470_pinmux_info,
511 #endif
512 #ifdef CONFIG_PINCTRL_PFC_R8A774A1
514 .compatible = "renesas,pfc-r8a774a1",
515 .data = &r8a774a1_pinmux_info,
517 #endif
518 #ifdef CONFIG_PINCTRL_PFC_R8A774B1
520 .compatible = "renesas,pfc-r8a774b1",
521 .data = &r8a774b1_pinmux_info,
523 #endif
524 #ifdef CONFIG_PINCTRL_PFC_R8A774C0
526 .compatible = "renesas,pfc-r8a774c0",
527 .data = &r8a774c0_pinmux_info,
529 #endif
530 #ifdef CONFIG_PINCTRL_PFC_R8A7778
532 .compatible = "renesas,pfc-r8a7778",
533 .data = &r8a7778_pinmux_info,
535 #endif
536 #ifdef CONFIG_PINCTRL_PFC_R8A7779
538 .compatible = "renesas,pfc-r8a7779",
539 .data = &r8a7779_pinmux_info,
541 #endif
542 #ifdef CONFIG_PINCTRL_PFC_R8A7790
544 .compatible = "renesas,pfc-r8a7790",
545 .data = &r8a7790_pinmux_info,
547 #endif
548 #ifdef CONFIG_PINCTRL_PFC_R8A7791
550 .compatible = "renesas,pfc-r8a7791",
551 .data = &r8a7791_pinmux_info,
553 #endif
554 #ifdef CONFIG_PINCTRL_PFC_R8A7792
556 .compatible = "renesas,pfc-r8a7792",
557 .data = &r8a7792_pinmux_info,
559 #endif
560 #ifdef CONFIG_PINCTRL_PFC_R8A7793
562 .compatible = "renesas,pfc-r8a7793",
563 .data = &r8a7793_pinmux_info,
565 #endif
566 #ifdef CONFIG_PINCTRL_PFC_R8A7794
568 .compatible = "renesas,pfc-r8a7794",
569 .data = &r8a7794_pinmux_info,
571 #endif
572 /* Both r8a7795 entries must be present to make sanity checks work */
573 #ifdef CONFIG_PINCTRL_PFC_R8A77950
575 .compatible = "renesas,pfc-r8a7795",
576 .data = &r8a77950_pinmux_info,
578 #endif
579 #ifdef CONFIG_PINCTRL_PFC_R8A77951
581 .compatible = "renesas,pfc-r8a7795",
582 .data = &r8a77951_pinmux_info,
584 #endif
585 #ifdef CONFIG_PINCTRL_PFC_R8A77960
587 .compatible = "renesas,pfc-r8a7796",
588 .data = &r8a77960_pinmux_info,
590 #endif
591 #ifdef CONFIG_PINCTRL_PFC_R8A77961
593 .compatible = "renesas,pfc-r8a77961",
594 .data = &r8a77961_pinmux_info,
596 #endif
597 #ifdef CONFIG_PINCTRL_PFC_R8A77965
599 .compatible = "renesas,pfc-r8a77965",
600 .data = &r8a77965_pinmux_info,
602 #endif
603 #ifdef CONFIG_PINCTRL_PFC_R8A77970
605 .compatible = "renesas,pfc-r8a77970",
606 .data = &r8a77970_pinmux_info,
608 #endif
609 #ifdef CONFIG_PINCTRL_PFC_R8A77980
611 .compatible = "renesas,pfc-r8a77980",
612 .data = &r8a77980_pinmux_info,
614 #endif
615 #ifdef CONFIG_PINCTRL_PFC_R8A77990
617 .compatible = "renesas,pfc-r8a77990",
618 .data = &r8a77990_pinmux_info,
620 #endif
621 #ifdef CONFIG_PINCTRL_PFC_R8A77995
623 .compatible = "renesas,pfc-r8a77995",
624 .data = &r8a77995_pinmux_info,
626 #endif
627 #ifdef CONFIG_PINCTRL_PFC_SH73A0
629 .compatible = "renesas,pfc-sh73a0",
630 .data = &sh73a0_pinmux_info,
632 #endif
633 { },
635 #endif
637 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM_PSCI_FW)
638 static void sh_pfc_nop_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx)
642 static void sh_pfc_save_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx)
644 pfc->saved_regs[idx] = sh_pfc_read(pfc, reg);
647 static void sh_pfc_restore_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx)
649 sh_pfc_write(pfc, reg, pfc->saved_regs[idx]);
652 static unsigned int sh_pfc_walk_regs(struct sh_pfc *pfc,
653 void (*do_reg)(struct sh_pfc *pfc, u32 reg, unsigned int idx))
655 unsigned int i, n = 0;
657 if (pfc->info->cfg_regs)
658 for (i = 0; pfc->info->cfg_regs[i].reg; i++)
659 do_reg(pfc, pfc->info->cfg_regs[i].reg, n++);
661 if (pfc->info->drive_regs)
662 for (i = 0; pfc->info->drive_regs[i].reg; i++)
663 do_reg(pfc, pfc->info->drive_regs[i].reg, n++);
665 if (pfc->info->bias_regs)
666 for (i = 0; pfc->info->bias_regs[i].puen; i++) {
667 do_reg(pfc, pfc->info->bias_regs[i].puen, n++);
668 if (pfc->info->bias_regs[i].pud)
669 do_reg(pfc, pfc->info->bias_regs[i].pud, n++);
672 if (pfc->info->ioctrl_regs)
673 for (i = 0; pfc->info->ioctrl_regs[i].reg; i++)
674 do_reg(pfc, pfc->info->ioctrl_regs[i].reg, n++);
676 return n;
679 static int sh_pfc_suspend_init(struct sh_pfc *pfc)
681 unsigned int n;
683 /* This is the best we can do to check for the presence of PSCI */
684 if (!psci_ops.cpu_suspend)
685 return 0;
687 n = sh_pfc_walk_regs(pfc, sh_pfc_nop_reg);
688 if (!n)
689 return 0;
691 pfc->saved_regs = devm_kmalloc_array(pfc->dev, n,
692 sizeof(*pfc->saved_regs),
693 GFP_KERNEL);
694 if (!pfc->saved_regs)
695 return -ENOMEM;
697 dev_dbg(pfc->dev, "Allocated space to save %u regs\n", n);
698 return 0;
701 static int sh_pfc_suspend_noirq(struct device *dev)
703 struct sh_pfc *pfc = dev_get_drvdata(dev);
705 if (pfc->saved_regs)
706 sh_pfc_walk_regs(pfc, sh_pfc_save_reg);
707 return 0;
710 static int sh_pfc_resume_noirq(struct device *dev)
712 struct sh_pfc *pfc = dev_get_drvdata(dev);
714 if (pfc->saved_regs)
715 sh_pfc_walk_regs(pfc, sh_pfc_restore_reg);
716 return 0;
719 static const struct dev_pm_ops sh_pfc_pm = {
720 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sh_pfc_suspend_noirq, sh_pfc_resume_noirq)
722 #define DEV_PM_OPS &sh_pfc_pm
723 #else
724 static int sh_pfc_suspend_init(struct sh_pfc *pfc) { return 0; }
725 #define DEV_PM_OPS NULL
726 #endif /* CONFIG_PM_SLEEP && CONFIG_ARM_PSCI_FW */
728 #ifdef DEBUG
729 static bool __init is0s(const u16 *enum_ids, unsigned int n)
731 unsigned int i;
733 for (i = 0; i < n; i++)
734 if (enum_ids[i])
735 return false;
737 return true;
740 static unsigned int sh_pfc_errors __initdata = 0;
741 static unsigned int sh_pfc_warnings __initdata = 0;
743 static void __init sh_pfc_check_cfg_reg(const char *drvname,
744 const struct pinmux_cfg_reg *cfg_reg)
746 unsigned int i, n, rw, fw;
748 if (cfg_reg->field_width) {
749 /* Checked at build time */
750 return;
753 for (i = 0, n = 0, rw = 0; (fw = cfg_reg->var_field_width[i]); i++) {
754 if (fw > 3 && is0s(&cfg_reg->enum_ids[n], 1 << fw)) {
755 pr_warn("%s: reg 0x%x: reserved field [%u:%u] can be split to reduce table size\n",
756 drvname, cfg_reg->reg, rw, rw + fw - 1);
757 sh_pfc_warnings++;
759 n += 1 << fw;
760 rw += fw;
763 if (rw != cfg_reg->reg_width) {
764 pr_err("%s: reg 0x%x: var_field_width declares %u instead of %u bits\n",
765 drvname, cfg_reg->reg, rw, cfg_reg->reg_width);
766 sh_pfc_errors++;
769 if (n != cfg_reg->nr_enum_ids) {
770 pr_err("%s: reg 0x%x: enum_ids[] has %u instead of %u values\n",
771 drvname, cfg_reg->reg, cfg_reg->nr_enum_ids, n);
772 sh_pfc_errors++;
776 static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info)
778 const struct sh_pfc_function *func;
779 const char *drvname = info->name;
780 unsigned int *refcnts;
781 unsigned int i, j, k;
783 pr_info("Checking %s\n", drvname);
785 /* Check pins */
786 for (i = 0; i < info->nr_pins; i++) {
787 for (j = 0; j < i; j++) {
788 if (!strcmp(info->pins[i].name, info->pins[j].name)) {
789 pr_err("%s: pin %s/%s: name conflict\n",
790 drvname, info->pins[i].name,
791 info->pins[j].name);
792 sh_pfc_errors++;
795 if (info->pins[i].pin != (u16)-1 &&
796 info->pins[i].pin == info->pins[j].pin) {
797 pr_err("%s: pin %s/%s: pin %u conflict\n",
798 drvname, info->pins[i].name,
799 info->pins[j].name, info->pins[i].pin);
800 sh_pfc_errors++;
803 if (info->pins[i].enum_id &&
804 info->pins[i].enum_id == info->pins[j].enum_id) {
805 pr_err("%s: pin %s/%s: enum_id %u conflict\n",
806 drvname, info->pins[i].name,
807 info->pins[j].name,
808 info->pins[i].enum_id);
809 sh_pfc_errors++;
814 /* Check groups and functions */
815 refcnts = kcalloc(info->nr_groups, sizeof(*refcnts), GFP_KERNEL);
816 if (!refcnts)
817 return;
819 for (i = 0; i < info->nr_functions; i++) {
820 func = &info->functions[i];
821 if (!func->name) {
822 pr_err("%s: empty function %u\n", drvname, i);
823 sh_pfc_errors++;
824 continue;
826 for (j = 0; j < func->nr_groups; j++) {
827 for (k = 0; k < info->nr_groups; k++) {
828 if (info->groups[k].name &&
829 !strcmp(func->groups[j],
830 info->groups[k].name)) {
831 refcnts[k]++;
832 break;
836 if (k == info->nr_groups) {
837 pr_err("%s: function %s: group %s not found\n",
838 drvname, func->name, func->groups[j]);
839 sh_pfc_errors++;
844 for (i = 0; i < info->nr_groups; i++) {
845 if (!info->groups[i].name) {
846 pr_err("%s: empty group %u\n", drvname, i);
847 sh_pfc_errors++;
848 continue;
850 if (!refcnts[i]) {
851 pr_err("%s: orphan group %s\n", drvname,
852 info->groups[i].name);
853 sh_pfc_errors++;
854 } else if (refcnts[i] > 1) {
855 pr_warn("%s: group %s referenced by %u functions\n",
856 drvname, info->groups[i].name, refcnts[i]);
857 sh_pfc_warnings++;
861 kfree(refcnts);
863 /* Check config register descriptions */
864 for (i = 0; info->cfg_regs && info->cfg_regs[i].reg; i++)
865 sh_pfc_check_cfg_reg(drvname, &info->cfg_regs[i]);
868 static void __init sh_pfc_check_driver(const struct platform_driver *pdrv)
870 unsigned int i;
872 pr_warn("Checking builtin pinmux tables\n");
874 for (i = 0; pdrv->id_table[i].name[0]; i++)
875 sh_pfc_check_info((void *)pdrv->id_table[i].driver_data);
877 #ifdef CONFIG_OF
878 for (i = 0; pdrv->driver.of_match_table[i].compatible[0]; i++)
879 sh_pfc_check_info(pdrv->driver.of_match_table[i].data);
880 #endif
882 pr_warn("Detected %u errors and %u warnings\n", sh_pfc_errors,
883 sh_pfc_warnings);
886 #else /* !DEBUG */
887 static inline void sh_pfc_check_driver(struct platform_driver *pdrv) {}
888 #endif /* !DEBUG */
890 #ifdef CONFIG_OF
891 static const void *sh_pfc_quirk_match(void)
893 #if defined(CONFIG_PINCTRL_PFC_R8A77950) || \
894 defined(CONFIG_PINCTRL_PFC_R8A77951)
895 const struct soc_device_attribute *match;
896 static const struct soc_device_attribute quirks[] = {
898 .soc_id = "r8a7795", .revision = "ES1.*",
899 .data = &r8a77950_pinmux_info,
902 .soc_id = "r8a7795",
903 .data = &r8a77951_pinmux_info,
906 { /* sentinel */ }
909 match = soc_device_match(quirks);
910 if (match)
911 return match->data ?: ERR_PTR(-ENODEV);
912 #endif /* CONFIG_PINCTRL_PFC_R8A77950 || CONFIG_PINCTRL_PFC_R8A77951 */
914 return NULL;
916 #endif /* CONFIG_OF */
918 static int sh_pfc_probe(struct platform_device *pdev)
920 const struct sh_pfc_soc_info *info;
921 struct sh_pfc *pfc;
922 int ret;
924 #ifdef CONFIG_OF
925 if (pdev->dev.of_node) {
926 info = sh_pfc_quirk_match();
927 if (IS_ERR(info))
928 return PTR_ERR(info);
930 if (!info)
931 info = of_device_get_match_data(&pdev->dev);
932 } else
933 #endif
934 info = (const void *)platform_get_device_id(pdev)->driver_data;
936 pfc = devm_kzalloc(&pdev->dev, sizeof(*pfc), GFP_KERNEL);
937 if (pfc == NULL)
938 return -ENOMEM;
940 pfc->info = info;
941 pfc->dev = &pdev->dev;
943 ret = sh_pfc_map_resources(pfc, pdev);
944 if (unlikely(ret < 0))
945 return ret;
947 spin_lock_init(&pfc->lock);
949 if (info->ops && info->ops->init) {
950 ret = info->ops->init(pfc);
951 if (ret < 0)
952 return ret;
954 /* .init() may have overridden pfc->info */
955 info = pfc->info;
958 ret = sh_pfc_suspend_init(pfc);
959 if (ret)
960 return ret;
962 /* Enable dummy states for those platforms without pinctrl support */
963 if (!of_have_populated_dt())
964 pinctrl_provide_dummies();
966 ret = sh_pfc_init_ranges(pfc);
967 if (ret < 0)
968 return ret;
971 * Initialize pinctrl bindings first
973 ret = sh_pfc_register_pinctrl(pfc);
974 if (unlikely(ret != 0))
975 return ret;
977 #ifdef CONFIG_PINCTRL_SH_PFC_GPIO
979 * Then the GPIO chip
981 ret = sh_pfc_register_gpiochip(pfc);
982 if (unlikely(ret != 0)) {
984 * If the GPIO chip fails to come up we still leave the
985 * PFC state as it is, given that there are already
986 * extant users of it that have succeeded by this point.
988 dev_notice(pfc->dev, "failed to init GPIO chip, ignoring...\n");
990 #endif
992 platform_set_drvdata(pdev, pfc);
994 dev_info(pfc->dev, "%s support registered\n", info->name);
996 return 0;
999 static const struct platform_device_id sh_pfc_id_table[] = {
1000 #ifdef CONFIG_PINCTRL_PFC_SH7203
1001 { "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info },
1002 #endif
1003 #ifdef CONFIG_PINCTRL_PFC_SH7264
1004 { "pfc-sh7264", (kernel_ulong_t)&sh7264_pinmux_info },
1005 #endif
1006 #ifdef CONFIG_PINCTRL_PFC_SH7269
1007 { "pfc-sh7269", (kernel_ulong_t)&sh7269_pinmux_info },
1008 #endif
1009 #ifdef CONFIG_PINCTRL_PFC_SH7720
1010 { "pfc-sh7720", (kernel_ulong_t)&sh7720_pinmux_info },
1011 #endif
1012 #ifdef CONFIG_PINCTRL_PFC_SH7722
1013 { "pfc-sh7722", (kernel_ulong_t)&sh7722_pinmux_info },
1014 #endif
1015 #ifdef CONFIG_PINCTRL_PFC_SH7723
1016 { "pfc-sh7723", (kernel_ulong_t)&sh7723_pinmux_info },
1017 #endif
1018 #ifdef CONFIG_PINCTRL_PFC_SH7724
1019 { "pfc-sh7724", (kernel_ulong_t)&sh7724_pinmux_info },
1020 #endif
1021 #ifdef CONFIG_PINCTRL_PFC_SH7734
1022 { "pfc-sh7734", (kernel_ulong_t)&sh7734_pinmux_info },
1023 #endif
1024 #ifdef CONFIG_PINCTRL_PFC_SH7757
1025 { "pfc-sh7757", (kernel_ulong_t)&sh7757_pinmux_info },
1026 #endif
1027 #ifdef CONFIG_PINCTRL_PFC_SH7785
1028 { "pfc-sh7785", (kernel_ulong_t)&sh7785_pinmux_info },
1029 #endif
1030 #ifdef CONFIG_PINCTRL_PFC_SH7786
1031 { "pfc-sh7786", (kernel_ulong_t)&sh7786_pinmux_info },
1032 #endif
1033 #ifdef CONFIG_PINCTRL_PFC_SHX3
1034 { "pfc-shx3", (kernel_ulong_t)&shx3_pinmux_info },
1035 #endif
1036 { },
1039 static struct platform_driver sh_pfc_driver = {
1040 .probe = sh_pfc_probe,
1041 .id_table = sh_pfc_id_table,
1042 .driver = {
1043 .name = DRV_NAME,
1044 .of_match_table = of_match_ptr(sh_pfc_of_table),
1045 .pm = DEV_PM_OPS,
1049 static int __init sh_pfc_init(void)
1051 sh_pfc_check_driver(&sh_pfc_driver);
1052 return platform_driver_register(&sh_pfc_driver);
1054 postcore_initcall(sh_pfc_init);