drivers/pinctrl/sh-pfc/pfc-r8a7778.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * r8a7778 processor support - PFC hardware block
   4  *
   5  * Copyright (C) 2013  Renesas Solutions Corp.
   6  * Copyright (C) 2013  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
   7  * Copyright (C) 2013  Cogent Embedded, Inc.
   8  * Copyright (C) 2015  Ulrich Hecht
   9  *
  10  * based on
  11  * Copyright (C) 2011  Renesas Solutions Corp.
  12  * Copyright (C) 2011  Magnus Damm
  13  */
  14
  15 #include <linux/io.h>
  16 #include <linux/kernel.h>
  17 #include <linux/pinctrl/pinconf-generic.h>
  18
  19 #include "core.h"
  20 #include "sh_pfc.h"
  21
  22 #define PORT_GP_PUP_1(bank, pin, fn, sfx)       \
  23         PORT_GP_CFG_1(bank, pin, fn, sfx, SH_PFC_PIN_CFG_PULL_UP)
  24
  25 #define CPU_ALL_GP(fn, sfx)             \
  26         PORT_GP_CFG_32(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),             \
  27         PORT_GP_CFG_32(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),             \
  28         PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),             \
  29         PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_PULL_UP),             \
  30         PORT_GP_CFG_27(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP)
  31
  32 #define CPU_ALL_NOGP(fn)                \
  33         PIN_NOGP(CLKOUT, "B25", fn),    \
  34         PIN_NOGP(CS0, "A20", fn),       \
  35         PIN_NOGP(CS1_A26, "C20", fn)
  36
  37 enum {
  38         PINMUX_RESERVED = 0,
  39
  40         PINMUX_DATA_BEGIN,
  41         GP_ALL(DATA), /* GP_0_0_DATA -> GP_4_26_DATA */
  42         PINMUX_DATA_END,
  43
  44         PINMUX_FUNCTION_BEGIN,
  45         GP_ALL(FN), /* GP_0_0_FN -> GP_4_26_FN */
  46
  47         /* GPSR0 */
  48         FN_IP0_1_0,     FN_PENC0,       FN_PENC1,       FN_IP0_4_2,
  49         FN_IP0_7_5,     FN_IP0_11_8,    FN_IP0_14_12,   FN_A1,
  50         FN_A2,          FN_A3,          FN_IP0_15,      FN_IP0_16,
  51         FN_IP0_17,      FN_IP0_18,      FN_IP0_19,      FN_IP0_20,
  52         FN_IP0_21,      FN_IP0_22,      FN_IP0_23,      FN_IP0_24,
  53         FN_IP0_25,      FN_IP0_26,      FN_IP0_27,      FN_IP0_28,
  54         FN_IP0_29,      FN_IP0_30,      FN_IP1_0,       FN_IP1_1,
  55         FN_IP1_4_2,     FN_IP1_7_5,     FN_IP1_10_8,    FN_IP1_14_11,
  56
  57         /* GPSR1 */
  58         FN_IP1_23_21,   FN_WE0,         FN_IP1_24,      FN_IP1_27_25,
  59         FN_IP1_29_28,   FN_IP2_2_0,     FN_IP2_5_3,     FN_IP2_8_6,
  60         FN_IP2_11_9,    FN_IP2_13_12,   FN_IP2_16_14,   FN_IP2_17,
  61         FN_IP2_30,      FN_IP2_31,      FN_IP3_1_0,     FN_IP3_4_2,
  62         FN_IP3_7_5,     FN_IP3_9_8,     FN_IP3_12_10,   FN_IP3_15_13,
  63         FN_IP3_18_16,   FN_IP3_20_19,   FN_IP3_23_21,   FN_IP3_26_24,
  64         FN_IP3_27,      FN_IP3_28,      FN_IP3_29,      FN_IP3_30,
  65         FN_IP3_31,      FN_IP4_0,       FN_IP4_3_1,     FN_IP4_6_4,
  66
  67         /* GPSR2 */
  68         FN_IP4_7,       FN_IP4_8,       FN_IP4_10_9,    FN_IP4_12_11,
  69         FN_IP4_14_13,   FN_IP4_16_15,   FN_IP4_20_17,   FN_IP4_24_21,
  70         FN_IP4_26_25,   FN_IP4_28_27,   FN_IP4_30_29,   FN_IP5_1_0,
  71         FN_IP5_3_2,     FN_IP5_5_4,     FN_IP5_6,       FN_IP5_7,
  72         FN_IP5_9_8,     FN_IP5_11_10,   FN_IP5_12,      FN_IP5_14_13,
  73         FN_IP5_17_15,   FN_IP5_20_18,   FN_AUDIO_CLKA,  FN_AUDIO_CLKB,
  74         FN_IP5_22_21,   FN_IP5_25_23,   FN_IP5_28_26,   FN_IP5_30_29,
  75         FN_IP6_1_0,     FN_IP6_4_2,     FN_IP6_6_5,     FN_IP6_7,
  76
  77         /* GPSR3 */
  78         FN_IP6_8,       FN_IP6_9,       FN_SSI_SCK34,   FN_IP6_10,
  79         FN_IP6_12_11,   FN_IP6_13,      FN_IP6_15_14,   FN_IP6_16,
  80         FN_IP6_18_17,   FN_IP6_20_19,   FN_IP6_21,      FN_IP6_23_22,
  81         FN_IP6_25_24,   FN_IP6_27_26,   FN_IP6_29_28,   FN_IP6_31_30,
  82         FN_IP7_1_0,     FN_IP7_3_2,     FN_IP7_5_4,     FN_IP7_8_6,
  83         FN_IP7_11_9,    FN_IP7_14_12,   FN_IP7_17_15,   FN_IP7_20_18,
  84         FN_IP7_21,      FN_IP7_24_22,   FN_IP7_28_25,   FN_IP7_31_29,
  85         FN_IP8_2_0,     FN_IP8_5_3,     FN_IP8_8_6,     FN_IP8_10_9,
  86
  87         /* GPSR4 */
  88         FN_IP8_13_11,   FN_IP8_15_14,   FN_IP8_18_16,   FN_IP8_21_19,
  89         FN_IP8_23_22,   FN_IP8_26_24,   FN_IP8_29_27,   FN_IP9_2_0,
  90         FN_IP9_5_3,     FN_IP9_8_6,     FN_IP9_11_9,    FN_IP9_14_12,
  91         FN_IP9_17_15,   FN_IP9_20_18,   FN_IP9_23_21,   FN_IP9_26_24,
  92         FN_IP9_29_27,   FN_IP10_2_0,    FN_IP10_5_3,    FN_IP10_8_6,
  93         FN_IP10_12_9,   FN_IP10_15_13,  FN_IP10_18_16,  FN_IP10_21_19,
  94         FN_IP10_24_22,  FN_AVS1,        FN_AVS2,
  95
  96         /* IPSR0 */
  97         FN_PRESETOUT,   FN_PWM1,        FN_AUDATA0,     FN_ARM_TRACEDATA_0,
  98         FN_GPSCLK_C,    FN_USB_OVC0,    FN_TX2_E,       FN_SDA2_B,
  99         FN_AUDATA1,     FN_ARM_TRACEDATA_1,             FN_GPSIN_C,
 100         FN_USB_OVC1,    FN_RX2_E,       FN_SCL2_B,      FN_SD1_DAT2_A,
 101         FN_MMC_D2,      FN_BS,          FN_ATADIR0_A,   FN_SDSELF_A,
 102         FN_PWM4_B,      FN_SD1_DAT3_A,  FN_MMC_D3,      FN_A0,
 103         FN_ATAG0_A,     FN_REMOCON_B,   FN_A4,          FN_A5,
 104         FN_A6,          FN_A7,          FN_A8,          FN_A9,
 105         FN_A10,         FN_A11,         FN_A12,         FN_A13,
 106         FN_A14,         FN_A15,         FN_A16,         FN_A17,
 107         FN_A18,         FN_A19,
 108
 109         /* IPSR1 */
 110         FN_A20,         FN_HSPI_CS1_B,  FN_A21,         FN_HSPI_CLK1_B,
 111         FN_A22,         FN_HRTS0_B,     FN_RX2_B,       FN_DREQ2_A,
 112         FN_A23,         FN_HTX0_B,      FN_TX2_B,       FN_DACK2_A,
 113         FN_TS_SDEN0_A,  FN_SD1_CD_A,    FN_MMC_D6,      FN_A24,
 114         FN_DREQ1_A,     FN_HRX0_B,      FN_TS_SPSYNC0_A,
 115         FN_SD1_WP_A,    FN_MMC_D7,      FN_A25, FN_DACK1_A,
 116         FN_HCTS0_B,     FN_RX3_C,       FN_TS_SDAT0_A,  FN_CLKOUT,
 117         FN_HSPI_TX1_B,  FN_PWM0_B,      FN_CS0,         FN_HSPI_RX1_B,
 118         FN_SSI_SCK1_B,  FN_ATAG0_B,     FN_CS1_A26,     FN_SDA2_A,
 119         FN_SCK2_B,      FN_MMC_D5,      FN_ATADIR0_B,   FN_RD_WR,
 120         FN_WE1,         FN_ATAWR0_B,    FN_SSI_WS1_B,   FN_EX_CS0,
 121         FN_SCL2_A,      FN_TX3_C,       FN_TS_SCK0_A,   FN_EX_CS1,
 122         FN_MMC_D4,
 123
 124         /* IPSR2 */
 125         FN_SD1_CLK_A,   FN_MMC_CLK,     FN_ATACS00,     FN_EX_CS2,
 126         FN_SD1_CMD_A,   FN_MMC_CMD,     FN_ATACS10,     FN_EX_CS3,
 127         FN_SD1_DAT0_A,  FN_MMC_D0,      FN_ATARD0,      FN_EX_CS4,
 128         FN_EX_WAIT1_A,  FN_SD1_DAT1_A,  FN_MMC_D1,      FN_ATAWR0_A,
 129         FN_EX_CS5,      FN_EX_WAIT2_A,  FN_DREQ0_A,     FN_RX3_A,
 130         FN_DACK0,       FN_TX3_A,       FN_DRACK0,      FN_EX_WAIT0,
 131         FN_PWM0_C,      FN_D0,          FN_D1,          FN_D2,
 132         FN_D3,          FN_D4,          FN_D5,          FN_D6,
 133         FN_D7,          FN_D8,          FN_D9,          FN_D10,
 134         FN_D11,         FN_RD_WR_B,     FN_IRQ0,        FN_MLB_CLK,
 135         FN_IRQ1_A,
 136
 137         /* IPSR3 */
 138         FN_MLB_SIG,     FN_RX5_B,       FN_SDA3_A,      FN_IRQ2_A,
 139         FN_MLB_DAT,     FN_TX5_B,       FN_SCL3_A,      FN_IRQ3_A,
 140         FN_SDSELF_B,    FN_SD1_CMD_B,   FN_SCIF_CLK,    FN_AUDIO_CLKOUT_B,
 141         FN_CAN_CLK_B,   FN_SDA3_B,      FN_SD1_CLK_B,   FN_HTX0_A,
 142         FN_TX0_A,       FN_SD1_DAT0_B,  FN_HRX0_A,      FN_RX0_A,
 143         FN_SD1_DAT1_B,  FN_HSCK0,       FN_SCK0,        FN_SCL3_B,
 144         FN_SD1_DAT2_B,  FN_HCTS0_A,     FN_CTS0,        FN_SD1_DAT3_B,
 145         FN_HRTS0_A,     FN_RTS0,        FN_SSI_SCK4,    FN_DU0_DR0,
 146         FN_LCDOUT0,     FN_AUDATA2,     FN_ARM_TRACEDATA_2,
 147         FN_SDA3_C,      FN_ADICHS1,     FN_TS_SDEN0_B,  FN_SSI_WS4,
 148         FN_DU0_DR1,     FN_LCDOUT1,     FN_AUDATA3,     FN_ARM_TRACEDATA_3,
 149         FN_SCL3_C,      FN_ADICHS2,     FN_TS_SPSYNC0_B,
 150         FN_DU0_DR2,     FN_LCDOUT2,     FN_DU0_DR3,     FN_LCDOUT3,
 151         FN_DU0_DR4,     FN_LCDOUT4,     FN_DU0_DR5,     FN_LCDOUT5,
 152         FN_DU0_DR6,     FN_LCDOUT6,
 153
 154         /* IPSR4 */
 155         FN_DU0_DR7,     FN_LCDOUT7,     FN_DU0_DG0,     FN_LCDOUT8,
 156         FN_AUDATA4,     FN_ARM_TRACEDATA_4,             FN_TX1_D,
 157         FN_CAN0_TX_A,   FN_ADICHS0,     FN_DU0_DG1,     FN_LCDOUT9,
 158         FN_AUDATA5,     FN_ARM_TRACEDATA_5,             FN_RX1_D,
 159         FN_CAN0_RX_A,   FN_ADIDATA,     FN_DU0_DG2,     FN_LCDOUT10,
 160         FN_DU0_DG3,     FN_LCDOUT11,    FN_DU0_DG4,     FN_LCDOUT12,
 161         FN_RX0_B,       FN_DU0_DG5,     FN_LCDOUT13,    FN_TX0_B,
 162         FN_DU0_DG6,     FN_LCDOUT14,    FN_RX4_A,       FN_DU0_DG7,
 163         FN_LCDOUT15,    FN_TX4_A,       FN_SSI_SCK2_B,  FN_VI0_R0_B,
 164         FN_DU0_DB0,     FN_LCDOUT16,    FN_AUDATA6,     FN_ARM_TRACEDATA_6,
 165         FN_GPSCLK_A,    FN_PWM0_A,      FN_ADICLK,      FN_TS_SDAT0_B,
 166         FN_AUDIO_CLKC,  FN_VI0_R1_B,    FN_DU0_DB1,     FN_LCDOUT17,
 167         FN_AUDATA7,     FN_ARM_TRACEDATA_7,             FN_GPSIN_A,
 168         FN_ADICS_SAMP,  FN_TS_SCK0_B,   FN_VI0_R2_B,    FN_DU0_DB2,
 169         FN_LCDOUT18,    FN_VI0_R3_B,    FN_DU0_DB3,     FN_LCDOUT19,
 170         FN_VI0_R4_B,    FN_DU0_DB4,     FN_LCDOUT20,
 171
 172         /* IPSR5 */
 173         FN_VI0_R5_B,    FN_DU0_DB5,     FN_LCDOUT21,    FN_VI1_DATA10_B,
 174         FN_DU0_DB6,     FN_LCDOUT22,    FN_VI1_DATA11_B,
 175         FN_DU0_DB7,     FN_LCDOUT23,    FN_DU0_DOTCLKIN,
 176         FN_QSTVA_QVS,   FN_DU0_DOTCLKO_UT0,             FN_QCLK,
 177         FN_DU0_DOTCLKO_UT1,             FN_QSTVB_QVE,   FN_AUDIO_CLKOUT_A,
 178         FN_REMOCON_C,   FN_SSI_WS2_B,   FN_DU0_EXHSYNC_DU0_HSYNC,
 179         FN_QSTH_QHS,    FN_DU0_EXVSYNC_DU0_VSYNC,       FN_QSTB_QHE,
 180         FN_DU0_EXODDF_DU0_ODDF_DISP_CDE,
 181         FN_QCPV_QDE,    FN_FMCLK_D,     FN_SSI_SCK1_A,  FN_DU0_DISP,
 182         FN_QPOLA,       FN_AUDCK,       FN_ARM_TRACECLK,
 183         FN_BPFCLK_D,    FN_SSI_WS1_A,   FN_DU0_CDE,     FN_QPOLB,
 184         FN_AUDSYNC,     FN_ARM_TRACECTL,                FN_FMIN_D,
 185         FN_SD1_CD_B,    FN_SSI_SCK78,   FN_HSPI_RX0_B,  FN_TX1_B,
 186         FN_SD1_WP_B,    FN_SSI_WS78,    FN_HSPI_CLK0_B, FN_RX1_B,
 187         FN_CAN_CLK_D,   FN_SSI_SDATA8,  FN_SSI_SCK2_A,  FN_HSPI_CS0_B,
 188         FN_TX2_A,       FN_CAN0_TX_B,   FN_SSI_SDATA7,  FN_HSPI_TX0_B,
 189         FN_RX2_A,       FN_CAN0_RX_B,
 190
 191         /* IPSR6 */
 192         FN_SSI_SCK6,    FN_HSPI_RX2_A,  FN_FMCLK_B,     FN_CAN1_TX_B,
 193         FN_SSI_WS6,     FN_HSPI_CLK2_A, FN_BPFCLK_B,    FN_CAN1_RX_B,
 194         FN_SSI_SDATA6,  FN_HSPI_TX2_A,  FN_FMIN_B,      FN_SSI_SCK5,
 195         FN_RX4_C,       FN_SSI_WS5,     FN_TX4_C,       FN_SSI_SDATA5,
 196         FN_RX0_D,       FN_SSI_WS34,    FN_ARM_TRACEDATA_8,
 197         FN_SSI_SDATA4,  FN_SSI_WS2_A,   FN_ARM_TRACEDATA_9,
 198         FN_SSI_SDATA3,  FN_ARM_TRACEDATA_10,
 199         FN_SSI_SCK012,  FN_ARM_TRACEDATA_11,
 200         FN_TX0_D,       FN_SSI_WS012,   FN_ARM_TRACEDATA_12,
 201         FN_SSI_SDATA2,  FN_HSPI_CS2_A,  FN_ARM_TRACEDATA_13,
 202         FN_SDA1_A,      FN_SSI_SDATA1,  FN_ARM_TRACEDATA_14,
 203         FN_SCL1_A,      FN_SCK2_A,      FN_SSI_SDATA0,
 204         FN_ARM_TRACEDATA_15,
 205         FN_SD0_CLK,     FN_SUB_TDO,     FN_SD0_CMD,     FN_SUB_TRST,
 206         FN_SD0_DAT0,    FN_SUB_TMS,     FN_SD0_DAT1,    FN_SUB_TCK,
 207         FN_SD0_DAT2,    FN_SUB_TDI,
 208
 209         /* IPSR7 */
 210         FN_SD0_DAT3,    FN_IRQ1_B,      FN_SD0_CD,      FN_TX5_A,
 211         FN_SD0_WP,      FN_RX5_A,       FN_VI1_CLKENB,  FN_HSPI_CLK0_A,
 212         FN_HTX1_A,      FN_RTS1_C,      FN_VI1_FIELD,   FN_HSPI_CS0_A,
 213         FN_HRX1_A,      FN_SCK1_C,      FN_VI1_HSYNC,   FN_HSPI_RX0_A,
 214         FN_HRTS1_A,     FN_FMCLK_A,     FN_RX1_C,       FN_VI1_VSYNC,
 215         FN_HSPI_TX0,    FN_HCTS1_A,     FN_BPFCLK_A,    FN_TX1_C,
 216         FN_TCLK0,       FN_HSCK1_A,     FN_FMIN_A,      FN_IRQ2_C,
 217         FN_CTS1_C,      FN_SPEEDIN,     FN_VI0_CLK,     FN_CAN_CLK_A,
 218         FN_VI0_CLKENB,  FN_SD2_DAT2_B,  FN_VI1_DATA0,   FN_DU1_DG6,
 219         FN_HSPI_RX1_A,  FN_RX4_B,       FN_VI0_FIELD,   FN_SD2_DAT3_B,
 220         FN_VI0_R3_C,    FN_VI1_DATA1,   FN_DU1_DG7,     FN_HSPI_CLK1_A,
 221         FN_TX4_B,       FN_VI0_HSYNC,   FN_SD2_CD_B,    FN_VI1_DATA2,
 222         FN_DU1_DR2,     FN_HSPI_CS1_A,  FN_RX3_B,
 223
 224         /* IPSR8 */
 225         FN_VI0_VSYNC,   FN_SD2_WP_B,    FN_VI1_DATA3,   FN_DU1_DR3,
 226         FN_HSPI_TX1_A,  FN_TX3_B,       FN_VI0_DATA0_VI0_B0,
 227         FN_DU1_DG2,     FN_IRQ2_B,      FN_RX3_D,       FN_VI0_DATA1_VI0_B1,
 228         FN_DU1_DG3,     FN_IRQ3_B,      FN_TX3_D,       FN_VI0_DATA2_VI0_B2,
 229         FN_DU1_DG4,     FN_RX0_C,       FN_VI0_DATA3_VI0_B3,
 230         FN_DU1_DG5,     FN_TX1_A,       FN_TX0_C,       FN_VI0_DATA4_VI0_B4,
 231         FN_DU1_DB2,     FN_RX1_A,       FN_VI0_DATA5_VI0_B5,
 232         FN_DU1_DB3,     FN_SCK1_A,      FN_PWM4,        FN_HSCK1_B,
 233         FN_VI0_DATA6_VI0_G0,            FN_DU1_DB4,     FN_CTS1_A,
 234         FN_PWM5,        FN_VI0_DATA7_VI0_G1,            FN_DU1_DB5,
 235         FN_RTS1_A,      FN_VI0_G2,      FN_SD2_CLK_B,   FN_VI1_DATA4,
 236         FN_DU1_DR4,     FN_HTX1_B,      FN_VI0_G3,      FN_SD2_CMD_B,
 237         FN_VI1_DATA5,   FN_DU1_DR5,     FN_HRX1_B,
 238
 239         /* IPSR9 */
 240         FN_VI0_G4,      FN_SD2_DAT0_B,  FN_VI1_DATA6,   FN_DU1_DR6,
 241         FN_HRTS1_B,     FN_VI0_G5,      FN_SD2_DAT1_B,  FN_VI1_DATA7,
 242         FN_DU1_DR7,     FN_HCTS1_B,     FN_VI0_R0_A,    FN_VI1_CLK,
 243         FN_ETH_REF_CLK, FN_DU1_DOTCLKIN,                FN_VI0_R1_A,
 244         FN_VI1_DATA8,   FN_DU1_DB6,     FN_ETH_TXD0,    FN_PWM2,
 245         FN_TCLK1,       FN_VI0_R2_A,    FN_VI1_DATA9,   FN_DU1_DB7,
 246         FN_ETH_TXD1,    FN_PWM3,        FN_VI0_R3_A,    FN_ETH_CRS_DV,
 247         FN_IECLK,       FN_SCK2_C,      FN_VI0_R4_A,    FN_ETH_TX_EN,
 248         FN_IETX,        FN_TX2_C,       FN_VI0_R5_A,    FN_ETH_RX_ER,
 249         FN_FMCLK_C,     FN_IERX,        FN_RX2_C,       FN_VI1_DATA10_A,
 250         FN_DU1_DOTCLKOUT,               FN_ETH_RXD0,    FN_BPFCLK_C,
 251         FN_TX2_D,       FN_SDA2_C,      FN_VI1_DATA11_A,
 252         FN_DU1_EXHSYNC_DU1_HSYNC,       FN_ETH_RXD1,    FN_FMIN_C,
 253         FN_RX2_D,       FN_SCL2_C,
 254
 255         /* IPSR10 */
 256         FN_SD2_CLK_A,   FN_DU1_EXVSYNC_DU1_VSYNC,       FN_ATARD1,
 257         FN_ETH_MDC,     FN_SDA1_B,      FN_SD2_CMD_A,
 258         FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,                FN_ATAWR1,
 259         FN_ETH_MDIO,    FN_SCL1_B,      FN_SD2_DAT0_A,  FN_DU1_DISP,
 260         FN_ATACS01,     FN_DREQ1_B,     FN_ETH_LINK,    FN_CAN1_RX_A,
 261         FN_SD2_DAT1_A,  FN_DU1_CDE,     FN_ATACS11,     FN_DACK1_B,
 262         FN_ETH_MAGIC,   FN_CAN1_TX_A,   FN_PWM6,        FN_SD2_DAT2_A,
 263         FN_VI1_DATA12,  FN_DREQ2_B,     FN_ATADIR1,     FN_HSPI_CLK2_B,
 264         FN_GPSCLK_B,    FN_SD2_DAT3_A,  FN_VI1_DATA13,  FN_DACK2_B,
 265         FN_ATAG1,       FN_HSPI_CS2_B,  FN_GPSIN_B,     FN_SD2_CD_A,
 266         FN_VI1_DATA14,  FN_EX_WAIT1_B,  FN_DREQ0_B,     FN_HSPI_RX2_B,
 267         FN_REMOCON_A,   FN_SD2_WP_A,    FN_VI1_DATA15,  FN_EX_WAIT2_B,
 268         FN_DACK0_B,     FN_HSPI_TX2_B,  FN_CAN_CLK_C,
 269
 270         /* SEL */
 271         FN_SEL_SCIF5_A, FN_SEL_SCIF5_B,
 272         FN_SEL_SCIF4_A, FN_SEL_SCIF4_B, FN_SEL_SCIF4_C,
 273         FN_SEL_SCIF3_A, FN_SEL_SCIF3_B, FN_SEL_SCIF3_C, FN_SEL_SCIF3_D,
 274         FN_SEL_SCIF2_A, FN_SEL_SCIF2_B, FN_SEL_SCIF2_C, FN_SEL_SCIF2_D, FN_SEL_SCIF2_E,
 275         FN_SEL_SCIF1_A, FN_SEL_SCIF1_B, FN_SEL_SCIF1_C, FN_SEL_SCIF1_D,
 276         FN_SEL_SCIF0_A, FN_SEL_SCIF0_B, FN_SEL_SCIF0_C, FN_SEL_SCIF0_D,
 277         FN_SEL_SSI2_A,  FN_SEL_SSI2_B,
 278         FN_SEL_SSI1_A,  FN_SEL_SSI1_B,
 279         FN_SEL_VI1_A,   FN_SEL_VI1_B,
 280         FN_SEL_VI0_A,   FN_SEL_VI0_B,   FN_SEL_VI0_C,   FN_SEL_VI0_D,
 281         FN_SEL_SD2_A,   FN_SEL_SD2_B,
 282         FN_SEL_SD1_A,   FN_SEL_SD1_B,
 283         FN_SEL_IRQ3_A,  FN_SEL_IRQ3_B,
 284         FN_SEL_IRQ2_A,  FN_SEL_IRQ2_B,  FN_SEL_IRQ2_C,
 285         FN_SEL_IRQ1_A,  FN_SEL_IRQ1_B,
 286         FN_SEL_DREQ2_A, FN_SEL_DREQ2_B,
 287         FN_SEL_DREQ1_A, FN_SEL_DREQ1_B,
 288         FN_SEL_DREQ0_A, FN_SEL_DREQ0_B,
 289         FN_SEL_WAIT2_A, FN_SEL_WAIT2_B,
 290         FN_SEL_WAIT1_A, FN_SEL_WAIT1_B,
 291         FN_SEL_CAN1_A,  FN_SEL_CAN1_B,
 292         FN_SEL_CAN0_A,  FN_SEL_CAN0_B,
 293         FN_SEL_CANCLK_A,        FN_SEL_CANCLK_B,
 294         FN_SEL_CANCLK_C,        FN_SEL_CANCLK_D,
 295         FN_SEL_HSCIF1_A,        FN_SEL_HSCIF1_B,
 296         FN_SEL_HSCIF0_A,        FN_SEL_HSCIF0_B,
 297         FN_SEL_REMOCON_A,       FN_SEL_REMOCON_B,       FN_SEL_REMOCON_C,
 298         FN_SEL_FM_A,    FN_SEL_FM_B,    FN_SEL_FM_C,    FN_SEL_FM_D,
 299         FN_SEL_GPS_A,   FN_SEL_GPS_B,   FN_SEL_GPS_C,
 300         FN_SEL_TSIF0_A, FN_SEL_TSIF0_B,
 301         FN_SEL_HSPI2_A, FN_SEL_HSPI2_B,
 302         FN_SEL_HSPI1_A, FN_SEL_HSPI1_B,
 303         FN_SEL_HSPI0_A, FN_SEL_HSPI0_B,
 304         FN_SEL_I2C3_A,  FN_SEL_I2C3_B,  FN_SEL_I2C3_C,
 305         FN_SEL_I2C2_A,  FN_SEL_I2C2_B,  FN_SEL_I2C2_C,
 306         FN_SEL_I2C1_A,  FN_SEL_I2C1_B,
 307         PINMUX_FUNCTION_END,
 308
 309         PINMUX_MARK_BEGIN,
 310
 311         /* GPSR0 */
 312         PENC0_MARK,     PENC1_MARK,     A1_MARK,        A2_MARK,        A3_MARK,
 313
 314         /* GPSR1 */
 315         WE0_MARK,
 316
 317         /* GPSR2 */
 318         AUDIO_CLKA_MARK,
 319         AUDIO_CLKB_MARK,
 320
 321         /* GPSR3 */
 322         SSI_SCK34_MARK,
 323
 324         /* GPSR4 */
 325         AVS1_MARK,
 326         AVS2_MARK,
 327
 328         VI0_R0_C_MARK,          /* see sel_vi0 */
 329         VI0_R1_C_MARK,          /* see sel_vi0 */
 330         VI0_R2_C_MARK,          /* see sel_vi0 */
 331         /* VI0_R3_C_MARK, */
 332         VI0_R4_C_MARK,          /* see sel_vi0 */
 333         VI0_R5_C_MARK,          /* see sel_vi0 */
 334
 335         VI0_R0_D_MARK,          /* see sel_vi0 */
 336         VI0_R1_D_MARK,          /* see sel_vi0 */
 337         VI0_R2_D_MARK,          /* see sel_vi0 */
 338         VI0_R3_D_MARK,          /* see sel_vi0 */
 339         VI0_R4_D_MARK,          /* see sel_vi0 */
 340         VI0_R5_D_MARK,          /* see sel_vi0 */
 341
 342         /* IPSR0 */
 343         PRESETOUT_MARK, PWM1_MARK,      AUDATA0_MARK,
 344         ARM_TRACEDATA_0_MARK,           GPSCLK_C_MARK,  USB_OVC0_MARK,
 345         TX2_E_MARK,     SDA2_B_MARK,    AUDATA1_MARK,   ARM_TRACEDATA_1_MARK,
 346         GPSIN_C_MARK,   USB_OVC1_MARK,  RX2_E_MARK,     SCL2_B_MARK,
 347         SD1_DAT2_A_MARK,                MMC_D2_MARK,    BS_MARK,
 348         ATADIR0_A_MARK, SDSELF_A_MARK,  PWM4_B_MARK,    SD1_DAT3_A_MARK,
 349         MMC_D3_MARK,    A0_MARK,        ATAG0_A_MARK,   REMOCON_B_MARK,
 350         A4_MARK,        A5_MARK,        A6_MARK,        A7_MARK,
 351         A8_MARK,        A9_MARK,        A10_MARK,       A11_MARK,
 352         A12_MARK,       A13_MARK,       A14_MARK,       A15_MARK,
 353         A16_MARK,       A17_MARK,       A18_MARK,       A19_MARK,
 354
 355         /* IPSR1 */
 356         A20_MARK,       HSPI_CS1_B_MARK,                A21_MARK,
 357         HSPI_CLK1_B_MARK,               A22_MARK,       HRTS0_B_MARK,
 358         RX2_B_MARK,     DREQ2_A_MARK,   A23_MARK,       HTX0_B_MARK,
 359         TX2_B_MARK,     DACK2_A_MARK,   TS_SDEN0_A_MARK,
 360         SD1_CD_A_MARK,  MMC_D6_MARK,    A24_MARK,       DREQ1_A_MARK,
 361         HRX0_B_MARK,    TS_SPSYNC0_A_MARK,              SD1_WP_A_MARK,
 362         MMC_D7_MARK,    A25_MARK,       DACK1_A_MARK,   HCTS0_B_MARK,
 363         RX3_C_MARK,     TS_SDAT0_A_MARK,                CLKOUT_MARK,
 364         HSPI_TX1_B_MARK,                PWM0_B_MARK,    CS0_MARK,
 365         HSPI_RX1_B_MARK,                SSI_SCK1_B_MARK,
 366         ATAG0_B_MARK,   CS1_A26_MARK,   SDA2_A_MARK,    SCK2_B_MARK,
 367         MMC_D5_MARK,    ATADIR0_B_MARK, RD_WR_MARK,     WE1_MARK,
 368         ATAWR0_B_MARK,  SSI_WS1_B_MARK, EX_CS0_MARK,    SCL2_A_MARK,
 369         TX3_C_MARK,     TS_SCK0_A_MARK, EX_CS1_MARK,    MMC_D4_MARK,
 370
 371         /* IPSR2 */
 372         SD1_CLK_A_MARK, MMC_CLK_MARK,   ATACS00_MARK,   EX_CS2_MARK,
 373         SD1_CMD_A_MARK, MMC_CMD_MARK,   ATACS10_MARK,   EX_CS3_MARK,
 374         SD1_DAT0_A_MARK,                MMC_D0_MARK,    ATARD0_MARK,
 375         EX_CS4_MARK,    EX_WAIT1_A_MARK,                SD1_DAT1_A_MARK,
 376         MMC_D1_MARK,    ATAWR0_A_MARK,  EX_CS5_MARK,    EX_WAIT2_A_MARK,
 377         DREQ0_A_MARK,   RX3_A_MARK,     DACK0_MARK,     TX3_A_MARK,
 378         DRACK0_MARK,    EX_WAIT0_MARK,  PWM0_C_MARK,    D0_MARK,
 379         D1_MARK,        D2_MARK,        D3_MARK,        D4_MARK,
 380         D5_MARK,        D6_MARK,        D7_MARK,        D8_MARK,
 381         D9_MARK,        D10_MARK,       D11_MARK,       RD_WR_B_MARK,
 382         IRQ0_MARK,      MLB_CLK_MARK,   IRQ1_A_MARK,
 383
 384         /* IPSR3 */
 385         MLB_SIG_MARK,   RX5_B_MARK,     SDA3_A_MARK,    IRQ2_A_MARK,
 386         MLB_DAT_MARK,   TX5_B_MARK,     SCL3_A_MARK,    IRQ3_A_MARK,
 387         SDSELF_B_MARK,  SD1_CMD_B_MARK, SCIF_CLK_MARK,  AUDIO_CLKOUT_B_MARK,
 388         CAN_CLK_B_MARK, SDA3_B_MARK,    SD1_CLK_B_MARK, HTX0_A_MARK,
 389         TX0_A_MARK,     SD1_DAT0_B_MARK,                HRX0_A_MARK,
 390         RX0_A_MARK,     SD1_DAT1_B_MARK,                HSCK0_MARK,
 391         SCK0_MARK,      SCL3_B_MARK,    SD1_DAT2_B_MARK,
 392         HCTS0_A_MARK,   CTS0_MARK,      SD1_DAT3_B_MARK,
 393         HRTS0_A_MARK,   RTS0_MARK,      SSI_SCK4_MARK,
 394         DU0_DR0_MARK,   LCDOUT0_MARK,   AUDATA2_MARK,   ARM_TRACEDATA_2_MARK,
 395         SDA3_C_MARK,    ADICHS1_MARK,   TS_SDEN0_B_MARK,
 396         SSI_WS4_MARK,   DU0_DR1_MARK,   LCDOUT1_MARK,   AUDATA3_MARK,
 397         ARM_TRACEDATA_3_MARK,           SCL3_C_MARK,    ADICHS2_MARK,
 398         TS_SPSYNC0_B_MARK,              DU0_DR2_MARK,   LCDOUT2_MARK,
 399         DU0_DR3_MARK,   LCDOUT3_MARK,   DU0_DR4_MARK,   LCDOUT4_MARK,
 400         DU0_DR5_MARK,   LCDOUT5_MARK,   DU0_DR6_MARK,   LCDOUT6_MARK,
 401
 402         /* IPSR4 */
 403         DU0_DR7_MARK,   LCDOUT7_MARK,   DU0_DG0_MARK,   LCDOUT8_MARK,
 404         AUDATA4_MARK,   ARM_TRACEDATA_4_MARK,
 405         TX1_D_MARK,     CAN0_TX_A_MARK, ADICHS0_MARK,   DU0_DG1_MARK,
 406         LCDOUT9_MARK,   AUDATA5_MARK,   ARM_TRACEDATA_5_MARK,
 407         RX1_D_MARK,     CAN0_RX_A_MARK, ADIDATA_MARK,   DU0_DG2_MARK,
 408         LCDOUT10_MARK,  DU0_DG3_MARK,   LCDOUT11_MARK,  DU0_DG4_MARK,
 409         LCDOUT12_MARK,  RX0_B_MARK,     DU0_DG5_MARK,   LCDOUT13_MARK,
 410         TX0_B_MARK,     DU0_DG6_MARK,   LCDOUT14_MARK,  RX4_A_MARK,
 411         DU0_DG7_MARK,   LCDOUT15_MARK,  TX4_A_MARK,     SSI_SCK2_B_MARK,
 412         VI0_R0_B_MARK,  DU0_DB0_MARK,   LCDOUT16_MARK,  AUDATA6_MARK,
 413         ARM_TRACEDATA_6_MARK,           GPSCLK_A_MARK,  PWM0_A_MARK,
 414         ADICLK_MARK,    TS_SDAT0_B_MARK,                AUDIO_CLKC_MARK,
 415         VI0_R1_B_MARK,  DU0_DB1_MARK,   LCDOUT17_MARK,  AUDATA7_MARK,
 416         ARM_TRACEDATA_7_MARK,           GPSIN_A_MARK,   ADICS_SAMP_MARK,
 417         TS_SCK0_B_MARK, VI0_R2_B_MARK,  DU0_DB2_MARK,   LCDOUT18_MARK,
 418         VI0_R3_B_MARK,  DU0_DB3_MARK,   LCDOUT19_MARK,  VI0_R4_B_MARK,
 419         DU0_DB4_MARK,   LCDOUT20_MARK,
 420
 421         /* IPSR5 */
 422         VI0_R5_B_MARK,  DU0_DB5_MARK,   LCDOUT21_MARK,  VI1_DATA10_B_MARK,
 423         DU0_DB6_MARK,   LCDOUT22_MARK,  VI1_DATA11_B_MARK,
 424         DU0_DB7_MARK,   LCDOUT23_MARK,  DU0_DOTCLKIN_MARK,
 425         QSTVA_QVS_MARK, DU0_DOTCLKO_UT0_MARK,
 426         QCLK_MARK,      DU0_DOTCLKO_UT1_MARK,           QSTVB_QVE_MARK,
 427         AUDIO_CLKOUT_A_MARK,            REMOCON_C_MARK, SSI_WS2_B_MARK,
 428         DU0_EXHSYNC_DU0_HSYNC_MARK,     QSTH_QHS_MARK,
 429         DU0_EXVSYNC_DU0_VSYNC_MARK,     QSTB_QHE_MARK,
 430         DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK,
 431         QCPV_QDE_MARK,  FMCLK_D_MARK,   SSI_SCK1_A_MARK,
 432         DU0_DISP_MARK,  QPOLA_MARK,     AUDCK_MARK,     ARM_TRACECLK_MARK,
 433         BPFCLK_D_MARK,  SSI_WS1_A_MARK, DU0_CDE_MARK,   QPOLB_MARK,
 434         AUDSYNC_MARK,   ARM_TRACECTL_MARK,              FMIN_D_MARK,
 435         SD1_CD_B_MARK,  SSI_SCK78_MARK, HSPI_RX0_B_MARK,
 436         TX1_B_MARK,     SD1_WP_B_MARK,  SSI_WS78_MARK,  HSPI_CLK0_B_MARK,
 437         RX1_B_MARK,     CAN_CLK_D_MARK, SSI_SDATA8_MARK,
 438         SSI_SCK2_A_MARK,                HSPI_CS0_B_MARK,
 439         TX2_A_MARK,     CAN0_TX_B_MARK, SSI_SDATA7_MARK,
 440         HSPI_TX0_B_MARK,                RX2_A_MARK,     CAN0_RX_B_MARK,
 441
 442         /* IPSR6 */
 443         SSI_SCK6_MARK,  HSPI_RX2_A_MARK,                FMCLK_B_MARK,
 444         CAN1_TX_B_MARK, SSI_WS6_MARK,   HSPI_CLK2_A_MARK,
 445         BPFCLK_B_MARK,  CAN1_RX_B_MARK, SSI_SDATA6_MARK,
 446         HSPI_TX2_A_MARK,                FMIN_B_MARK,    SSI_SCK5_MARK,
 447         RX4_C_MARK,     SSI_WS5_MARK,   TX4_C_MARK,     SSI_SDATA5_MARK,
 448         RX0_D_MARK,     SSI_WS34_MARK,  ARM_TRACEDATA_8_MARK,
 449         SSI_SDATA4_MARK,                SSI_WS2_A_MARK, ARM_TRACEDATA_9_MARK,
 450         SSI_SDATA3_MARK,                ARM_TRACEDATA_10_MARK,
 451         SSI_SCK012_MARK,                ARM_TRACEDATA_11_MARK,
 452         TX0_D_MARK,     SSI_WS012_MARK, ARM_TRACEDATA_12_MARK,
 453         SSI_SDATA2_MARK,                HSPI_CS2_A_MARK,
 454         ARM_TRACEDATA_13_MARK,          SDA1_A_MARK,    SSI_SDATA1_MARK,
 455         ARM_TRACEDATA_14_MARK,          SCL1_A_MARK,    SCK2_A_MARK,
 456         SSI_SDATA0_MARK,                ARM_TRACEDATA_15_MARK,
 457         SD0_CLK_MARK,   SUB_TDO_MARK,   SD0_CMD_MARK,   SUB_TRST_MARK,
 458         SD0_DAT0_MARK,  SUB_TMS_MARK,   SD0_DAT1_MARK,  SUB_TCK_MARK,
 459         SD0_DAT2_MARK,  SUB_TDI_MARK,
 460
 461         /* IPSR7 */
 462         SD0_DAT3_MARK,  IRQ1_B_MARK,    SD0_CD_MARK,    TX5_A_MARK,
 463         SD0_WP_MARK,    RX5_A_MARK,     VI1_CLKENB_MARK,
 464         HSPI_CLK0_A_MARK,       HTX1_A_MARK,    RTS1_C_MARK,    VI1_FIELD_MARK,
 465         HSPI_CS0_A_MARK,        HRX1_A_MARK,    SCK1_C_MARK,    VI1_HSYNC_MARK,
 466         HSPI_RX0_A_MARK,        HRTS1_A_MARK,   FMCLK_A_MARK,   RX1_C_MARK,
 467         VI1_VSYNC_MARK, HSPI_TX0_MARK,  HCTS1_A_MARK,   BPFCLK_A_MARK,
 468         TX1_C_MARK,     TCLK0_MARK,     HSCK1_A_MARK,   FMIN_A_MARK,
 469         IRQ2_C_MARK,    CTS1_C_MARK,    SPEEDIN_MARK,   VI0_CLK_MARK,
 470         CAN_CLK_A_MARK, VI0_CLKENB_MARK,                SD2_DAT2_B_MARK,
 471         VI1_DATA0_MARK, DU1_DG6_MARK,   HSPI_RX1_A_MARK,
 472         RX4_B_MARK,     VI0_FIELD_MARK, SD2_DAT3_B_MARK,
 473         VI0_R3_C_MARK,  VI1_DATA1_MARK, DU1_DG7_MARK,   HSPI_CLK1_A_MARK,
 474         TX4_B_MARK,     VI0_HSYNC_MARK, SD2_CD_B_MARK,  VI1_DATA2_MARK,
 475         DU1_DR2_MARK,   HSPI_CS1_A_MARK,                RX3_B_MARK,
 476
 477         /* IPSR8 */
 478         VI0_VSYNC_MARK, SD2_WP_B_MARK,  VI1_DATA3_MARK, DU1_DR3_MARK,
 479         HSPI_TX1_A_MARK,                TX3_B_MARK,     VI0_DATA0_VI0_B0_MARK,
 480         DU1_DG2_MARK,   IRQ2_B_MARK,    RX3_D_MARK,     VI0_DATA1_VI0_B1_MARK,
 481         DU1_DG3_MARK,   IRQ3_B_MARK,    TX3_D_MARK,     VI0_DATA2_VI0_B2_MARK,
 482         DU1_DG4_MARK,   RX0_C_MARK,     VI0_DATA3_VI0_B3_MARK,
 483         DU1_DG5_MARK,   TX1_A_MARK,     TX0_C_MARK,     VI0_DATA4_VI0_B4_MARK,
 484         DU1_DB2_MARK,   RX1_A_MARK,     VI0_DATA5_VI0_B5_MARK,
 485         DU1_DB3_MARK,   SCK1_A_MARK,    PWM4_MARK,      HSCK1_B_MARK,
 486         VI0_DATA6_VI0_G0_MARK,          DU1_DB4_MARK,   CTS1_A_MARK,
 487         PWM5_MARK,      VI0_DATA7_VI0_G1_MARK,          DU1_DB5_MARK,
 488         RTS1_A_MARK,    VI0_G2_MARK,    SD2_CLK_B_MARK, VI1_DATA4_MARK,
 489         DU1_DR4_MARK,   HTX1_B_MARK,    VI0_G3_MARK,    SD2_CMD_B_MARK,
 490         VI1_DATA5_MARK, DU1_DR5_MARK,   HRX1_B_MARK,
 491
 492         /* IPSR9 */
 493         VI0_G4_MARK,    SD2_DAT0_B_MARK,                VI1_DATA6_MARK,
 494         DU1_DR6_MARK,   HRTS1_B_MARK,   VI0_G5_MARK,    SD2_DAT1_B_MARK,
 495         VI1_DATA7_MARK, DU1_DR7_MARK,   HCTS1_B_MARK,   VI0_R0_A_MARK,
 496         VI1_CLK_MARK,   ETH_REF_CLK_MARK,               DU1_DOTCLKIN_MARK,
 497         VI0_R1_A_MARK,  VI1_DATA8_MARK, DU1_DB6_MARK,   ETH_TXD0_MARK,
 498         PWM2_MARK,      TCLK1_MARK,     VI0_R2_A_MARK,  VI1_DATA9_MARK,
 499         DU1_DB7_MARK,   ETH_TXD1_MARK,  PWM3_MARK,      VI0_R3_A_MARK,
 500         ETH_CRS_DV_MARK,                IECLK_MARK,     SCK2_C_MARK,
 501         VI0_R4_A_MARK,                  ETH_TX_EN_MARK, IETX_MARK,
 502         TX2_C_MARK,     VI0_R5_A_MARK,  ETH_RX_ER_MARK, FMCLK_C_MARK,
 503         IERX_MARK,      RX2_C_MARK,     VI1_DATA10_A_MARK,
 504         DU1_DOTCLKOUT_MARK,             ETH_RXD0_MARK,
 505         BPFCLK_C_MARK,  TX2_D_MARK,     SDA2_C_MARK,    VI1_DATA11_A_MARK,
 506         DU1_EXHSYNC_DU1_HSYNC_MARK,     ETH_RXD1_MARK,  FMIN_C_MARK,
 507         RX2_D_MARK,     SCL2_C_MARK,
 508
 509         /* IPSR10 */
 510         SD2_CLK_A_MARK, DU1_EXVSYNC_DU1_VSYNC_MARK,     ATARD1_MARK,
 511         ETH_MDC_MARK,   SDA1_B_MARK,    SD2_CMD_A_MARK,
 512         DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,              ATAWR1_MARK,
 513         ETH_MDIO_MARK,  SCL1_B_MARK,    SD2_DAT0_A_MARK,
 514         DU1_DISP_MARK,  ATACS01_MARK,   DREQ1_B_MARK,   ETH_LINK_MARK,
 515         CAN1_RX_A_MARK, SD2_DAT1_A_MARK,                DU1_CDE_MARK,
 516         ATACS11_MARK,   DACK1_B_MARK,   ETH_MAGIC_MARK, CAN1_TX_A_MARK,
 517         PWM6_MARK,      SD2_DAT2_A_MARK,                VI1_DATA12_MARK,
 518         DREQ2_B_MARK,   ATADIR1_MARK,   HSPI_CLK2_B_MARK,
 519         GPSCLK_B_MARK,  SD2_DAT3_A_MARK,                VI1_DATA13_MARK,
 520         DACK2_B_MARK,   ATAG1_MARK,     HSPI_CS2_B_MARK,
 521         GPSIN_B_MARK,   SD2_CD_A_MARK,  VI1_DATA14_MARK,
 522         EX_WAIT1_B_MARK,                DREQ0_B_MARK,   HSPI_RX2_B_MARK,
 523         REMOCON_A_MARK, SD2_WP_A_MARK,  VI1_DATA15_MARK,
 524         EX_WAIT2_B_MARK,                DACK0_B_MARK,
 525         HSPI_TX2_B_MARK,                CAN_CLK_C_MARK,
 526
 527         PINMUX_MARK_END,
 528 };
 529
 530 static const u16 pinmux_data[] = {
 531         PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
 532
 533         PINMUX_SINGLE(PENC0),
 534         PINMUX_SINGLE(PENC1),
 535         PINMUX_SINGLE(A1),
 536         PINMUX_SINGLE(A2),
 537         PINMUX_SINGLE(A3),
 538         PINMUX_SINGLE(WE0),
 539         PINMUX_SINGLE(AUDIO_CLKA),
 540         PINMUX_SINGLE(AUDIO_CLKB),
 541         PINMUX_SINGLE(SSI_SCK34),
 542         PINMUX_SINGLE(AVS1),
 543         PINMUX_SINGLE(AVS2),
 544
 545         /* IPSR0 */
 546         PINMUX_IPSR_GPSR(IP0_1_0,       PRESETOUT),
 547         PINMUX_IPSR_GPSR(IP0_1_0,       PWM1),
 548
 549         PINMUX_IPSR_GPSR(IP0_4_2,       AUDATA0),
 550         PINMUX_IPSR_GPSR(IP0_4_2,       ARM_TRACEDATA_0),
 551         PINMUX_IPSR_MSEL(IP0_4_2,       GPSCLK_C,       SEL_GPS_C),
 552         PINMUX_IPSR_GPSR(IP0_4_2,       USB_OVC0),
 553         PINMUX_IPSR_GPSR(IP0_4_2,       TX2_E),
 554         PINMUX_IPSR_MSEL(IP0_4_2,       SDA2_B,         SEL_I2C2_B),
 555
 556         PINMUX_IPSR_GPSR(IP0_7_5,       AUDATA1),
 557         PINMUX_IPSR_GPSR(IP0_7_5,       ARM_TRACEDATA_1),
 558         PINMUX_IPSR_MSEL(IP0_7_5,       GPSIN_C,        SEL_GPS_C),
 559         PINMUX_IPSR_GPSR(IP0_7_5,       USB_OVC1),
 560         PINMUX_IPSR_MSEL(IP0_7_5,       RX2_E,          SEL_SCIF2_E),
 561         PINMUX_IPSR_MSEL(IP0_7_5,       SCL2_B,         SEL_I2C2_B),
 562
 563         PINMUX_IPSR_MSEL(IP0_11_8,      SD1_DAT2_A,     SEL_SD1_A),
 564         PINMUX_IPSR_GPSR(IP0_11_8,      MMC_D2),
 565         PINMUX_IPSR_GPSR(IP0_11_8,      BS),
 566         PINMUX_IPSR_GPSR(IP0_11_8,      ATADIR0_A),
 567         PINMUX_IPSR_GPSR(IP0_11_8,      SDSELF_A),
 568         PINMUX_IPSR_GPSR(IP0_11_8,      PWM4_B),
 569
 570         PINMUX_IPSR_MSEL(IP0_14_12,     SD1_DAT3_A,     SEL_SD1_A),
 571         PINMUX_IPSR_GPSR(IP0_14_12,     MMC_D3),
 572         PINMUX_IPSR_GPSR(IP0_14_12,     A0),
 573         PINMUX_IPSR_GPSR(IP0_14_12,     ATAG0_A),
 574         PINMUX_IPSR_MSEL(IP0_14_12,     REMOCON_B,      SEL_REMOCON_B),
 575
 576         PINMUX_IPSR_GPSR(IP0_15,        A4),
 577         PINMUX_IPSR_GPSR(IP0_16,        A5),
 578         PINMUX_IPSR_GPSR(IP0_17,        A6),
 579         PINMUX_IPSR_GPSR(IP0_18,        A7),
 580         PINMUX_IPSR_GPSR(IP0_19,        A8),
 581         PINMUX_IPSR_GPSR(IP0_20,        A9),
 582         PINMUX_IPSR_GPSR(IP0_21,        A10),
 583         PINMUX_IPSR_GPSR(IP0_22,        A11),
 584         PINMUX_IPSR_GPSR(IP0_23,        A12),
 585         PINMUX_IPSR_GPSR(IP0_24,        A13),
 586         PINMUX_IPSR_GPSR(IP0_25,        A14),
 587         PINMUX_IPSR_GPSR(IP0_26,        A15),
 588         PINMUX_IPSR_GPSR(IP0_27,        A16),
 589         PINMUX_IPSR_GPSR(IP0_28,        A17),
 590         PINMUX_IPSR_GPSR(IP0_29,        A18),
 591         PINMUX_IPSR_GPSR(IP0_30,        A19),
 592
 593         /* IPSR1 */
 594         PINMUX_IPSR_GPSR(IP1_0,         A20),
 595         PINMUX_IPSR_MSEL(IP1_0,         HSPI_CS1_B,     SEL_HSPI1_B),
 596
 597         PINMUX_IPSR_GPSR(IP1_1,         A21),
 598         PINMUX_IPSR_MSEL(IP1_1,         HSPI_CLK1_B,    SEL_HSPI1_B),
 599
 600         PINMUX_IPSR_GPSR(IP1_4_2,       A22),
 601         PINMUX_IPSR_MSEL(IP1_4_2,       HRTS0_B,        SEL_HSCIF0_B),
 602         PINMUX_IPSR_MSEL(IP1_4_2,       RX2_B,          SEL_SCIF2_B),
 603         PINMUX_IPSR_MSEL(IP1_4_2,       DREQ2_A,        SEL_DREQ2_A),
 604
 605         PINMUX_IPSR_GPSR(IP1_7_5,       A23),
 606         PINMUX_IPSR_GPSR(IP1_7_5,       HTX0_B),
 607         PINMUX_IPSR_GPSR(IP1_7_5,       TX2_B),
 608         PINMUX_IPSR_GPSR(IP1_7_5,       DACK2_A),
 609         PINMUX_IPSR_MSEL(IP1_7_5,       TS_SDEN0_A,     SEL_TSIF0_A),
 610
 611         PINMUX_IPSR_MSEL(IP1_10_8,      SD1_CD_A,       SEL_SD1_A),
 612         PINMUX_IPSR_GPSR(IP1_10_8,      MMC_D6),
 613         PINMUX_IPSR_GPSR(IP1_10_8,      A24),
 614         PINMUX_IPSR_MSEL(IP1_10_8,      DREQ1_A,        SEL_DREQ1_A),
 615         PINMUX_IPSR_MSEL(IP1_10_8,      HRX0_B,         SEL_HSCIF0_B),
 616         PINMUX_IPSR_MSEL(IP1_10_8,      TS_SPSYNC0_A,   SEL_TSIF0_A),
 617
 618         PINMUX_IPSR_MSEL(IP1_14_11,     SD1_WP_A,       SEL_SD1_A),
 619         PINMUX_IPSR_GPSR(IP1_14_11,     MMC_D7),
 620         PINMUX_IPSR_GPSR(IP1_14_11,     A25),
 621         PINMUX_IPSR_GPSR(IP1_14_11,     DACK1_A),
 622         PINMUX_IPSR_MSEL(IP1_14_11,     HCTS0_B,        SEL_HSCIF0_B),
 623         PINMUX_IPSR_MSEL(IP1_14_11,     RX3_C,          SEL_SCIF3_C),
 624         PINMUX_IPSR_MSEL(IP1_14_11,     TS_SDAT0_A,     SEL_TSIF0_A),
 625
 626         PINMUX_IPSR_NOGP(IP1_16_15,     CLKOUT),
 627         PINMUX_IPSR_NOGP(IP1_16_15,     HSPI_TX1_B),
 628         PINMUX_IPSR_NOGP(IP1_16_15,     PWM0_B),
 629
 630         PINMUX_IPSR_NOGP(IP1_17,        CS0),
 631         PINMUX_IPSR_NOGM(IP1_17,        HSPI_RX1_B,     SEL_HSPI1_B),
 632
 633         PINMUX_IPSR_NOGM(IP1_20_18,     SSI_SCK1_B,     SEL_SSI1_B),
 634         PINMUX_IPSR_NOGP(IP1_20_18,     ATAG0_B),
 635         PINMUX_IPSR_NOGP(IP1_20_18,     CS1_A26),
 636         PINMUX_IPSR_NOGM(IP1_20_18,     SDA2_A,         SEL_I2C2_A),
 637         PINMUX_IPSR_NOGM(IP1_20_18,     SCK2_B,         SEL_SCIF2_B),
 638
 639         PINMUX_IPSR_GPSR(IP1_23_21,     MMC_D5),
 640         PINMUX_IPSR_GPSR(IP1_23_21,     ATADIR0_B),
 641         PINMUX_IPSR_GPSR(IP1_23_21,     RD_WR),
 642
 643         PINMUX_IPSR_GPSR(IP1_24,        WE1),
 644         PINMUX_IPSR_GPSR(IP1_24,        ATAWR0_B),
 645
 646         PINMUX_IPSR_MSEL(IP1_27_25,     SSI_WS1_B,      SEL_SSI1_B),
 647         PINMUX_IPSR_GPSR(IP1_27_25,     EX_CS0),
 648         PINMUX_IPSR_MSEL(IP1_27_25,     SCL2_A,         SEL_I2C2_A),
 649         PINMUX_IPSR_GPSR(IP1_27_25,     TX3_C),
 650         PINMUX_IPSR_MSEL(IP1_27_25,     TS_SCK0_A,      SEL_TSIF0_A),
 651
 652         PINMUX_IPSR_GPSR(IP1_29_28,     EX_CS1),
 653         PINMUX_IPSR_GPSR(IP1_29_28,     MMC_D4),
 654
 655         /* IPSR2 */
 656         PINMUX_IPSR_GPSR(IP2_2_0,       SD1_CLK_A),
 657         PINMUX_IPSR_GPSR(IP2_2_0,       MMC_CLK),
 658         PINMUX_IPSR_GPSR(IP2_2_0,       ATACS00),
 659         PINMUX_IPSR_GPSR(IP2_2_0,       EX_CS2),
 660
 661         PINMUX_IPSR_MSEL(IP2_5_3,       SD1_CMD_A,      SEL_SD1_A),
 662         PINMUX_IPSR_GPSR(IP2_5_3,       MMC_CMD),
 663         PINMUX_IPSR_GPSR(IP2_5_3,       ATACS10),
 664         PINMUX_IPSR_GPSR(IP2_5_3,       EX_CS3),
 665
 666         PINMUX_IPSR_MSEL(IP2_8_6,       SD1_DAT0_A,     SEL_SD1_A),
 667         PINMUX_IPSR_GPSR(IP2_8_6,       MMC_D0),
 668         PINMUX_IPSR_GPSR(IP2_8_6,       ATARD0),
 669         PINMUX_IPSR_GPSR(IP2_8_6,       EX_CS4),
 670         PINMUX_IPSR_MSEL(IP2_8_6,       EX_WAIT1_A,     SEL_WAIT1_A),
 671
 672         PINMUX_IPSR_MSEL(IP2_11_9,      SD1_DAT1_A,     SEL_SD1_A),
 673         PINMUX_IPSR_GPSR(IP2_11_9,      MMC_D1),
 674         PINMUX_IPSR_GPSR(IP2_11_9,      ATAWR0_A),
 675         PINMUX_IPSR_GPSR(IP2_11_9,      EX_CS5),
 676         PINMUX_IPSR_MSEL(IP2_11_9,      EX_WAIT2_A,     SEL_WAIT2_A),
 677
 678         PINMUX_IPSR_MSEL(IP2_13_12,     DREQ0_A,        SEL_DREQ0_A),
 679         PINMUX_IPSR_MSEL(IP2_13_12,     RX3_A,          SEL_SCIF3_A),
 680
 681         PINMUX_IPSR_GPSR(IP2_16_14,     DACK0),
 682         PINMUX_IPSR_GPSR(IP2_16_14,     TX3_A),
 683         PINMUX_IPSR_GPSR(IP2_16_14,     DRACK0),
 684
 685         PINMUX_IPSR_GPSR(IP2_17,        EX_WAIT0),
 686         PINMUX_IPSR_GPSR(IP2_17,        PWM0_C),
 687
 688         PINMUX_IPSR_NOGP(IP2_18,        D0),
 689         PINMUX_IPSR_NOGP(IP2_19,        D1),
 690         PINMUX_IPSR_NOGP(IP2_20,        D2),
 691         PINMUX_IPSR_NOGP(IP2_21,        D3),
 692         PINMUX_IPSR_NOGP(IP2_22,        D4),
 693         PINMUX_IPSR_NOGP(IP2_23,        D5),
 694         PINMUX_IPSR_NOGP(IP2_24,        D6),
 695         PINMUX_IPSR_NOGP(IP2_25,        D7),
 696         PINMUX_IPSR_NOGP(IP2_26,        D8),
 697         PINMUX_IPSR_NOGP(IP2_27,        D9),
 698         PINMUX_IPSR_NOGP(IP2_28,        D10),
 699         PINMUX_IPSR_NOGP(IP2_29,        D11),
 700
 701         PINMUX_IPSR_GPSR(IP2_30,        RD_WR_B),
 702         PINMUX_IPSR_GPSR(IP2_30,        IRQ0),
 703
 704         PINMUX_IPSR_GPSR(IP2_31,        MLB_CLK),
 705         PINMUX_IPSR_MSEL(IP2_31,        IRQ1_A,         SEL_IRQ1_A),
 706
 707         /* IPSR3 */
 708         PINMUX_IPSR_GPSR(IP3_1_0,       MLB_SIG),
 709         PINMUX_IPSR_MSEL(IP3_1_0,       RX5_B,          SEL_SCIF5_B),
 710         PINMUX_IPSR_MSEL(IP3_1_0,       SDA3_A,         SEL_I2C3_A),
 711         PINMUX_IPSR_MSEL(IP3_1_0,       IRQ2_A,         SEL_IRQ2_A),
 712
 713         PINMUX_IPSR_GPSR(IP3_4_2,       MLB_DAT),
 714         PINMUX_IPSR_GPSR(IP3_4_2,       TX5_B),
 715         PINMUX_IPSR_MSEL(IP3_4_2,       SCL3_A,         SEL_I2C3_A),
 716         PINMUX_IPSR_MSEL(IP3_4_2,       IRQ3_A,         SEL_IRQ3_A),
 717         PINMUX_IPSR_GPSR(IP3_4_2,       SDSELF_B),
 718
 719         PINMUX_IPSR_MSEL(IP3_7_5,       SD1_CMD_B,      SEL_SD1_B),
 720         PINMUX_IPSR_GPSR(IP3_7_5,       SCIF_CLK),
 721         PINMUX_IPSR_GPSR(IP3_7_5,       AUDIO_CLKOUT_B),
 722         PINMUX_IPSR_MSEL(IP3_7_5,       CAN_CLK_B,      SEL_CANCLK_B),
 723         PINMUX_IPSR_MSEL(IP3_7_5,       SDA3_B,         SEL_I2C3_B),
 724
 725         PINMUX_IPSR_GPSR(IP3_9_8,       SD1_CLK_B),
 726         PINMUX_IPSR_GPSR(IP3_9_8,       HTX0_A),
 727         PINMUX_IPSR_GPSR(IP3_9_8,       TX0_A),
 728
 729         PINMUX_IPSR_MSEL(IP3_12_10,     SD1_DAT0_B,     SEL_SD1_B),
 730         PINMUX_IPSR_MSEL(IP3_12_10,     HRX0_A,         SEL_HSCIF0_A),
 731         PINMUX_IPSR_MSEL(IP3_12_10,     RX0_A,          SEL_SCIF0_A),
 732
 733         PINMUX_IPSR_MSEL(IP3_15_13,     SD1_DAT1_B,     SEL_SD1_B),
 734         PINMUX_IPSR_MSEL(IP3_15_13,     HSCK0,          SEL_HSCIF0_A),
 735         PINMUX_IPSR_GPSR(IP3_15_13,     SCK0),
 736         PINMUX_IPSR_MSEL(IP3_15_13,     SCL3_B,         SEL_I2C3_B),
 737
 738         PINMUX_IPSR_MSEL(IP3_18_16,     SD1_DAT2_B,     SEL_SD1_B),
 739         PINMUX_IPSR_MSEL(IP3_18_16,     HCTS0_A,        SEL_HSCIF0_A),
 740         PINMUX_IPSR_GPSR(IP3_18_16,     CTS0),
 741
 742         PINMUX_IPSR_MSEL(IP3_20_19,     SD1_DAT3_B,     SEL_SD1_B),
 743         PINMUX_IPSR_MSEL(IP3_20_19,     HRTS0_A,        SEL_HSCIF0_A),
 744         PINMUX_IPSR_GPSR(IP3_20_19,     RTS0),
 745
 746         PINMUX_IPSR_GPSR(IP3_23_21,     SSI_SCK4),
 747         PINMUX_IPSR_GPSR(IP3_23_21,     DU0_DR0),
 748         PINMUX_IPSR_GPSR(IP3_23_21,     LCDOUT0),
 749         PINMUX_IPSR_GPSR(IP3_23_21,     AUDATA2),
 750         PINMUX_IPSR_GPSR(IP3_23_21,     ARM_TRACEDATA_2),
 751         PINMUX_IPSR_MSEL(IP3_23_21,     SDA3_C,         SEL_I2C3_C),
 752         PINMUX_IPSR_GPSR(IP3_23_21,     ADICHS1),
 753         PINMUX_IPSR_MSEL(IP3_23_21,     TS_SDEN0_B,     SEL_TSIF0_B),
 754
 755         PINMUX_IPSR_GPSR(IP3_26_24,     SSI_WS4),
 756         PINMUX_IPSR_GPSR(IP3_26_24,     DU0_DR1),
 757         PINMUX_IPSR_GPSR(IP3_26_24,     LCDOUT1),
 758         PINMUX_IPSR_GPSR(IP3_26_24,     AUDATA3),
 759         PINMUX_IPSR_GPSR(IP3_26_24,     ARM_TRACEDATA_3),
 760         PINMUX_IPSR_MSEL(IP3_26_24,     SCL3_C,         SEL_I2C3_C),
 761         PINMUX_IPSR_GPSR(IP3_26_24,     ADICHS2),
 762         PINMUX_IPSR_MSEL(IP3_26_24,     TS_SPSYNC0_B,   SEL_TSIF0_B),
 763
 764         PINMUX_IPSR_GPSR(IP3_27,        DU0_DR2),
 765         PINMUX_IPSR_GPSR(IP3_27,        LCDOUT2),
 766
 767         PINMUX_IPSR_GPSR(IP3_28,        DU0_DR3),
 768         PINMUX_IPSR_GPSR(IP3_28,        LCDOUT3),
 769
 770         PINMUX_IPSR_GPSR(IP3_29,        DU0_DR4),
 771         PINMUX_IPSR_GPSR(IP3_29,        LCDOUT4),
 772
 773         PINMUX_IPSR_GPSR(IP3_30,        DU0_DR5),
 774         PINMUX_IPSR_GPSR(IP3_30,        LCDOUT5),
 775
 776         PINMUX_IPSR_GPSR(IP3_31,        DU0_DR6),
 777         PINMUX_IPSR_GPSR(IP3_31,        LCDOUT6),
 778
 779         /* IPSR4 */
 780         PINMUX_IPSR_GPSR(IP4_0,         DU0_DR7),
 781         PINMUX_IPSR_GPSR(IP4_0,         LCDOUT7),
 782
 783         PINMUX_IPSR_GPSR(IP4_3_1,       DU0_DG0),
 784         PINMUX_IPSR_GPSR(IP4_3_1,       LCDOUT8),
 785         PINMUX_IPSR_GPSR(IP4_3_1,       AUDATA4),
 786         PINMUX_IPSR_GPSR(IP4_3_1,       ARM_TRACEDATA_4),
 787         PINMUX_IPSR_GPSR(IP4_3_1,       TX1_D),
 788         PINMUX_IPSR_GPSR(IP4_3_1,       CAN0_TX_A),
 789         PINMUX_IPSR_GPSR(IP4_3_1,       ADICHS0),
 790
 791         PINMUX_IPSR_GPSR(IP4_6_4,       DU0_DG1),
 792         PINMUX_IPSR_GPSR(IP4_6_4,       LCDOUT9),
 793         PINMUX_IPSR_GPSR(IP4_6_4,       AUDATA5),
 794         PINMUX_IPSR_GPSR(IP4_6_4,       ARM_TRACEDATA_5),
 795         PINMUX_IPSR_MSEL(IP4_6_4,       RX1_D,          SEL_SCIF1_D),
 796         PINMUX_IPSR_MSEL(IP4_6_4,       CAN0_RX_A,      SEL_CAN0_A),
 797         PINMUX_IPSR_GPSR(IP4_6_4,       ADIDATA),
 798
 799         PINMUX_IPSR_GPSR(IP4_7,         DU0_DG2),
 800         PINMUX_IPSR_GPSR(IP4_7,         LCDOUT10),
 801
 802         PINMUX_IPSR_GPSR(IP4_8,         DU0_DG3),
 803         PINMUX_IPSR_GPSR(IP4_8,         LCDOUT11),
 804
 805         PINMUX_IPSR_GPSR(IP4_10_9,      DU0_DG4),
 806         PINMUX_IPSR_GPSR(IP4_10_9,      LCDOUT12),
 807         PINMUX_IPSR_MSEL(IP4_10_9,      RX0_B,          SEL_SCIF0_B),
 808
 809         PINMUX_IPSR_GPSR(IP4_12_11,     DU0_DG5),
 810         PINMUX_IPSR_GPSR(IP4_12_11,     LCDOUT13),
 811         PINMUX_IPSR_GPSR(IP4_12_11,     TX0_B),
 812
 813         PINMUX_IPSR_GPSR(IP4_14_13,     DU0_DG6),
 814         PINMUX_IPSR_GPSR(IP4_14_13,     LCDOUT14),
 815         PINMUX_IPSR_MSEL(IP4_14_13,     RX4_A,          SEL_SCIF4_A),
 816
 817         PINMUX_IPSR_GPSR(IP4_16_15,     DU0_DG7),
 818         PINMUX_IPSR_GPSR(IP4_16_15,     LCDOUT15),
 819         PINMUX_IPSR_GPSR(IP4_16_15,     TX4_A),
 820
 821         PINMUX_IPSR_MSEL(IP4_20_17,     SSI_SCK2_B,     SEL_SSI2_B),
 822         PINMUX_DATA(VI0_R0_B_MARK,      FN_IP4_20_17,   FN_VI0_R0_B,    FN_SEL_VI0_B), /* see sel_vi0 */
 823         PINMUX_DATA(VI0_R0_D_MARK,      FN_IP4_20_17,   FN_VI0_R0_B,    FN_SEL_VI0_D), /* see sel_vi0 */
 824         PINMUX_IPSR_GPSR(IP4_20_17,     DU0_DB0),
 825         PINMUX_IPSR_GPSR(IP4_20_17,     LCDOUT16),
 826         PINMUX_IPSR_GPSR(IP4_20_17,     AUDATA6),
 827         PINMUX_IPSR_GPSR(IP4_20_17,     ARM_TRACEDATA_6),
 828         PINMUX_IPSR_MSEL(IP4_20_17,     GPSCLK_A,       SEL_GPS_A),
 829         PINMUX_IPSR_GPSR(IP4_20_17,     PWM0_A),
 830         PINMUX_IPSR_GPSR(IP4_20_17,     ADICLK),
 831         PINMUX_IPSR_MSEL(IP4_20_17,     TS_SDAT0_B,     SEL_TSIF0_B),
 832
 833         PINMUX_IPSR_GPSR(IP4_24_21,     AUDIO_CLKC),
 834         PINMUX_DATA(VI0_R1_B_MARK,      FN_IP4_24_21,   FN_VI0_R1_B,    FN_SEL_VI0_B), /* see sel_vi0 */
 835         PINMUX_DATA(VI0_R1_D_MARK,      FN_IP4_24_21,   FN_VI0_R1_B,    FN_SEL_VI0_D), /* see sel_vi0 */
 836         PINMUX_IPSR_GPSR(IP4_24_21,     DU0_DB1),
 837         PINMUX_IPSR_GPSR(IP4_24_21,     LCDOUT17),
 838         PINMUX_IPSR_GPSR(IP4_24_21,     AUDATA7),
 839         PINMUX_IPSR_GPSR(IP4_24_21,     ARM_TRACEDATA_7),
 840         PINMUX_IPSR_MSEL(IP4_24_21,     GPSIN_A,        SEL_GPS_A),
 841         PINMUX_IPSR_GPSR(IP4_24_21,     ADICS_SAMP),
 842         PINMUX_IPSR_MSEL(IP4_24_21,     TS_SCK0_B,      SEL_TSIF0_B),
 843
 844         PINMUX_DATA(VI0_R2_B_MARK,      FN_IP4_26_25,   FN_VI0_R2_B,    FN_SEL_VI0_B), /* see sel_vi0 */
 845         PINMUX_DATA(VI0_R2_D_MARK,      FN_IP4_26_25,   FN_VI0_R2_B,    FN_SEL_VI0_D), /* see sel_vi0 */
 846         PINMUX_IPSR_GPSR(IP4_26_25,     DU0_DB2),
 847         PINMUX_IPSR_GPSR(IP4_26_25,     LCDOUT18),
 848
 849         PINMUX_IPSR_MSEL(IP4_28_27,     VI0_R3_B,       SEL_VI0_B),
 850         PINMUX_IPSR_GPSR(IP4_28_27,     DU0_DB3),
 851         PINMUX_IPSR_GPSR(IP4_28_27,     LCDOUT19),
 852
 853         PINMUX_DATA(VI0_R4_B_MARK,      FN_IP4_30_29,   FN_VI0_R4_B,    FN_SEL_VI0_B), /* see sel_vi0 */
 854         PINMUX_DATA(VI0_R4_D_MARK,      FN_IP4_30_29,   FN_VI0_R4_B,    FN_SEL_VI0_D), /* see sel_vi0 */
 855         PINMUX_IPSR_GPSR(IP4_30_29,     DU0_DB4),
 856         PINMUX_IPSR_GPSR(IP4_30_29,     LCDOUT20),
 857
 858         /* IPSR5 */
 859         PINMUX_DATA(VI0_R5_B_MARK,      FN_IP5_1_0,     FN_VI0_R5_B,    FN_SEL_VI0_B), /* see sel_vi0 */
 860         PINMUX_DATA(VI0_R5_D_MARK,      FN_IP5_1_0,     FN_VI0_R5_B,    FN_SEL_VI0_D), /* see sel_vi0 */
 861         PINMUX_IPSR_GPSR(IP5_1_0,       DU0_DB5),
 862         PINMUX_IPSR_GPSR(IP5_1_0,       LCDOUT21),
 863
 864         PINMUX_IPSR_MSEL(IP5_3_2,       VI1_DATA10_B,   SEL_VI1_B),
 865         PINMUX_IPSR_GPSR(IP5_3_2,       DU0_DB6),
 866         PINMUX_IPSR_GPSR(IP5_3_2,       LCDOUT22),
 867
 868         PINMUX_IPSR_MSEL(IP5_5_4,       VI1_DATA11_B,   SEL_VI1_B),
 869         PINMUX_IPSR_GPSR(IP5_5_4,       DU0_DB7),
 870         PINMUX_IPSR_GPSR(IP5_5_4,       LCDOUT23),
 871
 872         PINMUX_IPSR_GPSR(IP5_6,         DU0_DOTCLKIN),
 873         PINMUX_IPSR_GPSR(IP5_6,         QSTVA_QVS),
 874
 875         PINMUX_IPSR_GPSR(IP5_7,         DU0_DOTCLKO_UT0),
 876         PINMUX_IPSR_GPSR(IP5_7,         QCLK),
 877
 878         PINMUX_IPSR_GPSR(IP5_9_8,       DU0_DOTCLKO_UT1),
 879         PINMUX_IPSR_GPSR(IP5_9_8,       QSTVB_QVE),
 880         PINMUX_IPSR_GPSR(IP5_9_8,       AUDIO_CLKOUT_A),
 881         PINMUX_IPSR_MSEL(IP5_9_8,       REMOCON_C,      SEL_REMOCON_C),
 882
 883         PINMUX_IPSR_MSEL(IP5_11_10,     SSI_WS2_B,      SEL_SSI2_B),
 884         PINMUX_IPSR_GPSR(IP5_11_10,     DU0_EXHSYNC_DU0_HSYNC),
 885         PINMUX_IPSR_GPSR(IP5_11_10,     QSTH_QHS),
 886
 887         PINMUX_IPSR_GPSR(IP5_12,        DU0_EXVSYNC_DU0_VSYNC),
 888         PINMUX_IPSR_GPSR(IP5_12,        QSTB_QHE),
 889
 890         PINMUX_IPSR_GPSR(IP5_14_13,     DU0_EXODDF_DU0_ODDF_DISP_CDE),
 891         PINMUX_IPSR_GPSR(IP5_14_13,     QCPV_QDE),
 892         PINMUX_IPSR_MSEL(IP5_14_13,     FMCLK_D,        SEL_FM_D),
 893
 894         PINMUX_IPSR_MSEL(IP5_17_15,     SSI_SCK1_A,     SEL_SSI1_A),
 895         PINMUX_IPSR_GPSR(IP5_17_15,     DU0_DISP),
 896         PINMUX_IPSR_GPSR(IP5_17_15,     QPOLA),
 897         PINMUX_IPSR_GPSR(IP5_17_15,     AUDCK),
 898         PINMUX_IPSR_GPSR(IP5_17_15,     ARM_TRACECLK),
 899         PINMUX_IPSR_GPSR(IP5_17_15,     BPFCLK_D),
 900
 901         PINMUX_IPSR_MSEL(IP5_20_18,     SSI_WS1_A,      SEL_SSI1_A),
 902         PINMUX_IPSR_GPSR(IP5_20_18,     DU0_CDE),
 903         PINMUX_IPSR_GPSR(IP5_20_18,     QPOLB),
 904         PINMUX_IPSR_GPSR(IP5_20_18,     AUDSYNC),
 905         PINMUX_IPSR_GPSR(IP5_20_18,     ARM_TRACECTL),
 906         PINMUX_IPSR_MSEL(IP5_20_18,     FMIN_D,         SEL_FM_D),
 907
 908         PINMUX_IPSR_MSEL(IP5_22_21,     SD1_CD_B,       SEL_SD1_B),
 909         PINMUX_IPSR_GPSR(IP5_22_21,     SSI_SCK78),
 910         PINMUX_IPSR_MSEL(IP5_22_21,     HSPI_RX0_B,     SEL_HSPI0_B),
 911         PINMUX_IPSR_GPSR(IP5_22_21,     TX1_B),
 912
 913         PINMUX_IPSR_MSEL(IP5_25_23,     SD1_WP_B,       SEL_SD1_B),
 914         PINMUX_IPSR_GPSR(IP5_25_23,     SSI_WS78),
 915         PINMUX_IPSR_MSEL(IP5_25_23,     HSPI_CLK0_B,    SEL_HSPI0_B),
 916         PINMUX_IPSR_MSEL(IP5_25_23,     RX1_B,          SEL_SCIF1_B),
 917         PINMUX_IPSR_MSEL(IP5_25_23,     CAN_CLK_D,      SEL_CANCLK_D),
 918
 919         PINMUX_IPSR_GPSR(IP5_28_26,     SSI_SDATA8),
 920         PINMUX_IPSR_MSEL(IP5_28_26,     SSI_SCK2_A,     SEL_SSI2_A),
 921         PINMUX_IPSR_MSEL(IP5_28_26,     HSPI_CS0_B,     SEL_HSPI0_B),
 922         PINMUX_IPSR_GPSR(IP5_28_26,     TX2_A),
 923         PINMUX_IPSR_GPSR(IP5_28_26,     CAN0_TX_B),
 924
 925         PINMUX_IPSR_GPSR(IP5_30_29,     SSI_SDATA7),
 926         PINMUX_IPSR_GPSR(IP5_30_29,     HSPI_TX0_B),
 927         PINMUX_IPSR_MSEL(IP5_30_29,     RX2_A,          SEL_SCIF2_A),
 928         PINMUX_IPSR_MSEL(IP5_30_29,     CAN0_RX_B,      SEL_CAN0_B),
 929
 930         /* IPSR6 */
 931         PINMUX_IPSR_GPSR(IP6_1_0,       SSI_SCK6),
 932         PINMUX_IPSR_MSEL(IP6_1_0,       HSPI_RX2_A,     SEL_HSPI2_A),
 933         PINMUX_IPSR_MSEL(IP6_1_0,       FMCLK_B,        SEL_FM_B),
 934         PINMUX_IPSR_GPSR(IP6_1_0,       CAN1_TX_B),
 935
 936         PINMUX_IPSR_GPSR(IP6_4_2,       SSI_WS6),
 937         PINMUX_IPSR_MSEL(IP6_4_2,       HSPI_CLK2_A,    SEL_HSPI2_A),
 938         PINMUX_IPSR_GPSR(IP6_4_2,       BPFCLK_B),
 939         PINMUX_IPSR_MSEL(IP6_4_2,       CAN1_RX_B,      SEL_CAN1_B),
 940
 941         PINMUX_IPSR_GPSR(IP6_6_5,       SSI_SDATA6),
 942         PINMUX_IPSR_GPSR(IP6_6_5,       HSPI_TX2_A),
 943         PINMUX_IPSR_MSEL(IP6_6_5,       FMIN_B,         SEL_FM_B),
 944
 945         PINMUX_IPSR_GPSR(IP6_7,         SSI_SCK5),
 946         PINMUX_IPSR_MSEL(IP6_7,         RX4_C,          SEL_SCIF4_C),
 947
 948         PINMUX_IPSR_GPSR(IP6_8,         SSI_WS5),
 949         PINMUX_IPSR_GPSR(IP6_8,         TX4_C),
 950
 951         PINMUX_IPSR_GPSR(IP6_9,         SSI_SDATA5),
 952         PINMUX_IPSR_MSEL(IP6_9,         RX0_D,          SEL_SCIF0_D),
 953
 954         PINMUX_IPSR_GPSR(IP6_10,        SSI_WS34),
 955         PINMUX_IPSR_GPSR(IP6_10,        ARM_TRACEDATA_8),
 956
 957         PINMUX_IPSR_GPSR(IP6_12_11,     SSI_SDATA4),
 958         PINMUX_IPSR_MSEL(IP6_12_11,     SSI_WS2_A,      SEL_SSI2_A),
 959         PINMUX_IPSR_GPSR(IP6_12_11,     ARM_TRACEDATA_9),
 960
 961         PINMUX_IPSR_GPSR(IP6_13,        SSI_SDATA3),
 962         PINMUX_IPSR_GPSR(IP6_13,        ARM_TRACEDATA_10),
 963
 964         PINMUX_IPSR_GPSR(IP6_15_14,     SSI_SCK012),
 965         PINMUX_IPSR_GPSR(IP6_15_14,     ARM_TRACEDATA_11),
 966         PINMUX_IPSR_GPSR(IP6_15_14,     TX0_D),
 967
 968         PINMUX_IPSR_GPSR(IP6_16,        SSI_WS012),
 969         PINMUX_IPSR_GPSR(IP6_16,        ARM_TRACEDATA_12),
 970
 971         PINMUX_IPSR_GPSR(IP6_18_17,     SSI_SDATA2),
 972         PINMUX_IPSR_MSEL(IP6_18_17,     HSPI_CS2_A,     SEL_HSPI2_A),
 973         PINMUX_IPSR_GPSR(IP6_18_17,     ARM_TRACEDATA_13),
 974         PINMUX_IPSR_MSEL(IP6_18_17,     SDA1_A,         SEL_I2C1_A),
 975
 976         PINMUX_IPSR_GPSR(IP6_20_19,     SSI_SDATA1),
 977         PINMUX_IPSR_GPSR(IP6_20_19,     ARM_TRACEDATA_14),
 978         PINMUX_IPSR_MSEL(IP6_20_19,     SCL1_A,         SEL_I2C1_A),
 979         PINMUX_IPSR_MSEL(IP6_20_19,     SCK2_A,         SEL_SCIF2_A),
 980
 981         PINMUX_IPSR_GPSR(IP6_21,        SSI_SDATA0),
 982         PINMUX_IPSR_GPSR(IP6_21,        ARM_TRACEDATA_15),
 983
 984         PINMUX_IPSR_GPSR(IP6_23_22,     SD0_CLK),
 985         PINMUX_IPSR_GPSR(IP6_23_22,     SUB_TDO),
 986
 987         PINMUX_IPSR_GPSR(IP6_25_24,     SD0_CMD),
 988         PINMUX_IPSR_GPSR(IP6_25_24,     SUB_TRST),
 989
 990         PINMUX_IPSR_GPSR(IP6_27_26,     SD0_DAT0),
 991         PINMUX_IPSR_GPSR(IP6_27_26,     SUB_TMS),
 992
 993         PINMUX_IPSR_GPSR(IP6_29_28,     SD0_DAT1),
 994         PINMUX_IPSR_GPSR(IP6_29_28,     SUB_TCK),
 995
 996         PINMUX_IPSR_GPSR(IP6_31_30,     SD0_DAT2),
 997         PINMUX_IPSR_GPSR(IP6_31_30,     SUB_TDI),
 998
 999         /* IPSR7 */
1000         PINMUX_IPSR_GPSR(IP7_1_0,       SD0_DAT3),
1001         PINMUX_IPSR_MSEL(IP7_1_0,       IRQ1_B,         SEL_IRQ1_B),
1002
1003         PINMUX_IPSR_GPSR(IP7_3_2,       SD0_CD),
1004         PINMUX_IPSR_GPSR(IP7_3_2,       TX5_A),
1005
1006         PINMUX_IPSR_GPSR(IP7_5_4,       SD0_WP),
1007         PINMUX_IPSR_MSEL(IP7_5_4,       RX5_A,          SEL_SCIF5_A),
1008
1009         PINMUX_IPSR_GPSR(IP7_8_6,       VI1_CLKENB),
1010         PINMUX_IPSR_MSEL(IP7_8_6,       HSPI_CLK0_A,    SEL_HSPI0_A),
1011         PINMUX_IPSR_GPSR(IP7_8_6,       HTX1_A),
1012         PINMUX_IPSR_MSEL(IP7_8_6,       RTS1_C,         SEL_SCIF1_C),
1013
1014         PINMUX_IPSR_GPSR(IP7_11_9,      VI1_FIELD),
1015         PINMUX_IPSR_MSEL(IP7_11_9,      HSPI_CS0_A,     SEL_HSPI0_A),
1016         PINMUX_IPSR_MSEL(IP7_11_9,      HRX1_A,         SEL_HSCIF1_A),
1017         PINMUX_IPSR_MSEL(IP7_11_9,      SCK1_C,         SEL_SCIF1_C),
1018
1019         PINMUX_IPSR_GPSR(IP7_14_12,     VI1_HSYNC),
1020         PINMUX_IPSR_MSEL(IP7_14_12,     HSPI_RX0_A,     SEL_HSPI0_A),
1021         PINMUX_IPSR_MSEL(IP7_14_12,     HRTS1_A,        SEL_HSCIF1_A),
1022         PINMUX_IPSR_MSEL(IP7_14_12,     FMCLK_A,        SEL_FM_A),
1023         PINMUX_IPSR_MSEL(IP7_14_12,     RX1_C,          SEL_SCIF1_C),
1024
1025         PINMUX_IPSR_GPSR(IP7_17_15,     VI1_VSYNC),
1026         PINMUX_IPSR_GPSR(IP7_17_15,     HSPI_TX0),
1027         PINMUX_IPSR_MSEL(IP7_17_15,     HCTS1_A,        SEL_HSCIF1_A),
1028         PINMUX_IPSR_GPSR(IP7_17_15,     BPFCLK_A),
1029         PINMUX_IPSR_GPSR(IP7_17_15,     TX1_C),
1030
1031         PINMUX_IPSR_GPSR(IP7_20_18,     TCLK0),
1032         PINMUX_IPSR_MSEL(IP7_20_18,     HSCK1_A,        SEL_HSCIF1_A),
1033         PINMUX_IPSR_MSEL(IP7_20_18,     FMIN_A,         SEL_FM_A),
1034         PINMUX_IPSR_MSEL(IP7_20_18,     IRQ2_C,         SEL_IRQ2_C),
1035         PINMUX_IPSR_MSEL(IP7_20_18,     CTS1_C,         SEL_SCIF1_C),
1036         PINMUX_IPSR_GPSR(IP7_20_18,     SPEEDIN),
1037
1038         PINMUX_IPSR_GPSR(IP7_21,        VI0_CLK),
1039         PINMUX_IPSR_MSEL(IP7_21,        CAN_CLK_A,      SEL_CANCLK_A),
1040
1041         PINMUX_IPSR_GPSR(IP7_24_22,     VI0_CLKENB),
1042         PINMUX_IPSR_MSEL(IP7_24_22,     SD2_DAT2_B,     SEL_SD2_B),
1043         PINMUX_IPSR_GPSR(IP7_24_22,     VI1_DATA0),
1044         PINMUX_IPSR_GPSR(IP7_24_22,     DU1_DG6),
1045         PINMUX_IPSR_MSEL(IP7_24_22,     HSPI_RX1_A,     SEL_HSPI1_A),
1046         PINMUX_IPSR_MSEL(IP7_24_22,     RX4_B,          SEL_SCIF4_B),
1047
1048         PINMUX_IPSR_GPSR(IP7_28_25,     VI0_FIELD),
1049         PINMUX_IPSR_MSEL(IP7_28_25,     SD2_DAT3_B,     SEL_SD2_B),
1050         PINMUX_DATA(VI0_R3_C_MARK,      FN_IP7_28_25,   FN_VI0_R3_C,    FN_SEL_VI0_C), /* see sel_vi0 */
1051         PINMUX_DATA(VI0_R3_D_MARK,      FN_IP7_28_25,   FN_VI0_R3_C,    FN_SEL_VI0_D), /* see sel_vi0 */
1052         PINMUX_IPSR_GPSR(IP7_28_25,     VI1_DATA1),
1053         PINMUX_IPSR_GPSR(IP7_28_25,     DU1_DG7),
1054         PINMUX_IPSR_MSEL(IP7_28_25,     HSPI_CLK1_A,    SEL_HSPI1_A),
1055         PINMUX_IPSR_GPSR(IP7_28_25,     TX4_B),
1056
1057         PINMUX_IPSR_GPSR(IP7_31_29,     VI0_HSYNC),
1058         PINMUX_IPSR_MSEL(IP7_31_29,     SD2_CD_B,       SEL_SD2_B),
1059         PINMUX_IPSR_GPSR(IP7_31_29,     VI1_DATA2),
1060         PINMUX_IPSR_GPSR(IP7_31_29,     DU1_DR2),
1061         PINMUX_IPSR_MSEL(IP7_31_29,     HSPI_CS1_A,     SEL_HSPI1_A),
1062         PINMUX_IPSR_MSEL(IP7_31_29,     RX3_B,          SEL_SCIF3_B),
1063
1064         /* IPSR8 */
1065         PINMUX_IPSR_GPSR(IP8_2_0,       VI0_VSYNC),
1066         PINMUX_IPSR_MSEL(IP8_2_0,       SD2_WP_B,       SEL_SD2_B),
1067         PINMUX_IPSR_GPSR(IP8_2_0,       VI1_DATA3),
1068         PINMUX_IPSR_GPSR(IP8_2_0,       DU1_DR3),
1069         PINMUX_IPSR_GPSR(IP8_2_0,       HSPI_TX1_A),
1070         PINMUX_IPSR_GPSR(IP8_2_0,       TX3_B),
1071
1072         PINMUX_IPSR_GPSR(IP8_5_3,       VI0_DATA0_VI0_B0),
1073         PINMUX_IPSR_GPSR(IP8_5_3,       DU1_DG2),
1074         PINMUX_IPSR_MSEL(IP8_5_3,       IRQ2_B,         SEL_IRQ2_B),
1075         PINMUX_IPSR_MSEL(IP8_5_3,       RX3_D,          SEL_SCIF3_D),
1076
1077         PINMUX_IPSR_GPSR(IP8_8_6,       VI0_DATA1_VI0_B1),
1078         PINMUX_IPSR_GPSR(IP8_8_6,       DU1_DG3),
1079         PINMUX_IPSR_MSEL(IP8_8_6,       IRQ3_B,         SEL_IRQ3_B),
1080         PINMUX_IPSR_GPSR(IP8_8_6,       TX3_D),
1081
1082         PINMUX_IPSR_GPSR(IP8_10_9,      VI0_DATA2_VI0_B2),
1083         PINMUX_IPSR_GPSR(IP8_10_9,      DU1_DG4),
1084         PINMUX_IPSR_MSEL(IP8_10_9,      RX0_C,          SEL_SCIF0_C),
1085
1086         PINMUX_IPSR_GPSR(IP8_13_11,     VI0_DATA3_VI0_B3),
1087         PINMUX_IPSR_GPSR(IP8_13_11,     DU1_DG5),
1088         PINMUX_IPSR_GPSR(IP8_13_11,     TX1_A),
1089         PINMUX_IPSR_GPSR(IP8_13_11,     TX0_C),
1090
1091         PINMUX_IPSR_GPSR(IP8_15_14,     VI0_DATA4_VI0_B4),
1092         PINMUX_IPSR_GPSR(IP8_15_14,     DU1_DB2),
1093         PINMUX_IPSR_MSEL(IP8_15_14,     RX1_A,          SEL_SCIF1_A),
1094
1095         PINMUX_IPSR_GPSR(IP8_18_16,     VI0_DATA5_VI0_B5),
1096         PINMUX_IPSR_GPSR(IP8_18_16,     DU1_DB3),
1097         PINMUX_IPSR_MSEL(IP8_18_16,     SCK1_A,         SEL_SCIF1_A),
1098         PINMUX_IPSR_GPSR(IP8_18_16,     PWM4),
1099         PINMUX_IPSR_MSEL(IP8_18_16,     HSCK1_B,        SEL_HSCIF1_B),
1100
1101         PINMUX_IPSR_GPSR(IP8_21_19,     VI0_DATA6_VI0_G0),
1102         PINMUX_IPSR_GPSR(IP8_21_19,     DU1_DB4),
1103         PINMUX_IPSR_MSEL(IP8_21_19,     CTS1_A,         SEL_SCIF1_A),
1104         PINMUX_IPSR_GPSR(IP8_21_19,     PWM5),
1105
1106         PINMUX_IPSR_GPSR(IP8_23_22,     VI0_DATA7_VI0_G1),
1107         PINMUX_IPSR_GPSR(IP8_23_22,     DU1_DB5),
1108         PINMUX_IPSR_MSEL(IP8_23_22,     RTS1_A,         SEL_SCIF1_A),
1109
1110         PINMUX_IPSR_GPSR(IP8_26_24,     VI0_G2),
1111         PINMUX_IPSR_GPSR(IP8_26_24,     SD2_CLK_B),
1112         PINMUX_IPSR_GPSR(IP8_26_24,     VI1_DATA4),
1113         PINMUX_IPSR_GPSR(IP8_26_24,     DU1_DR4),
1114         PINMUX_IPSR_GPSR(IP8_26_24,     HTX1_B),
1115
1116         PINMUX_IPSR_GPSR(IP8_29_27,     VI0_G3),
1117         PINMUX_IPSR_MSEL(IP8_29_27,     SD2_CMD_B,      SEL_SD2_B),
1118         PINMUX_IPSR_GPSR(IP8_29_27,     VI1_DATA5),
1119         PINMUX_IPSR_GPSR(IP8_29_27,     DU1_DR5),
1120         PINMUX_IPSR_MSEL(IP8_29_27,     HRX1_B,         SEL_HSCIF1_B),
1121
1122         /* IPSR9 */
1123         PINMUX_IPSR_GPSR(IP9_2_0,       VI0_G4),
1124         PINMUX_IPSR_MSEL(IP9_2_0,       SD2_DAT0_B,     SEL_SD2_B),
1125         PINMUX_IPSR_GPSR(IP9_2_0,       VI1_DATA6),
1126         PINMUX_IPSR_GPSR(IP9_2_0,       DU1_DR6),
1127         PINMUX_IPSR_MSEL(IP9_2_0,       HRTS1_B,        SEL_HSCIF1_B),
1128
1129         PINMUX_IPSR_GPSR(IP9_5_3,       VI0_G5),
1130         PINMUX_IPSR_MSEL(IP9_5_3,       SD2_DAT1_B,     SEL_SD2_B),
1131         PINMUX_IPSR_GPSR(IP9_5_3,       VI1_DATA7),
1132         PINMUX_IPSR_GPSR(IP9_5_3,       DU1_DR7),
1133         PINMUX_IPSR_MSEL(IP9_5_3,       HCTS1_B,        SEL_HSCIF1_B),
1134
1135         PINMUX_DATA(VI0_R0_A_MARK,      FN_IP9_8_6,     FN_VI0_R0_A,    FN_SEL_VI0_A), /* see sel_vi0 */
1136         PINMUX_DATA(VI0_R0_C_MARK,      FN_IP9_8_6,     FN_VI0_R0_A,    FN_SEL_VI0_C), /* see sel_vi0 */
1137         PINMUX_IPSR_GPSR(IP9_8_6,       VI1_CLK),
1138         PINMUX_IPSR_GPSR(IP9_8_6,       ETH_REF_CLK),
1139         PINMUX_IPSR_GPSR(IP9_8_6,       DU1_DOTCLKIN),
1140
1141         PINMUX_DATA(VI0_R1_A_MARK,      FN_IP9_11_9,    FN_VI0_R1_A,    FN_SEL_VI0_A), /* see sel_vi0 */
1142         PINMUX_DATA(VI0_R1_C_MARK,      FN_IP9_11_9,    FN_VI0_R1_A,    FN_SEL_VI0_C), /* see sel_vi0 */
1143         PINMUX_IPSR_GPSR(IP9_11_9,      VI1_DATA8),
1144         PINMUX_IPSR_GPSR(IP9_11_9,      DU1_DB6),
1145         PINMUX_IPSR_GPSR(IP9_11_9,      ETH_TXD0),
1146         PINMUX_IPSR_GPSR(IP9_11_9,      PWM2),
1147         PINMUX_IPSR_GPSR(IP9_11_9,      TCLK1),
1148
1149         PINMUX_DATA(VI0_R2_A_MARK,      FN_IP9_14_12,   FN_VI0_R2_A,    FN_SEL_VI0_A), /* see sel_vi0 */
1150         PINMUX_DATA(VI0_R2_C_MARK,      FN_IP9_14_12,   FN_VI0_R2_A,    FN_SEL_VI0_C), /* see sel_vi0 */
1151         PINMUX_IPSR_GPSR(IP9_14_12,     VI1_DATA9),
1152         PINMUX_IPSR_GPSR(IP9_14_12,     DU1_DB7),
1153         PINMUX_IPSR_GPSR(IP9_14_12,     ETH_TXD1),
1154         PINMUX_IPSR_GPSR(IP9_14_12,     PWM3),
1155
1156         PINMUX_IPSR_MSEL(IP9_17_15,     VI0_R3_A,       SEL_VI0_A),
1157         PINMUX_IPSR_GPSR(IP9_17_15,     ETH_CRS_DV),
1158         PINMUX_IPSR_GPSR(IP9_17_15,     IECLK),
1159         PINMUX_IPSR_MSEL(IP9_17_15,     SCK2_C,         SEL_SCIF2_C),
1160
1161         PINMUX_DATA(VI0_R4_A_MARK,      FN_IP9_20_18,   FN_VI0_R4_A,    FN_SEL_VI0_A), /* see sel_vi0 */
1162         PINMUX_DATA(VI0_R3_C_MARK,      FN_IP9_20_18,   FN_VI0_R4_A,    FN_SEL_VI0_C), /* see sel_vi0 */
1163         PINMUX_IPSR_GPSR(IP9_20_18,     ETH_TX_EN),
1164         PINMUX_IPSR_GPSR(IP9_20_18,     IETX),
1165         PINMUX_IPSR_GPSR(IP9_20_18,     TX2_C),
1166
1167         PINMUX_DATA(VI0_R5_A_MARK,      FN_IP9_23_21,   FN_VI0_R5_A,    FN_SEL_VI0_A), /* see sel_vi0 */
1168         PINMUX_DATA(VI0_R5_C_MARK,      FN_IP9_23_21,   FN_VI0_R5_A,    FN_SEL_VI0_C), /* see sel_vi0 */
1169         PINMUX_IPSR_GPSR(IP9_23_21,     ETH_RX_ER),
1170         PINMUX_IPSR_MSEL(IP9_23_21,     FMCLK_C,        SEL_FM_C),
1171         PINMUX_IPSR_GPSR(IP9_23_21,     IERX),
1172         PINMUX_IPSR_MSEL(IP9_23_21,     RX2_C,          SEL_SCIF2_C),
1173
1174         PINMUX_IPSR_MSEL(IP9_26_24,     VI1_DATA10_A,   SEL_VI1_A),
1175         PINMUX_IPSR_GPSR(IP9_26_24,     DU1_DOTCLKOUT),
1176         PINMUX_IPSR_GPSR(IP9_26_24,     ETH_RXD0),
1177         PINMUX_IPSR_GPSR(IP9_26_24,     BPFCLK_C),
1178         PINMUX_IPSR_GPSR(IP9_26_24,     TX2_D),
1179         PINMUX_IPSR_MSEL(IP9_26_24,     SDA2_C,         SEL_I2C2_C),
1180
1181         PINMUX_IPSR_MSEL(IP9_29_27,     VI1_DATA11_A,   SEL_VI1_A),
1182         PINMUX_IPSR_GPSR(IP9_29_27,     DU1_EXHSYNC_DU1_HSYNC),
1183         PINMUX_IPSR_GPSR(IP9_29_27,     ETH_RXD1),
1184         PINMUX_IPSR_MSEL(IP9_29_27,     FMIN_C,         SEL_FM_C),
1185         PINMUX_IPSR_MSEL(IP9_29_27,     RX2_D,          SEL_SCIF2_D),
1186         PINMUX_IPSR_MSEL(IP9_29_27,     SCL2_C,         SEL_I2C2_C),
1187
1188         /* IPSR10 */
1189         PINMUX_IPSR_GPSR(IP10_2_0,      SD2_CLK_A),
1190         PINMUX_IPSR_GPSR(IP10_2_0,      DU1_EXVSYNC_DU1_VSYNC),
1191         PINMUX_IPSR_GPSR(IP10_2_0,      ATARD1),
1192         PINMUX_IPSR_GPSR(IP10_2_0,      ETH_MDC),
1193         PINMUX_IPSR_MSEL(IP10_2_0,      SDA1_B,         SEL_I2C1_B),
1194
1195         PINMUX_IPSR_MSEL(IP10_5_3,      SD2_CMD_A,      SEL_SD2_A),
1196         PINMUX_IPSR_GPSR(IP10_5_3,      DU1_EXODDF_DU1_ODDF_DISP_CDE),
1197         PINMUX_IPSR_GPSR(IP10_5_3,      ATAWR1),
1198         PINMUX_IPSR_GPSR(IP10_5_3,      ETH_MDIO),
1199         PINMUX_IPSR_MSEL(IP10_5_3,      SCL1_B,         SEL_I2C1_B),
1200
1201         PINMUX_IPSR_MSEL(IP10_8_6,      SD2_DAT0_A,     SEL_SD2_A),
1202         PINMUX_IPSR_GPSR(IP10_8_6,      DU1_DISP),
1203         PINMUX_IPSR_GPSR(IP10_8_6,      ATACS01),
1204         PINMUX_IPSR_MSEL(IP10_8_6,      DREQ1_B,        SEL_DREQ1_B),
1205         PINMUX_IPSR_GPSR(IP10_8_6,      ETH_LINK),
1206         PINMUX_IPSR_MSEL(IP10_8_6,      CAN1_RX_A,      SEL_CAN1_A),
1207
1208         PINMUX_IPSR_MSEL(IP10_12_9,     SD2_DAT1_A,     SEL_SD2_A),
1209         PINMUX_IPSR_GPSR(IP10_12_9,     DU1_CDE),
1210         PINMUX_IPSR_GPSR(IP10_12_9,     ATACS11),
1211         PINMUX_IPSR_GPSR(IP10_12_9,     DACK1_B),
1212         PINMUX_IPSR_GPSR(IP10_12_9,     ETH_MAGIC),
1213         PINMUX_IPSR_GPSR(IP10_12_9,     CAN1_TX_A),
1214         PINMUX_IPSR_GPSR(IP10_12_9,     PWM6),
1215
1216         PINMUX_IPSR_MSEL(IP10_15_13,    SD2_DAT2_A,     SEL_SD2_A),
1217         PINMUX_IPSR_GPSR(IP10_15_13,    VI1_DATA12),
1218         PINMUX_IPSR_MSEL(IP10_15_13,    DREQ2_B,        SEL_DREQ2_B),
1219         PINMUX_IPSR_GPSR(IP10_15_13,    ATADIR1),
1220         PINMUX_IPSR_MSEL(IP10_15_13,    HSPI_CLK2_B,    SEL_HSPI2_B),
1221         PINMUX_IPSR_MSEL(IP10_15_13,    GPSCLK_B,       SEL_GPS_B),
1222
1223         PINMUX_IPSR_MSEL(IP10_18_16,    SD2_DAT3_A,     SEL_SD2_A),
1224         PINMUX_IPSR_GPSR(IP10_18_16,    VI1_DATA13),
1225         PINMUX_IPSR_GPSR(IP10_18_16,    DACK2_B),
1226         PINMUX_IPSR_GPSR(IP10_18_16,    ATAG1),
1227         PINMUX_IPSR_MSEL(IP10_18_16,    HSPI_CS2_B,     SEL_HSPI2_B),
1228         PINMUX_IPSR_MSEL(IP10_18_16,    GPSIN_B,        SEL_GPS_B),
1229
1230         PINMUX_IPSR_MSEL(IP10_21_19,    SD2_CD_A,       SEL_SD2_A),
1231         PINMUX_IPSR_GPSR(IP10_21_19,    VI1_DATA14),
1232         PINMUX_IPSR_MSEL(IP10_21_19,    EX_WAIT1_B,     SEL_WAIT1_B),
1233         PINMUX_IPSR_MSEL(IP10_21_19,    DREQ0_B,        SEL_DREQ0_B),
1234         PINMUX_IPSR_MSEL(IP10_21_19,    HSPI_RX2_B,     SEL_HSPI2_B),
1235         PINMUX_IPSR_MSEL(IP10_21_19,    REMOCON_A,      SEL_REMOCON_A),
1236
1237         PINMUX_IPSR_MSEL(IP10_24_22,    SD2_WP_A,       SEL_SD2_A),
1238         PINMUX_IPSR_GPSR(IP10_24_22,    VI1_DATA15),
1239         PINMUX_IPSR_MSEL(IP10_24_22,    EX_WAIT2_B,     SEL_WAIT2_B),
1240         PINMUX_IPSR_GPSR(IP10_24_22,    DACK0_B),
1241         PINMUX_IPSR_GPSR(IP10_24_22,    HSPI_TX2_B),
1242         PINMUX_IPSR_MSEL(IP10_24_22,    CAN_CLK_C,      SEL_CANCLK_C),
1243 };
1244
1245 /*
1246  * Pins not associated with a GPIO port.
1247  */
1248 enum {
1249         GP_ASSIGN_LAST(),
1250         NOGP_ALL(),
1251 };
1252
1253 static const struct sh_pfc_pin pinmux_pins[] = {
1254         PINMUX_GPIO_GP_ALL(),
1255         PINMUX_NOGP_ALL(),
1256 };
1257
1258 /* - macro */
1259 #define SH_PFC_PINS(name, args...) \
1260         static const unsigned int name ##_pins[] = { args }
1261 #define SH_PFC_MUX1(name, arg1)                                 \
1262         static const unsigned int name ##_mux[]  = { arg1##_MARK }
1263 #define SH_PFC_MUX2(name, arg1, arg2)                                   \
1264         static const unsigned int name ##_mux[]  = { arg1##_MARK, arg2##_MARK, }
1265 #define SH_PFC_MUX3(name, arg1, arg2, arg3)                                     \
1266         static const unsigned int name ##_mux[]  = { arg1##_MARK, arg2##_MARK,  \
1267                                                      arg3##_MARK }
1268 #define SH_PFC_MUX4(name, arg1, arg2, arg3, arg4)                       \
1269         static const unsigned int name ##_mux[]  = { arg1##_MARK, arg2##_MARK, \
1270                                                      arg3##_MARK, arg4##_MARK }
1271 #define SH_PFC_MUX8(name, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8) \
1272         static const unsigned int name ##_mux[]  = { arg1##_MARK, arg2##_MARK, \
1273                                                      arg3##_MARK, arg4##_MARK, \
1274                                                      arg5##_MARK, arg6##_MARK, \
1275                                                      arg7##_MARK, arg8##_MARK, }
1276
1277 /* - AUDIO macro -------------------------------------------------------------*/
1278 #define AUDIO_PFC_PIN(name, pin)        SH_PFC_PINS(name, pin)
1279 #define AUDIO_PFC_DAT(name, pin)        SH_PFC_MUX1(name, pin)
1280
1281 /* - AUDIO clock -------------------------------------------------------------*/
1282 AUDIO_PFC_PIN(audio_clk_a,      RCAR_GP_PIN(2, 22));
1283 AUDIO_PFC_DAT(audio_clk_a,      AUDIO_CLKA);
1284 AUDIO_PFC_PIN(audio_clk_b,      RCAR_GP_PIN(2, 23));
1285 AUDIO_PFC_DAT(audio_clk_b,      AUDIO_CLKB);
1286 AUDIO_PFC_PIN(audio_clk_c,      RCAR_GP_PIN(2, 7));
1287 AUDIO_PFC_DAT(audio_clk_c,      AUDIO_CLKC);
1288 AUDIO_PFC_PIN(audio_clkout_a,   RCAR_GP_PIN(2, 16));
1289 AUDIO_PFC_DAT(audio_clkout_a,   AUDIO_CLKOUT_A);
1290 AUDIO_PFC_PIN(audio_clkout_b,   RCAR_GP_PIN(1, 16));
1291 AUDIO_PFC_DAT(audio_clkout_b,   AUDIO_CLKOUT_B);
1292
1293 /* - CAN macro --------_----------------------------------------------------- */
1294 #define CAN_PFC_PINS(name, args...)             SH_PFC_PINS(name, args)
1295 #define CAN_PFC_DATA(name, tx, rx)              SH_PFC_MUX2(name, tx, rx)
1296 #define CAN_PFC_CLK(name, clk)                  SH_PFC_MUX1(name, clk)
1297
1298 /* - CAN0 ------------------------------------------------------------------- */
1299 CAN_PFC_PINS(can0_data_a,       RCAR_GP_PIN(1, 30),     RCAR_GP_PIN(1, 31));
1300 CAN_PFC_DATA(can0_data_a,       CAN0_TX_A,              CAN0_RX_A);
1301 CAN_PFC_PINS(can0_data_b,       RCAR_GP_PIN(2, 26),     RCAR_GP_PIN(2, 27));
1302 CAN_PFC_DATA(can0_data_b,       CAN0_TX_B,              CAN0_RX_B);
1303
1304 /* - CAN1 ------------------------------------------------------------------- */
1305 CAN_PFC_PINS(can1_data_a,       RCAR_GP_PIN(4, 20),     RCAR_GP_PIN(4, 19));
1306 CAN_PFC_DATA(can1_data_a,       CAN1_TX_A,              CAN1_RX_A);
1307 CAN_PFC_PINS(can1_data_b,       RCAR_GP_PIN(2, 28),     RCAR_GP_PIN(2, 29));
1308 CAN_PFC_DATA(can1_data_b,       CAN1_TX_B,              CAN1_RX_B);
1309
1310 /* - CAN_CLK  --------------------------------------------------------------- */
1311 CAN_PFC_PINS(can_clk_a,         RCAR_GP_PIN(3, 24));
1312 CAN_PFC_CLK(can_clk_a,          CAN_CLK_A);
1313 CAN_PFC_PINS(can_clk_b,         RCAR_GP_PIN(1, 16));
1314 CAN_PFC_CLK(can_clk_b,          CAN_CLK_B);
1315 CAN_PFC_PINS(can_clk_c,         RCAR_GP_PIN(4, 24));
1316 CAN_PFC_CLK(can_clk_c,          CAN_CLK_C);
1317 CAN_PFC_PINS(can_clk_d,         RCAR_GP_PIN(2, 25));
1318 CAN_PFC_CLK(can_clk_d,          CAN_CLK_D);
1319
1320 /* - Ether ------------------------------------------------------------------ */
1321 SH_PFC_PINS(ether_rmii,         RCAR_GP_PIN(4, 10),     RCAR_GP_PIN(4, 11),
1322                                 RCAR_GP_PIN(4, 13),     RCAR_GP_PIN(4, 9),
1323                                 RCAR_GP_PIN(4, 15),     RCAR_GP_PIN(4, 16),
1324                                 RCAR_GP_PIN(4, 12),     RCAR_GP_PIN(4, 14),
1325                                 RCAR_GP_PIN(4, 18),     RCAR_GP_PIN(4, 17));
1326 static const unsigned int ether_rmii_mux[] = {
1327         ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK,  ETH_REF_CLK_MARK,
1328         ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_CRS_DV_MARK, ETH_RX_ER_MARK,
1329         ETH_MDIO_MARK, ETH_MDC_MARK,
1330 };
1331 SH_PFC_PINS(ether_link,         RCAR_GP_PIN(4, 19));
1332 SH_PFC_MUX1(ether_link,         ETH_LINK);
1333 SH_PFC_PINS(ether_magic,        RCAR_GP_PIN(4, 20));
1334 SH_PFC_MUX1(ether_magic,        ETH_MAGIC);
1335
1336 /* - SCIF macro ------------------------------------------------------------- */
1337 #define SCIF_PFC_PIN(name, args...)     SH_PFC_PINS(name, args)
1338 #define SCIF_PFC_DAT(name, tx, rx)      SH_PFC_MUX2(name, tx, rx)
1339 #define SCIF_PFC_CTR(name, cts, rts)    SH_PFC_MUX2(name, cts, rts)
1340 #define SCIF_PFC_CLK(name, sck)         SH_PFC_MUX1(name, sck)
1341
1342 /* - HSCIF0 ----------------------------------------------------------------- */
1343 SCIF_PFC_PIN(hscif0_data_a,     RCAR_GP_PIN(1, 17),     RCAR_GP_PIN(1, 18));
1344 SCIF_PFC_DAT(hscif0_data_a,     HTX0_A,                 HRX0_A);
1345 SCIF_PFC_PIN(hscif0_data_b,     RCAR_GP_PIN(0, 29),     RCAR_GP_PIN(0, 30));
1346 SCIF_PFC_DAT(hscif0_data_b,     HTX0_B,                 HRX0_B);
1347 SCIF_PFC_PIN(hscif0_ctrl_a,     RCAR_GP_PIN(1, 20),     RCAR_GP_PIN(1, 21));
1348 SCIF_PFC_CTR(hscif0_ctrl_a,     HCTS0_A,                HRTS0_A);
1349 SCIF_PFC_PIN(hscif0_ctrl_b,     RCAR_GP_PIN(0, 31),     RCAR_GP_PIN(0, 28));
1350 SCIF_PFC_CTR(hscif0_ctrl_b,     HCTS0_B,                HRTS0_B);
1351 SCIF_PFC_PIN(hscif0_clk,        RCAR_GP_PIN(1, 19));
1352 SCIF_PFC_CLK(hscif0_clk,        HSCK0);
1353
1354 /* - HSCIF1 ----------------------------------------------------------------- */
1355 SCIF_PFC_PIN(hscif1_data_a,     RCAR_GP_PIN(3, 19),     RCAR_GP_PIN(3, 20));
1356 SCIF_PFC_DAT(hscif1_data_a,     HTX1_A,                 HRX1_A);
1357 SCIF_PFC_PIN(hscif1_data_b,     RCAR_GP_PIN(4, 5),      RCAR_GP_PIN(4, 6));
1358 SCIF_PFC_DAT(hscif1_data_b,     HTX1_B,                 HRX1_B);
1359 SCIF_PFC_PIN(hscif1_ctrl_a,     RCAR_GP_PIN(3, 22),     RCAR_GP_PIN(3, 21));
1360 SCIF_PFC_CTR(hscif1_ctrl_a,     HCTS1_A,                HRTS1_A);
1361 SCIF_PFC_PIN(hscif1_ctrl_b,     RCAR_GP_PIN(4, 8),      RCAR_GP_PIN(4, 7));
1362 SCIF_PFC_CTR(hscif1_ctrl_b,     HCTS1_B,                HRTS1_B);
1363 SCIF_PFC_PIN(hscif1_clk_a,      RCAR_GP_PIN(3, 23));
1364 SCIF_PFC_CLK(hscif1_clk_a,      HSCK1_A);
1365 SCIF_PFC_PIN(hscif1_clk_b,      RCAR_GP_PIN(4, 2));
1366 SCIF_PFC_CLK(hscif1_clk_b,      HSCK1_B);
1367
1368 /* - HSPI macro --------------------------------------------------------------*/
1369 #define HSPI_PFC_PIN(name, args...)             SH_PFC_PINS(name, args)
1370 #define HSPI_PFC_DAT(name, clk, cs, rx, tx)     SH_PFC_MUX4(name, clk, cs, rx, tx)
1371
1372 /* - HSPI0 -------------------------------------------------------------------*/
1373 HSPI_PFC_PIN(hspi0_a,   RCAR_GP_PIN(3, 19),     RCAR_GP_PIN(3, 20),
1374                         RCAR_GP_PIN(3, 21),     RCAR_GP_PIN(3, 22));
1375 HSPI_PFC_DAT(hspi0_a,   HSPI_CLK0_A,            HSPI_CS0_A,
1376                         HSPI_RX0_A,             HSPI_TX0);
1377
1378 HSPI_PFC_PIN(hspi0_b,   RCAR_GP_PIN(2, 25),     RCAR_GP_PIN(2, 26),
1379                         RCAR_GP_PIN(2, 24),     RCAR_GP_PIN(2, 27));
1380 HSPI_PFC_DAT(hspi0_b,   HSPI_CLK0_B,            HSPI_CS0_B,
1381                         HSPI_RX0_B,             HSPI_TX0_B);
1382
1383 /* - HSPI1 -------------------------------------------------------------------*/
1384 HSPI_PFC_PIN(hspi1_a,   RCAR_GP_PIN(3, 26),     RCAR_GP_PIN(3, 27),
1385                         RCAR_GP_PIN(3, 25),     RCAR_GP_PIN(3, 28));
1386 HSPI_PFC_DAT(hspi1_a,   HSPI_CLK1_A,            HSPI_CS1_A,
1387                         HSPI_RX1_A,             HSPI_TX1_A);
1388
1389 HSPI_PFC_PIN(hspi1_b,   RCAR_GP_PIN(0, 27),     RCAR_GP_PIN(0, 26),
1390                         PIN_CS0,                PIN_CLKOUT);
1391 HSPI_PFC_DAT(hspi1_b,   HSPI_CLK1_B,            HSPI_CS1_B,
1392                         HSPI_RX1_B,             HSPI_TX1_B);
1393
1394 /* - HSPI2 -------------------------------------------------------------------*/
1395 HSPI_PFC_PIN(hspi2_a,   RCAR_GP_PIN(2, 29),     RCAR_GP_PIN(3, 8),
1396                         RCAR_GP_PIN(2, 28),     RCAR_GP_PIN(2, 30));
1397 HSPI_PFC_DAT(hspi2_a,   HSPI_CLK2_A,            HSPI_CS2_A,
1398                         HSPI_RX2_A,             HSPI_TX2_A);
1399
1400 HSPI_PFC_PIN(hspi2_b,   RCAR_GP_PIN(4, 21),     RCAR_GP_PIN(4, 22),
1401                         RCAR_GP_PIN(4, 23),     RCAR_GP_PIN(4, 24));
1402 HSPI_PFC_DAT(hspi2_b,   HSPI_CLK2_B,            HSPI_CS2_B,
1403                         HSPI_RX2_B,             HSPI_TX2_B);
1404
1405 /* - I2C macro ------------------------------------------------------------- */
1406 #define I2C_PFC_PIN(name, args...)      SH_PFC_PINS(name, args)
1407 #define I2C_PFC_MUX(name, sda, scl)     SH_PFC_MUX2(name, sda, scl)
1408
1409 /* - I2C1 ------------------------------------------------------------------ */
1410 I2C_PFC_PIN(i2c1_a,     RCAR_GP_PIN(3, 8),      RCAR_GP_PIN(3, 9));
1411 I2C_PFC_MUX(i2c1_a,     SDA1_A,                 SCL1_A);
1412 I2C_PFC_PIN(i2c1_b,     RCAR_GP_PIN(4, 17),     RCAR_GP_PIN(4, 18));
1413 I2C_PFC_MUX(i2c1_b,     SDA1_B,                 SCL1_B);
1414
1415 /* - I2C2 ------------------------------------------------------------------ */
1416 I2C_PFC_PIN(i2c2_a,     PIN_CS1_A26,            RCAR_GP_PIN(1, 3));
1417 I2C_PFC_MUX(i2c2_a,     SDA2_A,                 SCL2_A);
1418 I2C_PFC_PIN(i2c2_b,     RCAR_GP_PIN(0, 3),      RCAR_GP_PIN(0, 4));
1419 I2C_PFC_MUX(i2c2_b,     SDA2_B,                 SCL2_B);
1420 I2C_PFC_PIN(i2c2_c,     RCAR_GP_PIN(4, 15),     RCAR_GP_PIN(4, 16));
1421 I2C_PFC_MUX(i2c2_c,     SDA2_C,                 SCL2_C);
1422
1423 /* - I2C3 ------------------------------------------------------------------ */
1424 I2C_PFC_PIN(i2c3_a,     RCAR_GP_PIN(1, 14),     RCAR_GP_PIN(1, 15));
1425 I2C_PFC_MUX(i2c3_a,     SDA3_A,                 SCL3_A);
1426 I2C_PFC_PIN(i2c3_b,     RCAR_GP_PIN(1, 16),     RCAR_GP_PIN(1, 19));
1427 I2C_PFC_MUX(i2c3_b,     SDA3_B,                 SCL3_B);
1428 I2C_PFC_PIN(i2c3_c,     RCAR_GP_PIN(1, 22),     RCAR_GP_PIN(1, 23));
1429 I2C_PFC_MUX(i2c3_c,     SDA3_C,                 SCL3_C);
1430
1431 /* - MMC macro -------------------------------------------------------------- */
1432 #define MMC_PFC_PINS(name, args...)             SH_PFC_PINS(name, args)
1433 #define MMC_PFC_CTRL(name, clk, cmd)            SH_PFC_MUX2(name, clk, cmd)
1434 #define MMC_PFC_DAT1(name, d0)                  SH_PFC_MUX1(name, d0)
1435 #define MMC_PFC_DAT4(name, d0, d1, d2, d3)      SH_PFC_MUX4(name, d0, d1, d2, d3)
1436 #define MMC_PFC_DAT8(name, d0, d1, d2, d3, d4, d5, d6, d7)      \
1437                         SH_PFC_MUX8(name, d0, d1, d2, d3, d4, d5, d6, d7)
1438
1439 /* - MMC -------------------------------------------------------------------- */
1440 MMC_PFC_PINS(mmc_ctrl,          RCAR_GP_PIN(1, 5),      RCAR_GP_PIN(1, 6));
1441 MMC_PFC_CTRL(mmc_ctrl,          MMC_CLK,                MMC_CMD);
1442 MMC_PFC_PINS(mmc_data1,         RCAR_GP_PIN(1, 7));
1443 MMC_PFC_DAT1(mmc_data1,         MMC_D0);
1444 MMC_PFC_PINS(mmc_data4,         RCAR_GP_PIN(1, 7),      RCAR_GP_PIN(1, 8),
1445                                 RCAR_GP_PIN(0, 5),      RCAR_GP_PIN(0, 6));
1446 MMC_PFC_DAT4(mmc_data4,         MMC_D0,                 MMC_D1,
1447                                 MMC_D2,                 MMC_D3);
1448 MMC_PFC_PINS(mmc_data8,         RCAR_GP_PIN(1, 7),      RCAR_GP_PIN(1, 8),
1449                                 RCAR_GP_PIN(0, 5),      RCAR_GP_PIN(0, 6),
1450                                 RCAR_GP_PIN(1, 4),      RCAR_GP_PIN(1, 0),
1451                                 RCAR_GP_PIN(0, 30),     RCAR_GP_PIN(0, 31));
1452 MMC_PFC_DAT8(mmc_data8,         MMC_D0,                 MMC_D1,
1453                                 MMC_D2,                 MMC_D3,
1454                                 MMC_D4,                 MMC_D5,
1455                                 MMC_D6,                 MMC_D7);
1456
1457 /* - SCIF CLOCK ------------------------------------------------------------- */
1458 SCIF_PFC_PIN(scif_clk,          RCAR_GP_PIN(1, 16));
1459 SCIF_PFC_CLK(scif_clk,          SCIF_CLK);
1460
1461 /* - SCIF0 ------------------------------------------------------------------ */
1462 SCIF_PFC_PIN(scif0_data_a,      RCAR_GP_PIN(1, 17),     RCAR_GP_PIN(1, 18));
1463 SCIF_PFC_DAT(scif0_data_a,      TX0_A,                  RX0_A);
1464 SCIF_PFC_PIN(scif0_data_b,      RCAR_GP_PIN(2, 3),      RCAR_GP_PIN(2, 2));
1465 SCIF_PFC_DAT(scif0_data_b,      TX0_B,                  RX0_B);
1466 SCIF_PFC_PIN(scif0_data_c,      RCAR_GP_PIN(4, 0),      RCAR_GP_PIN(3, 31));
1467 SCIF_PFC_DAT(scif0_data_c,      TX0_C,                  RX0_C);
1468 SCIF_PFC_PIN(scif0_data_d,      RCAR_GP_PIN(3, 6),      RCAR_GP_PIN(3, 1));
1469 SCIF_PFC_DAT(scif0_data_d,      TX0_D,                  RX0_D);
1470 SCIF_PFC_PIN(scif0_ctrl,        RCAR_GP_PIN(1, 20),     RCAR_GP_PIN(1, 21));
1471 SCIF_PFC_CTR(scif0_ctrl,        CTS0,                   RTS0);
1472 SCIF_PFC_PIN(scif0_clk,         RCAR_GP_PIN(1, 19));
1473 SCIF_PFC_CLK(scif0_clk,         SCK0);
1474
1475 /* - SCIF1 ------------------------------------------------------------------ */
1476 SCIF_PFC_PIN(scif1_data_a,      RCAR_GP_PIN(4, 0),      RCAR_GP_PIN(4, 1));
1477 SCIF_PFC_DAT(scif1_data_a,      TX1_A,                  RX1_A);
1478 SCIF_PFC_PIN(scif1_data_b,      RCAR_GP_PIN(2, 24),     RCAR_GP_PIN(2, 25));
1479 SCIF_PFC_DAT(scif1_data_b,      TX1_B,                  RX1_B);
1480 SCIF_PFC_PIN(scif1_data_c,      RCAR_GP_PIN(3, 22),     RCAR_GP_PIN(3, 21));
1481 SCIF_PFC_DAT(scif1_data_c,      TX1_C,                  RX1_C);
1482 SCIF_PFC_PIN(scif1_data_d,      RCAR_GP_PIN(1, 30),     RCAR_GP_PIN(1, 31));
1483 SCIF_PFC_DAT(scif1_data_d,      TX1_D,                  RX1_D);
1484 SCIF_PFC_PIN(scif1_ctrl_a,      RCAR_GP_PIN(4, 3),      RCAR_GP_PIN(4, 4));
1485 SCIF_PFC_CTR(scif1_ctrl_a,      CTS1_A,                 RTS1_A);
1486 SCIF_PFC_PIN(scif1_ctrl_c,      RCAR_GP_PIN(3, 23),     RCAR_GP_PIN(3, 19));
1487 SCIF_PFC_CTR(scif1_ctrl_c,      CTS1_C,                 RTS1_C);
1488 SCIF_PFC_PIN(scif1_clk_a,       RCAR_GP_PIN(4, 2));
1489 SCIF_PFC_CLK(scif1_clk_a,       SCK1_A);
1490 SCIF_PFC_PIN(scif1_clk_c,       RCAR_GP_PIN(3, 20));
1491 SCIF_PFC_CLK(scif1_clk_c,       SCK1_C);
1492
1493 /* - SCIF2 ------------------------------------------------------------------ */
1494 SCIF_PFC_PIN(scif2_data_a,      RCAR_GP_PIN(2, 26),     RCAR_GP_PIN(2, 27));
1495 SCIF_PFC_DAT(scif2_data_a,      TX2_A,                  RX2_A);
1496 SCIF_PFC_PIN(scif2_data_b,      RCAR_GP_PIN(0, 29),     RCAR_GP_PIN(0, 28));
1497 SCIF_PFC_DAT(scif2_data_b,      TX2_B,                  RX2_B);
1498 SCIF_PFC_PIN(scif2_data_c,      RCAR_GP_PIN(4, 13),     RCAR_GP_PIN(4, 14));
1499 SCIF_PFC_DAT(scif2_data_c,      TX2_C,                  RX2_C);
1500 SCIF_PFC_PIN(scif2_data_d,      RCAR_GP_PIN(4, 15),     RCAR_GP_PIN(4, 16));
1501 SCIF_PFC_DAT(scif2_data_d,      TX2_D,                  RX2_D);
1502 SCIF_PFC_PIN(scif2_data_e,      RCAR_GP_PIN(0, 3),      RCAR_GP_PIN(0, 4));
1503 SCIF_PFC_DAT(scif2_data_e,      TX2_E,                  RX2_E);
1504 SCIF_PFC_PIN(scif2_clk_a,       RCAR_GP_PIN(3, 9));
1505 SCIF_PFC_CLK(scif2_clk_a,       SCK2_A);
1506 SCIF_PFC_PIN(scif2_clk_b,       PIN_CS1_A26);
1507 SCIF_PFC_CLK(scif2_clk_b,       SCK2_B);
1508 SCIF_PFC_PIN(scif2_clk_c,       RCAR_GP_PIN(4, 12));
1509 SCIF_PFC_CLK(scif2_clk_c,       SCK2_C);
1510
1511 /* - SCIF3 ------------------------------------------------------------------ */
1512 SCIF_PFC_PIN(scif3_data_a,      RCAR_GP_PIN(1, 10),     RCAR_GP_PIN(1, 9));
1513 SCIF_PFC_DAT(scif3_data_a,      TX3_A,                  RX3_A);
1514 SCIF_PFC_PIN(scif3_data_b,      RCAR_GP_PIN(3, 28),     RCAR_GP_PIN(3, 27));
1515 SCIF_PFC_DAT(scif3_data_b,      TX3_B,                  RX3_B);
1516 SCIF_PFC_PIN(scif3_data_c,      RCAR_GP_PIN(1, 3),      RCAR_GP_PIN(0, 31));
1517 SCIF_PFC_DAT(scif3_data_c,      TX3_C,                  RX3_C);
1518 SCIF_PFC_PIN(scif3_data_d,      RCAR_GP_PIN(3, 30),     RCAR_GP_PIN(3, 29));
1519 SCIF_PFC_DAT(scif3_data_d,      TX3_D,                  RX3_D);
1520
1521 /* - SCIF4 ------------------------------------------------------------------ */
1522 SCIF_PFC_PIN(scif4_data_a,      RCAR_GP_PIN(2, 5),      RCAR_GP_PIN(2, 4));
1523 SCIF_PFC_DAT(scif4_data_a,      TX4_A,                  RX4_A);
1524 SCIF_PFC_PIN(scif4_data_b,      RCAR_GP_PIN(3, 26),     RCAR_GP_PIN(3, 25));
1525 SCIF_PFC_DAT(scif4_data_b,      TX4_B,                  RX4_B);
1526 SCIF_PFC_PIN(scif4_data_c,      RCAR_GP_PIN(3, 0),      RCAR_GP_PIN(2, 31));
1527 SCIF_PFC_DAT(scif4_data_c,      TX4_C,                  RX4_C);
1528
1529 /* - SCIF5 ------------------------------------------------------------------ */
1530 SCIF_PFC_PIN(scif5_data_a,      RCAR_GP_PIN(3, 17),     RCAR_GP_PIN(3, 18));
1531 SCIF_PFC_DAT(scif5_data_a,      TX5_A,                  RX5_A);
1532 SCIF_PFC_PIN(scif5_data_b,      RCAR_GP_PIN(1, 15),     RCAR_GP_PIN(1, 14));
1533 SCIF_PFC_DAT(scif5_data_b,      TX5_B,                  RX5_B);
1534
1535 /* - SDHI macro ------------------------------------------------------------- */
1536 #define SDHI_PFC_PINS(name, args...)            SH_PFC_PINS(name, args)
1537 #define SDHI_PFC_DAT1(name, d0)                 SH_PFC_MUX1(name, d0)
1538 #define SDHI_PFC_DAT4(name, d0, d1, d2, d3)     SH_PFC_MUX4(name, d0, d1, d2, d3)
1539 #define SDHI_PFC_CTRL(name, clk, cmd)           SH_PFC_MUX2(name, clk, cmd)
1540 #define SDHI_PFC_CDPN(name, cd)                 SH_PFC_MUX1(name, cd)
1541 #define SDHI_PFC_WPPN(name, wp)                 SH_PFC_MUX1(name, wp)
1542
1543 /* - SDHI0 ------------------------------------------------------------------ */
1544 SDHI_PFC_PINS(sdhi0_cd,         RCAR_GP_PIN(3, 17));
1545 SDHI_PFC_CDPN(sdhi0_cd,         SD0_CD);
1546 SDHI_PFC_PINS(sdhi0_ctrl,       RCAR_GP_PIN(3, 11),     RCAR_GP_PIN(3, 12));
1547 SDHI_PFC_CTRL(sdhi0_ctrl,       SD0_CLK,                SD0_CMD);
1548 SDHI_PFC_PINS(sdhi0_data1,      RCAR_GP_PIN(3, 13));
1549 SDHI_PFC_DAT1(sdhi0_data1,      SD0_DAT0);
1550 SDHI_PFC_PINS(sdhi0_data4,      RCAR_GP_PIN(3, 13),     RCAR_GP_PIN(3, 14),
1551                                 RCAR_GP_PIN(3, 15),     RCAR_GP_PIN(3, 16));
1552 SDHI_PFC_DAT4(sdhi0_data4,      SD0_DAT0,               SD0_DAT1,
1553                                 SD0_DAT2,               SD0_DAT3);
1554 SDHI_PFC_PINS(sdhi0_wp,         RCAR_GP_PIN(3, 18));
1555 SDHI_PFC_WPPN(sdhi0_wp,         SD0_WP);
1556
1557 /* - SDHI1 ------------------------------------------------------------------ */
1558 SDHI_PFC_PINS(sdhi1_cd_a,       RCAR_GP_PIN(0, 30));
1559 SDHI_PFC_CDPN(sdhi1_cd_a,       SD1_CD_A);
1560 SDHI_PFC_PINS(sdhi1_cd_b,       RCAR_GP_PIN(2, 24));
1561 SDHI_PFC_CDPN(sdhi1_cd_b,       SD1_CD_B);
1562 SDHI_PFC_PINS(sdhi1_ctrl_a,     RCAR_GP_PIN(1, 5),      RCAR_GP_PIN(1, 6));
1563 SDHI_PFC_CTRL(sdhi1_ctrl_a,     SD1_CLK_A,              SD1_CMD_A);
1564 SDHI_PFC_PINS(sdhi1_ctrl_b,     RCAR_GP_PIN(1, 17),     RCAR_GP_PIN(1, 16));
1565 SDHI_PFC_CTRL(sdhi1_ctrl_b,     SD1_CLK_B,              SD1_CMD_B);
1566 SDHI_PFC_PINS(sdhi1_data1_a,    RCAR_GP_PIN(1, 7));
1567 SDHI_PFC_DAT1(sdhi1_data1_a,    SD1_DAT0_A);
1568 SDHI_PFC_PINS(sdhi1_data1_b,    RCAR_GP_PIN(1, 18));
1569 SDHI_PFC_DAT1(sdhi1_data1_b,    SD1_DAT0_B);
1570 SDHI_PFC_PINS(sdhi1_data4_a,    RCAR_GP_PIN(1, 7),      RCAR_GP_PIN(1, 8),
1571                                 RCAR_GP_PIN(0, 5),      RCAR_GP_PIN(0, 6));
1572 SDHI_PFC_DAT4(sdhi1_data4_a,    SD1_DAT0_A,             SD1_DAT1_A,
1573                                 SD1_DAT2_A,             SD1_DAT3_A);
1574 SDHI_PFC_PINS(sdhi1_data4_b,    RCAR_GP_PIN(1, 18),     RCAR_GP_PIN(1, 19),
1575                                 RCAR_GP_PIN(1, 20),     RCAR_GP_PIN(1, 21));
1576 SDHI_PFC_DAT4(sdhi1_data4_b,    SD1_DAT0_B,             SD1_DAT1_B,
1577                                 SD1_DAT2_B,             SD1_DAT3_B);
1578 SDHI_PFC_PINS(sdhi1_wp_a,       RCAR_GP_PIN(0, 31));
1579 SDHI_PFC_WPPN(sdhi1_wp_a,       SD1_WP_A);
1580 SDHI_PFC_PINS(sdhi1_wp_b,       RCAR_GP_PIN(2, 25));
1581 SDHI_PFC_WPPN(sdhi1_wp_b,       SD1_WP_B);
1582
1583 /* - SDH2 ------------------------------------------------------------------- */
1584 SDHI_PFC_PINS(sdhi2_cd_a,       RCAR_GP_PIN(4, 23));
1585 SDHI_PFC_CDPN(sdhi2_cd_a,       SD2_CD_A);
1586 SDHI_PFC_PINS(sdhi2_cd_b,       RCAR_GP_PIN(3, 27));
1587 SDHI_PFC_CDPN(sdhi2_cd_b,       SD2_CD_B);
1588 SDHI_PFC_PINS(sdhi2_ctrl_a,     RCAR_GP_PIN(4, 17),     RCAR_GP_PIN(4, 18));
1589 SDHI_PFC_CTRL(sdhi2_ctrl_a,     SD2_CLK_A,              SD2_CMD_A);
1590 SDHI_PFC_PINS(sdhi2_ctrl_b,     RCAR_GP_PIN(4, 5),      RCAR_GP_PIN(4, 6));
1591 SDHI_PFC_CTRL(sdhi2_ctrl_b,     SD2_CLK_B,              SD2_CMD_B);
1592 SDHI_PFC_PINS(sdhi2_data1_a,    RCAR_GP_PIN(4, 19));
1593 SDHI_PFC_DAT1(sdhi2_data1_a,    SD2_DAT0_A);
1594 SDHI_PFC_PINS(sdhi2_data1_b,    RCAR_GP_PIN(4, 7));
1595 SDHI_PFC_DAT1(sdhi2_data1_b,    SD2_DAT0_B);
1596 SDHI_PFC_PINS(sdhi2_data4_a,    RCAR_GP_PIN(4, 19),     RCAR_GP_PIN(4, 20),
1597                                 RCAR_GP_PIN(4, 21),     RCAR_GP_PIN(4, 22));
1598 SDHI_PFC_DAT4(sdhi2_data4_a,    SD2_DAT0_A,             SD2_DAT1_A,
1599                                 SD2_DAT2_A,             SD2_DAT3_A);
1600 SDHI_PFC_PINS(sdhi2_data4_b,    RCAR_GP_PIN(4, 7),      RCAR_GP_PIN(4, 8),
1601                                 RCAR_GP_PIN(3, 25),     RCAR_GP_PIN(3, 26));
1602 SDHI_PFC_DAT4(sdhi2_data4_b,    SD2_DAT0_B,             SD2_DAT1_B,
1603                                 SD2_DAT2_B,             SD2_DAT3_B);
1604 SDHI_PFC_PINS(sdhi2_wp_a,       RCAR_GP_PIN(4, 24));
1605 SDHI_PFC_WPPN(sdhi2_wp_a,       SD2_WP_A);
1606 SDHI_PFC_PINS(sdhi2_wp_b,       RCAR_GP_PIN(3, 28));
1607 SDHI_PFC_WPPN(sdhi2_wp_b,       SD2_WP_B);
1608
1609 /* - SSI macro -------------------------------------------------------------- */
1610 #define SSI_PFC_PINS(name, args...)             SH_PFC_PINS(name, args)
1611 #define SSI_PFC_CTRL(name, sck, ws)             SH_PFC_MUX2(name, sck, ws)
1612 #define SSI_PFC_DATA(name, d)                   SH_PFC_MUX1(name, d)
1613
1614 /* - SSI 0/1/2 -------------------------------------------------------------- */
1615 SSI_PFC_PINS(ssi012_ctrl,       RCAR_GP_PIN(3, 6),      RCAR_GP_PIN(3, 7));
1616 SSI_PFC_CTRL(ssi012_ctrl,       SSI_SCK012,             SSI_WS012);
1617 SSI_PFC_PINS(ssi0_data,         RCAR_GP_PIN(3, 10));
1618 SSI_PFC_DATA(ssi0_data,         SSI_SDATA0);
1619 SSI_PFC_PINS(ssi1_a_ctrl,       RCAR_GP_PIN(2, 20),     RCAR_GP_PIN(2, 21));
1620 SSI_PFC_CTRL(ssi1_a_ctrl,       SSI_SCK1_A,             SSI_WS1_A);
1621 SSI_PFC_PINS(ssi1_b_ctrl,       PIN_CS1_A26,            RCAR_GP_PIN(1, 3));
1622 SSI_PFC_CTRL(ssi1_b_ctrl,       SSI_SCK1_B,             SSI_WS1_B);
1623 SSI_PFC_PINS(ssi1_data,         RCAR_GP_PIN(3, 9));
1624 SSI_PFC_DATA(ssi1_data,         SSI_SDATA1);
1625 SSI_PFC_PINS(ssi2_a_ctrl,       RCAR_GP_PIN(2, 26),     RCAR_GP_PIN(3, 4));
1626 SSI_PFC_CTRL(ssi2_a_ctrl,       SSI_SCK2_A,             SSI_WS2_A);
1627 SSI_PFC_PINS(ssi2_b_ctrl,       RCAR_GP_PIN(2, 6),      RCAR_GP_PIN(2, 17));
1628 SSI_PFC_CTRL(ssi2_b_ctrl,       SSI_SCK2_B,             SSI_WS2_B);
1629 SSI_PFC_PINS(ssi2_data,         RCAR_GP_PIN(3, 8));
1630 SSI_PFC_DATA(ssi2_data,         SSI_SDATA2);
1631
1632 /* - SSI 3/4 ---------------------------------------------------------------- */
1633 SSI_PFC_PINS(ssi34_ctrl,        RCAR_GP_PIN(3, 2),      RCAR_GP_PIN(3, 3));
1634 SSI_PFC_CTRL(ssi34_ctrl,        SSI_SCK34,              SSI_WS34);
1635 SSI_PFC_PINS(ssi3_data,         RCAR_GP_PIN(3, 5));
1636 SSI_PFC_DATA(ssi3_data,         SSI_SDATA3);
1637 SSI_PFC_PINS(ssi4_ctrl,         RCAR_GP_PIN(1, 22),     RCAR_GP_PIN(1, 23));
1638 SSI_PFC_CTRL(ssi4_ctrl,         SSI_SCK4,               SSI_WS4);
1639 SSI_PFC_PINS(ssi4_data,         RCAR_GP_PIN(3, 4));
1640 SSI_PFC_DATA(ssi4_data,         SSI_SDATA4);
1641
1642 /* - SSI 5 ------------------------------------------------------------------ */
1643 SSI_PFC_PINS(ssi5_ctrl,         RCAR_GP_PIN(2, 31),     RCAR_GP_PIN(3, 0));
1644 SSI_PFC_CTRL(ssi5_ctrl,         SSI_SCK5,               SSI_WS5);
1645 SSI_PFC_PINS(ssi5_data,         RCAR_GP_PIN(3, 1));
1646 SSI_PFC_DATA(ssi5_data,         SSI_SDATA5);
1647
1648 /* - SSI 6 ------------------------------------------------------------------ */
1649 SSI_PFC_PINS(ssi6_ctrl,         RCAR_GP_PIN(2, 28),     RCAR_GP_PIN(2, 29));
1650 SSI_PFC_CTRL(ssi6_ctrl,         SSI_SCK6,               SSI_WS6);
1651 SSI_PFC_PINS(ssi6_data,         RCAR_GP_PIN(2, 30));
1652 SSI_PFC_DATA(ssi6_data,         SSI_SDATA6);
1653
1654 /* - SSI 7/8  --------------------------------------------------------------- */
1655 SSI_PFC_PINS(ssi78_ctrl,        RCAR_GP_PIN(2, 24),     RCAR_GP_PIN(2, 25));
1656 SSI_PFC_CTRL(ssi78_ctrl,        SSI_SCK78,              SSI_WS78);
1657 SSI_PFC_PINS(ssi7_data,         RCAR_GP_PIN(2, 27));
1658 SSI_PFC_DATA(ssi7_data,         SSI_SDATA7);
1659 SSI_PFC_PINS(ssi8_data,         RCAR_GP_PIN(2, 26));
1660 SSI_PFC_DATA(ssi8_data,         SSI_SDATA8);
1661
1662 /* - USB0 ------------------------------------------------------------------- */
1663 SH_PFC_PINS(usb0,               RCAR_GP_PIN(0, 1));
1664 SH_PFC_MUX1(usb0,               PENC0);
1665 SH_PFC_PINS(usb0_ovc,           RCAR_GP_PIN(0, 3));
1666 SH_PFC_MUX1(usb0_ovc,           USB_OVC0);
1667
1668 /* - USB1 ------------------------------------------------------------------- */
1669 SH_PFC_PINS(usb1,               RCAR_GP_PIN(0, 2));
1670 SH_PFC_MUX1(usb1,               PENC1);
1671 SH_PFC_PINS(usb1_ovc,           RCAR_GP_PIN(0, 4));
1672 SH_PFC_MUX1(usb1_ovc,           USB_OVC1);
1673
1674 /* - VIN macros ------------------------------------------------------------- */
1675 #define VIN_PFC_PINS(name, args...)             SH_PFC_PINS(name, args)
1676 #define VIN_PFC_DAT8(name, d0, d1, d2, d3, d4, d5, d6, d7)      \
1677         SH_PFC_MUX8(name, d0, d1, d2, d3, d4, d5, d6, d7)
1678 #define VIN_PFC_CLK(name, clk)                  SH_PFC_MUX1(name, clk)
1679 #define VIN_PFC_SYNC(name, hsync, vsync)        SH_PFC_MUX2(name, hsync, vsync)
1680
1681 /* - VIN0 ------------------------------------------------------------------- */
1682 VIN_PFC_PINS(vin0_data8,        RCAR_GP_PIN(3, 29),     RCAR_GP_PIN(3, 30),
1683                                 RCAR_GP_PIN(3, 31),     RCAR_GP_PIN(4, 0),
1684                                 RCAR_GP_PIN(4, 1),      RCAR_GP_PIN(4, 2),
1685                                 RCAR_GP_PIN(4, 3),      RCAR_GP_PIN(4, 4));
1686 VIN_PFC_DAT8(vin0_data8,        VI0_DATA0_VI0_B0,       VI0_DATA1_VI0_B1,
1687                                 VI0_DATA2_VI0_B2,       VI0_DATA3_VI0_B3,
1688                                 VI0_DATA4_VI0_B4,       VI0_DATA5_VI0_B5,
1689                                 VI0_DATA6_VI0_G0,       VI0_DATA7_VI0_G1);
1690 VIN_PFC_PINS(vin0_clk,          RCAR_GP_PIN(3, 24));
1691 VIN_PFC_CLK(vin0_clk,           VI0_CLK);
1692 VIN_PFC_PINS(vin0_sync,         RCAR_GP_PIN(3, 27),     RCAR_GP_PIN(3, 28));
1693 VIN_PFC_SYNC(vin0_sync,         VI0_HSYNC,              VI0_VSYNC);
1694 /* - VIN1 ------------------------------------------------------------------- */
1695 VIN_PFC_PINS(vin1_data8,        RCAR_GP_PIN(3, 25),     RCAR_GP_PIN(3, 26),
1696                                 RCAR_GP_PIN(3, 27),     RCAR_GP_PIN(3, 28),
1697                                 RCAR_GP_PIN(4, 5),      RCAR_GP_PIN(4, 6),
1698                                 RCAR_GP_PIN(4, 7),      RCAR_GP_PIN(4, 8));
1699 VIN_PFC_DAT8(vin1_data8,        VI1_DATA0,              VI1_DATA1,
1700                                 VI1_DATA2,              VI1_DATA3,
1701                                 VI1_DATA4,              VI1_DATA5,
1702                                 VI1_DATA6,              VI1_DATA7);
1703 VIN_PFC_PINS(vin1_clk,          RCAR_GP_PIN(4, 9));
1704 VIN_PFC_CLK(vin1_clk,           VI1_CLK);
1705 VIN_PFC_PINS(vin1_sync,         RCAR_GP_PIN(3, 21),     RCAR_GP_PIN(3, 22));
1706 VIN_PFC_SYNC(vin1_sync,         VI1_HSYNC,              VI1_VSYNC);
1707
1708 static const struct sh_pfc_pin_group pinmux_groups[] = {
1709         SH_PFC_PIN_GROUP(audio_clk_a),
1710         SH_PFC_PIN_GROUP(audio_clk_b),
1711         SH_PFC_PIN_GROUP(audio_clk_c),
1712         SH_PFC_PIN_GROUP(audio_clkout_a),
1713         SH_PFC_PIN_GROUP(audio_clkout_b),
1714         SH_PFC_PIN_GROUP(can0_data_a),
1715         SH_PFC_PIN_GROUP(can0_data_b),
1716         SH_PFC_PIN_GROUP(can1_data_a),
1717         SH_PFC_PIN_GROUP(can1_data_b),
1718         SH_PFC_PIN_GROUP(can_clk_a),
1719         SH_PFC_PIN_GROUP(can_clk_b),
1720         SH_PFC_PIN_GROUP(can_clk_c),
1721         SH_PFC_PIN_GROUP(can_clk_d),
1722         SH_PFC_PIN_GROUP(ether_rmii),
1723         SH_PFC_PIN_GROUP(ether_link),
1724         SH_PFC_PIN_GROUP(ether_magic),
1725         SH_PFC_PIN_GROUP(hscif0_data_a),
1726         SH_PFC_PIN_GROUP(hscif0_data_b),
1727         SH_PFC_PIN_GROUP(hscif0_ctrl_a),
1728         SH_PFC_PIN_GROUP(hscif0_ctrl_b),
1729         SH_PFC_PIN_GROUP(hscif0_clk),
1730         SH_PFC_PIN_GROUP(hscif1_data_a),
1731         SH_PFC_PIN_GROUP(hscif1_data_b),
1732         SH_PFC_PIN_GROUP(hscif1_ctrl_a),
1733         SH_PFC_PIN_GROUP(hscif1_ctrl_b),
1734         SH_PFC_PIN_GROUP(hscif1_clk_a),
1735         SH_PFC_PIN_GROUP(hscif1_clk_b),
1736         SH_PFC_PIN_GROUP(hspi0_a),
1737         SH_PFC_PIN_GROUP(hspi0_b),
1738         SH_PFC_PIN_GROUP(hspi1_a),
1739         SH_PFC_PIN_GROUP(hspi1_b),
1740         SH_PFC_PIN_GROUP(hspi2_a),
1741         SH_PFC_PIN_GROUP(hspi2_b),
1742         SH_PFC_PIN_GROUP(i2c1_a),
1743         SH_PFC_PIN_GROUP(i2c1_b),
1744         SH_PFC_PIN_GROUP(i2c2_a),
1745         SH_PFC_PIN_GROUP(i2c2_b),
1746         SH_PFC_PIN_GROUP(i2c2_c),
1747         SH_PFC_PIN_GROUP(i2c3_a),
1748         SH_PFC_PIN_GROUP(i2c3_b),
1749         SH_PFC_PIN_GROUP(i2c3_c),
1750         SH_PFC_PIN_GROUP(mmc_ctrl),
1751         SH_PFC_PIN_GROUP(mmc_data1),
1752         SH_PFC_PIN_GROUP(mmc_data4),
1753         SH_PFC_PIN_GROUP(mmc_data8),
1754         SH_PFC_PIN_GROUP(scif_clk),
1755         SH_PFC_PIN_GROUP(scif0_data_a),
1756         SH_PFC_PIN_GROUP(scif0_data_b),
1757         SH_PFC_PIN_GROUP(scif0_data_c),
1758         SH_PFC_PIN_GROUP(scif0_data_d),
1759         SH_PFC_PIN_GROUP(scif0_ctrl),
1760         SH_PFC_PIN_GROUP(scif0_clk),
1761         SH_PFC_PIN_GROUP(scif1_data_a),
1762         SH_PFC_PIN_GROUP(scif1_data_b),
1763         SH_PFC_PIN_GROUP(scif1_data_c),
1764         SH_PFC_PIN_GROUP(scif1_data_d),
1765         SH_PFC_PIN_GROUP(scif1_ctrl_a),
1766         SH_PFC_PIN_GROUP(scif1_ctrl_c),
1767         SH_PFC_PIN_GROUP(scif1_clk_a),
1768         SH_PFC_PIN_GROUP(scif1_clk_c),
1769         SH_PFC_PIN_GROUP(scif2_data_a),
1770         SH_PFC_PIN_GROUP(scif2_data_b),
1771         SH_PFC_PIN_GROUP(scif2_data_c),
1772         SH_PFC_PIN_GROUP(scif2_data_d),
1773         SH_PFC_PIN_GROUP(scif2_data_e),
1774         SH_PFC_PIN_GROUP(scif2_clk_a),
1775         SH_PFC_PIN_GROUP(scif2_clk_b),
1776         SH_PFC_PIN_GROUP(scif2_clk_c),
1777         SH_PFC_PIN_GROUP(scif3_data_a),
1778         SH_PFC_PIN_GROUP(scif3_data_b),
1779         SH_PFC_PIN_GROUP(scif3_data_c),
1780         SH_PFC_PIN_GROUP(scif3_data_d),
1781         SH_PFC_PIN_GROUP(scif4_data_a),
1782         SH_PFC_PIN_GROUP(scif4_data_b),
1783         SH_PFC_PIN_GROUP(scif4_data_c),
1784         SH_PFC_PIN_GROUP(scif5_data_a),
1785         SH_PFC_PIN_GROUP(scif5_data_b),
1786         SH_PFC_PIN_GROUP(sdhi0_cd),
1787         SH_PFC_PIN_GROUP(sdhi0_ctrl),
1788         SH_PFC_PIN_GROUP(sdhi0_data1),
1789         SH_PFC_PIN_GROUP(sdhi0_data4),
1790         SH_PFC_PIN_GROUP(sdhi0_wp),
1791         SH_PFC_PIN_GROUP(sdhi1_cd_a),
1792         SH_PFC_PIN_GROUP(sdhi1_cd_b),
1793         SH_PFC_PIN_GROUP(sdhi1_ctrl_a),
1794         SH_PFC_PIN_GROUP(sdhi1_ctrl_b),
1795         SH_PFC_PIN_GROUP(sdhi1_data1_a),
1796         SH_PFC_PIN_GROUP(sdhi1_data1_b),
1797         SH_PFC_PIN_GROUP(sdhi1_data4_a),
1798         SH_PFC_PIN_GROUP(sdhi1_data4_b),
1799         SH_PFC_PIN_GROUP(sdhi1_wp_a),
1800         SH_PFC_PIN_GROUP(sdhi1_wp_b),
1801         SH_PFC_PIN_GROUP(sdhi2_cd_a),
1802         SH_PFC_PIN_GROUP(sdhi2_cd_b),
1803         SH_PFC_PIN_GROUP(sdhi2_ctrl_a),
1804         SH_PFC_PIN_GROUP(sdhi2_ctrl_b),
1805         SH_PFC_PIN_GROUP(sdhi2_data1_a),
1806         SH_PFC_PIN_GROUP(sdhi2_data1_b),
1807         SH_PFC_PIN_GROUP(sdhi2_data4_a),
1808         SH_PFC_PIN_GROUP(sdhi2_data4_b),
1809         SH_PFC_PIN_GROUP(sdhi2_wp_a),
1810         SH_PFC_PIN_GROUP(sdhi2_wp_b),
1811         SH_PFC_PIN_GROUP(ssi012_ctrl),
1812         SH_PFC_PIN_GROUP(ssi0_data),
1813         SH_PFC_PIN_GROUP(ssi1_a_ctrl),
1814         SH_PFC_PIN_GROUP(ssi1_b_ctrl),
1815         SH_PFC_PIN_GROUP(ssi1_data),
1816         SH_PFC_PIN_GROUP(ssi2_a_ctrl),
1817         SH_PFC_PIN_GROUP(ssi2_b_ctrl),
1818         SH_PFC_PIN_GROUP(ssi2_data),
1819         SH_PFC_PIN_GROUP(ssi34_ctrl),
1820         SH_PFC_PIN_GROUP(ssi3_data),
1821         SH_PFC_PIN_GROUP(ssi4_ctrl),
1822         SH_PFC_PIN_GROUP(ssi4_data),
1823         SH_PFC_PIN_GROUP(ssi5_ctrl),
1824         SH_PFC_PIN_GROUP(ssi5_data),
1825         SH_PFC_PIN_GROUP(ssi6_ctrl),
1826         SH_PFC_PIN_GROUP(ssi6_data),
1827         SH_PFC_PIN_GROUP(ssi78_ctrl),
1828         SH_PFC_PIN_GROUP(ssi7_data),
1829         SH_PFC_PIN_GROUP(ssi8_data),
1830         SH_PFC_PIN_GROUP(usb0),
1831         SH_PFC_PIN_GROUP(usb0_ovc),
1832         SH_PFC_PIN_GROUP(usb1),
1833         SH_PFC_PIN_GROUP(usb1_ovc),
1834         SH_PFC_PIN_GROUP(vin0_data8),
1835         SH_PFC_PIN_GROUP(vin0_clk),
1836         SH_PFC_PIN_GROUP(vin0_sync),
1837         SH_PFC_PIN_GROUP(vin1_data8),
1838         SH_PFC_PIN_GROUP(vin1_clk),
1839         SH_PFC_PIN_GROUP(vin1_sync),
1840 };
1841
1842 static const char * const audio_clk_groups[] = {
1843         "audio_clk_a",
1844         "audio_clk_b",
1845         "audio_clk_c",
1846         "audio_clkout_a",
1847         "audio_clkout_b",
1848 };
1849
1850 static const char * const can0_groups[] = {
1851         "can0_data_a",
1852         "can0_data_b",
1853         "can_clk_a",
1854         "can_clk_b",
1855         "can_clk_c",
1856         "can_clk_d",
1857 };
1858
1859 static const char * const can1_groups[] = {
1860         "can1_data_a",
1861         "can1_data_b",
1862         "can_clk_a",
1863         "can_clk_b",
1864         "can_clk_c",
1865         "can_clk_d",
1866 };
1867
1868 static const char * const ether_groups[] = {
1869         "ether_rmii",
1870         "ether_link",
1871         "ether_magic",
1872 };
1873
1874 static const char * const hscif0_groups[] = {
1875         "hscif0_data_a",
1876         "hscif0_data_b",
1877         "hscif0_ctrl_a",
1878         "hscif0_ctrl_b",
1879         "hscif0_clk",
1880 };
1881
1882 static const char * const hscif1_groups[] = {
1883         "hscif1_data_a",
1884         "hscif1_data_b",
1885         "hscif1_ctrl_a",
1886         "hscif1_ctrl_b",
1887         "hscif1_clk_a",
1888         "hscif1_clk_b",
1889 };
1890
1891 static const char * const hspi0_groups[] = {
1892         "hspi0_a",
1893         "hspi0_b",
1894 };
1895
1896 static const char * const hspi1_groups[] = {
1897         "hspi1_a",
1898         "hspi1_b",
1899 };
1900
1901 static const char * const hspi2_groups[] = {
1902         "hspi2_a",
1903         "hspi2_b",
1904 };
1905
1906 static const char * const i2c1_groups[] = {
1907         "i2c1_a",
1908         "i2c1_b",
1909 };
1910
1911 static const char * const i2c2_groups[] = {
1912         "i2c2_a",
1913         "i2c2_b",
1914         "i2c2_c",
1915 };
1916
1917 static const char * const i2c3_groups[] = {
1918         "i2c3_a",
1919         "i2c3_b",
1920         "i2c3_c",
1921 };
1922
1923 static const char * const mmc_groups[] = {
1924         "mmc_ctrl",
1925         "mmc_data1",
1926         "mmc_data4",
1927         "mmc_data8",
1928 };
1929
1930 static const char * const scif_clk_groups[] = {
1931         "scif_clk",
1932 };
1933
1934 static const char * const scif0_groups[] = {
1935         "scif0_data_a",
1936         "scif0_data_b",
1937         "scif0_data_c",
1938         "scif0_data_d",
1939         "scif0_ctrl",
1940         "scif0_clk",
1941 };
1942
1943 static const char * const scif1_groups[] = {
1944         "scif1_data_a",
1945         "scif1_data_b",
1946         "scif1_data_c",
1947         "scif1_data_d",
1948         "scif1_ctrl_a",
1949         "scif1_ctrl_c",
1950         "scif1_clk_a",
1951         "scif1_clk_c",
1952 };
1953
1954 static const char * const scif2_groups[] = {
1955         "scif2_data_a",
1956         "scif2_data_b",
1957         "scif2_data_c",
1958         "scif2_data_d",
1959         "scif2_data_e",
1960         "scif2_clk_a",
1961         "scif2_clk_b",
1962         "scif2_clk_c",
1963 };
1964
1965 static const char * const scif3_groups[] = {
1966         "scif3_data_a",
1967         "scif3_data_b",
1968         "scif3_data_c",
1969         "scif3_data_d",
1970 };
1971
1972 static const char * const scif4_groups[] = {
1973         "scif4_data_a",
1974         "scif4_data_b",
1975         "scif4_data_c",
1976 };
1977
1978 static const char * const scif5_groups[] = {
1979         "scif5_data_a",
1980         "scif5_data_b",
1981 };
1982
1983
1984 static const char * const sdhi0_groups[] = {
1985         "sdhi0_cd",
1986         "sdhi0_ctrl",
1987         "sdhi0_data1",
1988         "sdhi0_data4",
1989         "sdhi0_wp",
1990 };
1991
1992 static const char * const sdhi1_groups[] = {
1993         "sdhi1_cd_a",
1994         "sdhi1_cd_b",
1995         "sdhi1_ctrl_a",
1996         "sdhi1_ctrl_b",
1997         "sdhi1_data1_a",
1998         "sdhi1_data1_b",
1999         "sdhi1_data4_a",
2000         "sdhi1_data4_b",
2001         "sdhi1_wp_a",
2002         "sdhi1_wp_b",
2003 };
2004
2005 static const char * const sdhi2_groups[] = {
2006         "sdhi2_cd_a",
2007         "sdhi2_cd_b",
2008         "sdhi2_ctrl_a",
2009         "sdhi2_ctrl_b",
2010         "sdhi2_data1_a",
2011         "sdhi2_data1_b",
2012         "sdhi2_data4_a",
2013         "sdhi2_data4_b",
2014         "sdhi2_wp_a",
2015         "sdhi2_wp_b",
2016 };
2017
2018 static const char * const ssi_groups[] = {
2019         "ssi012_ctrl",
2020         "ssi0_data",
2021         "ssi1_a_ctrl",
2022         "ssi1_b_ctrl",
2023         "ssi1_data",
2024         "ssi2_a_ctrl",
2025         "ssi2_b_ctrl",
2026         "ssi2_data",
2027         "ssi34_ctrl",
2028         "ssi3_data",
2029         "ssi4_ctrl",
2030         "ssi4_data",
2031         "ssi5_ctrl",
2032         "ssi5_data",
2033         "ssi6_ctrl",
2034         "ssi6_data",
2035         "ssi78_ctrl",
2036         "ssi7_data",
2037         "ssi8_data",
2038 };
2039
2040 static const char * const usb0_groups[] = {
2041         "usb0",
2042         "usb0_ovc",
2043 };
2044
2045 static const char * const usb1_groups[] = {
2046         "usb1",
2047         "usb1_ovc",
2048 };
2049
2050 static const char * const vin0_groups[] = {
2051         "vin0_data8",
2052         "vin0_clk",
2053         "vin0_sync",
2054 };
2055
2056 static const char * const vin1_groups[] = {
2057         "vin1_data8",
2058         "vin1_clk",
2059         "vin1_sync",
2060 };
2061
2062 static const struct sh_pfc_function pinmux_functions[] = {
2063         SH_PFC_FUNCTION(audio_clk),
2064         SH_PFC_FUNCTION(can0),
2065         SH_PFC_FUNCTION(can1),
2066         SH_PFC_FUNCTION(ether),
2067         SH_PFC_FUNCTION(hscif0),
2068         SH_PFC_FUNCTION(hscif1),
2069         SH_PFC_FUNCTION(hspi0),
2070         SH_PFC_FUNCTION(hspi1),
2071         SH_PFC_FUNCTION(hspi2),
2072         SH_PFC_FUNCTION(i2c1),
2073         SH_PFC_FUNCTION(i2c2),
2074         SH_PFC_FUNCTION(i2c3),
2075         SH_PFC_FUNCTION(mmc),
2076         SH_PFC_FUNCTION(scif_clk),
2077         SH_PFC_FUNCTION(scif0),
2078         SH_PFC_FUNCTION(scif1),
2079         SH_PFC_FUNCTION(scif2),
2080         SH_PFC_FUNCTION(scif3),
2081         SH_PFC_FUNCTION(scif4),
2082         SH_PFC_FUNCTION(scif5),
2083         SH_PFC_FUNCTION(sdhi0),
2084         SH_PFC_FUNCTION(sdhi1),
2085         SH_PFC_FUNCTION(sdhi2),
2086         SH_PFC_FUNCTION(ssi),
2087         SH_PFC_FUNCTION(usb0),
2088         SH_PFC_FUNCTION(usb1),
2089         SH_PFC_FUNCTION(vin0),
2090         SH_PFC_FUNCTION(vin1),
2091 };
2092
2093 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2094         { PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1, GROUP(
2095                 GP_0_31_FN,     FN_IP1_14_11,
2096                 GP_0_30_FN,     FN_IP1_10_8,
2097                 GP_0_29_FN,     FN_IP1_7_5,
2098                 GP_0_28_FN,     FN_IP1_4_2,
2099                 GP_0_27_FN,     FN_IP1_1,
2100                 GP_0_26_FN,     FN_IP1_0,
2101                 GP_0_25_FN,     FN_IP0_30,
2102                 GP_0_24_FN,     FN_IP0_29,
2103                 GP_0_23_FN,     FN_IP0_28,
2104                 GP_0_22_FN,     FN_IP0_27,
2105                 GP_0_21_FN,     FN_IP0_26,
2106                 GP_0_20_FN,     FN_IP0_25,
2107                 GP_0_19_FN,     FN_IP0_24,
2108                 GP_0_18_FN,     FN_IP0_23,
2109                 GP_0_17_FN,     FN_IP0_22,
2110                 GP_0_16_FN,     FN_IP0_21,
2111                 GP_0_15_FN,     FN_IP0_20,
2112                 GP_0_14_FN,     FN_IP0_19,
2113                 GP_0_13_FN,     FN_IP0_18,
2114                 GP_0_12_FN,     FN_IP0_17,
2115                 GP_0_11_FN,     FN_IP0_16,
2116                 GP_0_10_FN,     FN_IP0_15,
2117                 GP_0_9_FN,      FN_A3,
2118                 GP_0_8_FN,      FN_A2,
2119                 GP_0_7_FN,      FN_A1,
2120                 GP_0_6_FN,      FN_IP0_14_12,
2121                 GP_0_5_FN,      FN_IP0_11_8,
2122                 GP_0_4_FN,      FN_IP0_7_5,
2123                 GP_0_3_FN,      FN_IP0_4_2,
2124                 GP_0_2_FN,      FN_PENC1,
2125                 GP_0_1_FN,      FN_PENC0,
2126                 GP_0_0_FN,      FN_IP0_1_0 ))
2127         },
2128         { PINMUX_CFG_REG("GPSR1", 0xfffc0008, 32, 1, GROUP(
2129                 GP_1_31_FN,     FN_IP4_6_4,
2130                 GP_1_30_FN,     FN_IP4_3_1,
2131                 GP_1_29_FN,     FN_IP4_0,
2132                 GP_1_28_FN,     FN_IP3_31,
2133                 GP_1_27_FN,     FN_IP3_30,
2134                 GP_1_26_FN,     FN_IP3_29,
2135                 GP_1_25_FN,     FN_IP3_28,
2136                 GP_1_24_FN,     FN_IP3_27,
2137                 GP_1_23_FN,     FN_IP3_26_24,
2138                 GP_1_22_FN,     FN_IP3_23_21,
2139                 GP_1_21_FN,     FN_IP3_20_19,
2140                 GP_1_20_FN,     FN_IP3_18_16,
2141                 GP_1_19_FN,     FN_IP3_15_13,
2142                 GP_1_18_FN,     FN_IP3_12_10,
2143                 GP_1_17_FN,     FN_IP3_9_8,
2144                 GP_1_16_FN,     FN_IP3_7_5,
2145                 GP_1_15_FN,     FN_IP3_4_2,
2146                 GP_1_14_FN,     FN_IP3_1_0,
2147                 GP_1_13_FN,     FN_IP2_31,
2148                 GP_1_12_FN,     FN_IP2_30,
2149                 GP_1_11_FN,     FN_IP2_17,
2150                 GP_1_10_FN,     FN_IP2_16_14,
2151                 GP_1_9_FN,      FN_IP2_13_12,
2152                 GP_1_8_FN,      FN_IP2_11_9,
2153                 GP_1_7_FN,      FN_IP2_8_6,
2154                 GP_1_6_FN,      FN_IP2_5_3,
2155                 GP_1_5_FN,      FN_IP2_2_0,
2156                 GP_1_4_FN,      FN_IP1_29_28,
2157                 GP_1_3_FN,      FN_IP1_27_25,
2158                 GP_1_2_FN,      FN_IP1_24,
2159                 GP_1_1_FN,      FN_WE0,
2160                 GP_1_0_FN,      FN_IP1_23_21 ))
2161         },
2162         { PINMUX_CFG_REG("GPSR2", 0xfffc000c, 32, 1, GROUP(
2163                 GP_2_31_FN,     FN_IP6_7,
2164                 GP_2_30_FN,     FN_IP6_6_5,
2165                 GP_2_29_FN,     FN_IP6_4_2,
2166                 GP_2_28_FN,     FN_IP6_1_0,
2167                 GP_2_27_FN,     FN_IP5_30_29,
2168                 GP_2_26_FN,     FN_IP5_28_26,
2169                 GP_2_25_FN,     FN_IP5_25_23,
2170                 GP_2_24_FN,     FN_IP5_22_21,
2171                 GP_2_23_FN,     FN_AUDIO_CLKB,
2172                 GP_2_22_FN,     FN_AUDIO_CLKA,
2173                 GP_2_21_FN,     FN_IP5_20_18,
2174                 GP_2_20_FN,     FN_IP5_17_15,
2175                 GP_2_19_FN,     FN_IP5_14_13,
2176                 GP_2_18_FN,     FN_IP5_12,
2177                 GP_2_17_FN,     FN_IP5_11_10,
2178                 GP_2_16_FN,     FN_IP5_9_8,
2179                 GP_2_15_FN,     FN_IP5_7,
2180                 GP_2_14_FN,     FN_IP5_6,
2181                 GP_2_13_FN,     FN_IP5_5_4,
2182                 GP_2_12_FN,     FN_IP5_3_2,
2183                 GP_2_11_FN,     FN_IP5_1_0,
2184                 GP_2_10_FN,     FN_IP4_30_29,
2185                 GP_2_9_FN,      FN_IP4_28_27,
2186                 GP_2_8_FN,      FN_IP4_26_25,
2187                 GP_2_7_FN,      FN_IP4_24_21,
2188                 GP_2_6_FN,      FN_IP4_20_17,
2189                 GP_2_5_FN,      FN_IP4_16_15,
2190                 GP_2_4_FN,      FN_IP4_14_13,
2191                 GP_2_3_FN,      FN_IP4_12_11,
2192                 GP_2_2_FN,      FN_IP4_10_9,
2193                 GP_2_1_FN,      FN_IP4_8,
2194                 GP_2_0_FN,      FN_IP4_7 ))
2195         },
2196         { PINMUX_CFG_REG("GPSR3", 0xfffc0010, 32, 1, GROUP(
2197                 GP_3_31_FN,     FN_IP8_10_9,
2198                 GP_3_30_FN,     FN_IP8_8_6,
2199                 GP_3_29_FN,     FN_IP8_5_3,
2200                 GP_3_28_FN,     FN_IP8_2_0,
2201                 GP_3_27_FN,     FN_IP7_31_29,
2202                 GP_3_26_FN,     FN_IP7_28_25,
2203                 GP_3_25_FN,     FN_IP7_24_22,
2204                 GP_3_24_FN,     FN_IP7_21,
2205                 GP_3_23_FN,     FN_IP7_20_18,
2206                 GP_3_22_FN,     FN_IP7_17_15,
2207                 GP_3_21_FN,     FN_IP7_14_12,
2208                 GP_3_20_FN,     FN_IP7_11_9,
2209                 GP_3_19_FN,     FN_IP7_8_6,
2210                 GP_3_18_FN,     FN_IP7_5_4,
2211                 GP_3_17_FN,     FN_IP7_3_2,
2212                 GP_3_16_FN,     FN_IP7_1_0,
2213                 GP_3_15_FN,     FN_IP6_31_30,
2214                 GP_3_14_FN,     FN_IP6_29_28,
2215                 GP_3_13_FN,     FN_IP6_27_26,
2216                 GP_3_12_FN,     FN_IP6_25_24,
2217                 GP_3_11_FN,     FN_IP6_23_22,
2218                 GP_3_10_FN,     FN_IP6_21,
2219                 GP_3_9_FN,      FN_IP6_20_19,
2220                 GP_3_8_FN,      FN_IP6_18_17,
2221                 GP_3_7_FN,      FN_IP6_16,
2222                 GP_3_6_FN,      FN_IP6_15_14,
2223                 GP_3_5_FN,      FN_IP6_13,
2224                 GP_3_4_FN,      FN_IP6_12_11,
2225                 GP_3_3_FN,      FN_IP6_10,
2226                 GP_3_2_FN,      FN_SSI_SCK34,
2227                 GP_3_1_FN,      FN_IP6_9,
2228                 GP_3_0_FN,      FN_IP6_8 ))
2229         },
2230         { PINMUX_CFG_REG("GPSR4", 0xfffc0014, 32, 1, GROUP(
2231                 0, 0,
2232                 0, 0,
2233                 0, 0,
2234                 0, 0,
2235                 0, 0,
2236                 GP_4_26_FN,     FN_AVS2,
2237                 GP_4_25_FN,     FN_AVS1,
2238                 GP_4_24_FN,     FN_IP10_24_22,
2239                 GP_4_23_FN,     FN_IP10_21_19,
2240                 GP_4_22_FN,     FN_IP10_18_16,
2241                 GP_4_21_FN,     FN_IP10_15_13,
2242                 GP_4_20_FN,     FN_IP10_12_9,
2243                 GP_4_19_FN,     FN_IP10_8_6,
2244                 GP_4_18_FN,     FN_IP10_5_3,
2245                 GP_4_17_FN,     FN_IP10_2_0,
2246                 GP_4_16_FN,     FN_IP9_29_27,
2247                 GP_4_15_FN,     FN_IP9_26_24,
2248                 GP_4_14_FN,     FN_IP9_23_21,
2249                 GP_4_13_FN,     FN_IP9_20_18,
2250                 GP_4_12_FN,     FN_IP9_17_15,
2251                 GP_4_11_FN,     FN_IP9_14_12,
2252                 GP_4_10_FN,     FN_IP9_11_9,
2253                 GP_4_9_FN,      FN_IP9_8_6,
2254                 GP_4_8_FN,      FN_IP9_5_3,
2255                 GP_4_7_FN,      FN_IP9_2_0,
2256                 GP_4_6_FN,      FN_IP8_29_27,
2257                 GP_4_5_FN,      FN_IP8_26_24,
2258                 GP_4_4_FN,      FN_IP8_23_22,
2259                 GP_4_3_FN,      FN_IP8_21_19,
2260                 GP_4_2_FN,      FN_IP8_18_16,
2261                 GP_4_1_FN,      FN_IP8_15_14,
2262                 GP_4_0_FN,      FN_IP8_13_11 ))
2263         },
2264
2265         { PINMUX_CFG_REG_VAR("IPSR0", 0xfffc0020, 32,
2266                              GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2267                                    1, 1, 1, 1, 1, 3, 4, 3, 3, 2),
2268                              GROUP(
2269                 /* IP0_31 [1] */
2270                 0,      0,
2271                 /* IP0_30 [1] */
2272                 FN_A19, 0,
2273                 /* IP0_29 [1] */
2274                 FN_A18, 0,
2275                 /* IP0_28 [1] */
2276                 FN_A17, 0,
2277                 /* IP0_27 [1] */
2278                 FN_A16, 0,
2279                 /* IP0_26 [1] */
2280                 FN_A15, 0,
2281                 /* IP0_25 [1] */
2282                 FN_A14, 0,
2283                 /* IP0_24 [1] */
2284                 FN_A13, 0,
2285                 /* IP0_23 [1] */
2286                 FN_A12, 0,
2287                 /* IP0_22 [1] */
2288                 FN_A11, 0,
2289                 /* IP0_21 [1] */
2290                 FN_A10, 0,
2291                 /* IP0_20 [1] */
2292                 FN_A9,  0,
2293                 /* IP0_19 [1] */
2294                 FN_A8,  0,
2295                 /* IP0_18 [1] */
2296                 FN_A7,  0,
2297                 /* IP0_17 [1] */
2298                 FN_A6,  0,
2299                 /* IP0_16 [1] */
2300                 FN_A5,  0,
2301                 /* IP0_15 [1] */
2302                 FN_A4,  0,
2303                 /* IP0_14_12 [3] */
2304                 FN_SD1_DAT3_A,  FN_MMC_D3,      0,              FN_A0,
2305                 FN_ATAG0_A,     0,              FN_REMOCON_B,   0,
2306                 /* IP0_11_8 [4] */
2307                 FN_SD1_DAT2_A,  FN_MMC_D2,      0,              FN_BS,
2308                 FN_ATADIR0_A,   0,              FN_SDSELF_A,    0,
2309                 FN_PWM4_B,      0,              0,              0,
2310                 0,              0,              0,              0,
2311                 /* IP0_7_5 [3] */
2312                 FN_AUDATA1,     FN_ARM_TRACEDATA_1,     FN_GPSIN_C,     FN_USB_OVC1,
2313                 FN_RX2_E,       FN_SCL2_B,              0,              0,
2314                 /* IP0_4_2 [3] */
2315                 FN_AUDATA0,     FN_ARM_TRACEDATA_0,     FN_GPSCLK_C,    FN_USB_OVC0,
2316                 FN_TX2_E,       FN_SDA2_B,              0,              0,
2317                 /* IP0_1_0 [2] */
2318                 FN_PRESETOUT,   0,      FN_PWM1,        0,
2319                 ))
2320         },
2321         { PINMUX_CFG_REG_VAR("IPSR1", 0xfffc0024, 32,
2322                              GROUP(1, 1, 2, 3, 1, 3, 3, 1, 2, 4, 3, 3,
2323                                    3, 1, 1),
2324                              GROUP(
2325                 /* IP1_31 [1] */
2326                 0,      0,
2327                 /* IP1_30 [1] */
2328                 0,      0,
2329                 /* IP1_29_28 [2] */
2330                 FN_EX_CS1,      FN_MMC_D4,      0,      0,
2331                 /* IP1_27_25 [3] */
2332                 FN_SSI_WS1_B,   FN_EX_CS0,      FN_SCL2_A,      FN_TX3_C,
2333                 FN_TS_SCK0_A,   0,              0,              0,
2334                 /* IP1_24 [1] */
2335                 FN_WE1,         FN_ATAWR0_B,
2336                 /* IP1_23_21 [3] */
2337                 FN_MMC_D5,      FN_ATADIR0_B,   0,              FN_RD_WR,
2338                 0,              0,              0,              0,
2339                 /* IP1_20_18 [3] */
2340                 FN_SSI_SCK1_B,  FN_ATAG0_B,     FN_CS1_A26,     FN_SDA2_A,
2341                 FN_SCK2_B,      0,              0,              0,
2342                 /* IP1_17 [1] */
2343                 FN_CS0,         FN_HSPI_RX1_B,
2344                 /* IP1_16_15 [2] */
2345                 FN_CLKOUT,      FN_HSPI_TX1_B,  FN_PWM0_B,      0,
2346                 /* IP1_14_11 [4] */
2347                 FN_SD1_WP_A,    FN_MMC_D7,      0,              FN_A25,
2348                 FN_DACK1_A,     0,              FN_HCTS0_B,     FN_RX3_C,
2349                 FN_TS_SDAT0_A,  0,              0,              0,
2350                 0,              0,              0,              0,
2351                 /* IP1_10_8 [3] */
2352                 FN_SD1_CD_A,    FN_MMC_D6,      0,              FN_A24,
2353                 FN_DREQ1_A,     0,              FN_HRX0_B,      FN_TS_SPSYNC0_A,
2354                 /* IP1_7_5 [3] */
2355                 FN_A23,         FN_HTX0_B,      FN_TX2_B,       FN_DACK2_A,
2356                 FN_TS_SDEN0_A,  0,              0,              0,
2357                 /* IP1_4_2 [3] */
2358                 FN_A22,         FN_HRTS0_B,     FN_RX2_B,       FN_DREQ2_A,
2359                 0,              0,              0,              0,
2360                 /* IP1_1 [1] */
2361                 FN_A21,         FN_HSPI_CLK1_B,
2362                 /* IP1_0 [1] */
2363                 FN_A20,         FN_HSPI_CS1_B,
2364                 ))
2365         },
2366         { PINMUX_CFG_REG_VAR("IPSR2", 0xfffc0028, 32,
2367                              GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2368                                    1, 1, 1, 3, 2, 3, 3, 3, 3),
2369                              GROUP(
2370                 /* IP2_31 [1] */
2371                 FN_MLB_CLK,     FN_IRQ1_A,
2372                 /* IP2_30 [1] */
2373                 FN_RD_WR_B,     FN_IRQ0,
2374                 /* IP2_29 [1] */
2375                 FN_D11,         0,
2376                 /* IP2_28 [1] */
2377                 FN_D10,         0,
2378                 /* IP2_27 [1] */
2379                 FN_D9,          0,
2380                 /* IP2_26 [1] */
2381                 FN_D8,          0,
2382                 /* IP2_25 [1] */
2383                 FN_D7,          0,
2384                 /* IP2_24 [1] */
2385                 FN_D6,          0,
2386                 /* IP2_23 [1] */
2387                 FN_D5,          0,
2388                 /* IP2_22 [1] */
2389                 FN_D4,          0,
2390                 /* IP2_21 [1] */
2391                 FN_D3,          0,
2392                 /* IP2_20 [1] */
2393                 FN_D2,          0,
2394                 /* IP2_19 [1] */
2395                 FN_D1,          0,
2396                 /* IP2_18 [1] */
2397                 FN_D0,          0,
2398                 /* IP2_17 [1] */
2399                 FN_EX_WAIT0,    FN_PWM0_C,
2400                 /* IP2_16_14 [3] */
2401                 FN_DACK0,       0,      0,      FN_TX3_A,
2402                 FN_DRACK0,      0,      0,      0,
2403                 /* IP2_13_12 [2] */
2404                 FN_DREQ0_A,     0,      0,      FN_RX3_A,
2405                 /* IP2_11_9 [3] */
2406                 FN_SD1_DAT1_A,  FN_MMC_D1,      0,      FN_ATAWR0_A,
2407                 FN_EX_CS5,      FN_EX_WAIT2_A,  0,      0,
2408                 /* IP2_8_6 [3] */
2409                 FN_SD1_DAT0_A,  FN_MMC_D0,      0,      FN_ATARD0,
2410                 FN_EX_CS4,      FN_EX_WAIT1_A,  0,      0,
2411                 /* IP2_5_3 [3] */
2412                 FN_SD1_CMD_A,   FN_MMC_CMD,     0,      FN_ATACS10,
2413                 FN_EX_CS3,      0,              0,      0,
2414                 /* IP2_2_0 [3] */
2415                 FN_SD1_CLK_A,   FN_MMC_CLK,     0,      FN_ATACS00,
2416                 FN_EX_CS2,      0,              0,      0,
2417                 ))
2418         },
2419         { PINMUX_CFG_REG_VAR("IPSR3", 0xfffc002c, 32,
2420                              GROUP(1, 1, 1, 1, 1, 3, 3, 2, 3, 3, 3, 2,
2421                                    3, 3, 2),
2422                              GROUP(
2423                 /* IP3_31 [1] */
2424                 FN_DU0_DR6,     FN_LCDOUT6,
2425                 /* IP3_30 [1] */
2426                 FN_DU0_DR5,     FN_LCDOUT5,
2427                 /* IP3_29 [1] */
2428                 FN_DU0_DR4,     FN_LCDOUT4,
2429                 /* IP3_28 [1] */
2430                 FN_DU0_DR3,     FN_LCDOUT3,
2431                 /* IP3_27 [1] */
2432                 FN_DU0_DR2,     FN_LCDOUT2,
2433                 /* IP3_26_24 [3] */
2434                 FN_SSI_WS4,             FN_DU0_DR1,     FN_LCDOUT1,     FN_AUDATA3,
2435                 FN_ARM_TRACEDATA_3,     FN_SCL3_C,      FN_ADICHS2,     FN_TS_SPSYNC0_B,
2436                 /* IP3_23_21 [3] */
2437                 FN_SSI_SCK4,            FN_DU0_DR0,     FN_LCDOUT0,     FN_AUDATA2,
2438                 FN_ARM_TRACEDATA_2,     FN_SDA3_C,      FN_ADICHS1,     FN_TS_SDEN0_B,
2439                 /* IP3_20_19 [2] */
2440                 FN_SD1_DAT3_B,  FN_HRTS0_A,     FN_RTS0,        0,
2441                 /* IP3_18_16 [3] */
2442                 FN_SD1_DAT2_B,  FN_HCTS0_A,     FN_CTS0,        0,
2443                 0,              0,              0,              0,
2444                 /* IP3_15_13 [3] */
2445                 FN_SD1_DAT1_B,  FN_HSCK0,       FN_SCK0,        FN_SCL3_B,
2446                 0,              0,              0,              0,
2447                 /* IP3_12_10 [3] */
2448                 FN_SD1_DAT0_B,  FN_HRX0_A,      FN_RX0_A,       0,
2449                 0,              0,              0,              0,
2450                 /* IP3_9_8 [2] */
2451                 FN_SD1_CLK_B,   FN_HTX0_A,      FN_TX0_A,       0,
2452                 /* IP3_7_5 [3] */
2453                 FN_SD1_CMD_B,   FN_SCIF_CLK,    FN_AUDIO_CLKOUT_B,      FN_CAN_CLK_B,
2454                 FN_SDA3_B,      0,              0,                      0,
2455                 /* IP3_4_2 [3] */
2456                 FN_MLB_DAT,     FN_TX5_B,       FN_SCL3_A,      FN_IRQ3_A,
2457                 FN_SDSELF_B,    0,              0,              0,
2458                 /* IP3_1_0 [2] */
2459                 FN_MLB_SIG,     FN_RX5_B,       FN_SDA3_A,      FN_IRQ2_A,
2460                 ))
2461         },
2462         { PINMUX_CFG_REG_VAR("IPSR4", 0xfffc0030, 32,
2463                              GROUP(1, 2, 2, 2, 4, 4, 2, 2, 2, 2, 1, 1,
2464                                    3, 3, 1),
2465                              GROUP(
2466                 /* IP4_31 [1] */
2467                 0,      0,
2468                 /* IP4_30_29 [2] */
2469                 FN_VI0_R4_B,    FN_DU0_DB4,     FN_LCDOUT20,    0,
2470                 /* IP4_28_27 [2] */
2471                 FN_VI0_R3_B,    FN_DU0_DB3,     FN_LCDOUT19,    0,
2472                 /* IP4_26_25 [2] */
2473                 FN_VI0_R2_B,    FN_DU0_DB2,     FN_LCDOUT18,    0,
2474                 /* IP4_24_21 [4] */
2475                 FN_AUDIO_CLKC,  FN_VI0_R1_B,            FN_DU0_DB1,     FN_LCDOUT17,
2476                 FN_AUDATA7,     FN_ARM_TRACEDATA_7,     FN_GPSIN_A,     0,
2477                 FN_ADICS_SAMP,  FN_TS_SCK0_B,           0,              0,
2478                 0,              0,                      0,              0,
2479                 /* IP4_20_17 [4] */
2480                 FN_SSI_SCK2_B,  FN_VI0_R0_B,            FN_DU0_DB0,     FN_LCDOUT16,
2481                 FN_AUDATA6,     FN_ARM_TRACEDATA_6,     FN_GPSCLK_A,    FN_PWM0_A,
2482                 FN_ADICLK,      FN_TS_SDAT0_B,          0,              0,
2483                 0,              0,                      0,              0,
2484                 /* IP4_16_15 [2] */
2485                 FN_DU0_DG7,     FN_LCDOUT15,    FN_TX4_A,       0,
2486                 /* IP4_14_13 [2] */
2487                 FN_DU0_DG6,     FN_LCDOUT14,    FN_RX4_A,       0,
2488                 /* IP4_12_11 [2] */
2489                 FN_DU0_DG5,     FN_LCDOUT13,    FN_TX0_B,       0,
2490                 /* IP4_10_9 [2] */
2491                 FN_DU0_DG4,     FN_LCDOUT12,    FN_RX0_B,       0,
2492                 /* IP4_8 [1] */
2493                 FN_DU0_DG3,     FN_LCDOUT11,
2494                 /* IP4_7 [1] */
2495                 FN_DU0_DG2,     FN_LCDOUT10,
2496                 /* IP4_6_4 [3] */
2497                 FN_DU0_DG1,     FN_LCDOUT9,     FN_AUDATA5,     FN_ARM_TRACEDATA_5,
2498                 FN_RX1_D,       FN_CAN0_RX_A,   FN_ADIDATA,     0,
2499                 /* IP4_3_1 [3] */
2500                 FN_DU0_DG0,     FN_LCDOUT8,     FN_AUDATA4,     FN_ARM_TRACEDATA_4,
2501                 FN_TX1_D,       FN_CAN0_TX_A,   FN_ADICHS0,     0,
2502                 /* IP4_0 [1] */
2503                 FN_DU0_DR7,     FN_LCDOUT7,
2504                 ))
2505         },
2506         { PINMUX_CFG_REG_VAR("IPSR5", 0xfffc0034, 32,
2507                              GROUP(1, 2, 3, 3, 2, 3, 3, 2, 1, 2, 2, 1,
2508                                    1, 2, 2, 2),
2509                              GROUP(
2510
2511                 /* IP5_31 [1] */
2512                 0, 0,
2513                 /* IP5_30_29 [2] */
2514                 FN_SSI_SDATA7,  FN_HSPI_TX0_B,  FN_RX2_A,       FN_CAN0_RX_B,
2515                 /* IP5_28_26 [3] */
2516                 FN_SSI_SDATA8,  FN_SSI_SCK2_A,  FN_HSPI_CS0_B,  FN_TX2_A,
2517                 FN_CAN0_TX_B,   0,              0,              0,
2518                 /* IP5_25_23 [3] */
2519                 FN_SD1_WP_B,    FN_SSI_WS78,    FN_HSPI_CLK0_B, FN_RX1_B,
2520                 FN_CAN_CLK_D,   0,              0,              0,
2521                 /* IP5_22_21 [2] */
2522                 FN_SD1_CD_B,    FN_SSI_SCK78,   FN_HSPI_RX0_B,  FN_TX1_B,
2523                 /* IP5_20_18 [3] */
2524                 FN_SSI_WS1_A,           FN_DU0_CDE,     FN_QPOLB,       FN_AUDSYNC,
2525                 FN_ARM_TRACECTL,        FN_FMIN_D,      0,              0,
2526                 /* IP5_17_15 [3] */
2527                 FN_SSI_SCK1_A,          FN_DU0_DISP,    FN_QPOLA,       FN_AUDCK,
2528                 FN_ARM_TRACECLK,        FN_BPFCLK_D,    0,              0,
2529                 /* IP5_14_13 [2] */
2530                 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE,        FN_QCPV_QDE,
2531                 FN_FMCLK_D,                             0,
2532                 /* IP5_12 [1] */
2533                 FN_DU0_EXVSYNC_DU0_VSYNC,       FN_QSTB_QHE,
2534                 /* IP5_11_10 [2] */
2535                 FN_SSI_WS2_B,   FN_DU0_EXHSYNC_DU0_HSYNC,
2536                 FN_QSTH_QHS,    0,
2537                 /* IP5_9_8 [2] */
2538                 FN_DU0_DOTCLKO_UT1,     FN_QSTVB_QVE,
2539                 FN_AUDIO_CLKOUT_A,      FN_REMOCON_C,
2540                 /* IP5_7 [1] */
2541                 FN_DU0_DOTCLKO_UT0,     FN_QCLK,
2542                 /* IP5_6 [1] */
2543                 FN_DU0_DOTCLKIN,        FN_QSTVA_QVS,
2544                 /* IP5_5_4 [2] */
2545                 FN_VI1_DATA11_B,        FN_DU0_DB7,     FN_LCDOUT23,    0,
2546                 /* IP5_3_2 [2] */
2547                 FN_VI1_DATA10_B,        FN_DU0_DB6,     FN_LCDOUT22,    0,
2548                 /* IP5_1_0 [2] */
2549                 FN_VI0_R5_B,            FN_DU0_DB5,     FN_LCDOUT21,    0,
2550                 ))
2551         },
2552         { PINMUX_CFG_REG_VAR("IPSR6", 0xfffc0038, 32,
2553                              GROUP(2, 2, 2, 2, 2, 1, 2, 2, 1, 2, 1, 2,
2554                                    1, 1, 1, 1, 2, 3, 2),
2555                              GROUP(
2556                 /* IP6_31_30 [2] */
2557                 FN_SD0_DAT2,    0,      FN_SUB_TDI,     0,
2558                 /* IP6_29_28 [2] */
2559                 FN_SD0_DAT1,    0,      FN_SUB_TCK,     0,
2560                 /* IP6_27_26 [2] */
2561                 FN_SD0_DAT0,    0,      FN_SUB_TMS,     0,
2562                 /* IP6_25_24 [2] */
2563                 FN_SD0_CMD,     0,      FN_SUB_TRST,    0,
2564                 /* IP6_23_22 [2] */
2565                 FN_SD0_CLK,     0,      FN_SUB_TDO,     0,
2566                 /* IP6_21 [1] */
2567                 FN_SSI_SDATA0,          FN_ARM_TRACEDATA_15,
2568                 /* IP6_20_19 [2] */
2569                 FN_SSI_SDATA1,          FN_ARM_TRACEDATA_14,
2570                 FN_SCL1_A,              FN_SCK2_A,
2571                 /* IP6_18_17 [2] */
2572                 FN_SSI_SDATA2,          FN_HSPI_CS2_A,
2573                 FN_ARM_TRACEDATA_13,    FN_SDA1_A,
2574                 /* IP6_16 [1] */
2575                 FN_SSI_WS012,           FN_ARM_TRACEDATA_12,
2576                 /* IP6_15_14 [2] */
2577                 FN_SSI_SCK012,          FN_ARM_TRACEDATA_11,
2578                 FN_TX0_D,               0,
2579                 /* IP6_13 [1] */
2580                 FN_SSI_SDATA3,          FN_ARM_TRACEDATA_10,
2581                 /* IP6_12_11 [2] */
2582                 FN_SSI_SDATA4,          FN_SSI_WS2_A,
2583                 FN_ARM_TRACEDATA_9,     0,
2584                 /* IP6_10 [1] */
2585                 FN_SSI_WS34,            FN_ARM_TRACEDATA_8,
2586                 /* IP6_9 [1] */
2587                 FN_SSI_SDATA5,          FN_RX0_D,
2588                 /* IP6_8 [1] */
2589                 FN_SSI_WS5,             FN_TX4_C,
2590                 /* IP6_7 [1] */
2591                 FN_SSI_SCK5,            FN_RX4_C,
2592                 /* IP6_6_5 [2] */
2593                 FN_SSI_SDATA6,          FN_HSPI_TX2_A,
2594                 FN_FMIN_B,              0,
2595                 /* IP6_4_2 [3] */
2596                 FN_SSI_WS6,             FN_HSPI_CLK2_A,
2597                 FN_BPFCLK_B,            FN_CAN1_RX_B,
2598                 0,      0,      0,      0,
2599                 /* IP6_1_0 [2] */
2600                 FN_SSI_SCK6,            FN_HSPI_RX2_A,
2601                 FN_FMCLK_B,             FN_CAN1_TX_B,
2602                 ))
2603         },
2604         { PINMUX_CFG_REG_VAR("IPSR7", 0xfffc003c, 32,
2605                              GROUP(3, 4, 3, 1, 3, 3, 3, 3, 3, 2, 2, 2),
2606                              GROUP(
2607
2608                 /* IP7_31_29 [3] */
2609                 FN_VI0_HSYNC,   FN_SD2_CD_B,    FN_VI1_DATA2,   FN_DU1_DR2,
2610                 0,              FN_HSPI_CS1_A,  FN_RX3_B,       0,
2611                 /* IP7_28_25 [4] */
2612                 FN_VI0_FIELD,   FN_SD2_DAT3_B,  FN_VI0_R3_C,    FN_VI1_DATA1,
2613                 FN_DU1_DG7,     0,              FN_HSPI_CLK1_A, FN_TX4_B,
2614                 0,      0,      0,      0,
2615                 0,      0,      0,      0,
2616                 /* IP7_24_22 [3] */
2617                 FN_VI0_CLKENB,  FN_SD2_DAT2_B,  FN_VI1_DATA0,   FN_DU1_DG6,
2618                 0,              FN_HSPI_RX1_A,  FN_RX4_B,       0,
2619                 /* IP7_21 [1] */
2620                 FN_VI0_CLK,     FN_CAN_CLK_A,
2621                 /* IP7_20_18 [3] */
2622                 FN_TCLK0,       FN_HSCK1_A,     FN_FMIN_A,      0,
2623                 FN_IRQ2_C,      FN_CTS1_C,      FN_SPEEDIN,     0,
2624                 /* IP7_17_15 [3] */
2625                 FN_VI1_VSYNC,   FN_HSPI_TX0,    FN_HCTS1_A,     FN_BPFCLK_A,
2626                 0,              FN_TX1_C,       0,              0,
2627                 /* IP7_14_12 [3] */
2628                 FN_VI1_HSYNC,   FN_HSPI_RX0_A,  FN_HRTS1_A,     FN_FMCLK_A,
2629                 0,              FN_RX1_C,       0,              0,
2630                 /* IP7_11_9 [3] */
2631                 FN_VI1_FIELD,   FN_HSPI_CS0_A,  FN_HRX1_A,      0,
2632                 FN_SCK1_C,      0,              0,              0,
2633                 /* IP7_8_6 [3] */
2634                 FN_VI1_CLKENB,  FN_HSPI_CLK0_A, FN_HTX1_A,      0,
2635                 FN_RTS1_C,      0,              0,              0,
2636                 /* IP7_5_4 [2] */
2637                 FN_SD0_WP,      0,              FN_RX5_A,       0,
2638                 /* IP7_3_2 [2] */
2639                 FN_SD0_CD,      0,              FN_TX5_A,       0,
2640                 /* IP7_1_0 [2] */
2641                 FN_SD0_DAT3,    0,              FN_IRQ1_B,      0,
2642                 ))
2643         },
2644         { PINMUX_CFG_REG_VAR("IPSR8", 0xfffc0040, 32,
2645                              GROUP(1, 1, 3, 3, 2, 3, 3, 2, 3, 2, 3, 3, 3),
2646                              GROUP(
2647                 /* IP8_31 [1] */
2648                 0, 0,
2649                 /* IP8_30 [1] */
2650                 0, 0,
2651                 /* IP8_29_27 [3] */
2652                 FN_VI0_G3,      FN_SD2_CMD_B,   FN_VI1_DATA5,   FN_DU1_DR5,
2653                 0,              FN_HRX1_B,      0,              0,
2654                 /* IP8_26_24 [3] */
2655                 FN_VI0_G2,      FN_SD2_CLK_B,   FN_VI1_DATA4,   FN_DU1_DR4,
2656                 0,              FN_HTX1_B,      0,              0,
2657                 /* IP8_23_22 [2] */
2658                 FN_VI0_DATA7_VI0_G1,    FN_DU1_DB5,
2659                 FN_RTS1_A,              0,
2660                 /* IP8_21_19 [3] */
2661                 FN_VI0_DATA6_VI0_G0,    FN_DU1_DB4,
2662                 FN_CTS1_A,              FN_PWM5,
2663                 0,      0,      0,      0,
2664                 /* IP8_18_16 [3] */
2665                 FN_VI0_DATA5_VI0_B5,    FN_DU1_DB3,     FN_SCK1_A,      FN_PWM4,
2666                 0,                      FN_HSCK1_B,     0,              0,
2667                 /* IP8_15_14 [2] */
2668                 FN_VI0_DATA4_VI0_B4,    FN_DU1_DB2,     FN_RX1_A,       0,
2669                 /* IP8_13_11 [3] */
2670                 FN_VI0_DATA3_VI0_B3,    FN_DU1_DG5,     FN_TX1_A,       FN_TX0_C,
2671                 0,                       0,             0,              0,
2672                 /* IP8_10_9 [2] */
2673                 FN_VI0_DATA2_VI0_B2,    FN_DU1_DG4,     FN_RX0_C,       0,
2674                 /* IP8_8_6 [3] */
2675                 FN_VI0_DATA1_VI0_B1,    FN_DU1_DG3,     FN_IRQ3_B,      FN_TX3_D,
2676                 0,                       0,             0,              0,
2677                 /* IP8_5_3 [3] */
2678                 FN_VI0_DATA0_VI0_B0,    FN_DU1_DG2,     FN_IRQ2_B,      FN_RX3_D,
2679                 0,                       0,             0,              0,
2680                 /* IP8_2_0 [3] */
2681                 FN_VI0_VSYNC,           FN_SD2_WP_B,    FN_VI1_DATA3,   FN_DU1_DR3,
2682                 0,                      FN_HSPI_TX1_A,  FN_TX3_B,       0,
2683                 ))
2684         },
2685         { PINMUX_CFG_REG_VAR("IPSR9", 0xfffc0044, 32,
2686                              GROUP(1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3),
2687                              GROUP(
2688                 /* IP9_31 [1] */
2689                 0, 0,
2690                 /* IP9_30 [1] */
2691                 0, 0,
2692                 /* IP9_29_27 [3] */
2693                 FN_VI1_DATA11_A,        FN_DU1_EXHSYNC_DU1_HSYNC,
2694                 FN_ETH_RXD1,            FN_FMIN_C,
2695                 0,                      FN_RX2_D,
2696                 FN_SCL2_C,              0,
2697                 /* IP9_26_24 [3] */
2698                 FN_VI1_DATA10_A,        FN_DU1_DOTCLKOUT,
2699                 FN_ETH_RXD0,            FN_BPFCLK_C,
2700                 0,                      FN_TX2_D,
2701                 FN_SDA2_C,              0,
2702                 /* IP9_23_21 [3] */
2703                 FN_VI0_R5_A,    0,              FN_ETH_RX_ER,   FN_FMCLK_C,
2704                 FN_IERX,        FN_RX2_C,       0,              0,
2705                 /* IP9_20_18 [3] */
2706                 FN_VI0_R4_A,    FN_ETH_TX_EN,   0,              0,
2707                 FN_IETX,        FN_TX2_C,       0,              0,
2708                 /* IP9_17_15 [3] */
2709                 FN_VI0_R3_A,    FN_ETH_CRS_DV,  0,              FN_IECLK,
2710                 FN_SCK2_C,      0,              0,              0,
2711                 /* IP9_14_12 [3] */
2712                 FN_VI0_R2_A,    FN_VI1_DATA9,   FN_DU1_DB7,     FN_ETH_TXD1,
2713                 0,              FN_PWM3,        0,              0,
2714                 /* IP9_11_9 [3] */
2715                 FN_VI0_R1_A,    FN_VI1_DATA8,   FN_DU1_DB6,     FN_ETH_TXD0,
2716                 0,              FN_PWM2,        FN_TCLK1,       0,
2717                 /* IP9_8_6 [3] */
2718                 FN_VI0_R0_A,    FN_VI1_CLK,     FN_ETH_REF_CLK, FN_DU1_DOTCLKIN,
2719                 0,              0,              0,              0,
2720                 /* IP9_5_3 [3] */
2721                 FN_VI0_G5,      FN_SD2_DAT1_B,  FN_VI1_DATA7,   FN_DU1_DR7,
2722                 0,              FN_HCTS1_B,     0,              0,
2723                 /* IP9_2_0 [3] */
2724                 FN_VI0_G4,      FN_SD2_DAT0_B,  FN_VI1_DATA6,   FN_DU1_DR6,
2725                 0,              FN_HRTS1_B,     0,              0,
2726                 ))
2727         },
2728         { PINMUX_CFG_REG_VAR("IPSR10", 0xfffc0048, 32,
2729                              GROUP(1, 1, 1, 1, 1, 1, 1, 3, 3, 3, 3, 4,
2730                                    3, 3, 3),
2731                              GROUP(
2732
2733                 /* IP10_31 [1] */
2734                 0, 0,
2735                 /* IP10_30 [1] */
2736                 0, 0,
2737                 /* IP10_29 [1] */
2738                 0, 0,
2739                 /* IP10_28 [1] */
2740                 0, 0,
2741                 /* IP10_27 [1] */
2742                 0, 0,
2743                 /* IP10_26 [1] */
2744                 0, 0,
2745                 /* IP10_25 [1] */
2746                 0, 0,
2747                 /* IP10_24_22 [3] */
2748                 FN_SD2_WP_A,    FN_VI1_DATA15,  FN_EX_WAIT2_B,  FN_DACK0_B,
2749                 FN_HSPI_TX2_B,  FN_CAN_CLK_C,   0,              0,
2750                 /* IP10_21_19 [3] */
2751                 FN_SD2_CD_A,    FN_VI1_DATA14,  FN_EX_WAIT1_B,  FN_DREQ0_B,
2752                 FN_HSPI_RX2_B,  FN_REMOCON_A,   0,              0,
2753                 /* IP10_18_16 [3] */
2754                 FN_SD2_DAT3_A,  FN_VI1_DATA13,  FN_DACK2_B,     FN_ATAG1,
2755                 FN_HSPI_CS2_B,  FN_GPSIN_B,     0,              0,
2756                 /* IP10_15_13 [3] */
2757                 FN_SD2_DAT2_A,  FN_VI1_DATA12,  FN_DREQ2_B,     FN_ATADIR1,
2758                 FN_HSPI_CLK2_B, FN_GPSCLK_B,    0,              0,
2759                 /* IP10_12_9 [4] */
2760                 FN_SD2_DAT1_A,  FN_DU1_CDE,     FN_ATACS11,     FN_DACK1_B,
2761                 FN_ETH_MAGIC,   FN_CAN1_TX_A,   0,              FN_PWM6,
2762                 0, 0, 0, 0,
2763                 0, 0, 0, 0,
2764                 /* IP10_8_6 [3] */
2765                 FN_SD2_DAT0_A,  FN_DU1_DISP,    FN_ATACS01,     FN_DREQ1_B,
2766                 FN_ETH_LINK,    FN_CAN1_RX_A,   0,              0,
2767                 /* IP10_5_3 [3] */
2768                 FN_SD2_CMD_A,   FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
2769                 FN_ATAWR1,      FN_ETH_MDIO,
2770                 FN_SCL1_B,      0,
2771                 0,              0,
2772                 /* IP10_2_0 [3] */
2773                 FN_SD2_CLK_A,   FN_DU1_EXVSYNC_DU1_VSYNC,
2774                 FN_ATARD1,      FN_ETH_MDC,
2775                 FN_SDA1_B,      0,
2776                 0,              0,
2777                 ))
2778         },
2779         { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xfffc0050, 32,
2780                              GROUP(1, 1, 2, 2, 3, 2, 2, 1, 1, 1, 1, 2,
2781                                    1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1),
2782                              GROUP(
2783
2784                 /* SEL 31  [1] */
2785                 0, 0,
2786                 /* SEL_30 (SCIF5) [1] */
2787                 FN_SEL_SCIF5_A,         FN_SEL_SCIF5_B,
2788                 /* SEL_29_28 (SCIF4) [2] */
2789                 FN_SEL_SCIF4_A,         FN_SEL_SCIF4_B,
2790                 FN_SEL_SCIF4_C,         0,
2791                 /* SEL_27_26 (SCIF3) [2] */
2792                 FN_SEL_SCIF3_A,         FN_SEL_SCIF3_B,
2793                 FN_SEL_SCIF3_C,         FN_SEL_SCIF3_D,
2794                 /* SEL_25_23 (SCIF2) [3] */
2795                 FN_SEL_SCIF2_A,         FN_SEL_SCIF2_B,
2796                 FN_SEL_SCIF2_C,         FN_SEL_SCIF2_D,
2797                 FN_SEL_SCIF2_E,         0,
2798                 0,                      0,
2799                 /* SEL_22_21 (SCIF1) [2] */
2800                 FN_SEL_SCIF1_A,         FN_SEL_SCIF1_B,
2801                 FN_SEL_SCIF1_C,         FN_SEL_SCIF1_D,
2802                 /* SEL_20_19 (SCIF0) [2] */
2803                 FN_SEL_SCIF0_A,         FN_SEL_SCIF0_B,
2804                 FN_SEL_SCIF0_C,         FN_SEL_SCIF0_D,
2805                 /* SEL_18 [1] */
2806                 0, 0,
2807                 /* SEL_17 (SSI2) [1] */
2808                 FN_SEL_SSI2_A,          FN_SEL_SSI2_B,
2809                 /* SEL_16 (SSI1) [1] */
2810                 FN_SEL_SSI1_A,          FN_SEL_SSI1_B,
2811                 /* SEL_15 (VI1) [1] */
2812                 FN_SEL_VI1_A,           FN_SEL_VI1_B,
2813                 /* SEL_14_13 (VI0) [2] */
2814                 FN_SEL_VI0_A,           FN_SEL_VI0_B,
2815                 FN_SEL_VI0_C,           FN_SEL_VI0_D,
2816                 /* SEL_12 [1] */
2817                 0, 0,
2818                 /* SEL_11 (SD2) [1] */
2819                 FN_SEL_SD2_A,           FN_SEL_SD2_B,
2820                 /* SEL_10 (SD1) [1] */
2821                 FN_SEL_SD1_A,           FN_SEL_SD1_B,
2822                 /* SEL_9 (IRQ3) [1] */
2823                 FN_SEL_IRQ3_A,          FN_SEL_IRQ3_B,
2824                 /* SEL_8_7 (IRQ2) [2] */
2825                 FN_SEL_IRQ2_A,          FN_SEL_IRQ2_B,
2826                 FN_SEL_IRQ2_C,          0,
2827                 /* SEL_6 (IRQ1) [1] */
2828                 FN_SEL_IRQ1_A,          FN_SEL_IRQ1_B,
2829                 /* SEL_5 [1] */
2830                 0, 0,
2831                 /* SEL_4 (DREQ2) [1] */
2832                 FN_SEL_DREQ2_A,         FN_SEL_DREQ2_B,
2833                 /* SEL_3 (DREQ1) [1] */
2834                 FN_SEL_DREQ1_A,         FN_SEL_DREQ1_B,
2835                 /* SEL_2 (DREQ0) [1] */
2836                 FN_SEL_DREQ0_A,         FN_SEL_DREQ0_B,
2837                 /* SEL_1 (WAIT2) [1] */
2838                 FN_SEL_WAIT2_A,         FN_SEL_WAIT2_B,
2839                 /* SEL_0 (WAIT1) [1] */
2840                 FN_SEL_WAIT1_A,         FN_SEL_WAIT1_B,
2841                 ))
2842         },
2843         { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xfffc0054, 32,
2844                              GROUP(1, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1,
2845                                    1, 1, 1, 1, 2, 2, 2, 1, 1, 1, 1, 2, 2, 1),
2846                              GROUP(
2847
2848                 /* SEL_31 [1] */
2849                 0, 0,
2850                 /* SEL_30 [1] */
2851                 0, 0,
2852                 /* SEL_29 [1] */
2853                 0, 0,
2854                 /* SEL_28 [1] */
2855                 0, 0,
2856                 /* SEL_27 (CAN1) [1] */
2857                 FN_SEL_CAN1_A,          FN_SEL_CAN1_B,
2858                 /* SEL_26 (CAN0) [1] */
2859                 FN_SEL_CAN0_A,          FN_SEL_CAN0_B,
2860                 /* SEL_25_24 (CANCLK) [2] */
2861                 FN_SEL_CANCLK_A,        FN_SEL_CANCLK_B,
2862                 FN_SEL_CANCLK_C,        FN_SEL_CANCLK_D,
2863                 /* SEL_23 (HSCIF1) [1] */
2864                 FN_SEL_HSCIF1_A,        FN_SEL_HSCIF1_B,
2865                 /* SEL_22 (HSCIF0) [1] */
2866                 FN_SEL_HSCIF0_A,        FN_SEL_HSCIF0_B,
2867                 /* SEL_21 [1] */
2868                 0, 0,
2869                 /* SEL_20 [1] */
2870                 0, 0,
2871                 /* SEL_19 [1] */
2872                 0, 0,
2873                 /* SEL_18 [1] */
2874                 0, 0,
2875                 /* SEL_17 [1] */
2876                 0, 0,
2877                 /* SEL_16 [1] */
2878                 0, 0,
2879                 /* SEL_15 [1] */
2880                 0, 0,
2881                 /* SEL_14_13 (REMOCON) [2] */
2882                 FN_SEL_REMOCON_A,       FN_SEL_REMOCON_B,
2883                 FN_SEL_REMOCON_C,       0,
2884                 /* SEL_12_11 (FM) [2] */
2885                 FN_SEL_FM_A,            FN_SEL_FM_B,
2886                 FN_SEL_FM_C,            FN_SEL_FM_D,
2887                 /* SEL_10_9 (GPS) [2] */
2888                 FN_SEL_GPS_A,           FN_SEL_GPS_B,
2889                 FN_SEL_GPS_C,           0,
2890                 /* SEL_8 (TSIF0) [1] */
2891                 FN_SEL_TSIF0_A,         FN_SEL_TSIF0_B,
2892                 /* SEL_7 (HSPI2) [1] */
2893                 FN_SEL_HSPI2_A,         FN_SEL_HSPI2_B,
2894                 /* SEL_6 (HSPI1) [1] */
2895                 FN_SEL_HSPI1_A,         FN_SEL_HSPI1_B,
2896                 /* SEL_5 (HSPI0) [1] */
2897                 FN_SEL_HSPI0_A,         FN_SEL_HSPI0_B,
2898                 /* SEL_4_3 (I2C3) [2] */
2899                 FN_SEL_I2C3_A,          FN_SEL_I2C3_B,
2900                 FN_SEL_I2C3_C,          0,
2901                 /* SEL_2_1 (I2C2) [2] */
2902                 FN_SEL_I2C2_A,          FN_SEL_I2C2_B,
2903                 FN_SEL_I2C2_C,          0,
2904                 /* SEL_0 (I2C1) [1] */
2905                 FN_SEL_I2C1_A,          FN_SEL_I2C1_B,
2906                 ))
2907         },
2908         { },
2909 };
2910
2911 static const struct pinmux_bias_reg pinmux_bias_regs[] = {
2912         { PINMUX_BIAS_REG("PUPR0", 0x100, "N/A", 0) {
2913                 [ 0] = RCAR_GP_PIN(0,  6),      /* A0 */
2914                 [ 1] = RCAR_GP_PIN(0,  7),      /* A1 */
2915                 [ 2] = RCAR_GP_PIN(0,  8),      /* A2 */
2916                 [ 3] = RCAR_GP_PIN(0,  9),      /* A3 */
2917                 [ 4] = RCAR_GP_PIN(0, 10),      /* A4 */
2918                 [ 5] = RCAR_GP_PIN(0, 11),      /* A5 */
2919                 [ 6] = RCAR_GP_PIN(0, 12),      /* A6 */
2920                 [ 7] = RCAR_GP_PIN(0, 13),      /* A7 */
2921                 [ 8] = RCAR_GP_PIN(0, 14),      /* A8 */
2922                 [ 9] = RCAR_GP_PIN(0, 15),      /* A9 */
2923                 [10] = RCAR_GP_PIN(0, 16),      /* A10 */
2924                 [11] = RCAR_GP_PIN(0, 17),      /* A11 */
2925                 [12] = RCAR_GP_PIN(0, 18),      /* A12 */
2926                 [13] = RCAR_GP_PIN(0, 19),      /* A13 */
2927                 [14] = RCAR_GP_PIN(0, 20),      /* A14 */
2928                 [15] = RCAR_GP_PIN(0, 21),      /* A15 */
2929                 [16] = RCAR_GP_PIN(0, 22),      /* A16 */
2930                 [17] = RCAR_GP_PIN(0, 23),      /* A17 */
2931                 [18] = RCAR_GP_PIN(0, 24),      /* A18 */
2932                 [19] = RCAR_GP_PIN(0, 25),      /* A19 */
2933                 [20] = RCAR_GP_PIN(0, 26),      /* A20 */
2934                 [21] = RCAR_GP_PIN(0, 27),      /* A21 */
2935                 [22] = RCAR_GP_PIN(0, 28),      /* A22 */
2936                 [23] = RCAR_GP_PIN(0, 29),      /* A23 */
2937                 [24] = RCAR_GP_PIN(0, 30),      /* A24 */
2938                 [25] = RCAR_GP_PIN(0, 31),      /* A25 */
2939                 [26] = RCAR_GP_PIN(1,  3),      /* /EX_CS0 */
2940                 [27] = RCAR_GP_PIN(1,  4),      /* /EX_CS1 */
2941                 [28] = RCAR_GP_PIN(1,  5),      /* /EX_CS2 */
2942                 [29] = RCAR_GP_PIN(1,  6),      /* /EX_CS3 */
2943                 [30] = RCAR_GP_PIN(1,  7),      /* /EX_CS4 */
2944                 [31] = RCAR_GP_PIN(1,  8),      /* /EX_CS5 */
2945         } },
2946         { PINMUX_BIAS_REG("PUPR1", 0x104, "N/A", 0) {
2947                 [ 0] = RCAR_GP_PIN(0,  0),      /* /PRESETOUT   */
2948                 [ 1] = RCAR_GP_PIN(0,  5),      /* /BS          */
2949                 [ 2] = RCAR_GP_PIN(1,  0),      /* RD//WR       */
2950                 [ 3] = RCAR_GP_PIN(1,  1),      /* /WE0         */
2951                 [ 4] = RCAR_GP_PIN(1,  2),      /* /WE1         */
2952                 [ 5] = RCAR_GP_PIN(1, 11),      /* EX_WAIT0     */
2953                 [ 6] = RCAR_GP_PIN(1,  9),      /* DREQ0        */
2954                 [ 7] = RCAR_GP_PIN(1, 10),      /* DACK0        */
2955                 [ 8] = RCAR_GP_PIN(1, 12),      /* IRQ0         */
2956                 [ 9] = RCAR_GP_PIN(1, 13),      /* IRQ1         */
2957                 [10] = SH_PFC_PIN_NONE,
2958                 [11] = SH_PFC_PIN_NONE,
2959                 [12] = SH_PFC_PIN_NONE,
2960                 [13] = SH_PFC_PIN_NONE,
2961                 [14] = SH_PFC_PIN_NONE,
2962                 [15] = SH_PFC_PIN_NONE,
2963                 [16] = SH_PFC_PIN_NONE,
2964                 [17] = SH_PFC_PIN_NONE,
2965                 [18] = SH_PFC_PIN_NONE,
2966                 [19] = SH_PFC_PIN_NONE,
2967                 [20] = SH_PFC_PIN_NONE,
2968                 [21] = SH_PFC_PIN_NONE,
2969                 [22] = SH_PFC_PIN_NONE,
2970                 [23] = SH_PFC_PIN_NONE,
2971                 [24] = SH_PFC_PIN_NONE,
2972                 [25] = SH_PFC_PIN_NONE,
2973                 [26] = SH_PFC_PIN_NONE,
2974                 [27] = SH_PFC_PIN_NONE,
2975                 [28] = SH_PFC_PIN_NONE,
2976                 [29] = SH_PFC_PIN_NONE,
2977                 [30] = SH_PFC_PIN_NONE,
2978                 [31] = SH_PFC_PIN_NONE,
2979         } },
2980         { PINMUX_BIAS_REG("PUPR2", 0x108, "N/A", 0) {
2981                 [ 0] = RCAR_GP_PIN(1, 22),      /* DU0_DR0      */
2982                 [ 1] = RCAR_GP_PIN(1, 23),      /* DU0_DR1      */
2983                 [ 2] = RCAR_GP_PIN(1, 24),      /* DU0_DR2      */
2984                 [ 3] = RCAR_GP_PIN(1, 25),      /* DU0_DR3      */
2985                 [ 4] = RCAR_GP_PIN(1, 26),      /* DU0_DR4      */
2986                 [ 5] = RCAR_GP_PIN(1, 27),      /* DU0_DR5      */
2987                 [ 6] = RCAR_GP_PIN(1, 28),      /* DU0_DR6      */
2988                 [ 7] = RCAR_GP_PIN(1, 29),      /* DU0_DR7      */
2989                 [ 8] = RCAR_GP_PIN(1, 30),      /* DU0_DG0      */
2990                 [ 9] = RCAR_GP_PIN(1, 31),      /* DU0_DG1      */
2991                 [10] = RCAR_GP_PIN(2,  0),      /* DU0_DG2      */
2992                 [11] = RCAR_GP_PIN(2,  1),      /* DU0_DG3      */
2993                 [12] = RCAR_GP_PIN(2,  2),      /* DU0_DG4      */
2994                 [13] = RCAR_GP_PIN(2,  3),      /* DU0_DG5      */
2995                 [14] = RCAR_GP_PIN(2,  4),      /* DU0_DG6      */
2996                 [15] = RCAR_GP_PIN(2,  5),      /* DU0_DG7      */
2997                 [16] = RCAR_GP_PIN(2,  6),      /* DU0_DB0      */
2998                 [17] = RCAR_GP_PIN(2,  7),      /* DU0_DB1      */
2999                 [18] = RCAR_GP_PIN(2,  8),      /* DU0_DB2      */
3000                 [19] = RCAR_GP_PIN(2,  9),      /* DU0_DB3      */
3001                 [20] = RCAR_GP_PIN(2, 10),      /* DU0_DB4      */
3002                 [21] = RCAR_GP_PIN(2, 11),      /* DU0_DB5      */
3003                 [22] = RCAR_GP_PIN(2, 12),      /* DU0_DB6      */
3004                 [23] = RCAR_GP_PIN(2, 13),      /* DU0_DB7      */
3005                 [24] = RCAR_GP_PIN(2, 14),      /* DU0_DOTCLKIN */
3006                 [25] = RCAR_GP_PIN(2, 15),      /* DU0_DOTCLKOUT0 */
3007                 [26] = RCAR_GP_PIN(2, 17),      /* DU0_HSYNC    */
3008                 [27] = RCAR_GP_PIN(2, 18),      /* DU0_VSYNC    */
3009                 [28] = RCAR_GP_PIN(2, 19),      /* DU0_EXODDF   */
3010                 [29] = RCAR_GP_PIN(2, 20),      /* DU0_DISP     */
3011                 [30] = RCAR_GP_PIN(2, 21),      /* DU0_CDE      */
3012                 [31] = RCAR_GP_PIN(2, 16),      /* DU0_DOTCLKOUT1 */
3013         } },
3014         { PINMUX_BIAS_REG("PUPR3", 0x10c, "N/A", 0) {
3015                 [ 0] = RCAR_GP_PIN(3, 24),      /* VI0_CLK      */
3016                 [ 1] = RCAR_GP_PIN(3, 25),      /* VI0_CLKENB   */
3017                 [ 2] = RCAR_GP_PIN(3, 26),      /* VI0_FIELD    */
3018                 [ 3] = RCAR_GP_PIN(3, 27),      /* /VI0_HSYNC   */
3019                 [ 4] = RCAR_GP_PIN(3, 28),      /* /VI0_VSYNC   */
3020                 [ 5] = RCAR_GP_PIN(3, 29),      /* VI0_DATA0    */
3021                 [ 6] = RCAR_GP_PIN(3, 30),      /* VI0_DATA1    */
3022                 [ 7] = RCAR_GP_PIN(3, 31),      /* VI0_DATA2    */
3023                 [ 8] = RCAR_GP_PIN(4,  0),      /* VI0_DATA3    */
3024                 [ 9] = RCAR_GP_PIN(4,  1),      /* VI0_DATA4    */
3025                 [10] = RCAR_GP_PIN(4,  2),      /* VI0_DATA5    */
3026                 [11] = RCAR_GP_PIN(4,  3),      /* VI0_DATA6    */
3027                 [12] = RCAR_GP_PIN(4,  4),      /* VI0_DATA7    */
3028                 [13] = RCAR_GP_PIN(4,  5),      /* VI0_G2       */
3029                 [14] = RCAR_GP_PIN(4,  6),      /* VI0_G3       */
3030                 [15] = RCAR_GP_PIN(4,  7),      /* VI0_G4       */
3031                 [16] = RCAR_GP_PIN(4,  8),      /* VI0_G5       */
3032                 [17] = RCAR_GP_PIN(4, 21),      /* VI1_DATA12   */
3033                 [18] = RCAR_GP_PIN(4, 22),      /* VI1_DATA13   */
3034                 [19] = RCAR_GP_PIN(4, 23),      /* VI1_DATA14   */
3035                 [20] = RCAR_GP_PIN(4, 24),      /* VI1_DATA15   */
3036                 [21] = RCAR_GP_PIN(4,  9),      /* ETH_REF_CLK  */
3037                 [22] = RCAR_GP_PIN(4, 10),      /* ETH_TXD0     */
3038                 [23] = RCAR_GP_PIN(4, 11),      /* ETH_TXD1     */
3039                 [24] = RCAR_GP_PIN(4, 12),      /* ETH_CRS_DV   */
3040                 [25] = RCAR_GP_PIN(4, 13),      /* ETH_TX_EN    */
3041                 [26] = RCAR_GP_PIN(4, 14),      /* ETH_RX_ER    */
3042                 [27] = RCAR_GP_PIN(4, 15),      /* ETH_RXD0     */
3043                 [28] = RCAR_GP_PIN(4, 16),      /* ETH_RXD1     */
3044                 [29] = RCAR_GP_PIN(4, 17),      /* ETH_MDC      */
3045                 [30] = RCAR_GP_PIN(4, 18),      /* ETH_MDIO     */
3046                 [31] = RCAR_GP_PIN(4, 19),      /* ETH_LINK     */
3047         } },
3048         { PINMUX_BIAS_REG("PUPR4", 0x110, "N/A", 0) {
3049                 [ 0] = RCAR_GP_PIN(3,  6),      /* SSI_SCK012   */
3050                 [ 1] = RCAR_GP_PIN(3,  7),      /* SSI_WS012    */
3051                 [ 2] = RCAR_GP_PIN(3, 10),      /* SSI_SDATA0   */
3052                 [ 3] = RCAR_GP_PIN(3,  9),      /* SSI_SDATA1   */
3053                 [ 4] = RCAR_GP_PIN(3,  8),      /* SSI_SDATA2   */
3054                 [ 5] = RCAR_GP_PIN(3,  2),      /* SSI_SCK34    */
3055                 [ 6] = RCAR_GP_PIN(3,  3),      /* SSI_WS34     */
3056                 [ 7] = RCAR_GP_PIN(3,  5),      /* SSI_SDATA3   */
3057                 [ 8] = RCAR_GP_PIN(3,  4),      /* SSI_SDATA4   */
3058                 [ 9] = RCAR_GP_PIN(2, 31),      /* SSI_SCK5     */
3059                 [10] = RCAR_GP_PIN(3,  0),      /* SSI_WS5      */
3060                 [11] = RCAR_GP_PIN(3,  1),      /* SSI_SDATA5   */
3061                 [12] = RCAR_GP_PIN(2, 28),      /* SSI_SCK6     */
3062                 [13] = RCAR_GP_PIN(2, 29),      /* SSI_WS6      */
3063                 [14] = RCAR_GP_PIN(2, 30),      /* SSI_SDATA6   */
3064                 [15] = RCAR_GP_PIN(2, 24),      /* SSI_SCK78    */
3065                 [16] = RCAR_GP_PIN(2, 25),      /* SSI_WS78     */
3066                 [17] = RCAR_GP_PIN(2, 27),      /* SSI_SDATA7   */
3067                 [18] = RCAR_GP_PIN(2, 26),      /* SSI_SDATA8   */
3068                 [19] = RCAR_GP_PIN(3, 23),      /* TCLK0        */
3069                 [20] = RCAR_GP_PIN(3, 11),      /* SD0_CLK      */
3070                 [21] = RCAR_GP_PIN(3, 12),      /* SD0_CMD      */
3071                 [22] = RCAR_GP_PIN(3, 13),      /* SD0_DAT0     */
3072                 [23] = RCAR_GP_PIN(3, 14),      /* SD0_DAT1     */
3073                 [24] = RCAR_GP_PIN(3, 15),      /* SD0_DAT2     */
3074                 [25] = RCAR_GP_PIN(3, 16),      /* SD0_DAT3     */
3075                 [26] = RCAR_GP_PIN(3, 17),      /* SD0_CD       */
3076                 [27] = RCAR_GP_PIN(3, 18),      /* SD0_WP       */
3077                 [28] = RCAR_GP_PIN(2, 22),      /* AUDIO_CLKA   */
3078                 [29] = RCAR_GP_PIN(2, 23),      /* AUDIO_CLKB   */
3079                 [30] = RCAR_GP_PIN(1, 14),      /* IRQ2         */
3080                 [31] = RCAR_GP_PIN(1, 15),      /* IRQ3         */
3081         } },
3082         { PINMUX_BIAS_REG("PUPR5", 0x114, "N/A", 0) {
3083                 [ 0] = RCAR_GP_PIN(0,  1),      /* PENC0        */
3084                 [ 1] = RCAR_GP_PIN(0,  2),      /* PENC1        */
3085                 [ 2] = RCAR_GP_PIN(0,  3),      /* USB_OVC0     */
3086                 [ 3] = RCAR_GP_PIN(0,  4),      /* USB_OVC1     */
3087                 [ 4] = RCAR_GP_PIN(1, 16),      /* SCIF_CLK     */
3088                 [ 5] = RCAR_GP_PIN(1, 17),      /* TX0          */
3089                 [ 6] = RCAR_GP_PIN(1, 18),      /* RX0          */
3090                 [ 7] = RCAR_GP_PIN(1, 19),      /* SCK0         */
3091                 [ 8] = RCAR_GP_PIN(1, 20),      /* /CTS0        */
3092                 [ 9] = RCAR_GP_PIN(1, 21),      /* /RTS0        */
3093                 [10] = RCAR_GP_PIN(3, 19),      /* HSPI_CLK0    */
3094                 [11] = RCAR_GP_PIN(3, 20),      /* /HSPI_CS0    */
3095                 [12] = RCAR_GP_PIN(3, 21),      /* HSPI_RX0     */
3096                 [13] = RCAR_GP_PIN(3, 22),      /* HSPI_TX0     */
3097                 [14] = RCAR_GP_PIN(4, 20),      /* ETH_MAGIC    */
3098                 [15] = RCAR_GP_PIN(4, 25),      /* AVS1         */
3099                 [16] = RCAR_GP_PIN(4, 26),      /* AVS2         */
3100                 [17] = SH_PFC_PIN_NONE,
3101                 [18] = SH_PFC_PIN_NONE,
3102                 [19] = SH_PFC_PIN_NONE,
3103                 [20] = SH_PFC_PIN_NONE,
3104                 [21] = SH_PFC_PIN_NONE,
3105                 [22] = SH_PFC_PIN_NONE,
3106                 [23] = SH_PFC_PIN_NONE,
3107                 [24] = SH_PFC_PIN_NONE,
3108                 [25] = SH_PFC_PIN_NONE,
3109                 [26] = SH_PFC_PIN_NONE,
3110                 [27] = SH_PFC_PIN_NONE,
3111                 [28] = SH_PFC_PIN_NONE,
3112                 [29] = SH_PFC_PIN_NONE,
3113                 [30] = SH_PFC_PIN_NONE,
3114                 [31] = SH_PFC_PIN_NONE,
3115         } },
3116         { /* sentinel */ },
3117 };
3118
3119 static unsigned int r8a7778_pinmux_get_bias(struct sh_pfc *pfc,
3120                                             unsigned int pin)
3121 {
3122         const struct pinmux_bias_reg *reg;
3123         void __iomem *addr;
3124         unsigned int bit;
3125
3126         reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
3127         if (!reg)
3128                 return PIN_CONFIG_BIAS_DISABLE;
3129
3130         addr = pfc->windows->virt + reg->puen;
3131
3132         if (ioread32(addr) & BIT(bit))
3133                 return PIN_CONFIG_BIAS_PULL_UP;
3134         else
3135                 return PIN_CONFIG_BIAS_DISABLE;
3136 }
3137
3138 static void r8a7778_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
3139                                    unsigned int bias)
3140 {
3141         const struct pinmux_bias_reg *reg;
3142         void __iomem *addr;
3143         unsigned int bit;
3144         u32 value;
3145
3146         reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
3147         if (!reg)
3148                 return;
3149
3150         addr = pfc->windows->virt + reg->puen;
3151
3152         value = ioread32(addr) & ~BIT(bit);
3153         if (bias == PIN_CONFIG_BIAS_PULL_UP)
3154                 value |= BIT(bit);
3155         iowrite32(value, addr);
3156 }
3157
3158 static const struct sh_pfc_soc_operations r8a7778_pfc_ops = {
3159         .get_bias = r8a7778_pinmux_get_bias,
3160         .set_bias = r8a7778_pinmux_set_bias,
3161 };
3162
3163 const struct sh_pfc_soc_info r8a7778_pinmux_info = {
3164         .name = "r8a7778_pfc",
3165         .ops  = &r8a7778_pfc_ops,
3166
3167         .unlock_reg = 0xfffc0000, /* PMMR */
3168
3169         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
3170
3171         .pins = pinmux_pins,
3172         .nr_pins = ARRAY_SIZE(pinmux_pins),
3173
3174         .groups = pinmux_groups,
3175         .nr_groups = ARRAY_SIZE(pinmux_groups),
3176
3177         .functions = pinmux_functions,
3178         .nr_functions = ARRAY_SIZE(pinmux_functions),
3179
3180         .cfg_regs = pinmux_config_regs,
3181         .bias_regs = pinmux_bias_regs,
3182
3183         .pinmux_data = pinmux_data,
3184         .pinmux_data_size = ARRAY_SIZE(pinmux_data),
3185 };