| blob | a2496baca85d23f87d40fa9c2a32004f2947875d |
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * R8A7796 (R-Car M3-W/W+) support - PFC hardware block.
4 *
5 * Copyright (C) 2016-2019 Renesas Electronics Corp.
6 *
7 * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c
8 *
9 * R-Car Gen3 processor support - PFC hardware block.
10 *
11 * Copyright (C) 2015 Renesas Electronics Corporation
12 */
14 #include <linux/errno.h>
15 #include <linux/kernel.h>
20 #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
22 #define CPU_ALL_GP(fn, sfx) \
23 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
24 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
25 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
26 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
27 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
28 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
29 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
30 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
31 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
32 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
33 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
34 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
36 #define CPU_ALL_NOGP(fn) \
80 /*
81 * F_() : just information
82 * FM() : macro for FN_xxx / xxx_MARK
83 */
85 /* GPSR0 */
86 #define GPSR0_15 F_(D15, IP7_11_8)
87 #define GPSR0_14 F_(D14, IP7_7_4)
88 #define GPSR0_13 F_(D13, IP7_3_0)
89 #define GPSR0_12 F_(D12, IP6_31_28)
90 #define GPSR0_11 F_(D11, IP6_27_24)
91 #define GPSR0_10 F_(D10, IP6_23_20)
92 #define GPSR0_9 F_(D9, IP6_19_16)
93 #define GPSR0_8 F_(D8, IP6_15_12)
94 #define GPSR0_7 F_(D7, IP6_11_8)
95 #define GPSR0_6 F_(D6, IP6_7_4)
96 #define GPSR0_5 F_(D5, IP6_3_0)
97 #define GPSR0_4 F_(D4, IP5_31_28)
98 #define GPSR0_3 F_(D3, IP5_27_24)
99 #define GPSR0_2 F_(D2, IP5_23_20)
100 #define GPSR0_1 F_(D1, IP5_19_16)
101 #define GPSR0_0 F_(D0, IP5_15_12)
103 /* GPSR1 */
104 #define GPSR1_28 FM(CLKOUT)
105 #define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
106 #define GPSR1_26 F_(WE1_N, IP5_7_4)
107 #define GPSR1_25 F_(WE0_N, IP5_3_0)
108 #define GPSR1_24 F_(RD_WR_N, IP4_31_28)
109 #define GPSR1_23 F_(RD_N, IP4_27_24)
110 #define GPSR1_22 F_(BS_N, IP4_23_20)
111 #define GPSR1_21 F_(CS1_N, IP4_19_16)
112 #define GPSR1_20 F_(CS0_N, IP4_15_12)
113 #define GPSR1_19 F_(A19, IP4_11_8)
114 #define GPSR1_18 F_(A18, IP4_7_4)
115 #define GPSR1_17 F_(A17, IP4_3_0)
116 #define GPSR1_16 F_(A16, IP3_31_28)
117 #define GPSR1_15 F_(A15, IP3_27_24)
118 #define GPSR1_14 F_(A14, IP3_23_20)
119 #define GPSR1_13 F_(A13, IP3_19_16)
120 #define GPSR1_12 F_(A12, IP3_15_12)
121 #define GPSR1_11 F_(A11, IP3_11_8)
122 #define GPSR1_10 F_(A10, IP3_7_4)
123 #define GPSR1_9 F_(A9, IP3_3_0)
124 #define GPSR1_8 F_(A8, IP2_31_28)
125 #define GPSR1_7 F_(A7, IP2_27_24)
126 #define GPSR1_6 F_(A6, IP2_23_20)
127 #define GPSR1_5 F_(A5, IP2_19_16)
128 #define GPSR1_4 F_(A4, IP2_15_12)
129 #define GPSR1_3 F_(A3, IP2_11_8)
130 #define GPSR1_2 F_(A2, IP2_7_4)
131 #define GPSR1_1 F_(A1, IP2_3_0)
132 #define GPSR1_0 F_(A0, IP1_31_28)
134 /* GPSR2 */
135 #define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
136 #define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
137 #define GPSR2_12 F_(AVB_LINK, IP0_15_12)
138 #define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
139 #define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
140 #define GPSR2_9 F_(AVB_MDC, IP0_3_0)
141 #define GPSR2_8 F_(PWM2_A, IP1_27_24)
142 #define GPSR2_7 F_(PWM1_A, IP1_23_20)
143 #define GPSR2_6 F_(PWM0, IP1_19_16)
144 #define GPSR2_5 F_(IRQ5, IP1_15_12)
145 #define GPSR2_4 F_(IRQ4, IP1_11_8)
146 #define GPSR2_3 F_(IRQ3, IP1_7_4)
147 #define GPSR2_2 F_(IRQ2, IP1_3_0)
148 #define GPSR2_1 F_(IRQ1, IP0_31_28)
149 #define GPSR2_0 F_(IRQ0, IP0_27_24)
151 /* GPSR3 */
152 #define GPSR3_15 F_(SD1_WP, IP11_23_20)
153 #define GPSR3_14 F_(SD1_CD, IP11_19_16)
154 #define GPSR3_13 F_(SD0_WP, IP11_15_12)
155 #define GPSR3_12 F_(SD0_CD, IP11_11_8)
156 #define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
157 #define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
158 #define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
159 #define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
160 #define GPSR3_7 F_(SD1_CMD, IP8_15_12)
161 #define GPSR3_6 F_(SD1_CLK, IP8_11_8)
162 #define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
163 #define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
164 #define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
165 #define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
166 #define GPSR3_1 F_(SD0_CMD, IP7_23_20)
167 #define GPSR3_0 F_(SD0_CLK, IP7_19_16)
169 /* GPSR4 */
170 #define GPSR4_17 F_(SD3_DS, IP11_7_4)
171 #define GPSR4_16 F_(SD3_DAT7, IP11_3_0)
172 #define GPSR4_15 F_(SD3_DAT6, IP10_31_28)
173 #define GPSR4_14 F_(SD3_DAT5, IP10_27_24)
174 #define GPSR4_13 F_(SD3_DAT4, IP10_23_20)
175 #define GPSR4_12 F_(SD3_DAT3, IP10_19_16)
176 #define GPSR4_11 F_(SD3_DAT2, IP10_15_12)
177 #define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
178 #define GPSR4_9 F_(SD3_DAT0, IP10_7_4)
179 #define GPSR4_8 F_(SD3_CMD, IP10_3_0)
180 #define GPSR4_7 F_(SD3_CLK, IP9_31_28)
181 #define GPSR4_6 F_(SD2_DS, IP9_27_24)
182 #define GPSR4_5 F_(SD2_DAT3, IP9_23_20)
183 #define GPSR4_4 F_(SD2_DAT2, IP9_19_16)
184 #define GPSR4_3 F_(SD2_DAT1, IP9_15_12)
185 #define GPSR4_2 F_(SD2_DAT0, IP9_11_8)
186 #define GPSR4_1 F_(SD2_CMD, IP9_7_4)
187 #define GPSR4_0 F_(SD2_CLK, IP9_3_0)
189 /* GPSR5 */
190 #define GPSR5_25 F_(MLB_DAT, IP14_19_16)
191 #define GPSR5_24 F_(MLB_SIG, IP14_15_12)
192 #define GPSR5_23 F_(MLB_CLK, IP14_11_8)
193 #define GPSR5_22 FM(MSIOF0_RXD)
194 #define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4)
195 #define GPSR5_20 FM(MSIOF0_TXD)
196 #define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0)
197 #define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28)
198 #define GPSR5_17 FM(MSIOF0_SCK)
199 #define GPSR5_16 F_(HRTS0_N, IP13_27_24)
200 #define GPSR5_15 F_(HCTS0_N, IP13_23_20)
201 #define GPSR5_14 F_(HTX0, IP13_19_16)
202 #define GPSR5_13 F_(HRX0, IP13_15_12)
203 #define GPSR5_12 F_(HSCK0, IP13_11_8)
204 #define GPSR5_11 F_(RX2_A, IP13_7_4)
205 #define GPSR5_10 F_(TX2_A, IP13_3_0)
206 #define GPSR5_9 F_(SCK2, IP12_31_28)
207 #define GPSR5_8 F_(RTS1_N, IP12_27_24)
208 #define GPSR5_7 F_(CTS1_N, IP12_23_20)
209 #define GPSR5_6 F_(TX1_A, IP12_19_16)
210 #define GPSR5_5 F_(RX1_A, IP12_15_12)
211 #define GPSR5_4 F_(RTS0_N, IP12_11_8)
212 #define GPSR5_3 F_(CTS0_N, IP12_7_4)
213 #define GPSR5_2 F_(TX0, IP12_3_0)
214 #define GPSR5_1 F_(RX0, IP11_31_28)
215 #define GPSR5_0 F_(SCK0, IP11_27_24)
217 /* GPSR6 */
218 #define GPSR6_31 F_(GP6_31, IP18_7_4)
219 #define GPSR6_30 F_(GP6_30, IP18_3_0)
220 #define GPSR6_29 F_(USB30_OVC, IP17_31_28)
221 #define GPSR6_28 F_(USB30_PWEN, IP17_27_24)
222 #define GPSR6_27 F_(USB1_OVC, IP17_23_20)
223 #define GPSR6_26 F_(USB1_PWEN, IP17_19_16)
224 #define GPSR6_25 F_(USB0_OVC, IP17_15_12)
225 #define GPSR6_24 F_(USB0_PWEN, IP17_11_8)
226 #define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4)
227 #define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0)
228 #define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28)
229 #define GPSR6_20 F_(SSI_SDATA8, IP16_27_24)
230 #define GPSR6_19 F_(SSI_SDATA7, IP16_23_20)
231 #define GPSR6_18 F_(SSI_WS78, IP16_19_16)
232 #define GPSR6_17 F_(SSI_SCK78, IP16_15_12)
233 #define GPSR6_16 F_(SSI_SDATA6, IP16_11_8)
234 #define GPSR6_15 F_(SSI_WS6, IP16_7_4)
235 #define GPSR6_14 F_(SSI_SCK6, IP16_3_0)
236 #define GPSR6_13 FM(SSI_SDATA5)
237 #define GPSR6_12 FM(SSI_WS5)
238 #define GPSR6_11 FM(SSI_SCK5)
239 #define GPSR6_10 F_(SSI_SDATA4, IP15_31_28)
240 #define GPSR6_9 F_(SSI_WS4, IP15_27_24)
241 #define GPSR6_8 F_(SSI_SCK4, IP15_23_20)
242 #define GPSR6_7 F_(SSI_SDATA3, IP15_19_16)
243 #define GPSR6_6 F_(SSI_WS349, IP15_15_12)
244 #define GPSR6_5 F_(SSI_SCK349, IP15_11_8)
245 #define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4)
246 #define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0)
247 #define GPSR6_2 F_(SSI_SDATA0, IP14_31_28)
248 #define GPSR6_1 F_(SSI_WS01239, IP14_27_24)
249 #define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
251 /* GPSR7 */
252 #define GPSR7_3 FM(GP7_03)
253 #define GPSR7_2 FM(GP7_02)
254 #define GPSR7_1 FM(AVS2)
255 #define GPSR7_0 FM(AVS1)
258 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
259 #define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260 #define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261 #define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262 #define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263 #define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264 #define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265 #define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266 #define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267 #define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268 #define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269 #define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) F_(0, 0) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270 #define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) F_(0, 0) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271 #define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)F_(0, 0) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272 #define IP1_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273 #define IP1_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274 #define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
275 #define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
276 #define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277 #define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278 #define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279 #define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280 #define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281 #define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282 #define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283 #define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284 #define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285 #define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
288 #define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289 #define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290 #define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291 #define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292 #define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293 #define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294 #define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295 #define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296 #define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297 #define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298 #define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299 #define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300 #define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301 #define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302 #define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303 #define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304 #define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305 #define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306 #define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307 #define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308 #define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309 #define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310 #define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311 #define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312 #define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313 #define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314 #define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315 #define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316 #define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
319 #define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320 #define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321 #define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322 #define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323 #define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324 #define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325 #define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326 #define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327 #define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328 #define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329 #define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330 #define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331 #define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332 #define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333 #define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334 #define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335 #define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336 #define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337 #define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338 #define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339 #define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340 #define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
341 #define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
342 #define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343 #define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344 #define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345 #define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346 #define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347 #define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348 #define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349 #define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350 #define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351 #define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352 #define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
355 #define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
356 #define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357 #define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
358 #define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
359 #define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
360 #define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
361 #define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
362 #define IP12_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
363 #define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
364 #define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
365 #define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
366 #define IP12_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
367 #define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
368 #define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
369 #define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
370 #define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
371 #define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
372 #define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
373 #define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
374 #define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
375 #define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
376 #define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
377 #define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
378 #define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
379 #define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
380 #define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
381 #define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
382 #define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
384 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
385 #define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
386 #define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
387 #define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
388 #define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
389 #define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
390 #define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
391 #define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
392 #define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
393 #define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
394 #define IP16_3_0 FM(SSI_SCK6) F_(0, 0) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
395 #define IP16_7_4 FM(SSI_WS6) F_(0, 0) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
396 #define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
397 #define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
398 #define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
399 #define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
400 #define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
401 #define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
402 #define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
403 #define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
404 #define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
405 #define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
406 #define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
407 #define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
408 #define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
409 #define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
410 #define IP18_3_0 FM(GP6_30) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
411 #define IP18_7_4 FM(GP6_31) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
413 #define PINMUX_GPSR \
414 \
415 GPSR6_31 \
416 GPSR6_30 \
417 GPSR6_29 \
418 GPSR1_28 GPSR6_28 \
419 GPSR1_27 GPSR6_27 \
420 GPSR1_26 GPSR6_26 \
421 GPSR1_25 GPSR5_25 GPSR6_25 \
422 GPSR1_24 GPSR5_24 GPSR6_24 \
423 GPSR1_23 GPSR5_23 GPSR6_23 \
424 GPSR1_22 GPSR5_22 GPSR6_22 \
425 GPSR1_21 GPSR5_21 GPSR6_21 \
426 GPSR1_20 GPSR5_20 GPSR6_20 \
427 GPSR1_19 GPSR5_19 GPSR6_19 \
428 GPSR1_18 GPSR5_18 GPSR6_18 \
429 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
430 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
431 GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
432 GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
433 GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
434 GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
435 GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
436 GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
437 GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
438 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
439 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
440 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
441 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
442 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
443 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
444 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
445 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
446 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
448 #define PINMUX_IPSR \
449 \
450 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
451 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
452 FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
453 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
454 FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
455 FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
456 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
457 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
458 \
459 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
460 FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
461 FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
462 FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \
463 FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
464 FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
465 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
466 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
467 \
468 FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
469 FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
470 FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
471 FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
472 FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
473 FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
474 FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
475 FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
476 \
477 FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
478 FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
479 FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
480 FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
481 FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
482 FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
483 FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
484 FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
485 \
486 FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \
487 FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \
488 FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \
489 FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \
490 FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \
491 FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \
492 FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \
493 FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
496 #define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0)
497 #define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
498 #define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
499 #define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
500 #define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
501 #define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
502 #define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
503 #define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
504 #define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
505 #define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
506 #define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0)
507 #define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
508 #define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
509 #define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
510 #define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
511 #define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
512 #define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
513 #define MOD_SEL0_4_3 FM(SEL_ADGA_0) FM(SEL_ADGA_1) FM(SEL_ADGA_2) FM(SEL_ADGA_3)
516 #define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
517 #define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
518 #define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
519 #define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
520 #define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
521 #define MOD_SEL1_20 FM(SEL_SSI1_0) FM(SEL_SSI1_1)
522 #define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
523 #define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
524 #define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
525 #define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
526 #define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
527 #define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
528 #define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
529 #define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
530 #define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
531 #define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
532 #define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
533 #define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
534 #define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
535 #define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
536 #define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
537 #define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
540 #define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
541 #define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
542 #define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
543 #define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
544 #define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
545 #define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
546 #define MOD_SEL2_22 FM(SEL_NDF_0) FM(SEL_NDF_1)
547 #define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
548 #define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
549 #define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
550 #define MOD_SEL2_18 FM(SEL_ADGB_0) FM(SEL_ADGB_1)
551 #define MOD_SEL2_17 FM(SEL_ADGC_0) FM(SEL_ADGC_1)
552 #define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
554 #define PINMUX_MOD_SELS \
555 \
556 MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \
557 MOD_SEL2_30 \
558 MOD_SEL1_29_28_27 MOD_SEL2_29 \
559 MOD_SEL0_28_27 MOD_SEL2_28_27 \
560 MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \
561 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \
562 MOD_SEL0_23 MOD_SEL1_23_22_21 \
563 MOD_SEL0_22 MOD_SEL2_22 \
564 MOD_SEL0_21 MOD_SEL2_21 \
565 MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \
566 MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \
567 MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \
568 MOD_SEL2_17 \
569 MOD_SEL0_16 MOD_SEL1_16 \
570 MOD_SEL1_15_14 \
571 MOD_SEL0_14_13 \
572 MOD_SEL1_13 \
573 MOD_SEL0_12 MOD_SEL1_12 \
574 MOD_SEL0_11 MOD_SEL1_11 \
575 MOD_SEL0_10 MOD_SEL1_10 \
576 MOD_SEL0_9_8 MOD_SEL1_9 \
577 MOD_SEL0_7_6 \
578 MOD_SEL1_6 \
579 MOD_SEL0_5 MOD_SEL1_5 \
580 MOD_SEL0_4_3 MOD_SEL1_4 \
581 MOD_SEL1_3 \
582 MOD_SEL1_2 \
583 MOD_SEL1_1 \
584 MOD_SEL1_0 MOD_SEL2_0
586 /*
587 * These pins are not able to be muxed but have other properties
588 * that can be set, such as drive-strength or pull-up/pull-down enable.
589 */
590 #define PINMUX_STATIC \
591 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
592 FM(QSPI0_IO2) FM(QSPI0_IO3) \
593 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
594 FM(QSPI1_IO2) FM(QSPI1_IO3) \
595 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
596 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
597 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
598 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
599 FM(PRESETOUT) \
600 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) \
601 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
603 #define PINMUX_PHYS \
604 FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)
609 PINMUX_DATA_BEGIN,
611 PINMUX_DATA_END,
613 #define F_(x, y)
614 #define FM(x) FN_##x,
615 PINMUX_FUNCTION_BEGIN,
617 PINMUX_GPSR
618 PINMUX_IPSR
619 PINMUX_MOD_SELS
620 PINMUX_FUNCTION_END,
621 #undef F_
622 #undef FM
624 #define F_(x, y)
625 #define FM(x) x##_MARK,
626 PINMUX_MARK_BEGIN,
627 PINMUX_GPSR
628 PINMUX_IPSR
629 PINMUX_MOD_SELS
630 PINMUX_STATIC
631 PINMUX_PHYS
632 PINMUX_MARK_END,
633 #undef F_
634 #undef FM
635 };
652 /* IPSR0 */
694 /* IPSR1 */
746 /* IPSR2 */
807 /* IPSR3 */
861 /* IPSR4 */
907 /* IPSR5 */
957 /* IPSR6 */
1009 /* IPSR7 */
1051 /* IPSR8 */
1100 /* IPSR9 */
1125 /* IPSR10 */
1153 /* IPSR11 */
1197 /* IPSR12 */
1258 /* IPSR13 */
1318 /* IPSR14 */
1359 /* IPSR15 */
1406 /* IPSR16 */
1458 /* IPSR17 */
1524 /* IPSR18 */
1545 /*
1546 * Static pins can not be muxed between different functions but
1547 * still need mark entries in the pinmux list. Add each static
1548 * pin to the list without an associated function. The sh-pfc
1549 * core will do the right thing and skip trying to mux the pin
1550 * while still applying configuration to it.
1551 */
1552 #define FM(x) PINMUX_DATA(x##_MARK, 0),
1553 PINMUX_STATIC
1554 #undef FM
1555 };
1557 /*
1558 * Pins not associated with a GPIO port.
1559 */
1563 };
1568 };
1570 /* - AUDIO CLOCK ------------------------------------------------------------ */
1572 /* CLK A */
1574 };
1576 AUDIO_CLKA_A_MARK,
1577 };
1579 /* CLK A */
1581 };
1583 AUDIO_CLKA_B_MARK,
1584 };
1586 /* CLK A */
1588 };
1590 AUDIO_CLKA_C_MARK,
1591 };
1593 /* CLK B */
1595 };
1597 AUDIO_CLKB_A_MARK,
1598 };
1600 /* CLK B */
1602 };
1604 AUDIO_CLKB_B_MARK,
1605 };
1607 /* CLK C */
1609 };
1611 AUDIO_CLKC_A_MARK,
1612 };
1614 /* CLK C */
1616 };
1618 AUDIO_CLKC_B_MARK,
1619 };
1621 /* CLKOUT */
1623 };
1625 AUDIO_CLKOUT_A_MARK,
1626 };
1628 /* CLKOUT */
1630 };
1632 AUDIO_CLKOUT_B_MARK,
1633 };
1635 /* CLKOUT */
1637 };
1639 AUDIO_CLKOUT_C_MARK,
1640 };
1642 /* CLKOUT */
1644 };
1646 AUDIO_CLKOUT_D_MARK,
1647 };
1649 /* CLKOUT1 */
1651 };
1653 AUDIO_CLKOUT1_A_MARK,
1654 };
1656 /* CLKOUT1 */
1658 };
1660 AUDIO_CLKOUT1_B_MARK,
1661 };
1663 /* CLKOUT2 */
1665 };
1667 AUDIO_CLKOUT2_A_MARK,
1668 };
1670 /* CLKOUT2 */
1672 };
1674 AUDIO_CLKOUT2_B_MARK,
1675 };
1678 /* CLKOUT3 */
1680 };
1682 AUDIO_CLKOUT3_A_MARK,
1683 };
1685 /* CLKOUT3 */
1687 };
1689 AUDIO_CLKOUT3_B_MARK,
1690 };
1692 /* - EtherAVB --------------------------------------------------------------- */
1694 /* AVB_LINK */
1696 };
1698 AVB_LINK_MARK,
1699 };
1701 /* AVB_MAGIC_ */
1703 };
1705 AVB_MAGIC_MARK,
1706 };
1708 /* AVB_PHY_INT */
1710 };
1712 AVB_PHY_INT_MARK,
1713 };
1715 /* AVB_MDC, AVB_MDIO */
1717 };
1720 };
1722 /*
1723 * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1724 * AVB_TD1, AVB_TD2, AVB_TD3,
1725 * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1726 * AVB_RD1, AVB_RD2, AVB_RD3,
1727 * AVB_TXCREFCLK
1728 */
1733 PIN_AVB_TXCREFCLK,
1735 };
1741 AVB_TXCREFCLK_MARK,
1742 };
1744 /* AVB_AVTP_PPS */
1746 };
1748 AVB_AVTP_PPS_MARK,
1749 };
1751 /* AVB_AVTP_MATCH_A */
1753 };
1755 AVB_AVTP_MATCH_A_MARK,
1756 };
1758 /* AVB_AVTP_CAPTURE_A */
1760 };
1762 AVB_AVTP_CAPTURE_A_MARK,
1763 };
1765 /* AVB_AVTP_MATCH_B */
1767 };
1769 AVB_AVTP_MATCH_B_MARK,
1770 };
1772 /* AVB_AVTP_CAPTURE_B */
1774 };
1776 AVB_AVTP_CAPTURE_B_MARK,
1777 };
1779 /* - CAN ------------------------------------------------------------------ */
1781 /* TX, RX */
1783 };
1786 };
1788 /* TX, RX */
1790 };
1793 };
1795 /* TX, RX */
1797 };
1800 };
1802 /* - CAN Clock -------------------------------------------------------------- */
1804 /* CLK */
1806 };
1808 CAN_CLK_MARK,
1809 };
1811 /* - CAN FD --------------------------------------------------------------- */
1813 /* TX, RX */
1815 };
1818 };
1820 /* TX, RX */
1822 };
1825 };
1827 /* TX, RX */
1829 };
1832 };
1834 /* - DRIF0 --------------------------------------------------------------- */
1836 /* CLK, SYNC */
1838 };
1841 };
1843 /* D0 */
1845 };
1847 RIF0_D0_A_MARK,
1848 };
1850 /* D1 */
1852 };
1854 RIF0_D1_A_MARK,
1855 };
1857 /* CLK, SYNC */
1859 };
1862 };
1864 /* D0 */
1866 };
1868 RIF0_D0_B_MARK,
1869 };
1871 /* D1 */
1873 };
1875 RIF0_D1_B_MARK,
1876 };
1878 /* CLK, SYNC */
1880 };
1883 };
1885 /* D0 */
1887 };
1889 RIF0_D0_C_MARK,
1890 };
1892 /* D1 */
1894 };
1896 RIF0_D1_C_MARK,
1897 };
1898 /* - DRIF1 --------------------------------------------------------------- */
1900 /* CLK, SYNC */
1902 };
1905 };
1907 /* D0 */
1909 };
1911 RIF1_D0_A_MARK,
1912 };
1914 /* D1 */
1916 };
1918 RIF1_D1_A_MARK,
1919 };
1921 /* CLK, SYNC */
1923 };
1926 };
1928 /* D0 */
1930 };
1932 RIF1_D0_B_MARK,
1933 };
1935 /* D1 */
1937 };
1939 RIF1_D1_B_MARK,
1940 };
1942 /* CLK, SYNC */
1944 };
1947 };
1949 /* D0 */
1951 };
1953 RIF1_D0_C_MARK,
1954 };
1956 /* D1 */
1958 };
1960 RIF1_D1_C_MARK,
1961 };
1962 /* - DRIF2 --------------------------------------------------------------- */
1964 /* CLK, SYNC */
1966 };
1969 };
1971 /* D0 */
1973 };
1975 RIF2_D0_A_MARK,
1976 };
1978 /* D1 */
1980 };
1982 RIF2_D1_A_MARK,
1983 };
1985 /* CLK, SYNC */
1987 };
1990 };
1992 /* D0 */
1994 };
1996 RIF2_D0_B_MARK,
1997 };
1999 /* D1 */
2001 };
2003 RIF2_D1_B_MARK,
2004 };
2005 /* - DRIF3 --------------------------------------------------------------- */
2007 /* CLK, SYNC */
2009 };
2012 };
2014 /* D0 */
2016 };
2018 RIF3_D0_A_MARK,
2019 };
2021 /* D1 */
2023 };
2025 RIF3_D1_A_MARK,
2026 };
2028 /* CLK, SYNC */
2030 };
2033 };
2035 /* D0 */
2037 };
2039 RIF3_D0_B_MARK,
2040 };
2042 /* D1 */
2044 };
2046 RIF3_D1_B_MARK,
2047 };
2049 /* - DU --------------------------------------------------------------------- */
2051 /* R[7:2], G[7:2], B[7:2] */
2058 };
2066 };
2068 /* R[7:0], G[7:0], B[7:0] */
2078 };
2086 };
2088 /* CLKOUT */
2090 };
2092 DU_DOTCLKOUT0_MARK
2093 };
2095 /* CLKOUT */
2097 };
2099 DU_DOTCLKOUT1_MARK
2100 };
2102 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2104 };
2106 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
2107 };
2109 /* EXDISP/EXODDF/EXCDE */
2111 };
2113 DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
2114 };
2116 /* CDE */
2118 };
2120 DU_CDE_MARK,
2121 };
2123 /* DISP */
2125 };
2127 DU_DISP_MARK,
2128 };
2130 /* - HSCIF0 ----------------------------------------------------------------- */
2132 /* RX, TX */
2134 };
2137 };
2139 /* SCK */
2141 };
2143 HSCK0_MARK,
2144 };
2146 /* RTS, CTS */
2148 };
2151 };
2152 /* - HSCIF1 ----------------------------------------------------------------- */
2154 /* RX, TX */
2156 };
2159 };
2161 /* SCK */
2163 };
2165 HSCK1_A_MARK,
2166 };
2168 /* RTS, CTS */
2170 };
2173 };
2176 /* RX, TX */
2178 };
2181 };
2183 /* SCK */
2185 };
2187 HSCK1_B_MARK,
2188 };
2190 /* RTS, CTS */
2192 };
2195 };
2196 /* - HSCIF2 ----------------------------------------------------------------- */
2198 /* RX, TX */
2200 };
2203 };
2205 /* SCK */
2207 };
2209 HSCK2_A_MARK,
2210 };
2212 /* RTS, CTS */
2214 };
2217 };
2220 /* RX, TX */
2222 };
2225 };
2227 /* SCK */
2229 };
2231 HSCK2_B_MARK,
2232 };
2234 /* RTS, CTS */
2236 };
2239 };
2242 /* RX, TX */
2244 };
2247 };
2249 /* SCK */
2251 };
2253 HSCK2_C_MARK,
2254 };
2256 /* RTS, CTS */
2258 };
2261 };
2262 /* - HSCIF3 ----------------------------------------------------------------- */
2264 /* RX, TX */
2266 };
2269 };
2271 /* SCK */
2273 };
2275 HSCK3_MARK,
2276 };
2278 /* RTS, CTS */
2280 };
2283 };
2286 /* RX, TX */
2288 };
2291 };
2293 /* RX, TX */
2295 };
2298 };
2300 /* RX, TX */
2302 };
2305 };
2306 /* - HSCIF4 ----------------------------------------------------------------- */
2308 /* RX, TX */
2310 };
2313 };
2315 /* SCK */
2317 };
2319 HSCK4_MARK,
2320 };
2322 /* RTS, CTS */
2324 };
2327 };
2330 /* RX, TX */
2332 };
2335 };
2337 /* - I2C -------------------------------------------------------------------- */
2339 /* SCL, SDA */
2341 };
2345 };
2348 /* SDA, SCL */
2350 };
2353 };
2355 /* SDA, SCL */
2357 };
2360 };
2362 /* SDA, SCL */
2364 };
2367 };
2369 /* SDA, SCL */
2371 };
2374 };
2377 /* SCL, SDA */
2379 };
2383 };
2386 /* SCL, SDA */
2388 };
2392 };
2395 /* SDA, SCL */
2397 };
2400 };
2402 /* SDA, SCL */
2404 };
2407 };
2409 /* SDA, SCL */
2411 };
2414 };
2416 /* - INTC-EX ---------------------------------------------------------------- */
2418 /* IRQ0 */
2420 };
2422 IRQ0_MARK,
2423 };
2425 /* IRQ1 */
2427 };
2429 IRQ1_MARK,
2430 };
2432 /* IRQ2 */
2434 };
2436 IRQ2_MARK,
2437 };
2439 /* IRQ3 */
2441 };
2443 IRQ3_MARK,
2444 };
2446 /* IRQ4 */
2448 };
2450 IRQ4_MARK,
2451 };
2453 /* IRQ5 */
2455 };
2457 IRQ5_MARK,
2458 };
2460 /* - MSIOF0 ----------------------------------------------------------------- */
2462 /* SCK */
2464 };
2466 MSIOF0_SCK_MARK,
2467 };
2469 /* SYNC */
2471 };
2473 MSIOF0_SYNC_MARK,
2474 };
2476 /* SS1 */
2478 };
2480 MSIOF0_SS1_MARK,
2481 };
2483 /* SS2 */
2485 };
2487 MSIOF0_SS2_MARK,
2488 };
2490 /* TXD */
2492 };
2494 MSIOF0_TXD_MARK,
2495 };
2497 /* RXD */
2499 };
2501 MSIOF0_RXD_MARK,
2502 };
2503 /* - MSIOF1 ----------------------------------------------------------------- */
2505 /* SCK */
2507 };
2509 MSIOF1_SCK_A_MARK,
2510 };
2512 /* SYNC */
2514 };
2516 MSIOF1_SYNC_A_MARK,
2517 };
2519 /* SS1 */
2521 };
2523 MSIOF1_SS1_A_MARK,
2524 };
2526 /* SS2 */
2528 };
2530 MSIOF1_SS2_A_MARK,
2531 };
2533 /* TXD */
2535 };
2537 MSIOF1_TXD_A_MARK,
2538 };
2540 /* RXD */
2542 };
2544 MSIOF1_RXD_A_MARK,
2545 };
2547 /* SCK */
2549 };
2551 MSIOF1_SCK_B_MARK,
2552 };
2554 /* SYNC */
2556 };
2558 MSIOF1_SYNC_B_MARK,
2559 };
2561 /* SS1 */
2563 };
2565 MSIOF1_SS1_B_MARK,
2566 };
2568 /* SS2 */
2570 };
2572 MSIOF1_SS2_B_MARK,
2573 };
2575 /* TXD */
2577 };
2579 MSIOF1_TXD_B_MARK,
2580 };
2582 /* RXD */
2584 };
2586 MSIOF1_RXD_B_MARK,
2587 };
2589 /* SCK */
2591 };
2593 MSIOF1_SCK_C_MARK,
2594 };
2596 /* SYNC */
2598 };
2600 MSIOF1_SYNC_C_MARK,
2601 };
2603 /* SS1 */
2605 };
2607 MSIOF1_SS1_C_MARK,
2608 };
2610 /* SS2 */
2612 };
2614 MSIOF1_SS2_C_MARK,
2615 };
2617 /* TXD */
2619 };
2621 MSIOF1_TXD_C_MARK,
2622 };
2624 /* RXD */
2626 };
2628 MSIOF1_RXD_C_MARK,
2629 };
2631 /* SCK */
2633 };
2635 MSIOF1_SCK_D_MARK,
2636 };
2638 /* SYNC */
2640 };
2642 MSIOF1_SYNC_D_MARK,
2643 };
2645 /* SS1 */
2647 };
2649 MSIOF1_SS1_D_MARK,
2650 };
2652 /* SS2 */
2654 };
2656 MSIOF1_SS2_D_MARK,
2657 };
2659 /* TXD */
2661 };
2663 MSIOF1_TXD_D_MARK,
2664 };
2666 /* RXD */
2668 };
2670 MSIOF1_RXD_D_MARK,
2671 };
2673 /* SCK */
2675 };
2677 MSIOF1_SCK_E_MARK,
2678 };
2680 /* SYNC */
2682 };
2684 MSIOF1_SYNC_E_MARK,
2685 };
2687 /* SS1 */
2689 };
2691 MSIOF1_SS1_E_MARK,
2692 };
2694 /* SS2 */
2696 };
2698 MSIOF1_SS2_E_MARK,
2699 };
2701 /* TXD */
2703 };
2705 MSIOF1_TXD_E_MARK,
2706 };
2708 /* RXD */
2710 };
2712 MSIOF1_RXD_E_MARK,
2713 };
2715 /* SCK */
2717 };
2719 MSIOF1_SCK_F_MARK,
2720 };
2722 /* SYNC */
2724 };
2726 MSIOF1_SYNC_F_MARK,
2727 };
2729 /* SS1 */
2731 };
2733 MSIOF1_SS1_F_MARK,
2734 };
2736 /* SS2 */
2738 };
2740 MSIOF1_SS2_F_MARK,
2741 };
2743 /* TXD */
2745 };
2747 MSIOF1_TXD_F_MARK,
2748 };
2750 /* RXD */
2752 };
2754 MSIOF1_RXD_F_MARK,
2755 };
2757 /* SCK */
2759 };
2761 MSIOF1_SCK_G_MARK,
2762 };
2764 /* SYNC */
2766 };
2768 MSIOF1_SYNC_G_MARK,
2769 };
2771 /* SS1 */
2773 };
2775 MSIOF1_SS1_G_MARK,
2776 };
2778 /* SS2 */
2780 };
2782 MSIOF1_SS2_G_MARK,
2783 };
2785 /* TXD */
2787 };
2789 MSIOF1_TXD_G_MARK,
2790 };
2792 /* RXD */
2794 };
2796 MSIOF1_RXD_G_MARK,
2797 };
2798 /* - MSIOF2 ----------------------------------------------------------------- */
2800 /* SCK */
2802 };
2804 MSIOF2_SCK_A_MARK,
2805 };
2807 /* SYNC */
2809 };
2811 MSIOF2_SYNC_A_MARK,
2812 };
2814 /* SS1 */
2816 };
2818 MSIOF2_SS1_A_MARK,
2819 };
2821 /* SS2 */
2823 };
2825 MSIOF2_SS2_A_MARK,
2826 };
2828 /* TXD */
2830 };
2832 MSIOF2_TXD_A_MARK,
2833 };
2835 /* RXD */
2837 };
2839 MSIOF2_RXD_A_MARK,
2840 };
2842 /* SCK */
2844 };
2846 MSIOF2_SCK_B_MARK,
2847 };
2849 /* SYNC */
2851 };
2853 MSIOF2_SYNC_B_MARK,
2854 };
2856 /* SS1 */
2858 };
2860 MSIOF2_SS1_B_MARK,
2861 };
2863 /* SS2 */
2865 };
2867 MSIOF2_SS2_B_MARK,
2868 };
2870 /* TXD */
2872 };
2874 MSIOF2_TXD_B_MARK,
2875 };
2877 /* RXD */
2879 };
2881 MSIOF2_RXD_B_MARK,
2882 };
2884 /* SCK */
2886 };
2888 MSIOF2_SCK_C_MARK,
2889 };
2891 /* SYNC */
2893 };
2895 MSIOF2_SYNC_C_MARK,
2896 };
2898 /* SS1 */
2900 };
2902 MSIOF2_SS1_C_MARK,
2903 };
2905 /* SS2 */
2907 };
2909 MSIOF2_SS2_C_MARK,
2910 };
2912 /* TXD */
2914 };
2916 MSIOF2_TXD_C_MARK,
2917 };
2919 /* RXD */
2921 };
2923 MSIOF2_RXD_C_MARK,
2924 };
2926 /* SCK */
2928 };
2930 MSIOF2_SCK_D_MARK,
2931 };
2933 /* SYNC */
2935 };
2937 MSIOF2_SYNC_D_MARK,
2938 };
2940 /* SS1 */
2942 };
2944 MSIOF2_SS1_D_MARK,
2945 };
2947 /* SS2 */
2949 };
2951 MSIOF2_SS2_D_MARK,
2952 };
2954 /* TXD */
2956 };
2958 MSIOF2_TXD_D_MARK,
2959 };
2961 /* RXD */
2963 };
2965 MSIOF2_RXD_D_MARK,
2966 };
2967 /* - MSIOF3 ----------------------------------------------------------------- */
2969 /* SCK */
2971 };
2973 MSIOF3_SCK_A_MARK,
2974 };
2976 /* SYNC */
2978 };
2980 MSIOF3_SYNC_A_MARK,
2981 };
2983 /* SS1 */
2985 };
2987 MSIOF3_SS1_A_MARK,
2988 };
2990 /* SS2 */
2992 };
2994 MSIOF3_SS2_A_MARK,
2995 };
2997 /* TXD */
2999 };
3001 MSIOF3_TXD_A_MARK,
3002 };
3004 /* RXD */
3006 };
3008 MSIOF3_RXD_A_MARK,
3009 };
3011 /* SCK */
3013 };
3015 MSIOF3_SCK_B_MARK,
3016 };
3018 /* SYNC */
3020 };
3022 MSIOF3_SYNC_B_MARK,
3023 };
3025 /* SS1 */
3027 };
3029 MSIOF3_SS1_B_MARK,
3030 };
3032 /* SS2 */
3034 };
3036 MSIOF3_SS2_B_MARK,
3037 };
3039 /* TXD */
3041 };
3043 MSIOF3_TXD_B_MARK,
3044 };
3046 /* RXD */
3048 };
3050 MSIOF3_RXD_B_MARK,
3051 };
3053 /* SCK */
3055 };
3057 MSIOF3_SCK_C_MARK,
3058 };
3060 /* SYNC */
3062 };
3064 MSIOF3_SYNC_C_MARK,
3065 };
3067 /* TXD */
3069 };
3071 MSIOF3_TXD_C_MARK,
3072 };
3074 /* RXD */
3076 };
3078 MSIOF3_RXD_C_MARK,
3079 };
3081 /* SCK */
3083 };
3085 MSIOF3_SCK_D_MARK,
3086 };
3088 /* SYNC */
3090 };
3092 MSIOF3_SYNC_D_MARK,
3093 };
3095 /* SS1 */
3097 };
3099 MSIOF3_SS1_D_MARK,
3100 };
3102 /* TXD */
3104 };
3106 MSIOF3_TXD_D_MARK,
3107 };
3109 /* RXD */
3111 };
3113 MSIOF3_RXD_D_MARK,
3114 };
3117 /* SCK */
3119 };
3121 MSIOF3_SCK_E_MARK,
3122 };
3124 /* SYNC */
3126 };
3128 MSIOF3_SYNC_E_MARK,
3129 };
3131 /* SS1 */
3133 };
3135 MSIOF3_SS1_E_MARK,
3136 };
3138 /* SS2 */
3140 };
3142 MSIOF3_SS2_E_MARK,
3143 };
3145 /* TXD */
3147 };
3149 MSIOF3_TXD_E_MARK,
3150 };
3152 /* RXD */
3154 };
3156 MSIOF3_RXD_E_MARK,
3157 };
3159 /* - PWM0 --------------------------------------------------------------------*/
3161 /* PWM */
3163 };
3165 PWM0_MARK,
3166 };
3167 /* - PWM1 --------------------------------------------------------------------*/
3169 /* PWM */
3171 };
3173 PWM1_A_MARK,
3174 };
3176 /* PWM */
3178 };
3180 PWM1_B_MARK,
3181 };
3182 /* - PWM2 --------------------------------------------------------------------*/
3184 /* PWM */
3186 };
3188 PWM2_A_MARK,
3189 };
3191 /* PWM */
3193 };
3195 PWM2_B_MARK,
3196 };
3197 /* - PWM3 --------------------------------------------------------------------*/
3199 /* PWM */
3201 };
3203 PWM3_A_MARK,
3204 };
3206 /* PWM */
3208 };
3210 PWM3_B_MARK,
3211 };
3212 /* - PWM4 --------------------------------------------------------------------*/
3214 /* PWM */
3216 };
3218 PWM4_A_MARK,
3219 };
3221 /* PWM */
3223 };
3225 PWM4_B_MARK,
3226 };
3227 /* - PWM5 --------------------------------------------------------------------*/
3229 /* PWM */
3231 };
3233 PWM5_A_MARK,
3234 };
3236 /* PWM */
3238 };
3240 PWM5_B_MARK,
3241 };
3242 /* - PWM6 --------------------------------------------------------------------*/
3244 /* PWM */
3246 };
3248 PWM6_A_MARK,
3249 };
3251 /* PWM */
3253 };
3255 PWM6_B_MARK,
3256 };
3258 /* - SCIF0 ------------------------------------------------------------------ */
3260 /* RX, TX */
3262 };
3265 };
3267 /* SCK */
3269 };
3271 SCK0_MARK,
3272 };
3274 /* RTS, CTS */
3276 };
3279 };
3280 /* - SCIF1 ------------------------------------------------------------------ */
3282 /* RX, TX */
3284 };
3287 };
3289 /* SCK */
3291 };
3293 SCK1_MARK,
3294 };
3296 /* RTS, CTS */
3298 };
3301 };
3304 /* RX, TX */
3306 };
3309 };
3310 /* - SCIF2 ------------------------------------------------------------------ */
3312 /* RX, TX */
3314 };
3317 };
3319 /* SCK */
3321 };
3323 SCK2_MARK,
3324 };
3326 /* RX, TX */
3328 };
3331 };
3332 /* - SCIF3 ------------------------------------------------------------------ */
3334 /* RX, TX */
3336 };
3339 };
3341 /* SCK */
3343 };
3345 SCK3_MARK,
3346 };
3348 /* RTS, CTS */
3350 };
3353 };
3355 /* RX, TX */
3357 };
3360 };
3361 /* - SCIF4 ------------------------------------------------------------------ */
3363 /* RX, TX */
3365 };
3368 };
3370 /* SCK */
3372 };
3374 SCK4_A_MARK,
3375 };
3377 /* RTS, CTS */
3379 };
3382 };
3384 /* RX, TX */
3386 };
3389 };
3391 /* SCK */
3393 };
3395 SCK4_B_MARK,
3396 };
3398 /* RTS, CTS */
3400 };
3403 };
3405 /* RX, TX */
3407 };
3410 };
3412 /* SCK */
3414 };
3416 SCK4_C_MARK,
3417 };
3419 /* RTS, CTS */
3421 };
3424 };
3425 /* - SCIF5 ------------------------------------------------------------------ */
3427 /* RX, TX */
3429 };
3432 };
3434 /* SCK */
3436 };
3438 SCK5_A_MARK,
3439 };
3442 /* RX, TX */
3444 };
3447 };
3449 /* SCK */
3451 };
3453 SCK5_B_MARK,
3454 };
3456 /* - SCIF Clock ------------------------------------------------------------- */
3458 /* SCIF_CLK */
3460 };
3462 SCIF_CLK_A_MARK,
3463 };
3465 /* SCIF_CLK */
3467 };
3469 SCIF_CLK_B_MARK,
3470 };
3472 /* - SDHI0 ------------------------------------------------------------------ */
3474 /* D0 */
3476 };
3478 SD0_DAT0_MARK,
3479 };
3481 /* D[0:3] */
3484 };
3488 };
3490 /* CLK, CMD */
3492 };
3495 };
3497 /* CD */
3499 };
3501 SD0_CD_MARK,
3502 };
3504 /* WP */
3506 };
3508 SD0_WP_MARK,
3509 };
3510 /* - SDHI1 ------------------------------------------------------------------ */
3512 /* D0 */
3514 };
3516 SD1_DAT0_MARK,
3517 };
3519 /* D[0:3] */
3522 };
3526 };
3528 /* CLK, CMD */
3530 };
3533 };
3535 /* CD */
3537 };
3539 SD1_CD_MARK,
3540 };
3542 /* WP */
3544 };
3546 SD1_WP_MARK,
3547 };
3548 /* - SDHI2 ------------------------------------------------------------------ */
3550 /* D0 */
3552 };
3554 SD2_DAT0_MARK,
3555 };
3557 /* D[0:3] */
3560 };
3564 };
3566 /* D[0:7] */
3571 };
3577 };
3579 /* CLK, CMD */
3581 };
3584 };
3586 /* CD */
3588 };
3590 SD2_CD_A_MARK,
3591 };
3593 /* CD */
3595 };
3597 SD2_CD_B_MARK,
3598 };
3600 /* WP */
3602 };
3604 SD2_WP_A_MARK,
3605 };
3607 /* WP */
3609 };
3611 SD2_WP_B_MARK,
3612 };
3614 /* DS */
3616 };
3618 SD2_DS_MARK,
3619 };
3620 /* - SDHI3 ------------------------------------------------------------------ */
3622 /* D0 */
3624 };
3626 SD3_DAT0_MARK,
3627 };
3629 /* D[0:3] */
3632 };
3636 };
3638 /* D[0:7] */
3643 };
3649 };
3651 /* CLK, CMD */
3653 };
3656 };
3658 /* CD */
3660 };
3662 SD3_CD_MARK,
3663 };
3665 /* WP */
3667 };
3669 SD3_WP_MARK,
3670 };
3672 /* DS */
3674 };
3676 SD3_DS_MARK,
3677 };
3679 /* - SSI -------------------------------------------------------------------- */
3681 /* SDATA */
3683 };
3685 SSI_SDATA0_MARK,
3686 };
3688 /* SCK, WS */
3690 };
3693 };
3695 /* SDATA */
3697 };
3699 SSI_SDATA1_A_MARK,
3700 };
3702 /* SDATA */
3704 };
3706 SSI_SDATA1_B_MARK,
3707 };
3709 /* SCK, WS */
3711 };
3714 };
3716 /* SCK, WS */
3718 };
3721 };
3723 /* SDATA */
3725 };
3727 SSI_SDATA2_A_MARK,
3728 };
3730 /* SDATA */
3732 };
3734 SSI_SDATA2_B_MARK,
3735 };
3737 /* SCK, WS */
3739 };
3742 };
3744 /* SCK, WS */
3746 };
3749 };
3751 /* SDATA */
3753 };
3755 SSI_SDATA3_MARK,
3756 };
3758 /* SCK, WS */
3760 };
3763 };
3765 /* SDATA */
3767 };
3769 SSI_SDATA4_MARK,
3770 };
3772 /* SCK, WS */
3774 };
3777 };
3779 /* SDATA */
3781 };
3783 SSI_SDATA5_MARK,
3784 };
3786 /* SCK, WS */
3788 };
3791 };
3793 /* SDATA */
3795 };
3797 SSI_SDATA6_MARK,
3798 };
3800 /* SCK, WS */
3802 };
3805 };
3807 /* SDATA */
3809 };
3811 SSI_SDATA7_MARK,
3812 };
3814 /* SCK, WS */
3816 };
3819 };
3821 /* SDATA */
3823 };
3825 SSI_SDATA8_MARK,
3826 };
3828 /* SDATA */
3830 };
3832 SSI_SDATA9_A_MARK,
3833 };
3835 /* SDATA */
3837 };
3839 SSI_SDATA9_B_MARK,
3840 };
3842 /* SCK, WS */
3844 };
3847 };
3849 /* SCK, WS */
3851 };
3854 };
3856 /* - TMU -------------------------------------------------------------------- */
3858 /* TCLK */
3860 };
3862 TCLK1_A_MARK,
3863 };
3865 /* TCLK */
3867 };
3869 TCLK1_B_MARK,
3870 };
3872 /* TCLK */
3874 };
3876 TCLK2_A_MARK,
3877 };
3879 /* TCLK */
3881 };
3883 TCLK2_B_MARK,
3884 };
3886 /* - TPU ------------------------------------------------------------------- */
3888 /* TPU0TO0 */
3890 };
3892 TPU0TO0_MARK,
3893 };
3895 /* TPU0TO1 */
3897 };
3899 TPU0TO1_MARK,
3900 };
3902 /* TPU0TO2 */
3904 };
3906 TPU0TO2_MARK,
3907 };
3909 /* TPU0TO3 */
3911 };
3913 TPU0TO3_MARK,
3914 };
3916 /* - USB0 ------------------------------------------------------------------- */
3918 /* PWEN, OVC */
3920 };
3923 };
3924 /* - USB1 ------------------------------------------------------------------- */
3926 /* PWEN, OVC */
3928 };
3931 };
3933 /* - USB30 ------------------------------------------------------------------ */
3935 /* PWEN, OVC */
3937 };
3940 };
3942 /* - VIN4 ------------------------------------------------------------------- */
3953 };
3964 };
3975 };
3986 };
4001 },
4002 };
4017 },
4018 };
4033 },
4034 };
4049 },
4050 };
4052 /* HSYNC#, VSYNC# */
4054 };
4057 };
4059 /* FIELD */
4061 };
4063 VI4_FIELD_MARK,
4064 };
4066 /* CLKENB */
4068 };
4070 VI4_CLKENB_MARK,
4071 };
4073 /* CLK */
4075 };
4077 VI4_CLK_MARK,
4078 };
4080 /* - VIN5 ------------------------------------------------------------------- */
4091 },
4092 };
4103 },
4104 };
4106 /* HSYNC#, VSYNC# */
4108 };
4111 };
4114 };
4116 /* FIELD */
4117 VI5_FIELD_MARK,
4118 };
4121 };
4123 /* CLKENB */
4124 VI5_CLKENB_MARK,
4125 };
4128 };
4130 /* CLK */
4131 VI5_CLK_MARK,
4132 };
4455 },
4487 }
4488 };
4508 };
4522 };
4527 };
4531 };
4535 };
4540 };
4544 };
4556 };
4568 };
4577 };
4586 };
4597 };
4603 };
4612 };
4624 };
4633 };
4640 };
4644 };
4649 };
4654 };
4658 };
4662 };
4668 };
4677 };
4686 };
4731 };
4758 };
4788 };
4792 };
4797 };
4802 };
4807 };
4812 };
4817 };
4822 };
4828 };
4835 };
4841 };
4848 };
4860 };
4867 };
4872 };
4880 };
4888 };
4900 };
4910 };
4938 };
4945 };
4952 };
4956 };
4960 };
4964 };
4985 };
4996 };
5053 },
5059 }
5060 };
5063 #define F_(x, y) FN_##y
5064 #define FM(x) FN_##x
5098 },
5132 },
5166 },
5200 },
5234 },
5268 },
5302 },
5336 },
5337 #undef F_
5338 #undef FM
5340 #define F_(x, y) x,
5341 #define FM(x) FN_##x,
5343 IP0_31_28
5344 IP0_27_24
5345 IP0_23_20
5346 IP0_19_16
5347 IP0_15_12
5348 IP0_11_8
5349 IP0_7_4
5350 IP0_3_0 ))
5351 },
5353 IP1_31_28
5354 IP1_27_24
5355 IP1_23_20
5356 IP1_19_16
5357 IP1_15_12
5358 IP1_11_8
5359 IP1_7_4
5360 IP1_3_0 ))
5361 },
5363 IP2_31_28
5364 IP2_27_24
5365 IP2_23_20
5366 IP2_19_16
5367 IP2_15_12
5368 IP2_11_8
5369 IP2_7_4
5370 IP2_3_0 ))
5371 },
5373 IP3_31_28
5374 IP3_27_24
5375 IP3_23_20
5376 IP3_19_16
5377 IP3_15_12
5378 IP3_11_8
5379 IP3_7_4
5380 IP3_3_0 ))
5381 },
5383 IP4_31_28
5384 IP4_27_24
5385 IP4_23_20
5386 IP4_19_16
5387 IP4_15_12
5388 IP4_11_8
5389 IP4_7_4
5390 IP4_3_0 ))
5391 },
5393 IP5_31_28
5394 IP5_27_24
5395 IP5_23_20
5396 IP5_19_16
5397 IP5_15_12
5398 IP5_11_8
5399 IP5_7_4
5400 IP5_3_0 ))
5401 },
5403 IP6_31_28
5404 IP6_27_24
5405 IP6_23_20
5406 IP6_19_16
5407 IP6_15_12
5408 IP6_11_8
5409 IP6_7_4
5410 IP6_3_0 ))
5411 },
5413 IP7_31_28
5414 IP7_27_24
5415 IP7_23_20
5416 IP7_19_16
5418 IP7_11_8
5419 IP7_7_4
5420 IP7_3_0 ))
5421 },
5423 IP8_31_28
5424 IP8_27_24
5425 IP8_23_20
5426 IP8_19_16
5427 IP8_15_12
5428 IP8_11_8
5429 IP8_7_4
5430 IP8_3_0 ))
5431 },
5433 IP9_31_28
5434 IP9_27_24
5435 IP9_23_20
5436 IP9_19_16
5437 IP9_15_12
5438 IP9_11_8
5439 IP9_7_4
5440 IP9_3_0 ))
5441 },
5443 IP10_31_28
5444 IP10_27_24
5445 IP10_23_20
5446 IP10_19_16
5447 IP10_15_12
5448 IP10_11_8
5449 IP10_7_4
5450 IP10_3_0 ))
5451 },
5453 IP11_31_28
5454 IP11_27_24
5455 IP11_23_20
5456 IP11_19_16
5457 IP11_15_12
5458 IP11_11_8
5459 IP11_7_4
5460 IP11_3_0 ))
5461 },
5463 IP12_31_28
5464 IP12_27_24
5465 IP12_23_20
5466 IP12_19_16
5467 IP12_15_12
5468 IP12_11_8
5469 IP12_7_4
5470 IP12_3_0 ))
5471 },
5473 IP13_31_28
5474 IP13_27_24
5475 IP13_23_20
5476 IP13_19_16
5477 IP13_15_12
5478 IP13_11_8
5479 IP13_7_4
5480 IP13_3_0 ))
5481 },
5483 IP14_31_28
5484 IP14_27_24
5485 IP14_23_20
5486 IP14_19_16
5487 IP14_15_12
5488 IP14_11_8
5489 IP14_7_4
5490 IP14_3_0 ))
5491 },
5493 IP15_31_28
5494 IP15_27_24
5495 IP15_23_20
5496 IP15_19_16
5497 IP15_15_12
5498 IP15_11_8
5499 IP15_7_4
5500 IP15_3_0 ))
5501 },
5503 IP16_31_28
5504 IP16_27_24
5505 IP16_23_20
5506 IP16_19_16
5507 IP16_15_12
5508 IP16_11_8
5509 IP16_7_4
5510 IP16_3_0 ))
5511 },
5513 IP17_31_28
5514 IP17_27_24
5515 IP17_23_20
5516 IP17_19_16
5517 IP17_15_12
5518 IP17_11_8
5519 IP17_7_4
5520 IP17_3_0 ))
5521 },
5529 IP18_7_4
5530 IP18_3_0 ))
5531 },
5532 #undef F_
5533 #undef FM
5535 #define F_(x, y) x,
5536 #define FM(x) FN_##x,
5541 MOD_SEL0_31_30_29
5542 MOD_SEL0_28_27
5543 MOD_SEL0_26_25_24
5544 MOD_SEL0_23
5545 MOD_SEL0_22
5546 MOD_SEL0_21
5547 MOD_SEL0_20
5548 MOD_SEL0_19
5549 MOD_SEL0_18_17
5550 MOD_SEL0_16
5552 MOD_SEL0_14_13
5553 MOD_SEL0_12
5554 MOD_SEL0_11
5555 MOD_SEL0_10
5556 MOD_SEL0_9_8
5557 MOD_SEL0_7_6
5558 MOD_SEL0_5
5559 MOD_SEL0_4_3
5560 /* RESERVED 2, 1, 0 */
5562 },
5567 MOD_SEL1_31_30
5568 MOD_SEL1_29_28_27
5569 MOD_SEL1_26
5570 MOD_SEL1_25_24
5571 MOD_SEL1_23_22_21
5572 MOD_SEL1_20
5573 MOD_SEL1_19
5574 MOD_SEL1_18_17
5575 MOD_SEL1_16
5576 MOD_SEL1_15_14
5577 MOD_SEL1_13
5578 MOD_SEL1_12
5579 MOD_SEL1_11
5580 MOD_SEL1_10
5581 MOD_SEL1_9
5583 MOD_SEL1_6
5584 MOD_SEL1_5
5585 MOD_SEL1_4
5586 MOD_SEL1_3
5587 MOD_SEL1_2
5588 MOD_SEL1_1
5589 MOD_SEL1_0 ))
5590 },
5595 MOD_SEL2_31
5596 MOD_SEL2_30
5597 MOD_SEL2_29
5598 MOD_SEL2_28_27
5599 MOD_SEL2_26
5600 MOD_SEL2_25_24_23
5601 MOD_SEL2_22
5602 MOD_SEL2_21
5603 MOD_SEL2_20
5604 MOD_SEL2_19
5605 MOD_SEL2_18
5606 MOD_SEL2_17
5607 /* RESERVED 16 */
5609 /* RESERVED 15, 14, 13, 12 */
5612 /* RESERVED 11, 10, 9, 8 */
5615 /* RESERVED 7, 6, 5, 4 */
5618 /* RESERVED 3, 2, 1 */
5620 MOD_SEL2_0 ))
5621 },
5622 { },
5623 };
5635 } },
5645 } },
5655 } },
5665 } },
5675 } },
5685 } },
5695 } },
5705 } },
5715 } },
5725 } },
5735 } },
5745 } },
5750 } },
5760 } },
5770 } },
5780 } },
5790 } },
5800 } },
5810 } },
5820 } },
5830 } },
5840 } },
5850 } },
5860 } },
5869 } },
5870 { },
5871 };
5874 POCCTRL,
5875 TDSELCTRL,
5876 };
5882 };
5885 {
5897 }
5933 } },
5967 } },
6001 } },
6035 } },
6069 } },
6103 } },
6137 } },
6139 };
6143 {
6155 else
6157 }
6161 {
6180 }
6186 };
6188 #ifdef CONFIG_PINCTRL_PFC_R8A774A1
6210 };
6211 #endif
6213 #ifdef CONFIG_PINCTRL_PFC_R8A77960
6237 };
6238 #endif
6240 #ifdef CONFIG_PINCTRL_PFC_R8A77961
6264 };
6265 #endif