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treewide: remove redundant IS_ERR() before error code check
[linux/fpc-iii.git] / drivers / pinctrl / sh-pfc / pfc-r8a77970.c
blob25e27b6bee89366fa56505df9c326b883d0075ec
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * R8A77970 processor support - PFC hardware block.
4 *
5 * Copyright (C) 2016 Renesas Electronics Corp.
6 * Copyright (C) 2017 Cogent Embedded, Inc. <source@cogentembedded.com>
7 *
8 * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c
9 *
10 * R-Car Gen3 processor support - PFC hardware block.
11 *
12 * Copyright (C) 2015 Renesas Electronics Corporation
13 */
14
15 #include <linux/errno.h>
16 #include <linux/io.h>
17 #include <linux/kernel.h>
18
19 #include "core.h"
20 #include "sh_pfc.h"
21
22 #define CPU_ALL_GP(fn, sfx) \
23 PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
24 PORT_GP_28(1, fn, sfx), \
25 PORT_GP_CFG_17(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
26 PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
27 PORT_GP_6(4, fn, sfx), \
28 PORT_GP_15(5, fn, sfx)
29 /*
30 * F_() : just information
31 * FM() : macro for FN_xxx / xxx_MARK
32 */
33
34 /* GPSR0 */
35 #define GPSR0_21 F_(DU_EXODDF_DU_ODDF_DISP_CDE, IP2_23_20)
36 #define GPSR0_20 F_(DU_EXVSYNC_DU_VSYNC, IP2_19_16)
37 #define GPSR0_19 F_(DU_EXHSYNC_DU_HSYNC, IP2_15_12)
38 #define GPSR0_18 F_(DU_DOTCLKOUT, IP2_11_8)
39 #define GPSR0_17 F_(DU_DB7, IP2_7_4)
40 #define GPSR0_16 F_(DU_DB6, IP2_3_0)
41 #define GPSR0_15 F_(DU_DB5, IP1_31_28)
42 #define GPSR0_14 F_(DU_DB4, IP1_27_24)
43 #define GPSR0_13 F_(DU_DB3, IP1_23_20)
44 #define GPSR0_12 F_(DU_DB2, IP1_19_16)
45 #define GPSR0_11 F_(DU_DG7, IP1_15_12)
46 #define GPSR0_10 F_(DU_DG6, IP1_11_8)
47 #define GPSR0_9 F_(DU_DG5, IP1_7_4)
48 #define GPSR0_8 F_(DU_DG4, IP1_3_0)
49 #define GPSR0_7 F_(DU_DG3, IP0_31_28)
50 #define GPSR0_6 F_(DU_DG2, IP0_27_24)
51 #define GPSR0_5 F_(DU_DR7, IP0_23_20)
52 #define GPSR0_4 F_(DU_DR6, IP0_19_16)
53 #define GPSR0_3 F_(DU_DR5, IP0_15_12)
54 #define GPSR0_2 F_(DU_DR4, IP0_11_8)
55 #define GPSR0_1 F_(DU_DR3, IP0_7_4)
56 #define GPSR0_0 F_(DU_DR2, IP0_3_0)
57
58 /* GPSR1 */
59 #define GPSR1_27 F_(DIGRF_CLKOUT, IP8_27_24)
60 #define GPSR1_26 F_(DIGRF_CLKIN, IP8_23_20)
61 #define GPSR1_25 F_(CANFD_CLK_A, IP8_19_16)
62 #define GPSR1_24 F_(CANFD1_RX, IP8_15_12)
63 #define GPSR1_23 F_(CANFD1_TX, IP8_11_8)
64 #define GPSR1_22 F_(CANFD0_RX_A, IP8_7_4)
65 #define GPSR1_21 F_(CANFD0_TX_A, IP8_3_0)
66 #define GPSR1_20 F_(AVB0_AVTP_CAPTURE, IP7_31_28)
67 #define GPSR1_19 FM(AVB0_AVTP_MATCH)
68 #define GPSR1_18 FM(AVB0_LINK)
69 #define GPSR1_17 FM(AVB0_PHY_INT)
70 #define GPSR1_16 FM(AVB0_MAGIC)
71 #define GPSR1_15 FM(AVB0_MDC)
72 #define GPSR1_14 FM(AVB0_MDIO)
73 #define GPSR1_13 FM(AVB0_TXCREFCLK)
74 #define GPSR1_12 FM(AVB0_TD3)
75 #define GPSR1_11 FM(AVB0_TD2)
76 #define GPSR1_10 FM(AVB0_TD1)
77 #define GPSR1_9 FM(AVB0_TD0)
78 #define GPSR1_8 FM(AVB0_TXC)
79 #define GPSR1_7 FM(AVB0_TX_CTL)
80 #define GPSR1_6 FM(AVB0_RD3)
81 #define GPSR1_5 FM(AVB0_RD2)
82 #define GPSR1_4 FM(AVB0_RD1)
83 #define GPSR1_3 FM(AVB0_RD0)
84 #define GPSR1_2 FM(AVB0_RXC)
85 #define GPSR1_1 FM(AVB0_RX_CTL)
86 #define GPSR1_0 F_(IRQ0, IP2_27_24)
87
88 /* GPSR2 */
89 #define GPSR2_16 F_(VI0_FIELD, IP4_31_28)
90 #define GPSR2_15 F_(VI0_DATA11, IP4_27_24)
91 #define GPSR2_14 F_(VI0_DATA10, IP4_23_20)
92 #define GPSR2_13 F_(VI0_DATA9, IP4_19_16)
93 #define GPSR2_12 F_(VI0_DATA8, IP4_15_12)
94 #define GPSR2_11 F_(VI0_DATA7, IP4_11_8)
95 #define GPSR2_10 F_(VI0_DATA6, IP4_7_4)
96 #define GPSR2_9 F_(VI0_DATA5, IP4_3_0)
97 #define GPSR2_8 F_(VI0_DATA4, IP3_31_28)
98 #define GPSR2_7 F_(VI0_DATA3, IP3_27_24)
99 #define GPSR2_6 F_(VI0_DATA2, IP3_23_20)
100 #define GPSR2_5 F_(VI0_DATA1, IP3_19_16)
101 #define GPSR2_4 F_(VI0_DATA0, IP3_15_12)
102 #define GPSR2_3 F_(VI0_VSYNC_N, IP3_11_8)
103 #define GPSR2_2 F_(VI0_HSYNC_N, IP3_7_4)
104 #define GPSR2_1 F_(VI0_CLKENB, IP3_3_0)
105 #define GPSR2_0 F_(VI0_CLK, IP2_31_28)
106
107 /* GPSR3 */
108 #define GPSR3_16 F_(VI1_FIELD, IP7_3_0)
109 #define GPSR3_15 F_(VI1_DATA11, IP6_31_28)
110 #define GPSR3_14 F_(VI1_DATA10, IP6_27_24)
111 #define GPSR3_13 F_(VI1_DATA9, IP6_23_20)
112 #define GPSR3_12 F_(VI1_DATA8, IP6_19_16)
113 #define GPSR3_11 F_(VI1_DATA7, IP6_15_12)
114 #define GPSR3_10 F_(VI1_DATA6, IP6_11_8)
115 #define GPSR3_9 F_(VI1_DATA5, IP6_7_4)
116 #define GPSR3_8 F_(VI1_DATA4, IP6_3_0)
117 #define GPSR3_7 F_(VI1_DATA3, IP5_31_28)
118 #define GPSR3_6 F_(VI1_DATA2, IP5_27_24)
119 #define GPSR3_5 F_(VI1_DATA1, IP5_23_20)
120 #define GPSR3_4 F_(VI1_DATA0, IP5_19_16)
121 #define GPSR3_3 F_(VI1_VSYNC_N, IP5_15_12)
122 #define GPSR3_2 F_(VI1_HSYNC_N, IP5_11_8)
123 #define GPSR3_1 F_(VI1_CLKENB, IP5_7_4)
124 #define GPSR3_0 F_(VI1_CLK, IP5_3_0)
125
126 /* GPSR4 */
127 #define GPSR4_5 F_(SDA2, IP7_27_24)
128 #define GPSR4_4 F_(SCL2, IP7_23_20)
129 #define GPSR4_3 F_(SDA1, IP7_19_16)
130 #define GPSR4_2 F_(SCL1, IP7_15_12)
131 #define GPSR4_1 F_(SDA0, IP7_11_8)
132 #define GPSR4_0 F_(SCL0, IP7_7_4)
133
134 /* GPSR5 */
135 #define GPSR5_14 FM(RPC_INT_N)
136 #define GPSR5_13 FM(RPC_WP_N)
137 #define GPSR5_12 FM(RPC_RESET_N)
138 #define GPSR5_11 FM(QSPI1_SSL)
139 #define GPSR5_10 FM(QSPI1_IO3)
140 #define GPSR5_9 FM(QSPI1_IO2)
141 #define GPSR5_8 FM(QSPI1_MISO_IO1)
142 #define GPSR5_7 FM(QSPI1_MOSI_IO0)
143 #define GPSR5_6 FM(QSPI1_SPCLK)
144 #define GPSR5_5 FM(QSPI0_SSL)
145 #define GPSR5_4 FM(QSPI0_IO3)
146 #define GPSR5_3 FM(QSPI0_IO2)
147 #define GPSR5_2 FM(QSPI0_MISO_IO1)
148 #define GPSR5_1 FM(QSPI0_MOSI_IO0)
149 #define GPSR5_0 FM(QSPI0_SPCLK)
150
151
152 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
153 #define IP0_3_0 FM(DU_DR2) FM(HSCK0) F_(0, 0) FM(A0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
154 #define IP0_7_4 FM(DU_DR3) FM(HRTS0_N) F_(0, 0) FM(A1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
155 #define IP0_11_8 FM(DU_DR4) FM(HCTS0_N) F_(0, 0) FM(A2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
156 #define IP0_15_12 FM(DU_DR5) FM(HTX0) F_(0, 0) FM(A3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
157 #define IP0_19_16 FM(DU_DR6) FM(MSIOF3_RXD) F_(0, 0) FM(A4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
158 #define IP0_23_20 FM(DU_DR7) FM(MSIOF3_TXD) F_(0, 0) FM(A5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
159 #define IP0_27_24 FM(DU_DG2) FM(MSIOF3_SS1) F_(0, 0) FM(A6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
160 #define IP0_31_28 FM(DU_DG3) FM(MSIOF3_SS2) F_(0, 0) FM(A7) FM(PWMFSW0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
161 #define IP1_3_0 FM(DU_DG4) F_(0, 0) F_(0, 0) FM(A8) FM(FSO_CFE_0_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
162 #define IP1_7_4 FM(DU_DG5) F_(0, 0) F_(0, 0) FM(A9) FM(FSO_CFE_1_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
163 #define IP1_11_8 FM(DU_DG6) F_(0, 0) F_(0, 0) FM(A10) FM(FSO_TOE_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
164 #define IP1_15_12 FM(DU_DG7) F_(0, 0) F_(0, 0) FM(A11) FM(IRQ1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
165 #define IP1_19_16 FM(DU_DB2) F_(0, 0) F_(0, 0) FM(A12) FM(IRQ2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
166 #define IP1_23_20 FM(DU_DB3) F_(0, 0) F_(0, 0) FM(A13) FM(FXR_CLKOUT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
167 #define IP1_27_24 FM(DU_DB4) F_(0, 0) F_(0, 0) FM(A14) FM(FXR_CLKOUT2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
168 #define IP1_31_28 FM(DU_DB5) F_(0, 0) F_(0, 0) FM(A15) FM(FXR_TXENA_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
169 #define IP2_3_0 FM(DU_DB6) F_(0, 0) F_(0, 0) FM(A16) FM(FXR_TXENB_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
170 #define IP2_7_4 FM(DU_DB7) F_(0, 0) F_(0, 0) FM(A17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
171 #define IP2_11_8 FM(DU_DOTCLKOUT) FM(SCIF_CLK_A) F_(0, 0) FM(A18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
172 #define IP2_15_12 FM(DU_EXHSYNC_DU_HSYNC) FM(HRX0) F_(0, 0) FM(A19) FM(IRQ3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
173 #define IP2_19_16 FM(DU_EXVSYNC_DU_VSYNC) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
174 #define IP2_23_20 FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
175 #define IP2_27_24 FM(IRQ0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
176 #define IP2_31_28 FM(VI0_CLK) FM(MSIOF2_SCK) FM(SCK3) F_(0, 0) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
177 #define IP3_3_0 FM(VI0_CLKENB) FM(MSIOF2_RXD) FM(RX3) FM(RD_WR_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
178 #define IP3_7_4 FM(VI0_HSYNC_N) FM(MSIOF2_TXD) FM(TX3) F_(0, 0) FM(HRTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
179 #define IP3_11_8 FM(VI0_VSYNC_N) FM(MSIOF2_SYNC) FM(CTS3_N) F_(0, 0) FM(HTX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
180 #define IP3_15_12 FM(VI0_DATA0) FM(MSIOF2_SS1) FM(RTS3_N) F_(0, 0) FM(HRX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
181 #define IP3_19_16 FM(VI0_DATA1) FM(MSIOF2_SS2) FM(SCK1) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
182 #define IP3_23_20 FM(VI0_DATA2) FM(AVB0_AVTP_PPS) FM(SDA3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
183 #define IP3_27_24 FM(VI0_DATA3) FM(HSCK1) FM(SCL3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
184 #define IP3_31_28 FM(VI0_DATA4) FM(HRTS1_N) FM(RX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
185 #define IP4_3_0 FM(VI0_DATA5) FM(HCTS1_N) FM(TX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
186 #define IP4_7_4 FM(VI0_DATA6) FM(HTX1) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
187 #define IP4_11_8 FM(VI0_DATA7) FM(HRX1) FM(RTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
188 #define IP4_15_12 FM(VI0_DATA8) FM(HSCK2) FM(PWM0_A) FM(A22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
189 #define IP4_19_16 FM(VI0_DATA9) FM(HCTS2_N) FM(PWM1_A) FM(A23) FM(FSO_CFE_0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
190 #define IP4_23_20 FM(VI0_DATA10) FM(HRTS2_N) FM(PWM2_A) FM(A24) FM(FSO_CFE_1_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
191 #define IP4_27_24 FM(VI0_DATA11) FM(HTX2) FM(PWM3_A) FM(A25) FM(FSO_TOE_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
192 #define IP4_31_28 FM(VI0_FIELD) FM(HRX2) FM(PWM4_A) FM(CS1_N) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
193 #define IP5_3_0 FM(VI1_CLK) FM(MSIOF1_RXD) F_(0, 0) FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
194 #define IP5_7_4 FM(VI1_CLKENB) FM(MSIOF1_TXD) F_(0, 0) FM(D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
195 #define IP5_11_8 FM(VI1_HSYNC_N) FM(MSIOF1_SCK) F_(0, 0) FM(D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
196 #define IP5_15_12 FM(VI1_VSYNC_N) FM(MSIOF1_SYNC) F_(0, 0) FM(D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
197 #define IP5_19_16 FM(VI1_DATA0) FM(MSIOF1_SS1) F_(0, 0) FM(D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
198 #define IP5_23_20 FM(VI1_DATA1) FM(MSIOF1_SS2) F_(0, 0) FM(D4) FM(MMC_CMD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
199 #define IP5_27_24 FM(VI1_DATA2) FM(CANFD0_TX_B) F_(0, 0) FM(D5) FM(MMC_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
200 #define IP5_31_28 FM(VI1_DATA3) FM(CANFD0_RX_B) F_(0, 0) FM(D6) FM(MMC_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
201 #define IP6_3_0 FM(VI1_DATA4) FM(CANFD_CLK_B) F_(0, 0) FM(D7) FM(MMC_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
202 #define IP6_7_4 FM(VI1_DATA5) F_(0, 0) FM(SCK4) FM(D8) FM(MMC_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
203 #define IP6_11_8 FM(VI1_DATA6) F_(0, 0) FM(RX4) FM(D9) FM(MMC_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
204 #define IP6_15_12 FM(VI1_DATA7) F_(0, 0) FM(TX4) FM(D10) FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
205 #define IP6_19_16 FM(VI1_DATA8) F_(0, 0) FM(CTS4_N) FM(D11) FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
206 #define IP6_23_20 FM(VI1_DATA9) F_(0, 0) FM(RTS4_N) FM(D12) FM(MMC_D6) FM(SCL3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
207 #define IP6_27_24 FM(VI1_DATA10) F_(0, 0) F_(0, 0) FM(D13) FM(MMC_D7) FM(SDA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
208 #define IP6_31_28 FM(VI1_DATA11) FM(SCL4) FM(IRQ4) FM(D14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
209 #define IP7_3_0 FM(VI1_FIELD) FM(SDA4) FM(IRQ5) FM(D15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
210 #define IP7_7_4 FM(SCL0) FM(DU_DR0) FM(TPU0TO0) FM(CLKOUT) F_(0, 0) FM(MSIOF0_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
211 #define IP7_11_8 FM(SDA0) FM(DU_DR1) FM(TPU0TO1) FM(BS_N) FM(SCK0) FM(MSIOF0_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
212 #define IP7_15_12 FM(SCL1) FM(DU_DG0) FM(TPU0TO2) FM(RD_N) FM(CTS0_N) FM(MSIOF0_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
213 #define IP7_19_16 FM(SDA1) FM(DU_DG1) FM(TPU0TO3) FM(WE0_N) FM(RTS0_N) FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
214 #define IP7_23_20 FM(SCL2) FM(DU_DB0) FM(TCLK1_A) FM(WE1_N) FM(RX0) FM(MSIOF0_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
215 #define IP7_27_24 FM(SDA2) FM(DU_DB1) FM(TCLK2_A) FM(EX_WAIT0) FM(TX0) FM(MSIOF0_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
216 #define IP7_31_28 FM(AVB0_AVTP_CAPTURE) F_(0, 0) F_(0, 0) F_(0, 0) FM(FSCLKST2_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
217 #define IP8_3_0 FM(CANFD0_TX_A) FM(FXR_TXDA) FM(PWM0_B) FM(DU_DISP) FM(FSCLKST2_N_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
218 #define IP8_7_4 FM(CANFD0_RX_A) FM(RXDA_EXTFXR) FM(PWM1_B) FM(DU_CDE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219 #define IP8_11_8 FM(CANFD1_TX) FM(FXR_TXDB) FM(PWM2_B) FM(TCLK1_B) FM(TX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220 #define IP8_15_12 FM(CANFD1_RX) FM(RXDB_EXTFXR) FM(PWM3_B) FM(TCLK2_B) FM(RX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221 #define IP8_19_16 FM(CANFD_CLK_A) FM(CLK_EXTFXR) FM(PWM4_B) FM(SPEEDIN_B) FM(SCIF_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222 #define IP8_23_20 FM(DIGRF_CLKIN) FM(DIGRF_CLKEN_IN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223 #define IP8_27_24 FM(DIGRF_CLKOUT) FM(DIGRF_CLKEN_OUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
224 #define IP8_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225
226 #define PINMUX_GPSR \
227 \
228 GPSR1_27 \
229 GPSR1_26 \
230 GPSR1_25 \
231 GPSR1_24 \
232 GPSR1_23 \
233 GPSR1_22 \
234 GPSR0_21 GPSR1_21 \
235 GPSR0_20 GPSR1_20 \
236 GPSR0_19 GPSR1_19 \
237 GPSR0_18 GPSR1_18 \
238 GPSR0_17 GPSR1_17 \
239 GPSR0_16 GPSR1_16 GPSR2_16 GPSR3_16 \
240 GPSR0_15 GPSR1_15 GPSR2_15 GPSR3_15 \
241 GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR5_14 \
242 GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR5_13 \
243 GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR5_12 \
244 GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR5_11 \
245 GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR5_10 \
246 GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR5_9 \
247 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR5_8 \
248 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR5_7 \
249 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR5_6 \
250 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 \
251 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 \
252 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 \
253 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 \
254 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 \
255 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0
256
257 #define PINMUX_IPSR \
258 \
259 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
260 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
261 FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
262 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
263 FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
264 FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
265 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
266 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
267 \
268 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
269 FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
270 FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
271 FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \
272 FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
273 FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
274 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
275 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
276 \
277 FM(IP8_3_0) IP8_3_0 \
278 FM(IP8_7_4) IP8_7_4 \
279 FM(IP8_11_8) IP8_11_8 \
280 FM(IP8_15_12) IP8_15_12 \
281 FM(IP8_19_16) IP8_19_16 \
282 FM(IP8_23_20) IP8_23_20 \
283 FM(IP8_27_24) IP8_27_24 \
284 FM(IP8_31_28) IP8_31_28
285
286 /* MOD_SEL0 */ /* 0 */ /* 1 */
287 #define MOD_SEL0_11 FM(SEL_I2C3_0) FM(SEL_I2C3_1)
288 #define MOD_SEL0_10 FM(SEL_HSCIF0_0) FM(SEL_HSCIF0_1)
289 #define MOD_SEL0_9 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
290 #define MOD_SEL0_8 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
291 #define MOD_SEL0_7 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
292 #define MOD_SEL0_6 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
293 #define MOD_SEL0_5 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
294 #define MOD_SEL0_4 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
295 #define MOD_SEL0_3 FM(SEL_PWM0_0) FM(SEL_PWM0_1)
296 #define MOD_SEL0_2 FM(SEL_RFSO_0) FM(SEL_RFSO_1)
297 #define MOD_SEL0_1 FM(SEL_RSP_0) FM(SEL_RSP_1)
298 #define MOD_SEL0_0 FM(SEL_TMU_0) FM(SEL_TMU_1)
299
300 #define PINMUX_MOD_SELS \
301 \
302 MOD_SEL0_11 \
303 MOD_SEL0_10 \
304 MOD_SEL0_9 \
305 MOD_SEL0_8 \
306 MOD_SEL0_7 \
307 MOD_SEL0_6 \
308 MOD_SEL0_5 \
309 MOD_SEL0_4 \
310 MOD_SEL0_3 \
311 MOD_SEL0_2 \
312 MOD_SEL0_1 \
313 MOD_SEL0_0
314
315 enum {
316 PINMUX_RESERVED = 0,
317
318 PINMUX_DATA_BEGIN,
319 GP_ALL(DATA),
320 PINMUX_DATA_END,
321
322 #define F_(x, y)
323 #define FM(x) FN_##x,
324 PINMUX_FUNCTION_BEGIN,
325 GP_ALL(FN),
326 PINMUX_GPSR
327 PINMUX_IPSR
328 PINMUX_MOD_SELS
329 PINMUX_FUNCTION_END,
330 #undef F_
331 #undef FM
332
333 #define F_(x, y)
334 #define FM(x) x##_MARK,
335 PINMUX_MARK_BEGIN,
336 PINMUX_GPSR
337 PINMUX_IPSR
338 PINMUX_MOD_SELS
339 PINMUX_MARK_END,
340 #undef F_
341 #undef FM
342 };
343
344 static const u16 pinmux_data[] = {
345 PINMUX_DATA_GP_ALL(),
346
347 PINMUX_SINGLE(AVB0_RX_CTL),
348 PINMUX_SINGLE(AVB0_RXC),
349 PINMUX_SINGLE(AVB0_RD0),
350 PINMUX_SINGLE(AVB0_RD1),
351 PINMUX_SINGLE(AVB0_RD2),
352 PINMUX_SINGLE(AVB0_RD3),
353 PINMUX_SINGLE(AVB0_TX_CTL),
354 PINMUX_SINGLE(AVB0_TXC),
355 PINMUX_SINGLE(AVB0_TD0),
356 PINMUX_SINGLE(AVB0_TD1),
357 PINMUX_SINGLE(AVB0_TD2),
358 PINMUX_SINGLE(AVB0_TD3),
359 PINMUX_SINGLE(AVB0_TXCREFCLK),
360 PINMUX_SINGLE(AVB0_MDIO),
361 PINMUX_SINGLE(AVB0_MDC),
362 PINMUX_SINGLE(AVB0_MAGIC),
363 PINMUX_SINGLE(AVB0_PHY_INT),
364 PINMUX_SINGLE(AVB0_LINK),
365 PINMUX_SINGLE(AVB0_AVTP_MATCH),
366
367 PINMUX_SINGLE(QSPI0_SPCLK),
368 PINMUX_SINGLE(QSPI0_MOSI_IO0),
369 PINMUX_SINGLE(QSPI0_MISO_IO1),
370 PINMUX_SINGLE(QSPI0_IO2),
371 PINMUX_SINGLE(QSPI0_IO3),
372 PINMUX_SINGLE(QSPI0_SSL),
373 PINMUX_SINGLE(QSPI1_SPCLK),
374 PINMUX_SINGLE(QSPI1_MOSI_IO0),
375 PINMUX_SINGLE(QSPI1_MISO_IO1),
376 PINMUX_SINGLE(QSPI1_IO2),
377 PINMUX_SINGLE(QSPI1_IO3),
378 PINMUX_SINGLE(QSPI1_SSL),
379 PINMUX_SINGLE(RPC_RESET_N),
380 PINMUX_SINGLE(RPC_WP_N),
381 PINMUX_SINGLE(RPC_INT_N),
382
383 /* IPSR0 */
384 PINMUX_IPSR_GPSR(IP0_3_0, DU_DR2),
385 PINMUX_IPSR_GPSR(IP0_3_0, HSCK0),
386 PINMUX_IPSR_GPSR(IP0_3_0, A0),
387
388 PINMUX_IPSR_GPSR(IP0_7_4, DU_DR3),
389 PINMUX_IPSR_GPSR(IP0_7_4, HRTS0_N),
390 PINMUX_IPSR_GPSR(IP0_7_4, A1),
391
392 PINMUX_IPSR_GPSR(IP0_11_8, DU_DR4),
393 PINMUX_IPSR_GPSR(IP0_11_8, HCTS0_N),
394 PINMUX_IPSR_GPSR(IP0_11_8, A2),
395
396 PINMUX_IPSR_GPSR(IP0_15_12, DU_DR5),
397 PINMUX_IPSR_GPSR(IP0_15_12, HTX0),
398 PINMUX_IPSR_GPSR(IP0_15_12, A3),
399
400 PINMUX_IPSR_GPSR(IP0_19_16, DU_DR6),
401 PINMUX_IPSR_GPSR(IP0_19_16, MSIOF3_RXD),
402 PINMUX_IPSR_GPSR(IP0_19_16, A4),
403
404 PINMUX_IPSR_GPSR(IP0_23_20, DU_DR7),
405 PINMUX_IPSR_GPSR(IP0_23_20, MSIOF3_TXD),
406 PINMUX_IPSR_GPSR(IP0_23_20, A5),
407
408 PINMUX_IPSR_GPSR(IP0_27_24, DU_DG2),
409 PINMUX_IPSR_GPSR(IP0_27_24, MSIOF3_SS1),
410 PINMUX_IPSR_GPSR(IP0_27_24, A6),
411
412 PINMUX_IPSR_GPSR(IP0_31_28, DU_DG3),
413 PINMUX_IPSR_GPSR(IP0_31_28, MSIOF3_SS2),
414 PINMUX_IPSR_GPSR(IP0_31_28, A7),
415 PINMUX_IPSR_GPSR(IP0_31_28, PWMFSW0),
416
417 /* IPSR1 */
418 PINMUX_IPSR_GPSR(IP1_3_0, DU_DG4),
419 PINMUX_IPSR_GPSR(IP1_3_0, A8),
420 PINMUX_IPSR_MSEL(IP1_3_0, FSO_CFE_0_N_A, SEL_RFSO_0),
421
422 PINMUX_IPSR_GPSR(IP1_7_4, DU_DG5),
423 PINMUX_IPSR_GPSR(IP1_7_4, A9),
424 PINMUX_IPSR_MSEL(IP1_7_4, FSO_CFE_1_N_A, SEL_RFSO_0),
425
426 PINMUX_IPSR_GPSR(IP1_11_8, DU_DG6),
427 PINMUX_IPSR_GPSR(IP1_11_8, A10),
428 PINMUX_IPSR_MSEL(IP1_11_8, FSO_TOE_N_A, SEL_RFSO_0),
429
430 PINMUX_IPSR_GPSR(IP1_15_12, DU_DG7),
431 PINMUX_IPSR_GPSR(IP1_15_12, A11),
432 PINMUX_IPSR_GPSR(IP1_15_12, IRQ1),
433
434 PINMUX_IPSR_GPSR(IP1_19_16, DU_DB2),
435 PINMUX_IPSR_GPSR(IP1_19_16, A12),
436 PINMUX_IPSR_GPSR(IP1_19_16, IRQ2),
437
438 PINMUX_IPSR_GPSR(IP1_23_20, DU_DB3),
439 PINMUX_IPSR_GPSR(IP1_23_20, A13),
440 PINMUX_IPSR_GPSR(IP1_23_20, FXR_CLKOUT1),
441
442 PINMUX_IPSR_GPSR(IP1_27_24, DU_DB4),
443 PINMUX_IPSR_GPSR(IP1_27_24, A14),
444 PINMUX_IPSR_GPSR(IP1_27_24, FXR_CLKOUT2),
445
446 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB5),
447 PINMUX_IPSR_GPSR(IP1_31_28, A15),
448 PINMUX_IPSR_GPSR(IP1_31_28, FXR_TXENA_N),
449
450 /* IPSR2 */
451 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB6),
452 PINMUX_IPSR_GPSR(IP2_3_0, A16),
453 PINMUX_IPSR_GPSR(IP2_3_0, FXR_TXENB_N),
454
455 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB7),
456 PINMUX_IPSR_GPSR(IP2_7_4, A17),
457
458 PINMUX_IPSR_GPSR(IP2_11_8, DU_DOTCLKOUT),
459 PINMUX_IPSR_MSEL(IP2_11_8, SCIF_CLK_A, SEL_HSCIF0_0),
460 PINMUX_IPSR_GPSR(IP2_11_8, A18),
461
462 PINMUX_IPSR_GPSR(IP2_15_12, DU_EXHSYNC_DU_HSYNC),
463 PINMUX_IPSR_GPSR(IP2_15_12, HRX0),
464 PINMUX_IPSR_GPSR(IP2_15_12, A19),
465 PINMUX_IPSR_GPSR(IP2_15_12, IRQ3),
466
467 PINMUX_IPSR_GPSR(IP2_19_16, DU_EXVSYNC_DU_VSYNC),
468 PINMUX_IPSR_GPSR(IP2_19_16, MSIOF3_SCK),
469
470 PINMUX_IPSR_GPSR(IP2_23_20, DU_EXODDF_DU_ODDF_DISP_CDE),
471 PINMUX_IPSR_GPSR(IP2_23_20, MSIOF3_SYNC),
472
473 PINMUX_IPSR_GPSR(IP2_27_24, IRQ0),
474
475 PINMUX_IPSR_GPSR(IP2_31_28, VI0_CLK),
476 PINMUX_IPSR_GPSR(IP2_31_28, MSIOF2_SCK),
477 PINMUX_IPSR_GPSR(IP2_31_28, SCK3),
478 PINMUX_IPSR_GPSR(IP2_31_28, HSCK3),
479
480 /* IPSR3 */
481 PINMUX_IPSR_GPSR(IP3_3_0, VI0_CLKENB),
482 PINMUX_IPSR_GPSR(IP3_3_0, MSIOF2_RXD),
483 PINMUX_IPSR_GPSR(IP3_3_0, RX3),
484 PINMUX_IPSR_GPSR(IP3_3_0, RD_WR_N),
485 PINMUX_IPSR_GPSR(IP3_3_0, HCTS3_N),
486
487 PINMUX_IPSR_GPSR(IP3_7_4, VI0_HSYNC_N),
488 PINMUX_IPSR_GPSR(IP3_7_4, MSIOF2_TXD),
489 PINMUX_IPSR_GPSR(IP3_7_4, TX3),
490 PINMUX_IPSR_GPSR(IP3_7_4, HRTS3_N),
491
492 PINMUX_IPSR_GPSR(IP3_11_8, VI0_VSYNC_N),
493 PINMUX_IPSR_GPSR(IP3_11_8, MSIOF2_SYNC),
494 PINMUX_IPSR_GPSR(IP3_11_8, CTS3_N),
495 PINMUX_IPSR_GPSR(IP3_11_8, HTX3),
496
497 PINMUX_IPSR_GPSR(IP3_15_12, VI0_DATA0),
498 PINMUX_IPSR_GPSR(IP3_15_12, MSIOF2_SS1),
499 PINMUX_IPSR_GPSR(IP3_15_12, RTS3_N),
500 PINMUX_IPSR_GPSR(IP3_15_12, HRX3),
501
502 PINMUX_IPSR_GPSR(IP3_19_16, VI0_DATA1),
503 PINMUX_IPSR_GPSR(IP3_19_16, MSIOF2_SS2),
504 PINMUX_IPSR_GPSR(IP3_19_16, SCK1),
505 PINMUX_IPSR_MSEL(IP3_19_16, SPEEDIN_A, SEL_RSP_0),
506
507 PINMUX_IPSR_GPSR(IP3_23_20, VI0_DATA2),
508 PINMUX_IPSR_GPSR(IP3_23_20, AVB0_AVTP_PPS),
509 PINMUX_IPSR_MSEL(IP3_23_20, SDA3_A, SEL_I2C3_0),
510
511 PINMUX_IPSR_GPSR(IP3_27_24, VI0_DATA3),
512 PINMUX_IPSR_GPSR(IP3_27_24, HSCK1),
513 PINMUX_IPSR_MSEL(IP3_27_24, SCL3_A, SEL_I2C3_0),
514
515 PINMUX_IPSR_GPSR(IP3_31_28, VI0_DATA4),
516 PINMUX_IPSR_GPSR(IP3_31_28, HRTS1_N),
517 PINMUX_IPSR_MSEL(IP3_31_28, RX1_A, SEL_SCIF1_0),
518
519 /* IPSR4 */
520 PINMUX_IPSR_GPSR(IP4_3_0, VI0_DATA5),
521 PINMUX_IPSR_GPSR(IP4_3_0, HCTS1_N),
522 PINMUX_IPSR_MSEL(IP4_3_0, TX1_A, SEL_SCIF1_0),
523
524 PINMUX_IPSR_GPSR(IP4_7_4, VI0_DATA6),
525 PINMUX_IPSR_GPSR(IP4_7_4, HTX1),
526 PINMUX_IPSR_GPSR(IP4_7_4, CTS1_N),
527
528 PINMUX_IPSR_GPSR(IP4_11_8, VI0_DATA7),
529 PINMUX_IPSR_GPSR(IP4_11_8, HRX1),
530 PINMUX_IPSR_GPSR(IP4_11_8, RTS1_N),
531
532 PINMUX_IPSR_GPSR(IP4_15_12, VI0_DATA8),
533 PINMUX_IPSR_GPSR(IP4_15_12, HSCK2),
534 PINMUX_IPSR_MSEL(IP4_15_12, PWM0_A, SEL_PWM0_0),
535
536 PINMUX_IPSR_GPSR(IP4_19_16, VI0_DATA9),
537 PINMUX_IPSR_GPSR(IP4_19_16, HCTS2_N),
538 PINMUX_IPSR_MSEL(IP4_19_16, PWM1_A, SEL_PWM1_0),
539 PINMUX_IPSR_MSEL(IP4_19_16, FSO_CFE_0_N_B, SEL_RFSO_1),
540
541 PINMUX_IPSR_GPSR(IP4_23_20, VI0_DATA10),
542 PINMUX_IPSR_GPSR(IP4_23_20, HRTS2_N),
543 PINMUX_IPSR_MSEL(IP4_23_20, PWM2_A, SEL_PWM2_0),
544 PINMUX_IPSR_MSEL(IP4_23_20, FSO_CFE_1_N_B, SEL_RFSO_1),
545
546 PINMUX_IPSR_GPSR(IP4_27_24, VI0_DATA11),
547 PINMUX_IPSR_GPSR(IP4_27_24, HTX2),
548 PINMUX_IPSR_MSEL(IP4_27_24, PWM3_A, SEL_PWM3_0),
549 PINMUX_IPSR_MSEL(IP4_27_24, FSO_TOE_N_B, SEL_RFSO_1),
550
551 PINMUX_IPSR_GPSR(IP4_31_28, VI0_FIELD),
552 PINMUX_IPSR_GPSR(IP4_31_28, HRX2),
553 PINMUX_IPSR_MSEL(IP4_31_28, PWM4_A, SEL_PWM4_0),
554 PINMUX_IPSR_GPSR(IP4_31_28, CS1_N),
555 PINMUX_IPSR_GPSR(IP4_31_28, FSCLKST2_N_A),
556
557 /* IPSR5 */
558 PINMUX_IPSR_GPSR(IP5_3_0, VI1_CLK),
559 PINMUX_IPSR_GPSR(IP5_3_0, MSIOF1_RXD),
560 PINMUX_IPSR_GPSR(IP5_3_0, CS0_N),
561
562 PINMUX_IPSR_GPSR(IP5_7_4, VI1_CLKENB),
563 PINMUX_IPSR_GPSR(IP5_7_4, MSIOF1_TXD),
564 PINMUX_IPSR_GPSR(IP5_7_4, D0),
565
566 PINMUX_IPSR_GPSR(IP5_11_8, VI1_HSYNC_N),
567 PINMUX_IPSR_GPSR(IP5_11_8, MSIOF1_SCK),
568 PINMUX_IPSR_GPSR(IP5_11_8, D1),
569
570 PINMUX_IPSR_GPSR(IP5_15_12, VI1_VSYNC_N),
571 PINMUX_IPSR_GPSR(IP5_15_12, MSIOF1_SYNC),
572 PINMUX_IPSR_GPSR(IP5_15_12, D2),
573
574 PINMUX_IPSR_GPSR(IP5_19_16, VI1_DATA0),
575 PINMUX_IPSR_GPSR(IP5_19_16, MSIOF1_SS1),
576 PINMUX_IPSR_GPSR(IP5_19_16, D3),
577
578 PINMUX_IPSR_GPSR(IP5_23_20, VI1_DATA1),
579 PINMUX_IPSR_GPSR(IP5_23_20, MSIOF1_SS2),
580 PINMUX_IPSR_GPSR(IP5_23_20, D4),
581 PINMUX_IPSR_GPSR(IP5_23_20, MMC_CMD),
582
583 PINMUX_IPSR_GPSR(IP5_27_24, VI1_DATA2),
584 PINMUX_IPSR_MSEL(IP5_27_24, CANFD0_TX_B, SEL_CANFD0_1),
585 PINMUX_IPSR_GPSR(IP5_27_24, D5),
586 PINMUX_IPSR_GPSR(IP5_27_24, MMC_D0),
587
588 PINMUX_IPSR_GPSR(IP5_31_28, VI1_DATA3),
589 PINMUX_IPSR_MSEL(IP5_31_28, CANFD0_RX_B, SEL_CANFD0_1),
590 PINMUX_IPSR_GPSR(IP5_31_28, D6),
591 PINMUX_IPSR_GPSR(IP5_31_28, MMC_D1),
592
593 /* IPSR6 */
594 PINMUX_IPSR_GPSR(IP6_3_0, VI1_DATA4),
595 PINMUX_IPSR_MSEL(IP6_3_0, CANFD_CLK_B, SEL_CANFD0_1),
596 PINMUX_IPSR_GPSR(IP6_3_0, D7),
597 PINMUX_IPSR_GPSR(IP6_3_0, MMC_D2),
598
599 PINMUX_IPSR_GPSR(IP6_7_4, VI1_DATA5),
600 PINMUX_IPSR_GPSR(IP6_7_4, SCK4),
601 PINMUX_IPSR_GPSR(IP6_7_4, D8),
602 PINMUX_IPSR_GPSR(IP6_7_4, MMC_D3),
603
604 PINMUX_IPSR_GPSR(IP6_11_8, VI1_DATA6),
605 PINMUX_IPSR_GPSR(IP6_11_8, RX4),
606 PINMUX_IPSR_GPSR(IP6_11_8, D9),
607 PINMUX_IPSR_GPSR(IP6_11_8, MMC_CLK),
608
609 PINMUX_IPSR_GPSR(IP6_15_12, VI1_DATA7),
610 PINMUX_IPSR_GPSR(IP6_15_12, TX4),
611 PINMUX_IPSR_GPSR(IP6_15_12, D10),
612 PINMUX_IPSR_GPSR(IP6_15_12, MMC_D4),
613
614 PINMUX_IPSR_GPSR(IP6_19_16, VI1_DATA8),
615 PINMUX_IPSR_GPSR(IP6_19_16, CTS4_N),
616 PINMUX_IPSR_GPSR(IP6_19_16, D11),
617 PINMUX_IPSR_GPSR(IP6_19_16, MMC_D5),
618
619 PINMUX_IPSR_GPSR(IP6_23_20, VI1_DATA9),
620 PINMUX_IPSR_GPSR(IP6_23_20, RTS4_N),
621 PINMUX_IPSR_GPSR(IP6_23_20, D12),
622 PINMUX_IPSR_GPSR(IP6_23_20, MMC_D6),
623 PINMUX_IPSR_MSEL(IP6_23_20, SCL3_B, SEL_I2C3_1),
624
625 PINMUX_IPSR_GPSR(IP6_27_24, VI1_DATA10),
626 PINMUX_IPSR_GPSR(IP6_27_24, D13),
627 PINMUX_IPSR_GPSR(IP6_27_24, MMC_D7),
628 PINMUX_IPSR_MSEL(IP6_27_24, SDA3_B, SEL_I2C3_1),
629
630 PINMUX_IPSR_GPSR(IP6_31_28, VI1_DATA11),
631 PINMUX_IPSR_GPSR(IP6_31_28, SCL4),
632 PINMUX_IPSR_GPSR(IP6_31_28, IRQ4),
633 PINMUX_IPSR_GPSR(IP6_31_28, D14),
634
635 /* IPSR7 */
636 PINMUX_IPSR_GPSR(IP7_3_0, VI1_FIELD),
637 PINMUX_IPSR_GPSR(IP7_3_0, SDA4),
638 PINMUX_IPSR_GPSR(IP7_3_0, IRQ5),
639 PINMUX_IPSR_GPSR(IP7_3_0, D15),
640
641 PINMUX_IPSR_GPSR(IP7_7_4, SCL0),
642 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR0),
643 PINMUX_IPSR_GPSR(IP7_7_4, TPU0TO0),
644 PINMUX_IPSR_GPSR(IP7_7_4, CLKOUT),
645 PINMUX_IPSR_GPSR(IP7_7_4, MSIOF0_RXD),
646
647 PINMUX_IPSR_GPSR(IP7_11_8, SDA0),
648 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR1),
649 PINMUX_IPSR_GPSR(IP7_11_8, TPU0TO1),
650 PINMUX_IPSR_GPSR(IP7_11_8, BS_N),
651 PINMUX_IPSR_GPSR(IP7_11_8, SCK0),
652 PINMUX_IPSR_GPSR(IP7_11_8, MSIOF0_TXD),
653
654 PINMUX_IPSR_GPSR(IP7_15_12, SCL1),
655 PINMUX_IPSR_GPSR(IP7_15_12, DU_DG0),
656 PINMUX_IPSR_GPSR(IP7_15_12, TPU0TO2),
657 PINMUX_IPSR_GPSR(IP7_15_12, RD_N),
658 PINMUX_IPSR_GPSR(IP7_15_12, CTS0_N),
659 PINMUX_IPSR_GPSR(IP7_15_12, MSIOF0_SCK),
660
661 PINMUX_IPSR_GPSR(IP7_19_16, SDA1),
662 PINMUX_IPSR_GPSR(IP7_19_16, DU_DG1),
663 PINMUX_IPSR_GPSR(IP7_19_16, TPU0TO3),
664 PINMUX_IPSR_GPSR(IP7_19_16, WE0_N),
665 PINMUX_IPSR_GPSR(IP7_19_16, RTS0_N),
666 PINMUX_IPSR_GPSR(IP7_19_16, MSIOF0_SYNC),
667
668 PINMUX_IPSR_GPSR(IP7_23_20, SCL2),
669 PINMUX_IPSR_GPSR(IP7_23_20, DU_DB0),
670 PINMUX_IPSR_MSEL(IP7_23_20, TCLK1_A, SEL_TMU_0),
671 PINMUX_IPSR_GPSR(IP7_23_20, WE1_N),
672 PINMUX_IPSR_GPSR(IP7_23_20, RX0),
673 PINMUX_IPSR_GPSR(IP7_23_20, MSIOF0_SS1),
674
675 PINMUX_IPSR_GPSR(IP7_27_24, SDA2),
676 PINMUX_IPSR_GPSR(IP7_27_24, DU_DB1),
677 PINMUX_IPSR_MSEL(IP7_27_24, TCLK2_A, SEL_TMU_0),
678 PINMUX_IPSR_GPSR(IP7_27_24, EX_WAIT0),
679 PINMUX_IPSR_GPSR(IP7_27_24, TX0),
680 PINMUX_IPSR_GPSR(IP7_27_24, MSIOF0_SS2),
681
682 PINMUX_IPSR_GPSR(IP7_31_28, AVB0_AVTP_CAPTURE),
683 PINMUX_IPSR_GPSR(IP7_31_28, FSCLKST2_N_B),
684
685 /* IPSR8 */
686 PINMUX_IPSR_MSEL(IP8_3_0, CANFD0_TX_A, SEL_CANFD0_0),
687 PINMUX_IPSR_GPSR(IP8_3_0, FXR_TXDA),
688 PINMUX_IPSR_MSEL(IP8_3_0, PWM0_B, SEL_PWM0_1),
689 PINMUX_IPSR_GPSR(IP8_3_0, DU_DISP),
690 PINMUX_IPSR_GPSR(IP8_3_0, FSCLKST2_N_C),
691
692 PINMUX_IPSR_MSEL(IP8_7_4, CANFD0_RX_A, SEL_CANFD0_0),
693 PINMUX_IPSR_GPSR(IP8_7_4, RXDA_EXTFXR),
694 PINMUX_IPSR_MSEL(IP8_7_4, PWM1_B, SEL_PWM1_1),
695 PINMUX_IPSR_GPSR(IP8_7_4, DU_CDE),
696
697 PINMUX_IPSR_GPSR(IP8_11_8, CANFD1_TX),
698 PINMUX_IPSR_GPSR(IP8_11_8, FXR_TXDB),
699 PINMUX_IPSR_MSEL(IP8_11_8, PWM2_B, SEL_PWM2_1),
700 PINMUX_IPSR_MSEL(IP8_11_8, TCLK1_B, SEL_TMU_1),
701 PINMUX_IPSR_MSEL(IP8_11_8, TX1_B, SEL_SCIF1_1),
702
703 PINMUX_IPSR_GPSR(IP8_15_12, CANFD1_RX),
704 PINMUX_IPSR_GPSR(IP8_15_12, RXDB_EXTFXR),
705 PINMUX_IPSR_MSEL(IP8_15_12, PWM3_B, SEL_PWM3_1),
706 PINMUX_IPSR_MSEL(IP8_15_12, TCLK2_B, SEL_TMU_1),
707 PINMUX_IPSR_MSEL(IP8_15_12, RX1_B, SEL_SCIF1_1),
708
709 PINMUX_IPSR_MSEL(IP8_19_16, CANFD_CLK_A, SEL_CANFD0_0),
710 PINMUX_IPSR_GPSR(IP8_19_16, CLK_EXTFXR),
711 PINMUX_IPSR_MSEL(IP8_19_16, PWM4_B, SEL_PWM4_1),
712 PINMUX_IPSR_MSEL(IP8_19_16, SPEEDIN_B, SEL_RSP_1),
713 PINMUX_IPSR_MSEL(IP8_19_16, SCIF_CLK_B, SEL_HSCIF0_1),
714
715 PINMUX_IPSR_GPSR(IP8_23_20, DIGRF_CLKIN),
716 PINMUX_IPSR_GPSR(IP8_23_20, DIGRF_CLKEN_IN),
717
718 PINMUX_IPSR_GPSR(IP8_27_24, DIGRF_CLKOUT),
719 PINMUX_IPSR_GPSR(IP8_27_24, DIGRF_CLKEN_OUT),
720 };
721
722 static const struct sh_pfc_pin pinmux_pins[] = {
723 PINMUX_GPIO_GP_ALL(),
724 };
725
726 /* - AVB0 ------------------------------------------------------------------- */
727 static const unsigned int avb0_link_pins[] = {
728 /* AVB0_LINK */
729 RCAR_GP_PIN(1, 18),
730 };
731 static const unsigned int avb0_link_mux[] = {
732 AVB0_LINK_MARK,
733 };
734 static const unsigned int avb0_magic_pins[] = {
735 /* AVB0_MAGIC */
736 RCAR_GP_PIN(1, 16),
737 };
738 static const unsigned int avb0_magic_mux[] = {
739 AVB0_MAGIC_MARK,
740 };
741 static const unsigned int avb0_phy_int_pins[] = {
742 /* AVB0_PHY_INT */
743 RCAR_GP_PIN(1, 17),
744 };
745 static const unsigned int avb0_phy_int_mux[] = {
746 AVB0_PHY_INT_MARK,
747 };
748 static const unsigned int avb0_mdio_pins[] = {
749 /* AVB0_MDC, AVB0_MDIO */
750 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
751 };
752 static const unsigned int avb0_mdio_mux[] = {
753 AVB0_MDC_MARK, AVB0_MDIO_MARK,
754 };
755 static const unsigned int avb0_rgmii_pins[] = {
756 /*
757 * AVB0_TX_CTL, AVB0_TXC, AVB0_TD0, AVB0_TD1, AVB0_TD2, AVB0_TD3,
758 * AVB0_RX_CTL, AVB0_RXC, AVB0_RD0, AVB0_RD1, AVB0_RD2, AVB0_RD3
759 */
760 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8),
761 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10),
762 RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 12),
763 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2),
764 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 4),
765 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
766 };
767 static const unsigned int avb0_rgmii_mux[] = {
768 AVB0_TX_CTL_MARK, AVB0_TXC_MARK,
769 AVB0_TD0_MARK, AVB0_TD1_MARK, AVB0_TD2_MARK, AVB0_TD3_MARK,
770 AVB0_RX_CTL_MARK, AVB0_RXC_MARK,
771 AVB0_RD0_MARK, AVB0_RD1_MARK, AVB0_RD2_MARK, AVB0_RD3_MARK,
772 };
773 static const unsigned int avb0_txcrefclk_pins[] = {
774 /* AVB0_TXCREFCLK */
775 RCAR_GP_PIN(1, 13),
776 };
777 static const unsigned int avb0_txcrefclk_mux[] = {
778 AVB0_TXCREFCLK_MARK,
779 };
780 static const unsigned int avb0_avtp_pps_pins[] = {
781 /* AVB0_AVTP_PPS */
782 RCAR_GP_PIN(2, 6),
783 };
784 static const unsigned int avb0_avtp_pps_mux[] = {
785 AVB0_AVTP_PPS_MARK,
786 };
787 static const unsigned int avb0_avtp_capture_pins[] = {
788 /* AVB0_AVTP_CAPTURE */
789 RCAR_GP_PIN(1, 20),
790 };
791 static const unsigned int avb0_avtp_capture_mux[] = {
792 AVB0_AVTP_CAPTURE_MARK,
793 };
794 static const unsigned int avb0_avtp_match_pins[] = {
795 /* AVB0_AVTP_MATCH */
796 RCAR_GP_PIN(1, 19),
797 };
798 static const unsigned int avb0_avtp_match_mux[] = {
799 AVB0_AVTP_MATCH_MARK,
800 };
801
802 /* - CANFD Clock ------------------------------------------------------------ */
803 static const unsigned int canfd_clk_a_pins[] = {
804 /* CANFD_CLK */
805 RCAR_GP_PIN(1, 25),
806 };
807 static const unsigned int canfd_clk_a_mux[] = {
808 CANFD_CLK_A_MARK,
809 };
810 static const unsigned int canfd_clk_b_pins[] = {
811 /* CANFD_CLK */
812 RCAR_GP_PIN(3, 8),
813 };
814 static const unsigned int canfd_clk_b_mux[] = {
815 CANFD_CLK_B_MARK,
816 };
817
818 /* - CANFD0 ----------------------------------------------------------------- */
819 static const unsigned int canfd0_data_a_pins[] = {
820 /* TX, RX */
821 RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
822 };
823 static const unsigned int canfd0_data_a_mux[] = {
824 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
825 };
826 static const unsigned int canfd0_data_b_pins[] = {
827 /* TX, RX */
828 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
829 };
830 static const unsigned int canfd0_data_b_mux[] = {
831 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
832 };
833
834 /* - CANFD1 ----------------------------------------------------------------- */
835 static const unsigned int canfd1_data_pins[] = {
836 /* TX, RX */
837 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
838 };
839 static const unsigned int canfd1_data_mux[] = {
840 CANFD1_TX_MARK, CANFD1_RX_MARK,
841 };
842
843 /* - DU --------------------------------------------------------------------- */
844 static const unsigned int du_rgb666_pins[] = {
845 /* R[7:2], G[7:2], B[7:2] */
846 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3),
847 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
848 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9),
849 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6),
850 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 15),
851 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12),
852 };
853 static const unsigned int du_rgb666_mux[] = {
854 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK,
855 DU_DR4_MARK, DU_DR3_MARK, DU_DR2_MARK,
856 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK,
857 DU_DG4_MARK, DU_DG3_MARK, DU_DG2_MARK,
858 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK,
859 DU_DB4_MARK, DU_DB3_MARK, DU_DB2_MARK,
860 };
861 static const unsigned int du_clk_out_pins[] = {
862 /* DOTCLKOUT */
863 RCAR_GP_PIN(0, 18),
864 };
865 static const unsigned int du_clk_out_mux[] = {
866 DU_DOTCLKOUT_MARK,
867 };
868 static const unsigned int du_sync_pins[] = {
869 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
870 RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19),
871 };
872 static const unsigned int du_sync_mux[] = {
873 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
874 };
875 static const unsigned int du_oddf_pins[] = {
876 /* EXODDF/ODDF/DISP/CDE */
877 RCAR_GP_PIN(0, 21),
878 };
879 static const unsigned int du_oddf_mux[] = {
880 DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
881 };
882 static const unsigned int du_cde_pins[] = {
883 /* CDE */
884 RCAR_GP_PIN(1, 22),
885 };
886 static const unsigned int du_cde_mux[] = {
887 DU_CDE_MARK,
888 };
889 static const unsigned int du_disp_pins[] = {
890 /* DISP */
891 RCAR_GP_PIN(1, 21),
892 };
893 static const unsigned int du_disp_mux[] = {
894 DU_DISP_MARK,
895 };
896
897 /* - HSCIF0 ----------------------------------------------------------------- */
898 static const unsigned int hscif0_data_pins[] = {
899 /* HRX, HTX */
900 RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 3),
901 };
902 static const unsigned int hscif0_data_mux[] = {
903 HRX0_MARK, HTX0_MARK,
904 };
905 static const unsigned int hscif0_clk_pins[] = {
906 /* HSCK */
907 RCAR_GP_PIN(0, 0),
908 };
909 static const unsigned int hscif0_clk_mux[] = {
910 HSCK0_MARK,
911 };
912 static const unsigned int hscif0_ctrl_pins[] = {
913 /* HRTS#, HCTS# */
914 RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
915 };
916 static const unsigned int hscif0_ctrl_mux[] = {
917 HRTS0_N_MARK, HCTS0_N_MARK,
918 };
919
920 /* - HSCIF1 ----------------------------------------------------------------- */
921 static const unsigned int hscif1_data_pins[] = {
922 /* HRX, HTX */
923 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
924 };
925 static const unsigned int hscif1_data_mux[] = {
926 HRX1_MARK, HTX1_MARK,
927 };
928 static const unsigned int hscif1_clk_pins[] = {
929 /* HSCK */
930 RCAR_GP_PIN(2, 7),
931 };
932 static const unsigned int hscif1_clk_mux[] = {
933 HSCK1_MARK,
934 };
935 static const unsigned int hscif1_ctrl_pins[] = {
936 /* HRTS#, HCTS# */
937 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
938 };
939 static const unsigned int hscif1_ctrl_mux[] = {
940 HRTS1_N_MARK, HCTS1_N_MARK,
941 };
942
943 /* - HSCIF2 ----------------------------------------------------------------- */
944 static const unsigned int hscif2_data_pins[] = {
945 /* HRX, HTX */
946 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 15),
947 };
948 static const unsigned int hscif2_data_mux[] = {
949 HRX2_MARK, HTX2_MARK,
950 };
951 static const unsigned int hscif2_clk_pins[] = {
952 /* HSCK */
953 RCAR_GP_PIN(2, 12),
954 };
955 static const unsigned int hscif2_clk_mux[] = {
956 HSCK2_MARK,
957 };
958 static const unsigned int hscif2_ctrl_pins[] = {
959 /* HRTS#, HCTS# */
960 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
961 };
962 static const unsigned int hscif2_ctrl_mux[] = {
963 HRTS2_N_MARK, HCTS2_N_MARK,
964 };
965
966 /* - HSCIF3 ----------------------------------------------------------------- */
967 static const unsigned int hscif3_data_pins[] = {
968 /* HRX, HTX */
969 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
970 };
971 static const unsigned int hscif3_data_mux[] = {
972 HRX3_MARK, HTX3_MARK,
973 };
974 static const unsigned int hscif3_clk_pins[] = {
975 /* HSCK */
976 RCAR_GP_PIN(2, 0),
977 };
978 static const unsigned int hscif3_clk_mux[] = {
979 HSCK3_MARK,
980 };
981 static const unsigned int hscif3_ctrl_pins[] = {
982 /* HRTS#, HCTS# */
983 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 1),
984 };
985 static const unsigned int hscif3_ctrl_mux[] = {
986 HRTS3_N_MARK, HCTS3_N_MARK,
987 };
988
989 /* - I2C0 ------------------------------------------------------------------- */
990 static const unsigned int i2c0_pins[] = {
991 /* SDA, SCL */
992 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0),
993 };
994 static const unsigned int i2c0_mux[] = {
995 SDA0_MARK, SCL0_MARK,
996 };
997
998 /* - I2C1 ------------------------------------------------------------------- */
999 static const unsigned int i2c1_pins[] = {
1000 /* SDA, SCL */
1001 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
1002 };
1003 static const unsigned int i2c1_mux[] = {
1004 SDA1_MARK, SCL1_MARK,
1005 };
1006
1007 /* - I2C2 ------------------------------------------------------------------- */
1008 static const unsigned int i2c2_pins[] = {
1009 /* SDA, SCL */
1010 RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 4),
1011 };
1012 static const unsigned int i2c2_mux[] = {
1013 SDA2_MARK, SCL2_MARK,
1014 };
1015
1016 /* - I2C3 ------------------------------------------------------------------- */
1017 static const unsigned int i2c3_a_pins[] = {
1018 /* SDA, SCL */
1019 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
1020 };
1021 static const unsigned int i2c3_a_mux[] = {
1022 SDA3_A_MARK, SCL3_A_MARK,
1023 };
1024 static const unsigned int i2c3_b_pins[] = {
1025 /* SDA, SCL */
1026 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
1027 };
1028 static const unsigned int i2c3_b_mux[] = {
1029 SDA3_B_MARK, SCL3_B_MARK,
1030 };
1031
1032 /* - I2C4 ------------------------------------------------------------------- */
1033 static const unsigned int i2c4_pins[] = {
1034 /* SDA, SCL */
1035 RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 15),
1036 };
1037 static const unsigned int i2c4_mux[] = {
1038 SDA4_MARK, SCL4_MARK,
1039 };
1040
1041 /* - INTC-EX ---------------------------------------------------------------- */
1042 static const unsigned int intc_ex_irq0_pins[] = {
1043 /* IRQ0 */
1044 RCAR_GP_PIN(1, 0),
1045 };
1046 static const unsigned int intc_ex_irq0_mux[] = {
1047 IRQ0_MARK,
1048 };
1049 static const unsigned int intc_ex_irq1_pins[] = {
1050 /* IRQ1 */
1051 RCAR_GP_PIN(0, 11),
1052 };
1053 static const unsigned int intc_ex_irq1_mux[] = {
1054 IRQ1_MARK,
1055 };
1056 static const unsigned int intc_ex_irq2_pins[] = {
1057 /* IRQ2 */
1058 RCAR_GP_PIN(0, 12),
1059 };
1060 static const unsigned int intc_ex_irq2_mux[] = {
1061 IRQ2_MARK,
1062 };
1063 static const unsigned int intc_ex_irq3_pins[] = {
1064 /* IRQ3 */
1065 RCAR_GP_PIN(0, 19),
1066 };
1067 static const unsigned int intc_ex_irq3_mux[] = {
1068 IRQ3_MARK,
1069 };
1070 static const unsigned int intc_ex_irq4_pins[] = {
1071 /* IRQ4 */
1072 RCAR_GP_PIN(3, 15),
1073 };
1074 static const unsigned int intc_ex_irq4_mux[] = {
1075 IRQ4_MARK,
1076 };
1077 static const unsigned int intc_ex_irq5_pins[] = {
1078 /* IRQ5 */
1079 RCAR_GP_PIN(3, 16),
1080 };
1081 static const unsigned int intc_ex_irq5_mux[] = {
1082 IRQ5_MARK,
1083 };
1084
1085 /* - MMC -------------------------------------------------------------------- */
1086 static const unsigned int mmc_data1_pins[] = {
1087 /* D0 */
1088 RCAR_GP_PIN(3, 6),
1089 };
1090 static const unsigned int mmc_data1_mux[] = {
1091 MMC_D0_MARK,
1092 };
1093 static const unsigned int mmc_data4_pins[] = {
1094 /* D[0:3] */
1095 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1096 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1097 };
1098 static const unsigned int mmc_data4_mux[] = {
1099 MMC_D0_MARK, MMC_D1_MARK,
1100 MMC_D2_MARK, MMC_D3_MARK,
1101 };
1102 static const unsigned int mmc_data8_pins[] = {
1103 /* D[0:7] */
1104 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1105 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1106 RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
1107 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
1108 };
1109 static const unsigned int mmc_data8_mux[] = {
1110 MMC_D0_MARK, MMC_D1_MARK,
1111 MMC_D2_MARK, MMC_D3_MARK,
1112 MMC_D4_MARK, MMC_D5_MARK,
1113 MMC_D6_MARK, MMC_D7_MARK,
1114 };
1115 static const unsigned int mmc_ctrl_pins[] = {
1116 /* CLK, CMD */
1117 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 5),
1118 };
1119 static const unsigned int mmc_ctrl_mux[] = {
1120 MMC_CLK_MARK, MMC_CMD_MARK,
1121 };
1122
1123 /* - MSIOF0 ----------------------------------------------------------------- */
1124 static const unsigned int msiof0_clk_pins[] = {
1125 /* SCK */
1126 RCAR_GP_PIN(4, 2),
1127 };
1128 static const unsigned int msiof0_clk_mux[] = {
1129 MSIOF0_SCK_MARK,
1130 };
1131 static const unsigned int msiof0_sync_pins[] = {
1132 /* SYNC */
1133 RCAR_GP_PIN(4, 3),
1134 };
1135 static const unsigned int msiof0_sync_mux[] = {
1136 MSIOF0_SYNC_MARK,
1137 };
1138 static const unsigned int msiof0_ss1_pins[] = {
1139 /* SS1 */
1140 RCAR_GP_PIN(4, 4),
1141 };
1142 static const unsigned int msiof0_ss1_mux[] = {
1143 MSIOF0_SS1_MARK,
1144 };
1145 static const unsigned int msiof0_ss2_pins[] = {
1146 /* SS2 */
1147 RCAR_GP_PIN(4, 5),
1148 };
1149 static const unsigned int msiof0_ss2_mux[] = {
1150 MSIOF0_SS2_MARK,
1151 };
1152 static const unsigned int msiof0_txd_pins[] = {
1153 /* TXD */
1154 RCAR_GP_PIN(4, 1),
1155 };
1156 static const unsigned int msiof0_txd_mux[] = {
1157 MSIOF0_TXD_MARK,
1158 };
1159 static const unsigned int msiof0_rxd_pins[] = {
1160 /* RXD */
1161 RCAR_GP_PIN(4, 0),
1162 };
1163 static const unsigned int msiof0_rxd_mux[] = {
1164 MSIOF0_RXD_MARK,
1165 };
1166
1167 /* - MSIOF1 ----------------------------------------------------------------- */
1168 static const unsigned int msiof1_clk_pins[] = {
1169 /* SCK */
1170 RCAR_GP_PIN(3, 2),
1171 };
1172 static const unsigned int msiof1_clk_mux[] = {
1173 MSIOF1_SCK_MARK,
1174 };
1175 static const unsigned int msiof1_sync_pins[] = {
1176 /* SYNC */
1177 RCAR_GP_PIN(3, 3),
1178 };
1179 static const unsigned int msiof1_sync_mux[] = {
1180 MSIOF1_SYNC_MARK,
1181 };
1182 static const unsigned int msiof1_ss1_pins[] = {
1183 /* SS1 */
1184 RCAR_GP_PIN(3, 4),
1185 };
1186 static const unsigned int msiof1_ss1_mux[] = {
1187 MSIOF1_SS1_MARK,
1188 };
1189 static const unsigned int msiof1_ss2_pins[] = {
1190 /* SS2 */
1191 RCAR_GP_PIN(3, 5),
1192 };
1193 static const unsigned int msiof1_ss2_mux[] = {
1194 MSIOF1_SS2_MARK,
1195 };
1196 static const unsigned int msiof1_txd_pins[] = {
1197 /* TXD */
1198 RCAR_GP_PIN(3, 1),
1199 };
1200 static const unsigned int msiof1_txd_mux[] = {
1201 MSIOF1_TXD_MARK,
1202 };
1203 static const unsigned int msiof1_rxd_pins[] = {
1204 /* RXD */
1205 RCAR_GP_PIN(3, 0),
1206 };
1207 static const unsigned int msiof1_rxd_mux[] = {
1208 MSIOF1_RXD_MARK,
1209 };
1210
1211 /* - MSIOF2 ----------------------------------------------------------------- */
1212 static const unsigned int msiof2_clk_pins[] = {
1213 /* SCK */
1214 RCAR_GP_PIN(2, 0),
1215 };
1216 static const unsigned int msiof2_clk_mux[] = {
1217 MSIOF2_SCK_MARK,
1218 };
1219 static const unsigned int msiof2_sync_pins[] = {
1220 /* SYNC */
1221 RCAR_GP_PIN(2, 3),
1222 };
1223 static const unsigned int msiof2_sync_mux[] = {
1224 MSIOF2_SYNC_MARK,
1225 };
1226 static const unsigned int msiof2_ss1_pins[] = {
1227 /* SS1 */
1228 RCAR_GP_PIN(2, 4),
1229 };
1230 static const unsigned int msiof2_ss1_mux[] = {
1231 MSIOF2_SS1_MARK,
1232 };
1233 static const unsigned int msiof2_ss2_pins[] = {
1234 /* SS2 */
1235 RCAR_GP_PIN(2, 5),
1236 };
1237 static const unsigned int msiof2_ss2_mux[] = {
1238 MSIOF2_SS2_MARK,
1239 };
1240 static const unsigned int msiof2_txd_pins[] = {
1241 /* TXD */
1242 RCAR_GP_PIN(2, 2),
1243 };
1244 static const unsigned int msiof2_txd_mux[] = {
1245 MSIOF2_TXD_MARK,
1246 };
1247 static const unsigned int msiof2_rxd_pins[] = {
1248 /* RXD */
1249 RCAR_GP_PIN(2, 1),
1250 };
1251 static const unsigned int msiof2_rxd_mux[] = {
1252 MSIOF2_RXD_MARK,
1253 };
1254
1255 /* - MSIOF3 ----------------------------------------------------------------- */
1256 static const unsigned int msiof3_clk_pins[] = {
1257 /* SCK */
1258 RCAR_GP_PIN(0, 20),
1259 };
1260 static const unsigned int msiof3_clk_mux[] = {
1261 MSIOF3_SCK_MARK,
1262 };
1263 static const unsigned int msiof3_sync_pins[] = {
1264 /* SYNC */
1265 RCAR_GP_PIN(0, 21),
1266 };
1267 static const unsigned int msiof3_sync_mux[] = {
1268 MSIOF3_SYNC_MARK,
1269 };
1270 static const unsigned int msiof3_ss1_pins[] = {
1271 /* SS1 */
1272 RCAR_GP_PIN(0, 6),
1273 };
1274 static const unsigned int msiof3_ss1_mux[] = {
1275 MSIOF3_SS1_MARK,
1276 };
1277 static const unsigned int msiof3_ss2_pins[] = {
1278 /* SS2 */
1279 RCAR_GP_PIN(0, 7),
1280 };
1281 static const unsigned int msiof3_ss2_mux[] = {
1282 MSIOF3_SS2_MARK,
1283 };
1284 static const unsigned int msiof3_txd_pins[] = {
1285 /* TXD */
1286 RCAR_GP_PIN(0, 5),
1287 };
1288 static const unsigned int msiof3_txd_mux[] = {
1289 MSIOF3_TXD_MARK,
1290 };
1291 static const unsigned int msiof3_rxd_pins[] = {
1292 /* RXD */
1293 RCAR_GP_PIN(0, 4),
1294 };
1295 static const unsigned int msiof3_rxd_mux[] = {
1296 MSIOF3_RXD_MARK,
1297 };
1298
1299 /* - PWM0 ------------------------------------------------------------------- */
1300 static const unsigned int pwm0_a_pins[] = {
1301 RCAR_GP_PIN(2, 12),
1302 };
1303 static const unsigned int pwm0_a_mux[] = {
1304 PWM0_A_MARK,
1305 };
1306 static const unsigned int pwm0_b_pins[] = {
1307 RCAR_GP_PIN(1, 21),
1308 };
1309 static const unsigned int pwm0_b_mux[] = {
1310 PWM0_B_MARK,
1311 };
1312
1313 /* - PWM1 ------------------------------------------------------------------- */
1314 static const unsigned int pwm1_a_pins[] = {
1315 RCAR_GP_PIN(2, 13),
1316 };
1317 static const unsigned int pwm1_a_mux[] = {
1318 PWM1_A_MARK,
1319 };
1320 static const unsigned int pwm1_b_pins[] = {
1321 RCAR_GP_PIN(1, 22),
1322 };
1323 static const unsigned int pwm1_b_mux[] = {
1324 PWM1_B_MARK,
1325 };
1326
1327 /* - PWM2 ------------------------------------------------------------------- */
1328 static const unsigned int pwm2_a_pins[] = {
1329 RCAR_GP_PIN(2, 14),
1330 };
1331 static const unsigned int pwm2_a_mux[] = {
1332 PWM2_A_MARK,
1333 };
1334 static const unsigned int pwm2_b_pins[] = {
1335 RCAR_GP_PIN(1, 23),
1336 };
1337 static const unsigned int pwm2_b_mux[] = {
1338 PWM2_B_MARK,
1339 };
1340
1341 /* - PWM3 ------------------------------------------------------------------- */
1342 static const unsigned int pwm3_a_pins[] = {
1343 RCAR_GP_PIN(2, 15),
1344 };
1345 static const unsigned int pwm3_a_mux[] = {
1346 PWM3_A_MARK,
1347 };
1348 static const unsigned int pwm3_b_pins[] = {
1349 RCAR_GP_PIN(1, 24),
1350 };
1351 static const unsigned int pwm3_b_mux[] = {
1352 PWM3_B_MARK,
1353 };
1354
1355 /* - PWM4 ------------------------------------------------------------------- */
1356 static const unsigned int pwm4_a_pins[] = {
1357 RCAR_GP_PIN(2, 16),
1358 };
1359 static const unsigned int pwm4_a_mux[] = {
1360 PWM4_A_MARK,
1361 };
1362 static const unsigned int pwm4_b_pins[] = {
1363 RCAR_GP_PIN(1, 25),
1364 };
1365 static const unsigned int pwm4_b_mux[] = {
1366 PWM4_B_MARK,
1367 };
1368
1369 /* - QSPI0 ------------------------------------------------------------------ */
1370 static const unsigned int qspi0_ctrl_pins[] = {
1371 /* SPCLK, SSL */
1372 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 5),
1373 };
1374 static const unsigned int qspi0_ctrl_mux[] = {
1375 QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
1376 };
1377 static const unsigned int qspi0_data2_pins[] = {
1378 /* MOSI_IO0, MISO_IO1 */
1379 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1380 };
1381 static const unsigned int qspi0_data2_mux[] = {
1382 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
1383 };
1384 static const unsigned int qspi0_data4_pins[] = {
1385 /* MOSI_IO0, MISO_IO1, IO2, IO3 */
1386 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1387 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4),
1388 };
1389 static const unsigned int qspi0_data4_mux[] = {
1390 QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
1391 QSPI0_IO2_MARK, QSPI0_IO3_MARK
1392 };
1393
1394 /* - QSPI1 ------------------------------------------------------------------ */
1395 static const unsigned int qspi1_ctrl_pins[] = {
1396 /* SPCLK, SSL */
1397 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 11),
1398 };
1399 static const unsigned int qspi1_ctrl_mux[] = {
1400 QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
1401 };
1402 static const unsigned int qspi1_data2_pins[] = {
1403 /* MOSI_IO0, MISO_IO1 */
1404 RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
1405 };
1406 static const unsigned int qspi1_data2_mux[] = {
1407 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
1408 };
1409 static const unsigned int qspi1_data4_pins[] = {
1410 /* MOSI_IO0, MISO_IO1, IO2, IO3 */
1411 RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
1412 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
1413 };
1414 static const unsigned int qspi1_data4_mux[] = {
1415 QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
1416 QSPI1_IO2_MARK, QSPI1_IO3_MARK
1417 };
1418
1419 /* - SCIF Clock ------------------------------------------------------------- */
1420 static const unsigned int scif_clk_a_pins[] = {
1421 /* SCIF_CLK */
1422 RCAR_GP_PIN(0, 18),
1423 };
1424 static const unsigned int scif_clk_a_mux[] = {
1425 SCIF_CLK_A_MARK,
1426 };
1427 static const unsigned int scif_clk_b_pins[] = {
1428 /* SCIF_CLK */
1429 RCAR_GP_PIN(1, 25),
1430 };
1431 static const unsigned int scif_clk_b_mux[] = {
1432 SCIF_CLK_B_MARK,
1433 };
1434
1435 /* - SCIF0 ------------------------------------------------------------------ */
1436 static const unsigned int scif0_data_pins[] = {
1437 /* RX, TX */
1438 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
1439 };
1440 static const unsigned int scif0_data_mux[] = {
1441 RX0_MARK, TX0_MARK,
1442 };
1443 static const unsigned int scif0_clk_pins[] = {
1444 /* SCK */
1445 RCAR_GP_PIN(4, 1),
1446 };
1447 static const unsigned int scif0_clk_mux[] = {
1448 SCK0_MARK,
1449 };
1450 static const unsigned int scif0_ctrl_pins[] = {
1451 /* RTS#, CTS# */
1452 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
1453 };
1454 static const unsigned int scif0_ctrl_mux[] = {
1455 RTS0_N_MARK, CTS0_N_MARK,
1456 };
1457
1458 /* - SCIF1 ------------------------------------------------------------------ */
1459 static const unsigned int scif1_data_a_pins[] = {
1460 /* RX, TX */
1461 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1462 };
1463 static const unsigned int scif1_data_a_mux[] = {
1464 RX1_A_MARK, TX1_A_MARK,
1465 };
1466 static const unsigned int scif1_clk_pins[] = {
1467 /* SCK */
1468 RCAR_GP_PIN(2, 5),
1469 };
1470 static const unsigned int scif1_clk_mux[] = {
1471 SCK1_MARK,
1472 };
1473 static const unsigned int scif1_ctrl_pins[] = {
1474 /* RTS#, CTS# */
1475 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
1476 };
1477 static const unsigned int scif1_ctrl_mux[] = {
1478 RTS1_N_MARK, CTS1_N_MARK,
1479 };
1480 static const unsigned int scif1_data_b_pins[] = {
1481 /* RX, TX */
1482 RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 23),
1483 };
1484 static const unsigned int scif1_data_b_mux[] = {
1485 RX1_B_MARK, TX1_B_MARK,
1486 };
1487
1488 /* - SCIF3 ------------------------------------------------------------------ */
1489 static const unsigned int scif3_data_pins[] = {
1490 /* RX, TX */
1491 RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
1492 };
1493 static const unsigned int scif3_data_mux[] = {
1494 RX3_MARK, TX3_MARK,
1495 };
1496 static const unsigned int scif3_clk_pins[] = {
1497 /* SCK */
1498 RCAR_GP_PIN(2, 0),
1499 };
1500 static const unsigned int scif3_clk_mux[] = {
1501 SCK3_MARK,
1502 };
1503 static const unsigned int scif3_ctrl_pins[] = {
1504 /* RTS#, CTS# */
1505 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
1506 };
1507 static const unsigned int scif3_ctrl_mux[] = {
1508 RTS3_N_MARK, CTS3_N_MARK,
1509 };
1510
1511 /* - SCIF4 ------------------------------------------------------------------ */
1512 static const unsigned int scif4_data_pins[] = {
1513 /* RX, TX */
1514 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
1515 };
1516 static const unsigned int scif4_data_mux[] = {
1517 RX4_MARK, TX4_MARK,
1518 };
1519 static const unsigned int scif4_clk_pins[] = {
1520 /* SCK */
1521 RCAR_GP_PIN(3, 9),
1522 };
1523 static const unsigned int scif4_clk_mux[] = {
1524 SCK4_MARK,
1525 };
1526 static const unsigned int scif4_ctrl_pins[] = {
1527 /* RTS#, CTS# */
1528 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
1529 };
1530 static const unsigned int scif4_ctrl_mux[] = {
1531 RTS4_N_MARK, CTS4_N_MARK,
1532 };
1533
1534 /* - TMU -------------------------------------------------------------------- */
1535 static const unsigned int tmu_tclk1_a_pins[] = {
1536 /* TCLK1 */
1537 RCAR_GP_PIN(4, 4),
1538 };
1539 static const unsigned int tmu_tclk1_a_mux[] = {
1540 TCLK1_A_MARK,
1541 };
1542 static const unsigned int tmu_tclk1_b_pins[] = {
1543 /* TCLK1 */
1544 RCAR_GP_PIN(1, 23),
1545 };
1546 static const unsigned int tmu_tclk1_b_mux[] = {
1547 TCLK1_B_MARK,
1548 };
1549 static const unsigned int tmu_tclk2_a_pins[] = {
1550 /* TCLK2 */
1551 RCAR_GP_PIN(4, 5),
1552 };
1553 static const unsigned int tmu_tclk2_a_mux[] = {
1554 TCLK2_A_MARK,
1555 };
1556 static const unsigned int tmu_tclk2_b_pins[] = {
1557 /* TCLK2 */
1558 RCAR_GP_PIN(1, 24),
1559 };
1560 static const unsigned int tmu_tclk2_b_mux[] = {
1561 TCLK2_B_MARK,
1562 };
1563
1564 /* - VIN0 ------------------------------------------------------------------- */
1565 static const union vin_data12 vin0_data_pins = {
1566 .data12 = {
1567 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
1568 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
1569 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1570 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
1571 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
1572 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
1573 },
1574 };
1575 static const union vin_data12 vin0_data_mux = {
1576 .data12 = {
1577 VI0_DATA0_MARK, VI0_DATA1_MARK,
1578 VI0_DATA2_MARK, VI0_DATA3_MARK,
1579 VI0_DATA4_MARK, VI0_DATA5_MARK,
1580 VI0_DATA6_MARK, VI0_DATA7_MARK,
1581 VI0_DATA8_MARK, VI0_DATA9_MARK,
1582 VI0_DATA10_MARK, VI0_DATA11_MARK,
1583 },
1584 };
1585 static const unsigned int vin0_sync_pins[] = {
1586 /* HSYNC#, VSYNC# */
1587 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
1588 };
1589 static const unsigned int vin0_sync_mux[] = {
1590 VI0_HSYNC_N_MARK, VI0_VSYNC_N_MARK,
1591 };
1592 static const unsigned int vin0_field_pins[] = {
1593 /* FIELD */
1594 RCAR_GP_PIN(2, 16),
1595 };
1596 static const unsigned int vin0_field_mux[] = {
1597 VI0_FIELD_MARK,
1598 };
1599 static const unsigned int vin0_clkenb_pins[] = {
1600 /* CLKENB */
1601 RCAR_GP_PIN(2, 1),
1602 };
1603 static const unsigned int vin0_clkenb_mux[] = {
1604 VI0_CLKENB_MARK,
1605 };
1606 static const unsigned int vin0_clk_pins[] = {
1607 /* CLK */
1608 RCAR_GP_PIN(2, 0),
1609 };
1610 static const unsigned int vin0_clk_mux[] = {
1611 VI0_CLK_MARK,
1612 };
1613
1614 /* - VIN1 ------------------------------------------------------------------- */
1615 static const union vin_data12 vin1_data_pins = {
1616 .data12 = {
1617 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
1618 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1619 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1620 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
1621 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
1622 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
1623 },
1624 };
1625 static const union vin_data12 vin1_data_mux = {
1626 .data12 = {
1627 VI1_DATA0_MARK, VI1_DATA1_MARK,
1628 VI1_DATA2_MARK, VI1_DATA3_MARK,
1629 VI1_DATA4_MARK, VI1_DATA5_MARK,
1630 VI1_DATA6_MARK, VI1_DATA7_MARK,
1631 VI1_DATA8_MARK, VI1_DATA9_MARK,
1632 VI1_DATA10_MARK, VI1_DATA11_MARK,
1633 },
1634 };
1635 static const unsigned int vin1_sync_pins[] = {
1636 /* HSYNC#, VSYNC# */
1637 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
1638 };
1639 static const unsigned int vin1_sync_mux[] = {
1640 VI1_HSYNC_N_MARK, VI1_VSYNC_N_MARK,
1641 };
1642 static const unsigned int vin1_field_pins[] = {
1643 RCAR_GP_PIN(3, 16),
1644 };
1645 static const unsigned int vin1_field_mux[] = {
1646 /* FIELD */
1647 VI1_FIELD_MARK,
1648 };
1649 static const unsigned int vin1_clkenb_pins[] = {
1650 RCAR_GP_PIN(3, 1),
1651 };
1652 static const unsigned int vin1_clkenb_mux[] = {
1653 /* CLKENB */
1654 VI1_CLKENB_MARK,
1655 };
1656 static const unsigned int vin1_clk_pins[] = {
1657 RCAR_GP_PIN(3, 0),
1658 };
1659 static const unsigned int vin1_clk_mux[] = {
1660 /* CLK */
1661 VI1_CLK_MARK,
1662 };
1663
1664 static const struct sh_pfc_pin_group pinmux_groups[] = {
1665 SH_PFC_PIN_GROUP(avb0_link),
1666 SH_PFC_PIN_GROUP(avb0_magic),
1667 SH_PFC_PIN_GROUP(avb0_phy_int),
1668 SH_PFC_PIN_GROUP(avb0_mdio),
1669 SH_PFC_PIN_GROUP(avb0_rgmii),
1670 SH_PFC_PIN_GROUP(avb0_txcrefclk),
1671 SH_PFC_PIN_GROUP(avb0_avtp_pps),
1672 SH_PFC_PIN_GROUP(avb0_avtp_capture),
1673 SH_PFC_PIN_GROUP(avb0_avtp_match),
1674 SH_PFC_PIN_GROUP(canfd_clk_a),
1675 SH_PFC_PIN_GROUP(canfd_clk_b),
1676 SH_PFC_PIN_GROUP(canfd0_data_a),
1677 SH_PFC_PIN_GROUP(canfd0_data_b),
1678 SH_PFC_PIN_GROUP(canfd1_data),
1679 SH_PFC_PIN_GROUP(du_rgb666),
1680 SH_PFC_PIN_GROUP(du_clk_out),
1681 SH_PFC_PIN_GROUP(du_sync),
1682 SH_PFC_PIN_GROUP(du_oddf),
1683 SH_PFC_PIN_GROUP(du_cde),
1684 SH_PFC_PIN_GROUP(du_disp),
1685 SH_PFC_PIN_GROUP(hscif0_data),
1686 SH_PFC_PIN_GROUP(hscif0_clk),
1687 SH_PFC_PIN_GROUP(hscif0_ctrl),
1688 SH_PFC_PIN_GROUP(hscif1_data),
1689 SH_PFC_PIN_GROUP(hscif1_clk),
1690 SH_PFC_PIN_GROUP(hscif1_ctrl),
1691 SH_PFC_PIN_GROUP(hscif2_data),
1692 SH_PFC_PIN_GROUP(hscif2_clk),
1693 SH_PFC_PIN_GROUP(hscif2_ctrl),
1694 SH_PFC_PIN_GROUP(hscif3_data),
1695 SH_PFC_PIN_GROUP(hscif3_clk),
1696 SH_PFC_PIN_GROUP(hscif3_ctrl),
1697 SH_PFC_PIN_GROUP(i2c0),
1698 SH_PFC_PIN_GROUP(i2c1),
1699 SH_PFC_PIN_GROUP(i2c2),
1700 SH_PFC_PIN_GROUP(i2c3_a),
1701 SH_PFC_PIN_GROUP(i2c3_b),
1702 SH_PFC_PIN_GROUP(i2c4),
1703 SH_PFC_PIN_GROUP(intc_ex_irq0),
1704 SH_PFC_PIN_GROUP(intc_ex_irq1),
1705 SH_PFC_PIN_GROUP(intc_ex_irq2),
1706 SH_PFC_PIN_GROUP(intc_ex_irq3),
1707 SH_PFC_PIN_GROUP(intc_ex_irq4),
1708 SH_PFC_PIN_GROUP(intc_ex_irq5),
1709 SH_PFC_PIN_GROUP(mmc_data1),
1710 SH_PFC_PIN_GROUP(mmc_data4),
1711 SH_PFC_PIN_GROUP(mmc_data8),
1712 SH_PFC_PIN_GROUP(mmc_ctrl),
1713 SH_PFC_PIN_GROUP(msiof0_clk),
1714 SH_PFC_PIN_GROUP(msiof0_sync),
1715 SH_PFC_PIN_GROUP(msiof0_ss1),
1716 SH_PFC_PIN_GROUP(msiof0_ss2),
1717 SH_PFC_PIN_GROUP(msiof0_txd),
1718 SH_PFC_PIN_GROUP(msiof0_rxd),
1719 SH_PFC_PIN_GROUP(msiof1_clk),
1720 SH_PFC_PIN_GROUP(msiof1_sync),
1721 SH_PFC_PIN_GROUP(msiof1_ss1),
1722 SH_PFC_PIN_GROUP(msiof1_ss2),
1723 SH_PFC_PIN_GROUP(msiof1_txd),
1724 SH_PFC_PIN_GROUP(msiof1_rxd),
1725 SH_PFC_PIN_GROUP(msiof2_clk),
1726 SH_PFC_PIN_GROUP(msiof2_sync),
1727 SH_PFC_PIN_GROUP(msiof2_ss1),
1728 SH_PFC_PIN_GROUP(msiof2_ss2),
1729 SH_PFC_PIN_GROUP(msiof2_txd),
1730 SH_PFC_PIN_GROUP(msiof2_rxd),
1731 SH_PFC_PIN_GROUP(msiof3_clk),
1732 SH_PFC_PIN_GROUP(msiof3_sync),
1733 SH_PFC_PIN_GROUP(msiof3_ss1),
1734 SH_PFC_PIN_GROUP(msiof3_ss2),
1735 SH_PFC_PIN_GROUP(msiof3_txd),
1736 SH_PFC_PIN_GROUP(msiof3_rxd),
1737 SH_PFC_PIN_GROUP(pwm0_a),
1738 SH_PFC_PIN_GROUP(pwm0_b),
1739 SH_PFC_PIN_GROUP(pwm1_a),
1740 SH_PFC_PIN_GROUP(pwm1_b),
1741 SH_PFC_PIN_GROUP(pwm2_a),
1742 SH_PFC_PIN_GROUP(pwm2_b),
1743 SH_PFC_PIN_GROUP(pwm3_a),
1744 SH_PFC_PIN_GROUP(pwm3_b),
1745 SH_PFC_PIN_GROUP(pwm4_a),
1746 SH_PFC_PIN_GROUP(pwm4_b),
1747 SH_PFC_PIN_GROUP(qspi0_ctrl),
1748 SH_PFC_PIN_GROUP(qspi0_data2),
1749 SH_PFC_PIN_GROUP(qspi0_data4),
1750 SH_PFC_PIN_GROUP(qspi1_ctrl),
1751 SH_PFC_PIN_GROUP(qspi1_data2),
1752 SH_PFC_PIN_GROUP(qspi1_data4),
1753 SH_PFC_PIN_GROUP(scif_clk_a),
1754 SH_PFC_PIN_GROUP(scif_clk_b),
1755 SH_PFC_PIN_GROUP(scif0_data),
1756 SH_PFC_PIN_GROUP(scif0_clk),
1757 SH_PFC_PIN_GROUP(scif0_ctrl),
1758 SH_PFC_PIN_GROUP(scif1_data_a),
1759 SH_PFC_PIN_GROUP(scif1_clk),
1760 SH_PFC_PIN_GROUP(scif1_ctrl),
1761 SH_PFC_PIN_GROUP(scif1_data_b),
1762 SH_PFC_PIN_GROUP(scif3_data),
1763 SH_PFC_PIN_GROUP(scif3_clk),
1764 SH_PFC_PIN_GROUP(scif3_ctrl),
1765 SH_PFC_PIN_GROUP(scif4_data),
1766 SH_PFC_PIN_GROUP(scif4_clk),
1767 SH_PFC_PIN_GROUP(scif4_ctrl),
1768 SH_PFC_PIN_GROUP(tmu_tclk1_a),
1769 SH_PFC_PIN_GROUP(tmu_tclk1_b),
1770 SH_PFC_PIN_GROUP(tmu_tclk2_a),
1771 SH_PFC_PIN_GROUP(tmu_tclk2_b),
1772 VIN_DATA_PIN_GROUP(vin0_data, 8),
1773 VIN_DATA_PIN_GROUP(vin0_data, 10),
1774 VIN_DATA_PIN_GROUP(vin0_data, 12),
1775 SH_PFC_PIN_GROUP(vin0_sync),
1776 SH_PFC_PIN_GROUP(vin0_field),
1777 SH_PFC_PIN_GROUP(vin0_clkenb),
1778 SH_PFC_PIN_GROUP(vin0_clk),
1779 VIN_DATA_PIN_GROUP(vin1_data, 8),
1780 VIN_DATA_PIN_GROUP(vin1_data, 10),
1781 VIN_DATA_PIN_GROUP(vin1_data, 12),
1782 SH_PFC_PIN_GROUP(vin1_sync),
1783 SH_PFC_PIN_GROUP(vin1_field),
1784 SH_PFC_PIN_GROUP(vin1_clkenb),
1785 SH_PFC_PIN_GROUP(vin1_clk),
1786 };
1787
1788 static const char * const avb0_groups[] = {
1789 "avb0_link",
1790 "avb0_magic",
1791 "avb0_phy_int",
1792 "avb0_mdio",
1793 "avb0_rgmii",
1794 "avb0_txcrefclk",
1795 "avb0_avtp_pps",
1796 "avb0_avtp_capture",
1797 "avb0_avtp_match",
1798 };
1799
1800 static const char * const canfd_clk_groups[] = {
1801 "canfd_clk_a",
1802 "canfd_clk_b",
1803 };
1804
1805 static const char * const canfd0_groups[] = {
1806 "canfd0_data_a",
1807 "canfd0_data_b",
1808 };
1809
1810 static const char * const canfd1_groups[] = {
1811 "canfd1_data",
1812 };
1813
1814 static const char * const du_groups[] = {
1815 "du_rgb666",
1816 "du_clk_out",
1817 "du_sync",
1818 "du_oddf",
1819 "du_cde",
1820 "du_disp",
1821 };
1822
1823 static const char * const hscif0_groups[] = {
1824 "hscif0_data",
1825 "hscif0_clk",
1826 "hscif0_ctrl",
1827 };
1828
1829 static const char * const hscif1_groups[] = {
1830 "hscif1_data",
1831 "hscif1_clk",
1832 "hscif1_ctrl",
1833 };
1834
1835 static const char * const hscif2_groups[] = {
1836 "hscif2_data",
1837 "hscif2_clk",
1838 "hscif2_ctrl",
1839 };
1840
1841 static const char * const hscif3_groups[] = {
1842 "hscif3_data",
1843 "hscif3_clk",
1844 "hscif3_ctrl",
1845 };
1846
1847 static const char * const i2c0_groups[] = {
1848 "i2c0",
1849 };
1850
1851 static const char * const i2c1_groups[] = {
1852 "i2c1",
1853 };
1854
1855 static const char * const i2c2_groups[] = {
1856 "i2c2",
1857 };
1858
1859 static const char * const i2c3_groups[] = {
1860 "i2c3_a",
1861 "i2c3_b",
1862 };
1863
1864 static const char * const i2c4_groups[] = {
1865 "i2c4",
1866 };
1867
1868 static const char * const intc_ex_groups[] = {
1869 "intc_ex_irq0",
1870 "intc_ex_irq1",
1871 "intc_ex_irq2",
1872 "intc_ex_irq3",
1873 "intc_ex_irq4",
1874 "intc_ex_irq5",
1875 };
1876
1877 static const char * const mmc_groups[] = {
1878 "mmc_data1",
1879 "mmc_data4",
1880 "mmc_data8",
1881 "mmc_ctrl",
1882 };
1883
1884 static const char * const msiof0_groups[] = {
1885 "msiof0_clk",
1886 "msiof0_sync",
1887 "msiof0_ss1",
1888 "msiof0_ss2",
1889 "msiof0_txd",
1890 "msiof0_rxd",
1891 };
1892
1893 static const char * const msiof1_groups[] = {
1894 "msiof1_clk",
1895 "msiof1_sync",
1896 "msiof1_ss1",
1897 "msiof1_ss2",
1898 "msiof1_txd",
1899 "msiof1_rxd",
1900 };
1901
1902 static const char * const msiof2_groups[] = {
1903 "msiof2_clk",
1904 "msiof2_sync",
1905 "msiof2_ss1",
1906 "msiof2_ss2",
1907 "msiof2_txd",
1908 "msiof2_rxd",
1909 };
1910
1911 static const char * const msiof3_groups[] = {
1912 "msiof3_clk",
1913 "msiof3_sync",
1914 "msiof3_ss1",
1915 "msiof3_ss2",
1916 "msiof3_txd",
1917 "msiof3_rxd",
1918 };
1919
1920 static const char * const pwm0_groups[] = {
1921 "pwm0_a",
1922 "pwm0_b",
1923 };
1924
1925 static const char * const pwm1_groups[] = {
1926 "pwm1_a",
1927 "pwm1_b",
1928 };
1929
1930 static const char * const pwm2_groups[] = {
1931 "pwm2_a",
1932 "pwm2_b",
1933 };
1934
1935 static const char * const pwm3_groups[] = {
1936 "pwm3_a",
1937 "pwm3_b",
1938 };
1939
1940 static const char * const pwm4_groups[] = {
1941 "pwm4_a",
1942 "pwm4_b",
1943 };
1944
1945 static const char * const qspi0_groups[] = {
1946 "qspi0_ctrl",
1947 "qspi0_data2",
1948 "qspi0_data4",
1949 };
1950
1951 static const char * const qspi1_groups[] = {
1952 "qspi1_ctrl",
1953 "qspi1_data2",
1954 "qspi1_data4",
1955 };
1956
1957 static const char * const scif_clk_groups[] = {
1958 "scif_clk_a",
1959 "scif_clk_b",
1960 };
1961
1962 static const char * const scif0_groups[] = {
1963 "scif0_data",
1964 "scif0_clk",
1965 "scif0_ctrl",
1966 };
1967
1968 static const char * const scif1_groups[] = {
1969 "scif1_data_a",
1970 "scif1_clk",
1971 "scif1_ctrl",
1972 "scif1_data_b",
1973 };
1974
1975 static const char * const scif3_groups[] = {
1976 "scif3_data",
1977 "scif3_clk",
1978 "scif3_ctrl",
1979 };
1980
1981 static const char * const scif4_groups[] = {
1982 "scif4_data",
1983 "scif4_clk",
1984 "scif4_ctrl",
1985 };
1986
1987 static const char * const tmu_groups[] = {
1988 "tmu_tclk1_a",
1989 "tmu_tclk1_b",
1990 "tmu_tclk2_a",
1991 "tmu_tclk2_b",
1992 };
1993
1994 static const char * const vin0_groups[] = {
1995 "vin0_data8",
1996 "vin0_data10",
1997 "vin0_data12",
1998 "vin0_sync",
1999 "vin0_field",
2000 "vin0_clkenb",
2001 "vin0_clk",
2002 };
2003
2004 static const char * const vin1_groups[] = {
2005 "vin1_data8",
2006 "vin1_data10",
2007 "vin1_data12",
2008 "vin1_sync",
2009 "vin1_field",
2010 "vin1_clkenb",
2011 "vin1_clk",
2012 };
2013
2014 static const struct sh_pfc_function pinmux_functions[] = {
2015 SH_PFC_FUNCTION(avb0),
2016 SH_PFC_FUNCTION(canfd_clk),
2017 SH_PFC_FUNCTION(canfd0),
2018 SH_PFC_FUNCTION(canfd1),
2019 SH_PFC_FUNCTION(du),
2020 SH_PFC_FUNCTION(hscif0),
2021 SH_PFC_FUNCTION(hscif1),
2022 SH_PFC_FUNCTION(hscif2),
2023 SH_PFC_FUNCTION(hscif3),
2024 SH_PFC_FUNCTION(i2c0),
2025 SH_PFC_FUNCTION(i2c1),
2026 SH_PFC_FUNCTION(i2c2),
2027 SH_PFC_FUNCTION(i2c3),
2028 SH_PFC_FUNCTION(i2c4),
2029 SH_PFC_FUNCTION(intc_ex),
2030 SH_PFC_FUNCTION(mmc),
2031 SH_PFC_FUNCTION(msiof0),
2032 SH_PFC_FUNCTION(msiof1),
2033 SH_PFC_FUNCTION(msiof2),
2034 SH_PFC_FUNCTION(msiof3),
2035 SH_PFC_FUNCTION(pwm0),
2036 SH_PFC_FUNCTION(pwm1),
2037 SH_PFC_FUNCTION(pwm2),
2038 SH_PFC_FUNCTION(pwm3),
2039 SH_PFC_FUNCTION(pwm4),
2040 SH_PFC_FUNCTION(qspi0),
2041 SH_PFC_FUNCTION(qspi1),
2042 SH_PFC_FUNCTION(scif_clk),
2043 SH_PFC_FUNCTION(scif0),
2044 SH_PFC_FUNCTION(scif1),
2045 SH_PFC_FUNCTION(scif3),
2046 SH_PFC_FUNCTION(scif4),
2047 SH_PFC_FUNCTION(tmu),
2048 SH_PFC_FUNCTION(vin0),
2049 SH_PFC_FUNCTION(vin1),
2050 };
2051
2052 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2053 #define F_(x, y) FN_##y
2054 #define FM(x) FN_##x
2055 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
2056 0, 0,
2057 0, 0,
2058 0, 0,
2059 0, 0,
2060 0, 0,
2061 0, 0,
2062 0, 0,
2063 0, 0,
2064 0, 0,
2065 0, 0,
2066 GP_0_21_FN, GPSR0_21,
2067 GP_0_20_FN, GPSR0_20,
2068 GP_0_19_FN, GPSR0_19,
2069 GP_0_18_FN, GPSR0_18,
2070 GP_0_17_FN, GPSR0_17,
2071 GP_0_16_FN, GPSR0_16,
2072 GP_0_15_FN, GPSR0_15,
2073 GP_0_14_FN, GPSR0_14,
2074 GP_0_13_FN, GPSR0_13,
2075 GP_0_12_FN, GPSR0_12,
2076 GP_0_11_FN, GPSR0_11,
2077 GP_0_10_FN, GPSR0_10,
2078 GP_0_9_FN, GPSR0_9,
2079 GP_0_8_FN, GPSR0_8,
2080 GP_0_7_FN, GPSR0_7,
2081 GP_0_6_FN, GPSR0_6,
2082 GP_0_5_FN, GPSR0_5,
2083 GP_0_4_FN, GPSR0_4,
2084 GP_0_3_FN, GPSR0_3,
2085 GP_0_2_FN, GPSR0_2,
2086 GP_0_1_FN, GPSR0_1,
2087 GP_0_0_FN, GPSR0_0, ))
2088 },
2089 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
2090 0, 0,
2091 0, 0,
2092 0, 0,
2093 0, 0,
2094 GP_1_27_FN, GPSR1_27,
2095 GP_1_26_FN, GPSR1_26,
2096 GP_1_25_FN, GPSR1_25,
2097 GP_1_24_FN, GPSR1_24,
2098 GP_1_23_FN, GPSR1_23,
2099 GP_1_22_FN, GPSR1_22,
2100 GP_1_21_FN, GPSR1_21,
2101 GP_1_20_FN, GPSR1_20,
2102 GP_1_19_FN, GPSR1_19,
2103 GP_1_18_FN, GPSR1_18,
2104 GP_1_17_FN, GPSR1_17,
2105 GP_1_16_FN, GPSR1_16,
2106 GP_1_15_FN, GPSR1_15,
2107 GP_1_14_FN, GPSR1_14,
2108 GP_1_13_FN, GPSR1_13,
2109 GP_1_12_FN, GPSR1_12,
2110 GP_1_11_FN, GPSR1_11,
2111 GP_1_10_FN, GPSR1_10,
2112 GP_1_9_FN, GPSR1_9,
2113 GP_1_8_FN, GPSR1_8,
2114 GP_1_7_FN, GPSR1_7,
2115 GP_1_6_FN, GPSR1_6,
2116 GP_1_5_FN, GPSR1_5,
2117 GP_1_4_FN, GPSR1_4,
2118 GP_1_3_FN, GPSR1_3,
2119 GP_1_2_FN, GPSR1_2,
2120 GP_1_1_FN, GPSR1_1,
2121 GP_1_0_FN, GPSR1_0, ))
2122 },
2123 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
2124 0, 0,
2125 0, 0,
2126 0, 0,
2127 0, 0,
2128 0, 0,
2129 0, 0,
2130 0, 0,
2131 0, 0,
2132 0, 0,
2133 0, 0,
2134 0, 0,
2135 0, 0,
2136 0, 0,
2137 0, 0,
2138 0, 0,
2139 GP_2_16_FN, GPSR2_16,
2140 GP_2_15_FN, GPSR2_15,
2141 GP_2_14_FN, GPSR2_14,
2142 GP_2_13_FN, GPSR2_13,
2143 GP_2_12_FN, GPSR2_12,
2144 GP_2_11_FN, GPSR2_11,
2145 GP_2_10_FN, GPSR2_10,
2146 GP_2_9_FN, GPSR2_9,
2147 GP_2_8_FN, GPSR2_8,
2148 GP_2_7_FN, GPSR2_7,
2149 GP_2_6_FN, GPSR2_6,
2150 GP_2_5_FN, GPSR2_5,
2151 GP_2_4_FN, GPSR2_4,
2152 GP_2_3_FN, GPSR2_3,
2153 GP_2_2_FN, GPSR2_2,
2154 GP_2_1_FN, GPSR2_1,
2155 GP_2_0_FN, GPSR2_0, ))
2156 },
2157 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
2158 0, 0,
2159 0, 0,
2160 0, 0,
2161 0, 0,
2162 0, 0,
2163 0, 0,
2164 0, 0,
2165 0, 0,
2166 0, 0,
2167 0, 0,
2168 0, 0,
2169 0, 0,
2170 0, 0,
2171 0, 0,
2172 0, 0,
2173 GP_3_16_FN, GPSR3_16,
2174 GP_3_15_FN, GPSR3_15,
2175 GP_3_14_FN, GPSR3_14,
2176 GP_3_13_FN, GPSR3_13,
2177 GP_3_12_FN, GPSR3_12,
2178 GP_3_11_FN, GPSR3_11,
2179 GP_3_10_FN, GPSR3_10,
2180 GP_3_9_FN, GPSR3_9,
2181 GP_3_8_FN, GPSR3_8,
2182 GP_3_7_FN, GPSR3_7,
2183 GP_3_6_FN, GPSR3_6,
2184 GP_3_5_FN, GPSR3_5,
2185 GP_3_4_FN, GPSR3_4,
2186 GP_3_3_FN, GPSR3_3,
2187 GP_3_2_FN, GPSR3_2,
2188 GP_3_1_FN, GPSR3_1,
2189 GP_3_0_FN, GPSR3_0, ))
2190 },
2191 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
2192 0, 0,
2193 0, 0,
2194 0, 0,
2195 0, 0,
2196 0, 0,
2197 0, 0,
2198 0, 0,
2199 0, 0,
2200 0, 0,
2201 0, 0,
2202 0, 0,
2203 0, 0,
2204 0, 0,
2205 0, 0,
2206 0, 0,
2207 0, 0,
2208 0, 0,
2209 0, 0,
2210 0, 0,
2211 0, 0,
2212 0, 0,
2213 0, 0,
2214 0, 0,
2215 0, 0,
2216 0, 0,
2217 0, 0,
2218 GP_4_5_FN, GPSR4_5,
2219 GP_4_4_FN, GPSR4_4,
2220 GP_4_3_FN, GPSR4_3,
2221 GP_4_2_FN, GPSR4_2,
2222 GP_4_1_FN, GPSR4_1,
2223 GP_4_0_FN, GPSR4_0, ))
2224 },
2225 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
2226 0, 0,
2227 0, 0,
2228 0, 0,
2229 0, 0,
2230 0, 0,
2231 0, 0,
2232 0, 0,
2233 0, 0,
2234 0, 0,
2235 0, 0,
2236 0, 0,
2237 0, 0,
2238 0, 0,
2239 0, 0,
2240 0, 0,
2241 0, 0,
2242 0, 0,
2243 GP_5_14_FN, GPSR5_14,
2244 GP_5_13_FN, GPSR5_13,
2245 GP_5_12_FN, GPSR5_12,
2246 GP_5_11_FN, GPSR5_11,
2247 GP_5_10_FN, GPSR5_10,
2248 GP_5_9_FN, GPSR5_9,
2249 GP_5_8_FN, GPSR5_8,
2250 GP_5_7_FN, GPSR5_7,
2251 GP_5_6_FN, GPSR5_6,
2252 GP_5_5_FN, GPSR5_5,
2253 GP_5_4_FN, GPSR5_4,
2254 GP_5_3_FN, GPSR5_3,
2255 GP_5_2_FN, GPSR5_2,
2256 GP_5_1_FN, GPSR5_1,
2257 GP_5_0_FN, GPSR5_0, ))
2258 },
2259 #undef F_
2260 #undef FM
2261
2262 #define F_(x, y) x,
2263 #define FM(x) FN_##x,
2264 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
2265 IP0_31_28
2266 IP0_27_24
2267 IP0_23_20
2268 IP0_19_16
2269 IP0_15_12
2270 IP0_11_8
2271 IP0_7_4
2272 IP0_3_0 ))
2273 },
2274 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
2275 IP1_31_28
2276 IP1_27_24
2277 IP1_23_20
2278 IP1_19_16
2279 IP1_15_12
2280 IP1_11_8
2281 IP1_7_4
2282 IP1_3_0 ))
2283 },
2284 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
2285 IP2_31_28
2286 IP2_27_24
2287 IP2_23_20
2288 IP2_19_16
2289 IP2_15_12
2290 IP2_11_8
2291 IP2_7_4
2292 IP2_3_0 ))
2293 },
2294 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
2295 IP3_31_28
2296 IP3_27_24
2297 IP3_23_20
2298 IP3_19_16
2299 IP3_15_12
2300 IP3_11_8
2301 IP3_7_4
2302 IP3_3_0 ))
2303 },
2304 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
2305 IP4_31_28
2306 IP4_27_24
2307 IP4_23_20
2308 IP4_19_16
2309 IP4_15_12
2310 IP4_11_8
2311 IP4_7_4
2312 IP4_3_0 ))
2313 },
2314 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
2315 IP5_31_28
2316 IP5_27_24
2317 IP5_23_20
2318 IP5_19_16
2319 IP5_15_12
2320 IP5_11_8
2321 IP5_7_4
2322 IP5_3_0 ))
2323 },
2324 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
2325 IP6_31_28
2326 IP6_27_24
2327 IP6_23_20
2328 IP6_19_16
2329 IP6_15_12
2330 IP6_11_8
2331 IP6_7_4
2332 IP6_3_0 ))
2333 },
2334 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
2335 IP7_31_28
2336 IP7_27_24
2337 IP7_23_20
2338 IP7_19_16
2339 IP7_15_12
2340 IP7_11_8
2341 IP7_7_4
2342 IP7_3_0 ))
2343 },
2344 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
2345 IP8_31_28
2346 IP8_27_24
2347 IP8_23_20
2348 IP8_19_16
2349 IP8_15_12
2350 IP8_11_8
2351 IP8_7_4
2352 IP8_3_0 ))
2353 },
2354 #undef F_
2355 #undef FM
2356
2357 #define F_(x, y) x,
2358 #define FM(x) FN_##x,
2359 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
2360 GROUP(4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1,
2361 1, 1, 1, 1, 1),
2362 GROUP(
2363 /* RESERVED 31, 30, 29, 28 */
2364 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2365 /* RESERVED 27, 26, 25, 24 */
2366 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2367 /* RESERVED 23, 22, 21, 20 */
2368 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2369 /* RESERVED 19, 18, 17, 16 */
2370 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2371 /* RESERVED 15, 14, 13, 12 */
2372 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2373 MOD_SEL0_11
2374 MOD_SEL0_10
2375 MOD_SEL0_9
2376 MOD_SEL0_8
2377 MOD_SEL0_7
2378 MOD_SEL0_6
2379 MOD_SEL0_5
2380 MOD_SEL0_4
2381 MOD_SEL0_3
2382 MOD_SEL0_2
2383 MOD_SEL0_1
2384 MOD_SEL0_0 ))
2385 },
2386 { },
2387 };
2388
2389 enum ioctrl_regs {
2390 POCCTRL0,
2391 POCCTRL1,
2392 POCCTRL2,
2393 TDSELCTRL,
2394 };
2395
2396 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
2397 [POCCTRL0] = { 0xe6060380 },
2398 [POCCTRL1] = { 0xe6060384 },
2399 [POCCTRL2] = { 0xe6060388 },
2400 [TDSELCTRL] = { 0xe60603c0, },
2401 { /* sentinel */ },
2402 };
2403
2404 static int r8a77970_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
2405 u32 *pocctrl)
2406 {
2407 int bit = pin & 0x1f;
2408
2409 *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
2410 if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 21))
2411 return bit;
2412 if (pin >= RCAR_GP_PIN(2, 0) && pin <= RCAR_GP_PIN(2, 9))
2413 return bit + 22;
2414
2415 *pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg;
2416 if (pin >= RCAR_GP_PIN(2, 10) && pin <= RCAR_GP_PIN(2, 16))
2417 return bit - 10;
2418 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 16))
2419 return bit + 7;
2420
2421 return -EINVAL;
2422 }
2423
2424 static const struct sh_pfc_soc_operations pinmux_ops = {
2425 .pin_to_pocctrl = r8a77970_pin_to_pocctrl,
2426 };
2427
2428 const struct sh_pfc_soc_info r8a77970_pinmux_info = {
2429 .name = "r8a77970_pfc",
2430 .ops = &pinmux_ops,
2431 .unlock_reg = 0xe6060000, /* PMMR */
2432
2433 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2434
2435 .pins = pinmux_pins,
2436 .nr_pins = ARRAY_SIZE(pinmux_pins),
2437 .groups = pinmux_groups,
2438 .nr_groups = ARRAY_SIZE(pinmux_groups),
2439 .functions = pinmux_functions,
2440 .nr_functions = ARRAY_SIZE(pinmux_functions),
2441
2442 .cfg_regs = pinmux_config_regs,
2443 .ioctrl_regs = pinmux_ioctrl_regs,
2444
2445 .pinmux_data = pinmux_data,
2446 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
2447 };
Linux with added FPC-III support