drivers/pinctrl/sh-pfc/pfc-sh73a0.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * sh73a0 processor support - PFC hardware block
   4  *
   5  * Copyright (C) 2010 Renesas Solutions Corp.
   6  * Copyright (C) 2010 NISHIMOTO Hiroki
   7  */
   8 #include <linux/io.h>
   9 #include <linux/kernel.h>
  10 #include <linux/module.h>
  11 #include <linux/pinctrl/pinconf-generic.h>
  12 #include <linux/regulator/driver.h>
  13 #include <linux/regulator/machine.h>
  14 #include <linux/slab.h>
  15
  16 #include "core.h"
  17 #include "sh_pfc.h"
  18
  19 #define CPU_ALL_PORT(fn, pfx, sfx)                                      \
  20         PORT_10(0,  fn, pfx, sfx), PORT_90(0, fn, pfx, sfx),            \
  21         PORT_10(100, fn, pfx##10, sfx),                                 \
  22         PORT_1(110, fn, pfx##110, sfx), PORT_1(111, fn, pfx##111, sfx), \
  23         PORT_1(112, fn, pfx##112, sfx), PORT_1(113, fn, pfx##113, sfx), \
  24         PORT_1(114, fn, pfx##114, sfx), PORT_1(115, fn, pfx##115, sfx), \
  25         PORT_1(116, fn, pfx##116, sfx), PORT_1(117, fn, pfx##117, sfx), \
  26         PORT_1(118, fn, pfx##118, sfx),                                 \
  27         PORT_1(128, fn, pfx##128, sfx), PORT_1(129, fn, pfx##129, sfx), \
  28         PORT_10(130, fn, pfx##13, sfx), PORT_10(140, fn, pfx##14, sfx), \
  29         PORT_10(150, fn, pfx##15, sfx),                                 \
  30         PORT_1(160, fn, pfx##160, sfx), PORT_1(161, fn, pfx##161, sfx), \
  31         PORT_1(162, fn, pfx##162, sfx), PORT_1(163, fn, pfx##163, sfx), \
  32         PORT_1(164, fn, pfx##164, sfx),                                 \
  33         PORT_1(192, fn, pfx##192, sfx), PORT_1(193, fn, pfx##193, sfx), \
  34         PORT_1(194, fn, pfx##194, sfx), PORT_1(195, fn, pfx##195, sfx), \
  35         PORT_1(196, fn, pfx##196, sfx), PORT_1(197, fn, pfx##197, sfx), \
  36         PORT_1(198, fn, pfx##198, sfx), PORT_1(199, fn, pfx##199, sfx), \
  37         PORT_10(200, fn, pfx##20, sfx), PORT_10(210, fn, pfx##21, sfx), \
  38         PORT_10(220, fn, pfx##22, sfx), PORT_10(230, fn, pfx##23, sfx), \
  39         PORT_10(240, fn, pfx##24, sfx), PORT_10(250, fn, pfx##25, sfx), \
  40         PORT_10(260, fn, pfx##26, sfx), PORT_10(270, fn, pfx##27, sfx), \
  41         PORT_1(280, fn, pfx##280, sfx), PORT_1(281, fn, pfx##281, sfx), \
  42         PORT_1(282, fn, pfx##282, sfx),                                 \
  43         PORT_1(288, fn, pfx##288, sfx), PORT_1(289, fn, pfx##289, sfx), \
  44         PORT_10(290, fn, pfx##29, sfx), PORT_10(300, fn, pfx##30, sfx)
  45
  46 #define CPU_ALL_NOGP(fn)        \
  47         PIN_NOGP(A11, "F26", fn)
  48
  49 enum {
  50         PINMUX_RESERVED = 0,
  51
  52         PINMUX_DATA_BEGIN,
  53         PORT_ALL(DATA),                 /* PORT0_DATA -> PORT309_DATA */
  54         PINMUX_DATA_END,
  55
  56         PINMUX_INPUT_BEGIN,
  57         PORT_ALL(IN),                   /* PORT0_IN -> PORT309_IN */
  58         PINMUX_INPUT_END,
  59
  60         PINMUX_OUTPUT_BEGIN,
  61         PORT_ALL(OUT),                  /* PORT0_OUT -> PORT309_OUT */
  62         PINMUX_OUTPUT_END,
  63
  64         PINMUX_FUNCTION_BEGIN,
  65         PORT_ALL(FN_IN),                /* PORT0_FN_IN -> PORT309_FN_IN */
  66         PORT_ALL(FN_OUT),               /* PORT0_FN_OUT -> PORT309_FN_OUT */
  67         PORT_ALL(FN0),                  /* PORT0_FN0 -> PORT309_FN0 */
  68         PORT_ALL(FN1),                  /* PORT0_FN1 -> PORT309_FN1 */
  69         PORT_ALL(FN2),                  /* PORT0_FN2 -> PORT309_FN2 */
  70         PORT_ALL(FN3),                  /* PORT0_FN3 -> PORT309_FN3 */
  71         PORT_ALL(FN4),                  /* PORT0_FN4 -> PORT309_FN4 */
  72         PORT_ALL(FN5),                  /* PORT0_FN5 -> PORT309_FN5 */
  73         PORT_ALL(FN6),                  /* PORT0_FN6 -> PORT309_FN6 */
  74         PORT_ALL(FN7),                  /* PORT0_FN7 -> PORT309_FN7 */
  75
  76         MSEL2CR_MSEL19_0, MSEL2CR_MSEL19_1,
  77         MSEL2CR_MSEL18_0, MSEL2CR_MSEL18_1,
  78         MSEL2CR_MSEL17_0, MSEL2CR_MSEL17_1,
  79         MSEL2CR_MSEL16_0, MSEL2CR_MSEL16_1,
  80         MSEL2CR_MSEL14_0, MSEL2CR_MSEL14_1,
  81         MSEL2CR_MSEL13_0, MSEL2CR_MSEL13_1,
  82         MSEL2CR_MSEL12_0, MSEL2CR_MSEL12_1,
  83         MSEL2CR_MSEL11_0, MSEL2CR_MSEL11_1,
  84         MSEL2CR_MSEL10_0, MSEL2CR_MSEL10_1,
  85         MSEL2CR_MSEL9_0, MSEL2CR_MSEL9_1,
  86         MSEL2CR_MSEL8_0, MSEL2CR_MSEL8_1,
  87         MSEL2CR_MSEL7_0, MSEL2CR_MSEL7_1,
  88         MSEL2CR_MSEL6_0, MSEL2CR_MSEL6_1,
  89         MSEL2CR_MSEL4_0, MSEL2CR_MSEL4_1,
  90         MSEL2CR_MSEL5_0, MSEL2CR_MSEL5_1,
  91         MSEL2CR_MSEL3_0, MSEL2CR_MSEL3_1,
  92         MSEL2CR_MSEL2_0, MSEL2CR_MSEL2_1,
  93         MSEL2CR_MSEL1_0, MSEL2CR_MSEL1_1,
  94         MSEL2CR_MSEL0_0, MSEL2CR_MSEL0_1,
  95         MSEL3CR_MSEL28_0, MSEL3CR_MSEL28_1,
  96         MSEL3CR_MSEL15_0, MSEL3CR_MSEL15_1,
  97         MSEL3CR_MSEL11_0, MSEL3CR_MSEL11_1,
  98         MSEL3CR_MSEL9_0, MSEL3CR_MSEL9_1,
  99         MSEL3CR_MSEL6_0, MSEL3CR_MSEL6_1,
 100         MSEL3CR_MSEL2_0, MSEL3CR_MSEL2_1,
 101         MSEL4CR_MSEL29_0, MSEL4CR_MSEL29_1,
 102         MSEL4CR_MSEL27_0, MSEL4CR_MSEL27_1,
 103         MSEL4CR_MSEL26_0, MSEL4CR_MSEL26_1,
 104         MSEL4CR_MSEL22_0, MSEL4CR_MSEL22_1,
 105         MSEL4CR_MSEL21_0, MSEL4CR_MSEL21_1,
 106         MSEL4CR_MSEL20_0, MSEL4CR_MSEL20_1,
 107         MSEL4CR_MSEL19_0, MSEL4CR_MSEL19_1,
 108         MSEL4CR_MSEL15_0, MSEL4CR_MSEL15_1,
 109         MSEL4CR_MSEL13_0, MSEL4CR_MSEL13_1,
 110         MSEL4CR_MSEL12_0, MSEL4CR_MSEL12_1,
 111         MSEL4CR_MSEL11_0, MSEL4CR_MSEL11_1,
 112         MSEL4CR_MSEL10_0, MSEL4CR_MSEL10_1,
 113         MSEL4CR_MSEL9_0, MSEL4CR_MSEL9_1,
 114         MSEL4CR_MSEL8_0, MSEL4CR_MSEL8_1,
 115         MSEL4CR_MSEL7_0, MSEL4CR_MSEL7_1,
 116         MSEL4CR_MSEL4_0, MSEL4CR_MSEL4_1,
 117         MSEL4CR_MSEL1_0, MSEL4CR_MSEL1_1,
 118         PINMUX_FUNCTION_END,
 119
 120         PINMUX_MARK_BEGIN,
 121         /* Hardware manual Table 25-1 (Function 0-7) */
 122         VBUS_0_MARK,
 123         GPI0_MARK,
 124         GPI1_MARK,
 125         GPI2_MARK,
 126         GPI3_MARK,
 127         GPI4_MARK,
 128         GPI5_MARK,
 129         GPI6_MARK,
 130         GPI7_MARK,
 131         SCIFA7_RXD_MARK,
 132         SCIFA7_CTS__MARK,
 133         GPO7_MARK, MFG0_OUT2_MARK,
 134         GPO6_MARK, MFG1_OUT2_MARK,
 135         GPO5_MARK, SCIFA0_SCK_MARK, FSICOSLDT3_MARK, PORT16_VIO_CKOR_MARK,
 136         SCIFA0_TXD_MARK,
 137         SCIFA7_TXD_MARK,
 138         SCIFA7_RTS__MARK, PORT19_VIO_CKO2_MARK,
 139         GPO0_MARK,
 140         GPO1_MARK,
 141         GPO2_MARK, STATUS0_MARK,
 142         GPO3_MARK, STATUS1_MARK,
 143         GPO4_MARK, STATUS2_MARK,
 144         VINT_MARK,
 145         TCKON_MARK,
 146         XDVFS1_MARK, PORT27_I2C_SCL2_MARK, PORT27_I2C_SCL3_MARK, \
 147         MFG0_OUT1_MARK, PORT27_IROUT_MARK,
 148         XDVFS2_MARK, PORT28_I2C_SDA2_MARK, PORT28_I2C_SDA3_MARK, \
 149         PORT28_TPU1TO1_MARK,
 150         SIM_RST_MARK, PORT29_TPU1TO1_MARK,
 151         SIM_CLK_MARK, PORT30_VIO_CKOR_MARK,
 152         SIM_D_MARK, PORT31_IROUT_MARK,
 153         SCIFA4_TXD_MARK,
 154         SCIFA4_RXD_MARK, XWUP_MARK,
 155         SCIFA4_RTS__MARK,
 156         SCIFA4_CTS__MARK,
 157         FSIBOBT_MARK, FSIBIBT_MARK,
 158         FSIBOLR_MARK, FSIBILR_MARK,
 159         FSIBOSLD_MARK,
 160         FSIBISLD_MARK,
 161         VACK_MARK,
 162         XTAL1L_MARK,
 163         SCIFA0_RTS__MARK, FSICOSLDT2_MARK,
 164         SCIFA0_RXD_MARK,
 165         SCIFA0_CTS__MARK, FSICOSLDT1_MARK,
 166         FSICOBT_MARK, FSICIBT_MARK, FSIDOBT_MARK, FSIDIBT_MARK,
 167         FSICOLR_MARK, FSICILR_MARK, FSIDOLR_MARK, FSIDILR_MARK,
 168         FSICOSLD_MARK, PORT47_FSICSPDIF_MARK,
 169         FSICISLD_MARK, FSIDISLD_MARK,
 170         FSIACK_MARK, PORT49_IRDA_OUT_MARK, PORT49_IROUT_MARK, FSIAOMC_MARK,
 171         FSIAOLR_MARK, BBIF2_TSYNC2_MARK, TPU2TO2_MARK, FSIAILR_MARK,
 172
 173         FSIAOBT_MARK, BBIF2_TSCK2_MARK, TPU2TO3_MARK, FSIAIBT_MARK,
 174         FSIAOSLD_MARK, BBIF2_TXD2_MARK,
 175         FSIASPDIF_MARK, PORT53_IRDA_IN_MARK, TPU3TO3_MARK, FSIBSPDIF_MARK, \
 176         PORT53_FSICSPDIF_MARK,
 177         FSIBCK_MARK, PORT54_IRDA_FIRSEL_MARK, TPU3TO2_MARK, FSIBOMC_MARK, \
 178         FSICCK_MARK, FSICOMC_MARK,
 179         FSIAISLD_MARK, TPU0TO0_MARK,
 180         A0_MARK, BS__MARK,
 181         A12_MARK, PORT58_KEYOUT7_MARK, TPU4TO2_MARK,
 182         A13_MARK, PORT59_KEYOUT6_MARK, TPU0TO1_MARK,
 183         A14_MARK, KEYOUT5_MARK,
 184         A15_MARK, KEYOUT4_MARK,
 185         A16_MARK, KEYOUT3_MARK, MSIOF0_SS1_MARK,
 186         A17_MARK, KEYOUT2_MARK, MSIOF0_TSYNC_MARK,
 187         A18_MARK, KEYOUT1_MARK, MSIOF0_TSCK_MARK,
 188         A19_MARK, KEYOUT0_MARK, MSIOF0_TXD_MARK,
 189         A20_MARK, KEYIN0_MARK, MSIOF0_RSCK_MARK,
 190         A21_MARK, KEYIN1_MARK, MSIOF0_RSYNC_MARK,
 191         A22_MARK, KEYIN2_MARK, MSIOF0_MCK0_MARK,
 192         A23_MARK, KEYIN3_MARK, MSIOF0_MCK1_MARK,
 193         A24_MARK, KEYIN4_MARK, MSIOF0_RXD_MARK,
 194         A25_MARK, KEYIN5_MARK, MSIOF0_SS2_MARK,
 195         A26_MARK, KEYIN6_MARK,
 196         KEYIN7_MARK,
 197         D0_NAF0_MARK,
 198         D1_NAF1_MARK,
 199         D2_NAF2_MARK,
 200         D3_NAF3_MARK,
 201         D4_NAF4_MARK,
 202         D5_NAF5_MARK,
 203         D6_NAF6_MARK,
 204         D7_NAF7_MARK,
 205         D8_NAF8_MARK,
 206         D9_NAF9_MARK,
 207         D10_NAF10_MARK,
 208         D11_NAF11_MARK,
 209         D12_NAF12_MARK,
 210         D13_NAF13_MARK,
 211         D14_NAF14_MARK,
 212         D15_NAF15_MARK,
 213         CS4__MARK,
 214         CS5A__MARK, PORT91_RDWR_MARK,
 215         CS5B__MARK, FCE1__MARK,
 216         CS6B__MARK, DACK0_MARK,
 217         FCE0__MARK, CS6A__MARK,
 218         WAIT__MARK, DREQ0_MARK,
 219         RD__FSC_MARK,
 220         WE0__FWE_MARK, RDWR_FWE_MARK,
 221         WE1__MARK,
 222         FRB_MARK,
 223         CKO_MARK,
 224         NBRSTOUT__MARK,
 225         NBRST__MARK,
 226         BBIF2_TXD_MARK,
 227         BBIF2_RXD_MARK,
 228         BBIF2_SYNC_MARK,
 229         BBIF2_SCK_MARK,
 230         SCIFA3_CTS__MARK, MFG3_IN2_MARK,
 231         SCIFA3_RXD_MARK, MFG3_IN1_MARK,
 232         BBIF1_SS2_MARK, SCIFA3_RTS__MARK, MFG3_OUT1_MARK,
 233         SCIFA3_TXD_MARK,
 234         HSI_RX_DATA_MARK, BBIF1_RXD_MARK,
 235         HSI_TX_WAKE_MARK, BBIF1_TSCK_MARK,
 236         HSI_TX_DATA_MARK, BBIF1_TSYNC_MARK,
 237         HSI_TX_READY_MARK, BBIF1_TXD_MARK,
 238         HSI_RX_READY_MARK, BBIF1_RSCK_MARK, PORT115_I2C_SCL2_MARK, \
 239         PORT115_I2C_SCL3_MARK,
 240         HSI_RX_WAKE_MARK, BBIF1_RSYNC_MARK, PORT116_I2C_SDA2_MARK, \
 241         PORT116_I2C_SDA3_MARK,
 242         HSI_RX_FLAG_MARK, BBIF1_SS1_MARK, BBIF1_FLOW_MARK,
 243         HSI_TX_FLAG_MARK,
 244         VIO_VD_MARK, PORT128_LCD2VSYN_MARK, VIO2_VD_MARK, LCD2D0_MARK,
 245
 246         VIO_HD_MARK, PORT129_LCD2HSYN_MARK, PORT129_LCD2CS__MARK, \
 247         VIO2_HD_MARK, LCD2D1_MARK,
 248         VIO_D0_MARK, PORT130_MSIOF2_RXD_MARK, LCD2D10_MARK,
 249         VIO_D1_MARK, PORT131_KEYOUT6_MARK, PORT131_MSIOF2_SS1_MARK, \
 250         PORT131_KEYOUT11_MARK, LCD2D11_MARK,
 251         VIO_D2_MARK, PORT132_KEYOUT7_MARK, PORT132_MSIOF2_SS2_MARK, \
 252         PORT132_KEYOUT10_MARK, LCD2D12_MARK,
 253         VIO_D3_MARK, MSIOF2_TSYNC_MARK, LCD2D13_MARK,
 254         VIO_D4_MARK, MSIOF2_TXD_MARK, LCD2D14_MARK,
 255         VIO_D5_MARK, MSIOF2_TSCK_MARK, LCD2D15_MARK,
 256         VIO_D6_MARK, PORT136_KEYOUT8_MARK, LCD2D16_MARK,
 257         VIO_D7_MARK, PORT137_KEYOUT9_MARK, LCD2D17_MARK,
 258         VIO_D8_MARK, PORT138_KEYOUT8_MARK, VIO2_D0_MARK, LCD2D6_MARK,
 259         VIO_D9_MARK, PORT139_KEYOUT9_MARK, VIO2_D1_MARK, LCD2D7_MARK,
 260         VIO_D10_MARK, TPU0TO2_MARK, VIO2_D2_MARK, LCD2D8_MARK,
 261         VIO_D11_MARK, TPU0TO3_MARK, VIO2_D3_MARK, LCD2D9_MARK,
 262         VIO_D12_MARK, PORT142_KEYOUT10_MARK, VIO2_D4_MARK, LCD2D2_MARK,
 263         VIO_D13_MARK, PORT143_KEYOUT11_MARK, PORT143_KEYOUT6_MARK, \
 264         VIO2_D5_MARK, LCD2D3_MARK,
 265         VIO_D14_MARK, PORT144_KEYOUT7_MARK, VIO2_D6_MARK, LCD2D4_MARK,
 266         VIO_D15_MARK, TPU1TO3_MARK, PORT145_LCD2DISP_MARK, \
 267         PORT145_LCD2RS_MARK, VIO2_D7_MARK, LCD2D5_MARK,
 268         VIO_CLK_MARK, LCD2DCK_MARK, PORT146_LCD2WR__MARK, VIO2_CLK_MARK, \
 269         LCD2D18_MARK,
 270         VIO_FIELD_MARK, LCD2RD__MARK, VIO2_FIELD_MARK, LCD2D19_MARK,
 271         VIO_CKO_MARK,
 272         A27_MARK, PORT149_RDWR_MARK, MFG0_IN1_MARK, PORT149_KEYOUT9_MARK,
 273         MFG0_IN2_MARK,
 274         TS_SPSYNC3_MARK, MSIOF2_RSCK_MARK,
 275         TS_SDAT3_MARK, MSIOF2_RSYNC_MARK,
 276         TPU1TO2_MARK, TS_SDEN3_MARK, PORT153_MSIOF2_SS1_MARK,
 277         SCIFA2_TXD1_MARK, MSIOF2_MCK0_MARK,
 278         SCIFA2_RXD1_MARK, MSIOF2_MCK1_MARK,
 279         SCIFA2_RTS1__MARK, PORT156_MSIOF2_SS2_MARK,
 280         SCIFA2_CTS1__MARK, PORT157_MSIOF2_RXD_MARK,
 281         DINT__MARK, SCIFA2_SCK1_MARK, TS_SCK3_MARK,
 282         PORT159_SCIFB_SCK_MARK, PORT159_SCIFA5_SCK_MARK, NMI_MARK,
 283         PORT160_SCIFB_TXD_MARK, PORT160_SCIFA5_TXD_MARK,
 284         PORT161_SCIFB_CTS__MARK, PORT161_SCIFA5_CTS__MARK,
 285         PORT162_SCIFB_RXD_MARK, PORT162_SCIFA5_RXD_MARK,
 286         PORT163_SCIFB_RTS__MARK, PORT163_SCIFA5_RTS__MARK, TPU3TO0_MARK,
 287         LCDD0_MARK,
 288         LCDD1_MARK, PORT193_SCIFA5_CTS__MARK, BBIF2_TSYNC1_MARK,
 289         LCDD2_MARK, PORT194_SCIFA5_RTS__MARK, BBIF2_TSCK1_MARK,
 290         LCDD3_MARK, PORT195_SCIFA5_RXD_MARK, BBIF2_TXD1_MARK,
 291         LCDD4_MARK, PORT196_SCIFA5_TXD_MARK,
 292         LCDD5_MARK, PORT197_SCIFA5_SCK_MARK, MFG2_OUT2_MARK, TPU2TO1_MARK,
 293         LCDD6_MARK,
 294         LCDD7_MARK, TPU4TO1_MARK, MFG4_OUT2_MARK,
 295         LCDD8_MARK, D16_MARK,
 296         LCDD9_MARK, D17_MARK,
 297         LCDD10_MARK, D18_MARK,
 298         LCDD11_MARK, D19_MARK,
 299         LCDD12_MARK, D20_MARK,
 300         LCDD13_MARK, D21_MARK,
 301         LCDD14_MARK, D22_MARK,
 302         LCDD15_MARK, PORT207_MSIOF0L_SS1_MARK, D23_MARK,
 303         LCDD16_MARK, PORT208_MSIOF0L_SS2_MARK, D24_MARK,
 304         LCDD17_MARK, D25_MARK,
 305         LCDD18_MARK, DREQ2_MARK, PORT210_MSIOF0L_SS1_MARK, D26_MARK,
 306         LCDD19_MARK, PORT211_MSIOF0L_SS2_MARK, D27_MARK,
 307         LCDD20_MARK, TS_SPSYNC1_MARK, MSIOF0L_MCK0_MARK, D28_MARK,
 308         LCDD21_MARK, TS_SDAT1_MARK, MSIOF0L_MCK1_MARK, D29_MARK,
 309         LCDD22_MARK, TS_SDEN1_MARK, MSIOF0L_RSCK_MARK, D30_MARK,
 310         LCDD23_MARK, TS_SCK1_MARK, MSIOF0L_RSYNC_MARK, D31_MARK,
 311         LCDDCK_MARK, LCDWR__MARK,
 312         LCDRD__MARK, DACK2_MARK, PORT217_LCD2RS_MARK, MSIOF0L_TSYNC_MARK, \
 313         VIO2_FIELD3_MARK, PORT217_LCD2DISP_MARK,
 314         LCDHSYN_MARK, LCDCS__MARK, LCDCS2__MARK, DACK3_MARK, \
 315         PORT218_VIO_CKOR_MARK,
 316         LCDDISP_MARK, LCDRS_MARK, PORT219_LCD2WR__MARK, DREQ3_MARK, \
 317         MSIOF0L_TSCK_MARK, VIO2_CLK3_MARK, LCD2DCK_2_MARK,
 318         LCDVSYN_MARK, LCDVSYN2_MARK,
 319         LCDLCLK_MARK, DREQ1_MARK, PORT221_LCD2CS__MARK, PWEN_MARK, \
 320         MSIOF0L_RXD_MARK, VIO2_HD3_MARK, PORT221_LCD2HSYN_MARK,
 321         LCDDON_MARK, LCDDON2_MARK, DACK1_MARK, OVCN_MARK, MSIOF0L_TXD_MARK, \
 322         VIO2_VD3_MARK, PORT222_LCD2VSYN_MARK,
 323
 324         SCIFA1_TXD_MARK, OVCN2_MARK,
 325         EXTLP_MARK, SCIFA1_SCK_MARK, PORT226_VIO_CKO2_MARK,
 326         SCIFA1_RTS__MARK, IDIN_MARK,
 327         SCIFA1_RXD_MARK,
 328         SCIFA1_CTS__MARK, MFG1_IN1_MARK,
 329         MSIOF1_TXD_MARK, SCIFA2_TXD2_MARK,
 330         MSIOF1_TSYNC_MARK, SCIFA2_CTS2__MARK,
 331         MSIOF1_TSCK_MARK, SCIFA2_SCK2_MARK,
 332         MSIOF1_RXD_MARK, SCIFA2_RXD2_MARK,
 333         MSIOF1_RSCK_MARK, SCIFA2_RTS2__MARK, VIO2_CLK2_MARK, LCD2D20_MARK,
 334         MSIOF1_RSYNC_MARK, MFG1_IN2_MARK, VIO2_VD2_MARK, LCD2D21_MARK,
 335         MSIOF1_MCK0_MARK, PORT236_I2C_SDA2_MARK,
 336         MSIOF1_MCK1_MARK, PORT237_I2C_SCL2_MARK,
 337         MSIOF1_SS1_MARK, VIO2_FIELD2_MARK, LCD2D22_MARK,
 338         MSIOF1_SS2_MARK, VIO2_HD2_MARK, LCD2D23_MARK,
 339         SCIFA6_TXD_MARK,
 340         PORT241_IRDA_OUT_MARK, PORT241_IROUT_MARK, MFG4_OUT1_MARK, TPU4TO0_MARK,
 341         PORT242_IRDA_IN_MARK, MFG4_IN2_MARK,
 342         PORT243_IRDA_FIRSEL_MARK, PORT243_VIO_CKO2_MARK,
 343         PORT244_SCIFA5_CTS__MARK, MFG2_IN1_MARK, PORT244_SCIFB_CTS__MARK, \
 344         MSIOF2R_RXD_MARK,
 345         PORT245_SCIFA5_RTS__MARK, MFG2_IN2_MARK, PORT245_SCIFB_RTS__MARK, \
 346         MSIOF2R_TXD_MARK,
 347         PORT246_SCIFA5_RXD_MARK, MFG1_OUT1_MARK, PORT246_SCIFB_RXD_MARK, \
 348         TPU1TO0_MARK,
 349         PORT247_SCIFA5_TXD_MARK, MFG3_OUT2_MARK, PORT247_SCIFB_TXD_MARK, \
 350         TPU3TO1_MARK,
 351         PORT248_SCIFA5_SCK_MARK, MFG2_OUT1_MARK, PORT248_SCIFB_SCK_MARK, \
 352         TPU2TO0_MARK, PORT248_I2C_SCL3_MARK, MSIOF2R_TSCK_MARK,
 353         PORT249_IROUT_MARK, MFG4_IN1_MARK, PORT249_I2C_SDA3_MARK, \
 354         MSIOF2R_TSYNC_MARK,
 355         SDHICLK0_MARK,
 356         SDHICD0_MARK,
 357         SDHID0_0_MARK,
 358         SDHID0_1_MARK,
 359         SDHID0_2_MARK,
 360         SDHID0_3_MARK,
 361         SDHICMD0_MARK,
 362         SDHIWP0_MARK,
 363         SDHICLK1_MARK,
 364         SDHID1_0_MARK, TS_SPSYNC2_MARK,
 365         SDHID1_1_MARK, TS_SDAT2_MARK,
 366         SDHID1_2_MARK, TS_SDEN2_MARK,
 367         SDHID1_3_MARK, TS_SCK2_MARK,
 368         SDHICMD1_MARK,
 369         SDHICLK2_MARK,
 370         SDHID2_0_MARK, TS_SPSYNC4_MARK,
 371         SDHID2_1_MARK, TS_SDAT4_MARK,
 372         SDHID2_2_MARK, TS_SDEN4_MARK,
 373         SDHID2_3_MARK, TS_SCK4_MARK,
 374         SDHICMD2_MARK,
 375         MMCCLK0_MARK,
 376         MMCD0_0_MARK,
 377         MMCD0_1_MARK,
 378         MMCD0_2_MARK,
 379         MMCD0_3_MARK,
 380         MMCD0_4_MARK, TS_SPSYNC5_MARK,
 381         MMCD0_5_MARK, TS_SDAT5_MARK,
 382         MMCD0_6_MARK, TS_SDEN5_MARK,
 383         MMCD0_7_MARK, TS_SCK5_MARK,
 384         MMCCMD0_MARK,
 385         RESETOUTS__MARK, EXTAL2OUT_MARK,
 386         MCP_WAIT__MCP_FRB_MARK,
 387         MCP_CKO_MARK, MMCCLK1_MARK,
 388         MCP_D15_MCP_NAF15_MARK,
 389         MCP_D14_MCP_NAF14_MARK,
 390         MCP_D13_MCP_NAF13_MARK,
 391         MCP_D12_MCP_NAF12_MARK,
 392         MCP_D11_MCP_NAF11_MARK,
 393         MCP_D10_MCP_NAF10_MARK,
 394         MCP_D9_MCP_NAF9_MARK,
 395         MCP_D8_MCP_NAF8_MARK, MMCCMD1_MARK,
 396         MCP_D7_MCP_NAF7_MARK, MMCD1_7_MARK,
 397
 398         MCP_D6_MCP_NAF6_MARK, MMCD1_6_MARK,
 399         MCP_D5_MCP_NAF5_MARK, MMCD1_5_MARK,
 400         MCP_D4_MCP_NAF4_MARK, MMCD1_4_MARK,
 401         MCP_D3_MCP_NAF3_MARK, MMCD1_3_MARK,
 402         MCP_D2_MCP_NAF2_MARK, MMCD1_2_MARK,
 403         MCP_D1_MCP_NAF1_MARK, MMCD1_1_MARK,
 404         MCP_D0_MCP_NAF0_MARK, MMCD1_0_MARK,
 405         MCP_NBRSTOUT__MARK,
 406         MCP_WE0__MCP_FWE_MARK, MCP_RDWR_MCP_FWE_MARK,
 407
 408         /* MSEL2 special cases */
 409         TSIF2_TS_XX1_MARK,
 410         TSIF2_TS_XX2_MARK,
 411         TSIF2_TS_XX3_MARK,
 412         TSIF2_TS_XX4_MARK,
 413         TSIF2_TS_XX5_MARK,
 414         TSIF1_TS_XX1_MARK,
 415         TSIF1_TS_XX2_MARK,
 416         TSIF1_TS_XX3_MARK,
 417         TSIF1_TS_XX4_MARK,
 418         TSIF1_TS_XX5_MARK,
 419         TSIF0_TS_XX1_MARK,
 420         TSIF0_TS_XX2_MARK,
 421         TSIF0_TS_XX3_MARK,
 422         TSIF0_TS_XX4_MARK,
 423         TSIF0_TS_XX5_MARK,
 424         MST1_TS_XX1_MARK,
 425         MST1_TS_XX2_MARK,
 426         MST1_TS_XX3_MARK,
 427         MST1_TS_XX4_MARK,
 428         MST1_TS_XX5_MARK,
 429         MST0_TS_XX1_MARK,
 430         MST0_TS_XX2_MARK,
 431         MST0_TS_XX3_MARK,
 432         MST0_TS_XX4_MARK,
 433         MST0_TS_XX5_MARK,
 434
 435         /* MSEL3 special cases */
 436         SDHI0_VCCQ_MC0_ON_MARK,
 437         SDHI0_VCCQ_MC0_OFF_MARK,
 438         DEBUG_MON_VIO_MARK,
 439         DEBUG_MON_LCDD_MARK,
 440         LCDC_LCDC0_MARK,
 441         LCDC_LCDC1_MARK,
 442
 443         /* MSEL4 special cases */
 444         IRQ9_MEM_INT_MARK,
 445         IRQ9_MCP_INT_MARK,
 446         A11_MARK,
 447         KEYOUT8_MARK,
 448         TPU4TO3_MARK,
 449         RESETA_N_PU_ON_MARK,
 450         RESETA_N_PU_OFF_MARK,
 451         EDBGREQ_PD_MARK,
 452         EDBGREQ_PU_MARK,
 453
 454         PINMUX_MARK_END,
 455 };
 456
 457 static const u16 pinmux_data[] = {
 458         /* specify valid pin states for each pin in GPIO mode */
 459         PINMUX_DATA_ALL(),
 460
 461         /* Table 25-1 (Function 0-7) */
 462         PINMUX_DATA(VBUS_0_MARK, PORT0_FN1),
 463         PINMUX_DATA(GPI0_MARK, PORT1_FN1),
 464         PINMUX_DATA(GPI1_MARK, PORT2_FN1),
 465         PINMUX_DATA(GPI2_MARK, PORT3_FN1),
 466         PINMUX_DATA(GPI3_MARK, PORT4_FN1),
 467         PINMUX_DATA(GPI4_MARK, PORT5_FN1),
 468         PINMUX_DATA(GPI5_MARK, PORT6_FN1),
 469         PINMUX_DATA(GPI6_MARK, PORT7_FN1),
 470         PINMUX_DATA(GPI7_MARK, PORT8_FN1),
 471         PINMUX_DATA(SCIFA7_RXD_MARK, PORT12_FN2),
 472         PINMUX_DATA(SCIFA7_CTS__MARK, PORT13_FN2),
 473         PINMUX_DATA(GPO7_MARK, PORT14_FN1), \
 474         PINMUX_DATA(MFG0_OUT2_MARK, PORT14_FN4),
 475         PINMUX_DATA(GPO6_MARK, PORT15_FN1), \
 476         PINMUX_DATA(MFG1_OUT2_MARK, PORT15_FN4),
 477         PINMUX_DATA(GPO5_MARK, PORT16_FN1), \
 478         PINMUX_DATA(SCIFA0_SCK_MARK, PORT16_FN2), \
 479         PINMUX_DATA(FSICOSLDT3_MARK, PORT16_FN3), \
 480         PINMUX_DATA(PORT16_VIO_CKOR_MARK, PORT16_FN4),
 481         PINMUX_DATA(SCIFA0_TXD_MARK, PORT17_FN2),
 482         PINMUX_DATA(SCIFA7_TXD_MARK, PORT18_FN2),
 483         PINMUX_DATA(SCIFA7_RTS__MARK, PORT19_FN2), \
 484         PINMUX_DATA(PORT19_VIO_CKO2_MARK, PORT19_FN3),
 485         PINMUX_DATA(GPO0_MARK, PORT20_FN1),
 486         PINMUX_DATA(GPO1_MARK, PORT21_FN1),
 487         PINMUX_DATA(GPO2_MARK, PORT22_FN1), \
 488         PINMUX_DATA(STATUS0_MARK, PORT22_FN2),
 489         PINMUX_DATA(GPO3_MARK, PORT23_FN1), \
 490         PINMUX_DATA(STATUS1_MARK, PORT23_FN2),
 491         PINMUX_DATA(GPO4_MARK, PORT24_FN1), \
 492         PINMUX_DATA(STATUS2_MARK, PORT24_FN2),
 493         PINMUX_DATA(VINT_MARK, PORT25_FN1),
 494         PINMUX_DATA(TCKON_MARK, PORT26_FN1),
 495         PINMUX_DATA(XDVFS1_MARK, PORT27_FN1), \
 496         PINMUX_DATA(PORT27_I2C_SCL2_MARK, PORT27_FN2, MSEL2CR_MSEL17_0,
 497                 MSEL2CR_MSEL16_1), \
 498         PINMUX_DATA(PORT27_I2C_SCL3_MARK, PORT27_FN3, MSEL2CR_MSEL19_0,
 499                 MSEL2CR_MSEL18_1), \
 500         PINMUX_DATA(MFG0_OUT1_MARK, PORT27_FN4), \
 501         PINMUX_DATA(PORT27_IROUT_MARK, PORT27_FN7),
 502         PINMUX_DATA(XDVFS2_MARK, PORT28_FN1), \
 503         PINMUX_DATA(PORT28_I2C_SDA2_MARK, PORT28_FN2, MSEL2CR_MSEL17_0,
 504                 MSEL2CR_MSEL16_1), \
 505         PINMUX_DATA(PORT28_I2C_SDA3_MARK, PORT28_FN3, MSEL2CR_MSEL19_0,
 506                 MSEL2CR_MSEL18_1), \
 507         PINMUX_DATA(PORT28_TPU1TO1_MARK, PORT28_FN7),
 508         PINMUX_DATA(SIM_RST_MARK, PORT29_FN1), \
 509         PINMUX_DATA(PORT29_TPU1TO1_MARK, PORT29_FN4),
 510         PINMUX_DATA(SIM_CLK_MARK, PORT30_FN1), \
 511         PINMUX_DATA(PORT30_VIO_CKOR_MARK, PORT30_FN4),
 512         PINMUX_DATA(SIM_D_MARK, PORT31_FN1), \
 513         PINMUX_DATA(PORT31_IROUT_MARK, PORT31_FN4),
 514         PINMUX_DATA(SCIFA4_TXD_MARK, PORT32_FN2),
 515         PINMUX_DATA(SCIFA4_RXD_MARK, PORT33_FN2), \
 516         PINMUX_DATA(XWUP_MARK, PORT33_FN3),
 517         PINMUX_DATA(SCIFA4_RTS__MARK, PORT34_FN2),
 518         PINMUX_DATA(SCIFA4_CTS__MARK, PORT35_FN2),
 519         PINMUX_DATA(FSIBOBT_MARK, PORT36_FN1), \
 520         PINMUX_DATA(FSIBIBT_MARK, PORT36_FN2),
 521         PINMUX_DATA(FSIBOLR_MARK, PORT37_FN1), \
 522         PINMUX_DATA(FSIBILR_MARK, PORT37_FN2),
 523         PINMUX_DATA(FSIBOSLD_MARK, PORT38_FN1),
 524         PINMUX_DATA(FSIBISLD_MARK, PORT39_FN1),
 525         PINMUX_DATA(VACK_MARK, PORT40_FN1),
 526         PINMUX_DATA(XTAL1L_MARK, PORT41_FN1),
 527         PINMUX_DATA(SCIFA0_RTS__MARK, PORT42_FN2), \
 528         PINMUX_DATA(FSICOSLDT2_MARK, PORT42_FN3),
 529         PINMUX_DATA(SCIFA0_RXD_MARK, PORT43_FN2),
 530         PINMUX_DATA(SCIFA0_CTS__MARK, PORT44_FN2), \
 531         PINMUX_DATA(FSICOSLDT1_MARK, PORT44_FN3),
 532         PINMUX_DATA(FSICOBT_MARK, PORT45_FN1), \
 533         PINMUX_DATA(FSICIBT_MARK, PORT45_FN2), \
 534         PINMUX_DATA(FSIDOBT_MARK, PORT45_FN3), \
 535         PINMUX_DATA(FSIDIBT_MARK, PORT45_FN4),
 536         PINMUX_DATA(FSICOLR_MARK, PORT46_FN1), \
 537         PINMUX_DATA(FSICILR_MARK, PORT46_FN2), \
 538         PINMUX_DATA(FSIDOLR_MARK, PORT46_FN3), \
 539         PINMUX_DATA(FSIDILR_MARK, PORT46_FN4),
 540         PINMUX_DATA(FSICOSLD_MARK, PORT47_FN1), \
 541         PINMUX_DATA(PORT47_FSICSPDIF_MARK, PORT47_FN2),
 542         PINMUX_DATA(FSICISLD_MARK, PORT48_FN1), \
 543         PINMUX_DATA(FSIDISLD_MARK, PORT48_FN3),
 544         PINMUX_DATA(FSIACK_MARK, PORT49_FN1), \
 545         PINMUX_DATA(PORT49_IRDA_OUT_MARK, PORT49_FN2, MSEL4CR_MSEL19_1), \
 546         PINMUX_DATA(PORT49_IROUT_MARK, PORT49_FN4), \
 547         PINMUX_DATA(FSIAOMC_MARK, PORT49_FN5),
 548         PINMUX_DATA(FSIAOLR_MARK, PORT50_FN1), \
 549         PINMUX_DATA(BBIF2_TSYNC2_MARK, PORT50_FN2), \
 550         PINMUX_DATA(TPU2TO2_MARK, PORT50_FN3), \
 551         PINMUX_DATA(FSIAILR_MARK, PORT50_FN5),
 552
 553         PINMUX_DATA(FSIAOBT_MARK, PORT51_FN1), \
 554         PINMUX_DATA(BBIF2_TSCK2_MARK, PORT51_FN2), \
 555         PINMUX_DATA(TPU2TO3_MARK, PORT51_FN3), \
 556         PINMUX_DATA(FSIAIBT_MARK, PORT51_FN5),
 557         PINMUX_DATA(FSIAOSLD_MARK, PORT52_FN1), \
 558         PINMUX_DATA(BBIF2_TXD2_MARK, PORT52_FN2),
 559         PINMUX_DATA(FSIASPDIF_MARK, PORT53_FN1), \
 560         PINMUX_DATA(PORT53_IRDA_IN_MARK, PORT53_FN2, MSEL4CR_MSEL19_1), \
 561         PINMUX_DATA(TPU3TO3_MARK, PORT53_FN3), \
 562         PINMUX_DATA(FSIBSPDIF_MARK, PORT53_FN5), \
 563         PINMUX_DATA(PORT53_FSICSPDIF_MARK, PORT53_FN6),
 564         PINMUX_DATA(FSIBCK_MARK, PORT54_FN1), \
 565         PINMUX_DATA(PORT54_IRDA_FIRSEL_MARK, PORT54_FN2, MSEL4CR_MSEL19_1), \
 566         PINMUX_DATA(TPU3TO2_MARK, PORT54_FN3), \
 567         PINMUX_DATA(FSIBOMC_MARK, PORT54_FN5), \
 568         PINMUX_DATA(FSICCK_MARK, PORT54_FN6), \
 569         PINMUX_DATA(FSICOMC_MARK, PORT54_FN7),
 570         PINMUX_DATA(FSIAISLD_MARK, PORT55_FN1), \
 571         PINMUX_DATA(TPU0TO0_MARK, PORT55_FN3),
 572         PINMUX_DATA(A0_MARK, PORT57_FN1), \
 573         PINMUX_DATA(BS__MARK, PORT57_FN2),
 574         PINMUX_DATA(A12_MARK, PORT58_FN1), \
 575         PINMUX_DATA(PORT58_KEYOUT7_MARK, PORT58_FN2), \
 576         PINMUX_DATA(TPU4TO2_MARK, PORT58_FN4),
 577         PINMUX_DATA(A13_MARK, PORT59_FN1), \
 578         PINMUX_DATA(PORT59_KEYOUT6_MARK, PORT59_FN2), \
 579         PINMUX_DATA(TPU0TO1_MARK, PORT59_FN4),
 580         PINMUX_DATA(A14_MARK, PORT60_FN1), \
 581         PINMUX_DATA(KEYOUT5_MARK, PORT60_FN2),
 582         PINMUX_DATA(A15_MARK, PORT61_FN1), \
 583         PINMUX_DATA(KEYOUT4_MARK, PORT61_FN2),
 584         PINMUX_DATA(A16_MARK, PORT62_FN1), \
 585         PINMUX_DATA(KEYOUT3_MARK, PORT62_FN2), \
 586         PINMUX_DATA(MSIOF0_SS1_MARK, PORT62_FN4, MSEL3CR_MSEL11_0),
 587         PINMUX_DATA(A17_MARK, PORT63_FN1), \
 588         PINMUX_DATA(KEYOUT2_MARK, PORT63_FN2), \
 589         PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT63_FN4, MSEL3CR_MSEL11_0),
 590         PINMUX_DATA(A18_MARK, PORT64_FN1), \
 591         PINMUX_DATA(KEYOUT1_MARK, PORT64_FN2), \
 592         PINMUX_DATA(MSIOF0_TSCK_MARK, PORT64_FN4, MSEL3CR_MSEL11_0),
 593         PINMUX_DATA(A19_MARK, PORT65_FN1), \
 594         PINMUX_DATA(KEYOUT0_MARK, PORT65_FN2), \
 595         PINMUX_DATA(MSIOF0_TXD_MARK, PORT65_FN4, MSEL3CR_MSEL11_0),
 596         PINMUX_DATA(A20_MARK, PORT66_FN1), \
 597         PINMUX_DATA(KEYIN0_MARK, PORT66_FN2), \
 598         PINMUX_DATA(MSIOF0_RSCK_MARK, PORT66_FN4, MSEL3CR_MSEL11_0),
 599         PINMUX_DATA(A21_MARK, PORT67_FN1), \
 600         PINMUX_DATA(KEYIN1_MARK, PORT67_FN2), \
 601         PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT67_FN4, MSEL3CR_MSEL11_0),
 602         PINMUX_DATA(A22_MARK, PORT68_FN1), \
 603         PINMUX_DATA(KEYIN2_MARK, PORT68_FN2), \
 604         PINMUX_DATA(MSIOF0_MCK0_MARK, PORT68_FN4, MSEL3CR_MSEL11_0),
 605         PINMUX_DATA(A23_MARK, PORT69_FN1), \
 606         PINMUX_DATA(KEYIN3_MARK, PORT69_FN2), \
 607         PINMUX_DATA(MSIOF0_MCK1_MARK, PORT69_FN4, MSEL3CR_MSEL11_0),
 608         PINMUX_DATA(A24_MARK, PORT70_FN1), \
 609         PINMUX_DATA(KEYIN4_MARK, PORT70_FN2), \
 610         PINMUX_DATA(MSIOF0_RXD_MARK, PORT70_FN4, MSEL3CR_MSEL11_0),
 611         PINMUX_DATA(A25_MARK, PORT71_FN1), \
 612         PINMUX_DATA(KEYIN5_MARK, PORT71_FN2), \
 613         PINMUX_DATA(MSIOF0_SS2_MARK, PORT71_FN4, MSEL3CR_MSEL11_0),
 614         PINMUX_DATA(A26_MARK, PORT72_FN1), \
 615         PINMUX_DATA(KEYIN6_MARK, PORT72_FN2),
 616         PINMUX_DATA(KEYIN7_MARK, PORT73_FN2),
 617         PINMUX_DATA(D0_NAF0_MARK, PORT74_FN1),
 618         PINMUX_DATA(D1_NAF1_MARK, PORT75_FN1),
 619         PINMUX_DATA(D2_NAF2_MARK, PORT76_FN1),
 620         PINMUX_DATA(D3_NAF3_MARK, PORT77_FN1),
 621         PINMUX_DATA(D4_NAF4_MARK, PORT78_FN1),
 622         PINMUX_DATA(D5_NAF5_MARK, PORT79_FN1),
 623         PINMUX_DATA(D6_NAF6_MARK, PORT80_FN1),
 624         PINMUX_DATA(D7_NAF7_MARK, PORT81_FN1),
 625         PINMUX_DATA(D8_NAF8_MARK, PORT82_FN1),
 626         PINMUX_DATA(D9_NAF9_MARK, PORT83_FN1),
 627         PINMUX_DATA(D10_NAF10_MARK, PORT84_FN1),
 628         PINMUX_DATA(D11_NAF11_MARK, PORT85_FN1),
 629         PINMUX_DATA(D12_NAF12_MARK, PORT86_FN1),
 630         PINMUX_DATA(D13_NAF13_MARK, PORT87_FN1),
 631         PINMUX_DATA(D14_NAF14_MARK, PORT88_FN1),
 632         PINMUX_DATA(D15_NAF15_MARK, PORT89_FN1),
 633         PINMUX_DATA(CS4__MARK, PORT90_FN1),
 634         PINMUX_DATA(CS5A__MARK, PORT91_FN1), \
 635         PINMUX_DATA(PORT91_RDWR_MARK, PORT91_FN2),
 636         PINMUX_DATA(CS5B__MARK, PORT92_FN1), \
 637         PINMUX_DATA(FCE1__MARK, PORT92_FN2),
 638         PINMUX_DATA(CS6B__MARK, PORT93_FN1), \
 639         PINMUX_DATA(DACK0_MARK, PORT93_FN4),
 640         PINMUX_DATA(FCE0__MARK, PORT94_FN1), \
 641         PINMUX_DATA(CS6A__MARK, PORT94_FN2),
 642         PINMUX_DATA(WAIT__MARK, PORT95_FN1), \
 643         PINMUX_DATA(DREQ0_MARK, PORT95_FN2),
 644         PINMUX_DATA(RD__FSC_MARK, PORT96_FN1),
 645         PINMUX_DATA(WE0__FWE_MARK, PORT97_FN1), \
 646         PINMUX_DATA(RDWR_FWE_MARK, PORT97_FN2),
 647         PINMUX_DATA(WE1__MARK, PORT98_FN1),
 648         PINMUX_DATA(FRB_MARK, PORT99_FN1),
 649         PINMUX_DATA(CKO_MARK, PORT100_FN1),
 650         PINMUX_DATA(NBRSTOUT__MARK, PORT101_FN1),
 651         PINMUX_DATA(NBRST__MARK, PORT102_FN1),
 652         PINMUX_DATA(BBIF2_TXD_MARK, PORT103_FN3),
 653         PINMUX_DATA(BBIF2_RXD_MARK, PORT104_FN3),
 654         PINMUX_DATA(BBIF2_SYNC_MARK, PORT105_FN3),
 655         PINMUX_DATA(BBIF2_SCK_MARK, PORT106_FN3),
 656         PINMUX_DATA(SCIFA3_CTS__MARK, PORT107_FN3), \
 657         PINMUX_DATA(MFG3_IN2_MARK, PORT107_FN4),
 658         PINMUX_DATA(SCIFA3_RXD_MARK, PORT108_FN3), \
 659         PINMUX_DATA(MFG3_IN1_MARK, PORT108_FN4),
 660         PINMUX_DATA(BBIF1_SS2_MARK, PORT109_FN2), \
 661         PINMUX_DATA(SCIFA3_RTS__MARK, PORT109_FN3), \
 662         PINMUX_DATA(MFG3_OUT1_MARK, PORT109_FN4),
 663         PINMUX_DATA(SCIFA3_TXD_MARK, PORT110_FN3),
 664         PINMUX_DATA(HSI_RX_DATA_MARK, PORT111_FN1), \
 665         PINMUX_DATA(BBIF1_RXD_MARK, PORT111_FN3),
 666         PINMUX_DATA(HSI_TX_WAKE_MARK, PORT112_FN1), \
 667         PINMUX_DATA(BBIF1_TSCK_MARK, PORT112_FN3),
 668         PINMUX_DATA(HSI_TX_DATA_MARK, PORT113_FN1), \
 669         PINMUX_DATA(BBIF1_TSYNC_MARK, PORT113_FN3),
 670         PINMUX_DATA(HSI_TX_READY_MARK, PORT114_FN1), \
 671         PINMUX_DATA(BBIF1_TXD_MARK, PORT114_FN3),
 672         PINMUX_DATA(HSI_RX_READY_MARK, PORT115_FN1), \
 673         PINMUX_DATA(BBIF1_RSCK_MARK, PORT115_FN3), \
 674         PINMUX_DATA(PORT115_I2C_SCL2_MARK, PORT115_FN5, MSEL2CR_MSEL17_1), \
 675         PINMUX_DATA(PORT115_I2C_SCL3_MARK, PORT115_FN6, MSEL2CR_MSEL19_1),
 676         PINMUX_DATA(HSI_RX_WAKE_MARK, PORT116_FN1), \
 677         PINMUX_DATA(BBIF1_RSYNC_MARK, PORT116_FN3), \
 678         PINMUX_DATA(PORT116_I2C_SDA2_MARK, PORT116_FN5, MSEL2CR_MSEL17_1), \
 679         PINMUX_DATA(PORT116_I2C_SDA3_MARK, PORT116_FN6, MSEL2CR_MSEL19_1),
 680         PINMUX_DATA(HSI_RX_FLAG_MARK, PORT117_FN1), \
 681         PINMUX_DATA(BBIF1_SS1_MARK, PORT117_FN2), \
 682         PINMUX_DATA(BBIF1_FLOW_MARK, PORT117_FN3),
 683         PINMUX_DATA(HSI_TX_FLAG_MARK, PORT118_FN1),
 684         PINMUX_DATA(VIO_VD_MARK, PORT128_FN1), \
 685         PINMUX_DATA(PORT128_LCD2VSYN_MARK, PORT128_FN4, MSEL3CR_MSEL2_0), \
 686         PINMUX_DATA(VIO2_VD_MARK, PORT128_FN6, MSEL4CR_MSEL27_0), \
 687         PINMUX_DATA(LCD2D0_MARK, PORT128_FN7),
 688
 689         PINMUX_DATA(VIO_HD_MARK, PORT129_FN1), \
 690         PINMUX_DATA(PORT129_LCD2HSYN_MARK, PORT129_FN4), \
 691         PINMUX_DATA(PORT129_LCD2CS__MARK, PORT129_FN5), \
 692         PINMUX_DATA(VIO2_HD_MARK, PORT129_FN6, MSEL4CR_MSEL27_0), \
 693         PINMUX_DATA(LCD2D1_MARK, PORT129_FN7),
 694         PINMUX_DATA(VIO_D0_MARK, PORT130_FN1), \
 695         PINMUX_DATA(PORT130_MSIOF2_RXD_MARK, PORT130_FN3, MSEL4CR_MSEL11_0,
 696                 MSEL4CR_MSEL10_1), \
 697         PINMUX_DATA(LCD2D10_MARK, PORT130_FN7),
 698         PINMUX_DATA(VIO_D1_MARK, PORT131_FN1), \
 699         PINMUX_DATA(PORT131_KEYOUT6_MARK, PORT131_FN2), \
 700         PINMUX_DATA(PORT131_MSIOF2_SS1_MARK, PORT131_FN3), \
 701         PINMUX_DATA(PORT131_KEYOUT11_MARK, PORT131_FN4), \
 702         PINMUX_DATA(LCD2D11_MARK, PORT131_FN7),
 703         PINMUX_DATA(VIO_D2_MARK, PORT132_FN1), \
 704         PINMUX_DATA(PORT132_KEYOUT7_MARK, PORT132_FN2), \
 705         PINMUX_DATA(PORT132_MSIOF2_SS2_MARK, PORT132_FN3), \
 706         PINMUX_DATA(PORT132_KEYOUT10_MARK, PORT132_FN4), \
 707         PINMUX_DATA(LCD2D12_MARK, PORT132_FN7),
 708         PINMUX_DATA(VIO_D3_MARK, PORT133_FN1), \
 709         PINMUX_DATA(MSIOF2_TSYNC_MARK, PORT133_FN3, MSEL4CR_MSEL11_0), \
 710         PINMUX_DATA(LCD2D13_MARK, PORT133_FN7),
 711         PINMUX_DATA(VIO_D4_MARK, PORT134_FN1), \
 712         PINMUX_DATA(MSIOF2_TXD_MARK, PORT134_FN3, MSEL4CR_MSEL11_0), \
 713         PINMUX_DATA(LCD2D14_MARK, PORT134_FN7),
 714         PINMUX_DATA(VIO_D5_MARK, PORT135_FN1), \
 715         PINMUX_DATA(MSIOF2_TSCK_MARK, PORT135_FN3, MSEL4CR_MSEL11_0), \
 716         PINMUX_DATA(LCD2D15_MARK, PORT135_FN7),
 717         PINMUX_DATA(VIO_D6_MARK, PORT136_FN1), \
 718         PINMUX_DATA(PORT136_KEYOUT8_MARK, PORT136_FN2), \
 719         PINMUX_DATA(LCD2D16_MARK, PORT136_FN7),
 720         PINMUX_DATA(VIO_D7_MARK, PORT137_FN1), \
 721         PINMUX_DATA(PORT137_KEYOUT9_MARK, PORT137_FN2), \
 722         PINMUX_DATA(LCD2D17_MARK, PORT137_FN7),
 723         PINMUX_DATA(VIO_D8_MARK, PORT138_FN1), \
 724         PINMUX_DATA(PORT138_KEYOUT8_MARK, PORT138_FN2), \
 725         PINMUX_DATA(VIO2_D0_MARK, PORT138_FN6), \
 726         PINMUX_DATA(LCD2D6_MARK, PORT138_FN7),
 727         PINMUX_DATA(VIO_D9_MARK, PORT139_FN1), \
 728         PINMUX_DATA(PORT139_KEYOUT9_MARK, PORT139_FN2), \
 729         PINMUX_DATA(VIO2_D1_MARK, PORT139_FN6), \
 730         PINMUX_DATA(LCD2D7_MARK, PORT139_FN7),
 731         PINMUX_DATA(VIO_D10_MARK, PORT140_FN1), \
 732         PINMUX_DATA(TPU0TO2_MARK, PORT140_FN4), \
 733         PINMUX_DATA(VIO2_D2_MARK, PORT140_FN6), \
 734         PINMUX_DATA(LCD2D8_MARK, PORT140_FN7),
 735         PINMUX_DATA(VIO_D11_MARK, PORT141_FN1), \
 736         PINMUX_DATA(TPU0TO3_MARK, PORT141_FN4), \
 737         PINMUX_DATA(VIO2_D3_MARK, PORT141_FN6), \
 738         PINMUX_DATA(LCD2D9_MARK, PORT141_FN7),
 739         PINMUX_DATA(VIO_D12_MARK, PORT142_FN1), \
 740         PINMUX_DATA(PORT142_KEYOUT10_MARK, PORT142_FN2), \
 741         PINMUX_DATA(VIO2_D4_MARK, PORT142_FN6), \
 742         PINMUX_DATA(LCD2D2_MARK, PORT142_FN7),
 743         PINMUX_DATA(VIO_D13_MARK, PORT143_FN1), \
 744         PINMUX_DATA(PORT143_KEYOUT11_MARK, PORT143_FN2), \
 745         PINMUX_DATA(PORT143_KEYOUT6_MARK, PORT143_FN3), \
 746         PINMUX_DATA(VIO2_D5_MARK, PORT143_FN6), \
 747         PINMUX_DATA(LCD2D3_MARK, PORT143_FN7),
 748         PINMUX_DATA(VIO_D14_MARK, PORT144_FN1), \
 749         PINMUX_DATA(PORT144_KEYOUT7_MARK, PORT144_FN2), \
 750         PINMUX_DATA(VIO2_D6_MARK, PORT144_FN6), \
 751         PINMUX_DATA(LCD2D4_MARK, PORT144_FN7),
 752         PINMUX_DATA(VIO_D15_MARK, PORT145_FN1), \
 753         PINMUX_DATA(TPU1TO3_MARK, PORT145_FN3), \
 754         PINMUX_DATA(PORT145_LCD2DISP_MARK, PORT145_FN4), \
 755         PINMUX_DATA(PORT145_LCD2RS_MARK, PORT145_FN5), \
 756         PINMUX_DATA(VIO2_D7_MARK, PORT145_FN6), \
 757         PINMUX_DATA(LCD2D5_MARK, PORT145_FN7),
 758         PINMUX_DATA(VIO_CLK_MARK, PORT146_FN1), \
 759         PINMUX_DATA(LCD2DCK_MARK, PORT146_FN4), \
 760         PINMUX_DATA(PORT146_LCD2WR__MARK, PORT146_FN5), \
 761         PINMUX_DATA(VIO2_CLK_MARK, PORT146_FN6, MSEL4CR_MSEL27_0), \
 762         PINMUX_DATA(LCD2D18_MARK, PORT146_FN7),
 763         PINMUX_DATA(VIO_FIELD_MARK, PORT147_FN1), \
 764         PINMUX_DATA(LCD2RD__MARK, PORT147_FN4), \
 765         PINMUX_DATA(VIO2_FIELD_MARK, PORT147_FN6, MSEL4CR_MSEL27_0), \
 766         PINMUX_DATA(LCD2D19_MARK, PORT147_FN7),
 767         PINMUX_DATA(VIO_CKO_MARK, PORT148_FN1),
 768         PINMUX_DATA(A27_MARK, PORT149_FN1), \
 769         PINMUX_DATA(PORT149_RDWR_MARK, PORT149_FN2), \
 770         PINMUX_DATA(MFG0_IN1_MARK, PORT149_FN3), \
 771         PINMUX_DATA(PORT149_KEYOUT9_MARK, PORT149_FN4),
 772         PINMUX_DATA(MFG0_IN2_MARK, PORT150_FN3),
 773         PINMUX_DATA(TS_SPSYNC3_MARK, PORT151_FN4), \
 774         PINMUX_DATA(MSIOF2_RSCK_MARK, PORT151_FN5),
 775         PINMUX_DATA(TS_SDAT3_MARK, PORT152_FN4), \
 776         PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT152_FN5),
 777         PINMUX_DATA(TPU1TO2_MARK, PORT153_FN3), \
 778         PINMUX_DATA(TS_SDEN3_MARK, PORT153_FN4), \
 779         PINMUX_DATA(PORT153_MSIOF2_SS1_MARK, PORT153_FN5),
 780         PINMUX_DATA(SCIFA2_TXD1_MARK, PORT154_FN2, MSEL3CR_MSEL9_0), \
 781         PINMUX_DATA(MSIOF2_MCK0_MARK, PORT154_FN5),
 782         PINMUX_DATA(SCIFA2_RXD1_MARK, PORT155_FN2, MSEL3CR_MSEL9_0), \
 783         PINMUX_DATA(MSIOF2_MCK1_MARK, PORT155_FN5),
 784         PINMUX_DATA(SCIFA2_RTS1__MARK, PORT156_FN2, MSEL3CR_MSEL9_0), \
 785         PINMUX_DATA(PORT156_MSIOF2_SS2_MARK, PORT156_FN5),
 786         PINMUX_DATA(SCIFA2_CTS1__MARK, PORT157_FN2, MSEL3CR_MSEL9_0), \
 787         PINMUX_DATA(PORT157_MSIOF2_RXD_MARK, PORT157_FN5, MSEL4CR_MSEL11_0,
 788                 MSEL4CR_MSEL10_0),
 789         PINMUX_DATA(DINT__MARK, PORT158_FN1), \
 790         PINMUX_DATA(SCIFA2_SCK1_MARK, PORT158_FN2, MSEL3CR_MSEL9_0), \
 791         PINMUX_DATA(TS_SCK3_MARK, PORT158_FN4),
 792         PINMUX_DATA(PORT159_SCIFB_SCK_MARK, PORT159_FN1, MSEL4CR_MSEL22_0), \
 793         PINMUX_DATA(PORT159_SCIFA5_SCK_MARK, PORT159_FN2, MSEL4CR_MSEL21_1), \
 794         PINMUX_DATA(NMI_MARK, PORT159_FN3),
 795         PINMUX_DATA(PORT160_SCIFB_TXD_MARK, PORT160_FN1, MSEL4CR_MSEL22_0), \
 796         PINMUX_DATA(PORT160_SCIFA5_TXD_MARK, PORT160_FN2, MSEL4CR_MSEL21_1),
 797         PINMUX_DATA(PORT161_SCIFB_CTS__MARK, PORT161_FN1, MSEL4CR_MSEL22_0), \
 798         PINMUX_DATA(PORT161_SCIFA5_CTS__MARK, PORT161_FN2, MSEL4CR_MSEL21_1),
 799         PINMUX_DATA(PORT162_SCIFB_RXD_MARK, PORT162_FN1, MSEL4CR_MSEL22_0), \
 800         PINMUX_DATA(PORT162_SCIFA5_RXD_MARK, PORT162_FN2, MSEL4CR_MSEL21_1),
 801         PINMUX_DATA(PORT163_SCIFB_RTS__MARK, PORT163_FN1, MSEL4CR_MSEL22_0), \
 802         PINMUX_DATA(PORT163_SCIFA5_RTS__MARK, PORT163_FN2, MSEL4CR_MSEL21_1), \
 803         PINMUX_DATA(TPU3TO0_MARK, PORT163_FN5),
 804         PINMUX_DATA(LCDD0_MARK, PORT192_FN1),
 805         PINMUX_DATA(LCDD1_MARK, PORT193_FN1), \
 806         PINMUX_DATA(PORT193_SCIFA5_CTS__MARK, PORT193_FN3, MSEL4CR_MSEL21_0,
 807                 MSEL4CR_MSEL20_1), \
 808         PINMUX_DATA(BBIF2_TSYNC1_MARK, PORT193_FN5),
 809         PINMUX_DATA(LCDD2_MARK, PORT194_FN1), \
 810         PINMUX_DATA(PORT194_SCIFA5_RTS__MARK, PORT194_FN3, MSEL4CR_MSEL21_0,
 811                 MSEL4CR_MSEL20_1), \
 812         PINMUX_DATA(BBIF2_TSCK1_MARK, PORT194_FN5),
 813         PINMUX_DATA(LCDD3_MARK, PORT195_FN1), \
 814         PINMUX_DATA(PORT195_SCIFA5_RXD_MARK, PORT195_FN3, MSEL4CR_MSEL21_0,
 815                 MSEL4CR_MSEL20_1), \
 816         PINMUX_DATA(BBIF2_TXD1_MARK, PORT195_FN5),
 817         PINMUX_DATA(LCDD4_MARK, PORT196_FN1), \
 818         PINMUX_DATA(PORT196_SCIFA5_TXD_MARK, PORT196_FN3, MSEL4CR_MSEL21_0,
 819                 MSEL4CR_MSEL20_1),
 820         PINMUX_DATA(LCDD5_MARK, PORT197_FN1), \
 821         PINMUX_DATA(PORT197_SCIFA5_SCK_MARK, PORT197_FN3, MSEL4CR_MSEL21_0,
 822                 MSEL4CR_MSEL20_1), \
 823         PINMUX_DATA(MFG2_OUT2_MARK, PORT197_FN5), \
 824         PINMUX_DATA(TPU2TO1_MARK, PORT197_FN7),
 825         PINMUX_DATA(LCDD6_MARK, PORT198_FN1),
 826         PINMUX_DATA(LCDD7_MARK, PORT199_FN1), \
 827         PINMUX_DATA(TPU4TO1_MARK, PORT199_FN2), \
 828         PINMUX_DATA(MFG4_OUT2_MARK, PORT199_FN5),
 829         PINMUX_DATA(LCDD8_MARK, PORT200_FN1), \
 830         PINMUX_DATA(D16_MARK, PORT200_FN6),
 831         PINMUX_DATA(LCDD9_MARK, PORT201_FN1), \
 832         PINMUX_DATA(D17_MARK, PORT201_FN6),
 833         PINMUX_DATA(LCDD10_MARK, PORT202_FN1), \
 834         PINMUX_DATA(D18_MARK, PORT202_FN6),
 835         PINMUX_DATA(LCDD11_MARK, PORT203_FN1), \
 836         PINMUX_DATA(D19_MARK, PORT203_FN6),
 837         PINMUX_DATA(LCDD12_MARK, PORT204_FN1), \
 838         PINMUX_DATA(D20_MARK, PORT204_FN6),
 839         PINMUX_DATA(LCDD13_MARK, PORT205_FN1), \
 840         PINMUX_DATA(D21_MARK, PORT205_FN6),
 841         PINMUX_DATA(LCDD14_MARK, PORT206_FN1), \
 842         PINMUX_DATA(D22_MARK, PORT206_FN6),
 843         PINMUX_DATA(LCDD15_MARK, PORT207_FN1), \
 844         PINMUX_DATA(PORT207_MSIOF0L_SS1_MARK, PORT207_FN2, MSEL3CR_MSEL11_1), \
 845         PINMUX_DATA(D23_MARK, PORT207_FN6),
 846         PINMUX_DATA(LCDD16_MARK, PORT208_FN1), \
 847         PINMUX_DATA(PORT208_MSIOF0L_SS2_MARK, PORT208_FN2, MSEL3CR_MSEL11_1), \
 848         PINMUX_DATA(D24_MARK, PORT208_FN6),
 849         PINMUX_DATA(LCDD17_MARK, PORT209_FN1), \
 850         PINMUX_DATA(D25_MARK, PORT209_FN6),
 851         PINMUX_DATA(LCDD18_MARK, PORT210_FN1), \
 852         PINMUX_DATA(DREQ2_MARK, PORT210_FN2), \
 853         PINMUX_DATA(PORT210_MSIOF0L_SS1_MARK, PORT210_FN5, MSEL3CR_MSEL11_1), \
 854         PINMUX_DATA(D26_MARK, PORT210_FN6),
 855         PINMUX_DATA(LCDD19_MARK, PORT211_FN1), \
 856         PINMUX_DATA(PORT211_MSIOF0L_SS2_MARK, PORT211_FN5, MSEL3CR_MSEL11_1), \
 857         PINMUX_DATA(D27_MARK, PORT211_FN6),
 858         PINMUX_DATA(LCDD20_MARK, PORT212_FN1), \
 859         PINMUX_DATA(TS_SPSYNC1_MARK, PORT212_FN2), \
 860         PINMUX_DATA(MSIOF0L_MCK0_MARK, PORT212_FN5, MSEL3CR_MSEL11_1), \
 861         PINMUX_DATA(D28_MARK, PORT212_FN6),
 862         PINMUX_DATA(LCDD21_MARK, PORT213_FN1), \
 863         PINMUX_DATA(TS_SDAT1_MARK, PORT213_FN2), \
 864         PINMUX_DATA(MSIOF0L_MCK1_MARK, PORT213_FN5, MSEL3CR_MSEL11_1), \
 865         PINMUX_DATA(D29_MARK, PORT213_FN6),
 866         PINMUX_DATA(LCDD22_MARK, PORT214_FN1), \
 867         PINMUX_DATA(TS_SDEN1_MARK, PORT214_FN2), \
 868         PINMUX_DATA(MSIOF0L_RSCK_MARK, PORT214_FN5, MSEL3CR_MSEL11_1), \
 869         PINMUX_DATA(D30_MARK, PORT214_FN6),
 870         PINMUX_DATA(LCDD23_MARK, PORT215_FN1), \
 871         PINMUX_DATA(TS_SCK1_MARK, PORT215_FN2), \
 872         PINMUX_DATA(MSIOF0L_RSYNC_MARK, PORT215_FN5, MSEL3CR_MSEL11_1), \
 873         PINMUX_DATA(D31_MARK, PORT215_FN6),
 874         PINMUX_DATA(LCDDCK_MARK, PORT216_FN1), \
 875         PINMUX_DATA(LCDWR__MARK, PORT216_FN2),
 876         PINMUX_DATA(LCDRD__MARK, PORT217_FN1), \
 877         PINMUX_DATA(DACK2_MARK, PORT217_FN2), \
 878         PINMUX_DATA(PORT217_LCD2RS_MARK, PORT217_FN3), \
 879         PINMUX_DATA(MSIOF0L_TSYNC_MARK, PORT217_FN5, MSEL3CR_MSEL11_1), \
 880         PINMUX_DATA(VIO2_FIELD3_MARK, PORT217_FN6, MSEL4CR_MSEL27_1,
 881                 MSEL4CR_MSEL26_1), \
 882         PINMUX_DATA(PORT217_LCD2DISP_MARK, PORT217_FN7),
 883         PINMUX_DATA(LCDHSYN_MARK, PORT218_FN1), \
 884         PINMUX_DATA(LCDCS__MARK, PORT218_FN2), \
 885         PINMUX_DATA(LCDCS2__MARK, PORT218_FN3), \
 886         PINMUX_DATA(DACK3_MARK, PORT218_FN4), \
 887         PINMUX_DATA(PORT218_VIO_CKOR_MARK, PORT218_FN5),
 888         PINMUX_DATA(LCDDISP_MARK, PORT219_FN1), \
 889         PINMUX_DATA(LCDRS_MARK, PORT219_FN2), \
 890         PINMUX_DATA(PORT219_LCD2WR__MARK, PORT219_FN3), \
 891         PINMUX_DATA(DREQ3_MARK, PORT219_FN4), \
 892         PINMUX_DATA(MSIOF0L_TSCK_MARK, PORT219_FN5, MSEL3CR_MSEL11_1), \
 893         PINMUX_DATA(VIO2_CLK3_MARK, PORT219_FN6, MSEL4CR_MSEL27_1,
 894                 MSEL4CR_MSEL26_1), \
 895         PINMUX_DATA(LCD2DCK_2_MARK, PORT219_FN7),
 896         PINMUX_DATA(LCDVSYN_MARK, PORT220_FN1), \
 897         PINMUX_DATA(LCDVSYN2_MARK, PORT220_FN2),
 898         PINMUX_DATA(LCDLCLK_MARK, PORT221_FN1), \
 899         PINMUX_DATA(DREQ1_MARK, PORT221_FN2), \
 900         PINMUX_DATA(PORT221_LCD2CS__MARK, PORT221_FN3), \
 901         PINMUX_DATA(PWEN_MARK, PORT221_FN4), \
 902         PINMUX_DATA(MSIOF0L_RXD_MARK, PORT221_FN5, MSEL3CR_MSEL11_1), \
 903         PINMUX_DATA(VIO2_HD3_MARK, PORT221_FN6, MSEL4CR_MSEL27_1,
 904                 MSEL4CR_MSEL26_1), \
 905         PINMUX_DATA(PORT221_LCD2HSYN_MARK, PORT221_FN7),
 906         PINMUX_DATA(LCDDON_MARK, PORT222_FN1), \
 907         PINMUX_DATA(LCDDON2_MARK, PORT222_FN2), \
 908         PINMUX_DATA(DACK1_MARK, PORT222_FN3), \
 909         PINMUX_DATA(OVCN_MARK, PORT222_FN4), \
 910         PINMUX_DATA(MSIOF0L_TXD_MARK, PORT222_FN5, MSEL3CR_MSEL11_1), \
 911         PINMUX_DATA(VIO2_VD3_MARK, PORT222_FN6, MSEL4CR_MSEL27_1,
 912                 MSEL4CR_MSEL26_1), \
 913         PINMUX_DATA(PORT222_LCD2VSYN_MARK, PORT222_FN7, MSEL3CR_MSEL2_1),
 914
 915         PINMUX_DATA(SCIFA1_TXD_MARK, PORT225_FN2), \
 916         PINMUX_DATA(OVCN2_MARK, PORT225_FN4),
 917         PINMUX_DATA(EXTLP_MARK, PORT226_FN1), \
 918         PINMUX_DATA(SCIFA1_SCK_MARK, PORT226_FN2), \
 919         PINMUX_DATA(PORT226_VIO_CKO2_MARK, PORT226_FN5),
 920         PINMUX_DATA(SCIFA1_RTS__MARK, PORT227_FN2), \
 921         PINMUX_DATA(IDIN_MARK, PORT227_FN4),
 922         PINMUX_DATA(SCIFA1_RXD_MARK, PORT228_FN2),
 923         PINMUX_DATA(SCIFA1_CTS__MARK, PORT229_FN2), \
 924         PINMUX_DATA(MFG1_IN1_MARK, PORT229_FN3),
 925         PINMUX_DATA(MSIOF1_TXD_MARK, PORT230_FN1), \
 926         PINMUX_DATA(SCIFA2_TXD2_MARK, PORT230_FN2, MSEL3CR_MSEL9_1),
 927         PINMUX_DATA(MSIOF1_TSYNC_MARK, PORT231_FN1), \
 928         PINMUX_DATA(SCIFA2_CTS2__MARK, PORT231_FN2, MSEL3CR_MSEL9_1),
 929         PINMUX_DATA(MSIOF1_TSCK_MARK, PORT232_FN1), \
 930         PINMUX_DATA(SCIFA2_SCK2_MARK, PORT232_FN2, MSEL3CR_MSEL9_1),
 931         PINMUX_DATA(MSIOF1_RXD_MARK, PORT233_FN1), \
 932         PINMUX_DATA(SCIFA2_RXD2_MARK, PORT233_FN2, MSEL3CR_MSEL9_1),
 933         PINMUX_DATA(MSIOF1_RSCK_MARK, PORT234_FN1), \
 934         PINMUX_DATA(SCIFA2_RTS2__MARK, PORT234_FN2, MSEL3CR_MSEL9_1), \
 935         PINMUX_DATA(VIO2_CLK2_MARK, PORT234_FN6, MSEL4CR_MSEL27_1,
 936                 MSEL4CR_MSEL26_0), \
 937         PINMUX_DATA(LCD2D20_MARK, PORT234_FN7),
 938         PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT235_FN1), \
 939         PINMUX_DATA(MFG1_IN2_MARK, PORT235_FN3), \
 940         PINMUX_DATA(VIO2_VD2_MARK, PORT235_FN6, MSEL4CR_MSEL27_1,
 941                 MSEL4CR_MSEL26_0), \
 942         PINMUX_DATA(LCD2D21_MARK, PORT235_FN7),
 943         PINMUX_DATA(MSIOF1_MCK0_MARK, PORT236_FN1), \
 944         PINMUX_DATA(PORT236_I2C_SDA2_MARK, PORT236_FN2, MSEL2CR_MSEL17_0,
 945                 MSEL2CR_MSEL16_0),
 946         PINMUX_DATA(MSIOF1_MCK1_MARK, PORT237_FN1), \
 947         PINMUX_DATA(PORT237_I2C_SCL2_MARK, PORT237_FN2, MSEL2CR_MSEL17_0,
 948                 MSEL2CR_MSEL16_0),
 949         PINMUX_DATA(MSIOF1_SS1_MARK, PORT238_FN1), \
 950         PINMUX_DATA(VIO2_FIELD2_MARK, PORT238_FN6, MSEL4CR_MSEL27_1,
 951                 MSEL4CR_MSEL26_0), \
 952         PINMUX_DATA(LCD2D22_MARK, PORT238_FN7),
 953         PINMUX_DATA(MSIOF1_SS2_MARK, PORT239_FN1), \
 954         PINMUX_DATA(VIO2_HD2_MARK, PORT239_FN6, MSEL4CR_MSEL27_1,
 955                 MSEL4CR_MSEL26_0), \
 956         PINMUX_DATA(LCD2D23_MARK, PORT239_FN7),
 957         PINMUX_DATA(SCIFA6_TXD_MARK, PORT240_FN1),
 958         PINMUX_DATA(PORT241_IRDA_OUT_MARK, PORT241_FN1, MSEL4CR_MSEL19_0), \
 959         PINMUX_DATA(PORT241_IROUT_MARK, PORT241_FN2), \
 960         PINMUX_DATA(MFG4_OUT1_MARK, PORT241_FN3), \
 961         PINMUX_DATA(TPU4TO0_MARK, PORT241_FN4),
 962         PINMUX_DATA(PORT242_IRDA_IN_MARK, PORT242_FN1, MSEL4CR_MSEL19_0), \
 963         PINMUX_DATA(MFG4_IN2_MARK, PORT242_FN3),
 964         PINMUX_DATA(PORT243_IRDA_FIRSEL_MARK, PORT243_FN1, MSEL4CR_MSEL19_0), \
 965         PINMUX_DATA(PORT243_VIO_CKO2_MARK, PORT243_FN2),
 966         PINMUX_DATA(PORT244_SCIFA5_CTS__MARK, PORT244_FN1, MSEL4CR_MSEL21_0,
 967                 MSEL4CR_MSEL20_0), \
 968         PINMUX_DATA(MFG2_IN1_MARK, PORT244_FN2), \
 969         PINMUX_DATA(PORT244_SCIFB_CTS__MARK, PORT244_FN3, MSEL4CR_MSEL22_1), \
 970         PINMUX_DATA(MSIOF2R_RXD_MARK, PORT244_FN7, MSEL4CR_MSEL11_1),
 971         PINMUX_DATA(PORT245_SCIFA5_RTS__MARK, PORT245_FN1, MSEL4CR_MSEL21_0,
 972                 MSEL4CR_MSEL20_0), \
 973         PINMUX_DATA(MFG2_IN2_MARK, PORT245_FN2), \
 974         PINMUX_DATA(PORT245_SCIFB_RTS__MARK, PORT245_FN3, MSEL4CR_MSEL22_1), \
 975         PINMUX_DATA(MSIOF2R_TXD_MARK, PORT245_FN7, MSEL4CR_MSEL11_1),
 976         PINMUX_DATA(PORT246_SCIFA5_RXD_MARK, PORT246_FN1, MSEL4CR_MSEL21_0,
 977                 MSEL4CR_MSEL20_0), \
 978         PINMUX_DATA(MFG1_OUT1_MARK, PORT246_FN2), \
 979         PINMUX_DATA(PORT246_SCIFB_RXD_MARK, PORT246_FN3, MSEL4CR_MSEL22_1), \
 980         PINMUX_DATA(TPU1TO0_MARK, PORT246_FN4),
 981         PINMUX_DATA(PORT247_SCIFA5_TXD_MARK, PORT247_FN1, MSEL4CR_MSEL21_0,
 982                 MSEL4CR_MSEL20_0), \
 983         PINMUX_DATA(MFG3_OUT2_MARK, PORT247_FN2), \
 984         PINMUX_DATA(PORT247_SCIFB_TXD_MARK, PORT247_FN3, MSEL4CR_MSEL22_1), \
 985         PINMUX_DATA(TPU3TO1_MARK, PORT247_FN4),
 986         PINMUX_DATA(PORT248_SCIFA5_SCK_MARK, PORT248_FN1, MSEL4CR_MSEL21_0,
 987                 MSEL4CR_MSEL20_0), \
 988         PINMUX_DATA(MFG2_OUT1_MARK, PORT248_FN2), \
 989         PINMUX_DATA(PORT248_SCIFB_SCK_MARK, PORT248_FN3, MSEL4CR_MSEL22_1), \
 990         PINMUX_DATA(TPU2TO0_MARK, PORT248_FN4), \
 991         PINMUX_DATA(PORT248_I2C_SCL3_MARK, PORT248_FN5, MSEL2CR_MSEL19_0,
 992                 MSEL2CR_MSEL18_0), \
 993         PINMUX_DATA(MSIOF2R_TSCK_MARK, PORT248_FN7, MSEL4CR_MSEL11_1),
 994         PINMUX_DATA(PORT249_IROUT_MARK, PORT249_FN1), \
 995         PINMUX_DATA(MFG4_IN1_MARK, PORT249_FN2), \
 996         PINMUX_DATA(PORT249_I2C_SDA3_MARK, PORT249_FN5, MSEL2CR_MSEL19_0,
 997                 MSEL2CR_MSEL18_0), \
 998         PINMUX_DATA(MSIOF2R_TSYNC_MARK, PORT249_FN7, MSEL4CR_MSEL11_1),
 999         PINMUX_DATA(SDHICLK0_MARK, PORT250_FN1),
1000         PINMUX_DATA(SDHICD0_MARK, PORT251_FN1),
1001         PINMUX_DATA(SDHID0_0_MARK, PORT252_FN1),
1002         PINMUX_DATA(SDHID0_1_MARK, PORT253_FN1),
1003         PINMUX_DATA(SDHID0_2_MARK, PORT254_FN1),
1004         PINMUX_DATA(SDHID0_3_MARK, PORT255_FN1),
1005         PINMUX_DATA(SDHICMD0_MARK, PORT256_FN1),
1006         PINMUX_DATA(SDHIWP0_MARK, PORT257_FN1),
1007         PINMUX_DATA(SDHICLK1_MARK, PORT258_FN1),
1008         PINMUX_DATA(SDHID1_0_MARK, PORT259_FN1), \
1009         PINMUX_DATA(TS_SPSYNC2_MARK, PORT259_FN3),
1010         PINMUX_DATA(SDHID1_1_MARK, PORT260_FN1), \
1011         PINMUX_DATA(TS_SDAT2_MARK, PORT260_FN3),
1012         PINMUX_DATA(SDHID1_2_MARK, PORT261_FN1), \
1013         PINMUX_DATA(TS_SDEN2_MARK, PORT261_FN3),
1014         PINMUX_DATA(SDHID1_3_MARK, PORT262_FN1), \
1015         PINMUX_DATA(TS_SCK2_MARK, PORT262_FN3),
1016         PINMUX_DATA(SDHICMD1_MARK, PORT263_FN1),
1017         PINMUX_DATA(SDHICLK2_MARK, PORT264_FN1),
1018         PINMUX_DATA(SDHID2_0_MARK, PORT265_FN1), \
1019         PINMUX_DATA(TS_SPSYNC4_MARK, PORT265_FN3),
1020         PINMUX_DATA(SDHID2_1_MARK, PORT266_FN1), \
1021         PINMUX_DATA(TS_SDAT4_MARK, PORT266_FN3),
1022         PINMUX_DATA(SDHID2_2_MARK, PORT267_FN1), \
1023         PINMUX_DATA(TS_SDEN4_MARK, PORT267_FN3),
1024         PINMUX_DATA(SDHID2_3_MARK, PORT268_FN1), \
1025         PINMUX_DATA(TS_SCK4_MARK, PORT268_FN3),
1026         PINMUX_DATA(SDHICMD2_MARK, PORT269_FN1),
1027         PINMUX_DATA(MMCCLK0_MARK, PORT270_FN1, MSEL4CR_MSEL15_0),
1028         PINMUX_DATA(MMCD0_0_MARK, PORT271_FN1, MSEL4CR_MSEL15_0),
1029         PINMUX_DATA(MMCD0_1_MARK, PORT272_FN1, MSEL4CR_MSEL15_0),
1030         PINMUX_DATA(MMCD0_2_MARK, PORT273_FN1, MSEL4CR_MSEL15_0),
1031         PINMUX_DATA(MMCD0_3_MARK, PORT274_FN1, MSEL4CR_MSEL15_0),
1032         PINMUX_DATA(MMCD0_4_MARK, PORT275_FN1, MSEL4CR_MSEL15_0),
1033         PINMUX_DATA(TS_SPSYNC5_MARK, PORT275_FN3),
1034         PINMUX_DATA(MMCD0_5_MARK, PORT276_FN1, MSEL4CR_MSEL15_0),
1035         PINMUX_DATA(TS_SDAT5_MARK, PORT276_FN3),
1036         PINMUX_DATA(MMCD0_6_MARK, PORT277_FN1, MSEL4CR_MSEL15_0),
1037         PINMUX_DATA(TS_SDEN5_MARK, PORT277_FN3),
1038         PINMUX_DATA(MMCD0_7_MARK, PORT278_FN1, MSEL4CR_MSEL15_0),
1039         PINMUX_DATA(TS_SCK5_MARK, PORT278_FN3),
1040         PINMUX_DATA(MMCCMD0_MARK, PORT279_FN1, MSEL4CR_MSEL15_0),
1041         PINMUX_DATA(RESETOUTS__MARK, PORT281_FN1), \
1042         PINMUX_DATA(EXTAL2OUT_MARK, PORT281_FN2),
1043         PINMUX_DATA(MCP_WAIT__MCP_FRB_MARK, PORT288_FN1),
1044         PINMUX_DATA(MCP_CKO_MARK, PORT289_FN1), \
1045         PINMUX_DATA(MMCCLK1_MARK, PORT289_FN2, MSEL4CR_MSEL15_1),
1046         PINMUX_DATA(MCP_D15_MCP_NAF15_MARK, PORT290_FN1),
1047         PINMUX_DATA(MCP_D14_MCP_NAF14_MARK, PORT291_FN1),
1048         PINMUX_DATA(MCP_D13_MCP_NAF13_MARK, PORT292_FN1),
1049         PINMUX_DATA(MCP_D12_MCP_NAF12_MARK, PORT293_FN1),
1050         PINMUX_DATA(MCP_D11_MCP_NAF11_MARK, PORT294_FN1),
1051         PINMUX_DATA(MCP_D10_MCP_NAF10_MARK, PORT295_FN1),
1052         PINMUX_DATA(MCP_D9_MCP_NAF9_MARK, PORT296_FN1),
1053         PINMUX_DATA(MCP_D8_MCP_NAF8_MARK, PORT297_FN1), \
1054         PINMUX_DATA(MMCCMD1_MARK, PORT297_FN2, MSEL4CR_MSEL15_1),
1055         PINMUX_DATA(MCP_D7_MCP_NAF7_MARK, PORT298_FN1), \
1056         PINMUX_DATA(MMCD1_7_MARK, PORT298_FN2, MSEL4CR_MSEL15_1),
1057
1058         PINMUX_DATA(MCP_D6_MCP_NAF6_MARK, PORT299_FN1), \
1059         PINMUX_DATA(MMCD1_6_MARK, PORT299_FN2, MSEL4CR_MSEL15_1),
1060         PINMUX_DATA(MCP_D5_MCP_NAF5_MARK, PORT300_FN1), \
1061         PINMUX_DATA(MMCD1_5_MARK, PORT300_FN2, MSEL4CR_MSEL15_1),
1062         PINMUX_DATA(MCP_D4_MCP_NAF4_MARK, PORT301_FN1), \
1063         PINMUX_DATA(MMCD1_4_MARK, PORT301_FN2, MSEL4CR_MSEL15_1),
1064         PINMUX_DATA(MCP_D3_MCP_NAF3_MARK, PORT302_FN1), \
1065         PINMUX_DATA(MMCD1_3_MARK, PORT302_FN2, MSEL4CR_MSEL15_1),
1066         PINMUX_DATA(MCP_D2_MCP_NAF2_MARK, PORT303_FN1), \
1067         PINMUX_DATA(MMCD1_2_MARK, PORT303_FN2, MSEL4CR_MSEL15_1),
1068         PINMUX_DATA(MCP_D1_MCP_NAF1_MARK, PORT304_FN1), \
1069         PINMUX_DATA(MMCD1_1_MARK, PORT304_FN2, MSEL4CR_MSEL15_1),
1070         PINMUX_DATA(MCP_D0_MCP_NAF0_MARK, PORT305_FN1), \
1071         PINMUX_DATA(MMCD1_0_MARK, PORT305_FN2, MSEL4CR_MSEL15_1),
1072         PINMUX_DATA(MCP_NBRSTOUT__MARK, PORT306_FN1),
1073         PINMUX_DATA(MCP_WE0__MCP_FWE_MARK, PORT309_FN1), \
1074         PINMUX_DATA(MCP_RDWR_MCP_FWE_MARK, PORT309_FN2),
1075
1076         /* MSEL2 special cases */
1077         PINMUX_DATA(TSIF2_TS_XX1_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_0,
1078                 MSEL2CR_MSEL12_0),
1079         PINMUX_DATA(TSIF2_TS_XX2_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_0,
1080                 MSEL2CR_MSEL12_1),
1081         PINMUX_DATA(TSIF2_TS_XX3_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_1,
1082                 MSEL2CR_MSEL12_0),
1083         PINMUX_DATA(TSIF2_TS_XX4_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_1,
1084                 MSEL2CR_MSEL12_1),
1085         PINMUX_DATA(TSIF2_TS_XX5_MARK, MSEL2CR_MSEL14_1, MSEL2CR_MSEL13_0,
1086                 MSEL2CR_MSEL12_0),
1087         PINMUX_DATA(TSIF1_TS_XX1_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_0,
1088                 MSEL2CR_MSEL9_0),
1089         PINMUX_DATA(TSIF1_TS_XX2_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_0,
1090                 MSEL2CR_MSEL9_1),
1091         PINMUX_DATA(TSIF1_TS_XX3_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_1,
1092                 MSEL2CR_MSEL9_0),
1093         PINMUX_DATA(TSIF1_TS_XX4_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_1,
1094                 MSEL2CR_MSEL9_1),
1095         PINMUX_DATA(TSIF1_TS_XX5_MARK, MSEL2CR_MSEL11_1, MSEL2CR_MSEL10_0,
1096                 MSEL2CR_MSEL9_0),
1097         PINMUX_DATA(TSIF0_TS_XX1_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_0,
1098                 MSEL2CR_MSEL6_0),
1099         PINMUX_DATA(TSIF0_TS_XX2_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_0,
1100                 MSEL2CR_MSEL6_1),
1101         PINMUX_DATA(TSIF0_TS_XX3_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_1,
1102                 MSEL2CR_MSEL6_0),
1103         PINMUX_DATA(TSIF0_TS_XX4_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_1,
1104                 MSEL2CR_MSEL6_1),
1105         PINMUX_DATA(TSIF0_TS_XX5_MARK, MSEL2CR_MSEL8_1, MSEL2CR_MSEL7_0,
1106                 MSEL2CR_MSEL6_0),
1107         PINMUX_DATA(MST1_TS_XX1_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_0,
1108                 MSEL2CR_MSEL3_0),
1109         PINMUX_DATA(MST1_TS_XX2_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_0,
1110                 MSEL2CR_MSEL3_1),
1111         PINMUX_DATA(MST1_TS_XX3_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_1,
1112                 MSEL2CR_MSEL3_0),
1113         PINMUX_DATA(MST1_TS_XX4_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_1,
1114                 MSEL2CR_MSEL3_1),
1115         PINMUX_DATA(MST1_TS_XX5_MARK, MSEL2CR_MSEL5_1, MSEL2CR_MSEL4_0,
1116                 MSEL2CR_MSEL3_0),
1117         PINMUX_DATA(MST0_TS_XX1_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_0,
1118                 MSEL2CR_MSEL0_0),
1119         PINMUX_DATA(MST0_TS_XX2_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_0,
1120                 MSEL2CR_MSEL0_1),
1121         PINMUX_DATA(MST0_TS_XX3_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_1,
1122                 MSEL2CR_MSEL0_0),
1123         PINMUX_DATA(MST0_TS_XX4_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_1,
1124                 MSEL2CR_MSEL0_1),
1125         PINMUX_DATA(MST0_TS_XX5_MARK, MSEL2CR_MSEL2_1, MSEL2CR_MSEL1_0,
1126                 MSEL2CR_MSEL0_0),
1127
1128         /* MSEL3 special cases */
1129         PINMUX_DATA(SDHI0_VCCQ_MC0_ON_MARK, MSEL3CR_MSEL28_1),
1130         PINMUX_DATA(SDHI0_VCCQ_MC0_OFF_MARK, MSEL3CR_MSEL28_0),
1131         PINMUX_DATA(DEBUG_MON_VIO_MARK, MSEL3CR_MSEL15_0),
1132         PINMUX_DATA(DEBUG_MON_LCDD_MARK, MSEL3CR_MSEL15_1),
1133         PINMUX_DATA(LCDC_LCDC0_MARK, MSEL3CR_MSEL6_0),
1134         PINMUX_DATA(LCDC_LCDC1_MARK, MSEL3CR_MSEL6_1),
1135
1136         /* MSEL4 special cases */
1137         PINMUX_DATA(IRQ9_MEM_INT_MARK, MSEL4CR_MSEL29_0),
1138         PINMUX_DATA(IRQ9_MCP_INT_MARK, MSEL4CR_MSEL29_1),
1139         PINMUX_DATA(A11_MARK, MSEL4CR_MSEL13_0, MSEL4CR_MSEL12_0),
1140         PINMUX_DATA(KEYOUT8_MARK, MSEL4CR_MSEL13_0, MSEL4CR_MSEL12_1),
1141         PINMUX_DATA(TPU4TO3_MARK, MSEL4CR_MSEL13_1, MSEL4CR_MSEL12_0),
1142         PINMUX_DATA(RESETA_N_PU_ON_MARK, MSEL4CR_MSEL4_0),
1143         PINMUX_DATA(RESETA_N_PU_OFF_MARK, MSEL4CR_MSEL4_1),
1144         PINMUX_DATA(EDBGREQ_PD_MARK, MSEL4CR_MSEL1_0),
1145         PINMUX_DATA(EDBGREQ_PU_MARK, MSEL4CR_MSEL1_1),
1146 };
1147
1148 #define __I             (SH_PFC_PIN_CFG_INPUT)
1149 #define __O             (SH_PFC_PIN_CFG_OUTPUT)
1150 #define __IO            (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
1151 #define __PD            (SH_PFC_PIN_CFG_PULL_DOWN)
1152 #define __PU            (SH_PFC_PIN_CFG_PULL_UP)
1153 #define __PUD           (SH_PFC_PIN_CFG_PULL_UP_DOWN)
1154
1155 #define SH73A0_PIN_I_PD(pin)            SH_PFC_PIN_CFG(pin, __I | __PD)
1156 #define SH73A0_PIN_I_PU(pin)            SH_PFC_PIN_CFG(pin, __I | __PU)
1157 #define SH73A0_PIN_I_PU_PD(pin)         SH_PFC_PIN_CFG(pin, __I | __PUD)
1158 #define SH73A0_PIN_IO(pin)              SH_PFC_PIN_CFG(pin, __IO)
1159 #define SH73A0_PIN_IO_PD(pin)           SH_PFC_PIN_CFG(pin, __IO | __PD)
1160 #define SH73A0_PIN_IO_PU(pin)           SH_PFC_PIN_CFG(pin, __IO | __PU)
1161 #define SH73A0_PIN_IO_PU_PD(pin)        SH_PFC_PIN_CFG(pin, __IO | __PUD)
1162 #define SH73A0_PIN_O(pin)               SH_PFC_PIN_CFG(pin, __O)
1163
1164 /*
1165  * Pins not associated with a GPIO port.
1166  */
1167 enum {
1168         PORT_ASSIGN_LAST(),
1169         NOGP_ALL(),
1170 };
1171
1172 static const struct sh_pfc_pin pinmux_pins[] = {
1173         /* Table 25-1 (I/O and Pull U/D) */
1174         SH73A0_PIN_I_PD(0),
1175         SH73A0_PIN_I_PU(1),
1176         SH73A0_PIN_I_PU(2),
1177         SH73A0_PIN_I_PU(3),
1178         SH73A0_PIN_I_PU(4),
1179         SH73A0_PIN_I_PU(5),
1180         SH73A0_PIN_I_PU(6),
1181         SH73A0_PIN_I_PU(7),
1182         SH73A0_PIN_I_PU(8),
1183         SH73A0_PIN_I_PD(9),
1184         SH73A0_PIN_I_PD(10),
1185         SH73A0_PIN_I_PU_PD(11),
1186         SH73A0_PIN_IO_PU_PD(12),
1187         SH73A0_PIN_IO_PU_PD(13),
1188         SH73A0_PIN_IO_PU_PD(14),
1189         SH73A0_PIN_IO_PU_PD(15),
1190         SH73A0_PIN_IO_PD(16),
1191         SH73A0_PIN_IO_PD(17),
1192         SH73A0_PIN_IO_PU(18),
1193         SH73A0_PIN_IO_PU(19),
1194         SH73A0_PIN_O(20),
1195         SH73A0_PIN_O(21),
1196         SH73A0_PIN_O(22),
1197         SH73A0_PIN_O(23),
1198         SH73A0_PIN_O(24),
1199         SH73A0_PIN_I_PD(25),
1200         SH73A0_PIN_I_PD(26),
1201         SH73A0_PIN_IO_PU(27),
1202         SH73A0_PIN_IO_PU(28),
1203         SH73A0_PIN_IO_PD(29),
1204         SH73A0_PIN_IO_PD(30),
1205         SH73A0_PIN_IO_PU(31),
1206         SH73A0_PIN_IO_PD(32),
1207         SH73A0_PIN_I_PU_PD(33),
1208         SH73A0_PIN_IO_PD(34),
1209         SH73A0_PIN_I_PU_PD(35),
1210         SH73A0_PIN_IO_PD(36),
1211         SH73A0_PIN_IO(37),
1212         SH73A0_PIN_O(38),
1213         SH73A0_PIN_I_PU(39),
1214         SH73A0_PIN_I_PU_PD(40),
1215         SH73A0_PIN_O(41),
1216         SH73A0_PIN_IO_PD(42),
1217         SH73A0_PIN_IO_PU_PD(43),
1218         SH73A0_PIN_IO_PU_PD(44),
1219         SH73A0_PIN_IO_PD(45),
1220         SH73A0_PIN_IO_PD(46),
1221         SH73A0_PIN_IO_PD(47),
1222         SH73A0_PIN_I_PD(48),
1223         SH73A0_PIN_IO_PU_PD(49),
1224         SH73A0_PIN_IO_PD(50),
1225         SH73A0_PIN_IO_PD(51),
1226         SH73A0_PIN_O(52),
1227         SH73A0_PIN_IO_PU_PD(53),
1228         SH73A0_PIN_IO_PU_PD(54),
1229         SH73A0_PIN_IO_PD(55),
1230         SH73A0_PIN_I_PU_PD(56),
1231         SH73A0_PIN_IO(57),
1232         SH73A0_PIN_IO(58),
1233         SH73A0_PIN_IO(59),
1234         SH73A0_PIN_IO(60),
1235         SH73A0_PIN_IO(61),
1236         SH73A0_PIN_IO_PD(62),
1237         SH73A0_PIN_IO_PD(63),
1238         SH73A0_PIN_IO_PU_PD(64),
1239         SH73A0_PIN_IO_PD(65),
1240         SH73A0_PIN_IO_PU_PD(66),
1241         SH73A0_PIN_IO_PU_PD(67),
1242         SH73A0_PIN_IO_PU_PD(68),
1243         SH73A0_PIN_IO_PU_PD(69),
1244         SH73A0_PIN_IO_PU_PD(70),
1245         SH73A0_PIN_IO_PU_PD(71),
1246         SH73A0_PIN_IO_PU_PD(72),
1247         SH73A0_PIN_I_PU_PD(73),
1248         SH73A0_PIN_IO_PU(74),
1249         SH73A0_PIN_IO_PU(75),
1250         SH73A0_PIN_IO_PU(76),
1251         SH73A0_PIN_IO_PU(77),
1252         SH73A0_PIN_IO_PU(78),
1253         SH73A0_PIN_IO_PU(79),
1254         SH73A0_PIN_IO_PU(80),
1255         SH73A0_PIN_IO_PU(81),
1256         SH73A0_PIN_IO_PU(82),
1257         SH73A0_PIN_IO_PU(83),
1258         SH73A0_PIN_IO_PU(84),
1259         SH73A0_PIN_IO_PU(85),
1260         SH73A0_PIN_IO_PU(86),
1261         SH73A0_PIN_IO_PU(87),
1262         SH73A0_PIN_IO_PU(88),
1263         SH73A0_PIN_IO_PU(89),
1264         SH73A0_PIN_O(90),
1265         SH73A0_PIN_IO_PU(91),
1266         SH73A0_PIN_O(92),
1267         SH73A0_PIN_IO_PU(93),
1268         SH73A0_PIN_O(94),
1269         SH73A0_PIN_I_PU_PD(95),
1270         SH73A0_PIN_IO(96),
1271         SH73A0_PIN_IO(97),
1272         SH73A0_PIN_IO(98),
1273         SH73A0_PIN_I_PU(99),
1274         SH73A0_PIN_O(100),
1275         SH73A0_PIN_O(101),
1276         SH73A0_PIN_I_PU(102),
1277         SH73A0_PIN_IO_PD(103),
1278         SH73A0_PIN_I_PU_PD(104),
1279         SH73A0_PIN_I_PD(105),
1280         SH73A0_PIN_I_PD(106),
1281         SH73A0_PIN_I_PU_PD(107),
1282         SH73A0_PIN_I_PU_PD(108),
1283         SH73A0_PIN_IO_PD(109),
1284         SH73A0_PIN_IO_PD(110),
1285         SH73A0_PIN_IO_PU_PD(111),
1286         SH73A0_PIN_IO_PU_PD(112),
1287         SH73A0_PIN_IO_PU_PD(113),
1288         SH73A0_PIN_IO_PD(114),
1289         SH73A0_PIN_IO_PU(115),
1290         SH73A0_PIN_IO_PU(116),
1291         SH73A0_PIN_IO_PU_PD(117),
1292         SH73A0_PIN_IO_PU_PD(118),
1293         SH73A0_PIN_IO_PD(128),
1294         SH73A0_PIN_IO_PD(129),
1295         SH73A0_PIN_IO_PU_PD(130),
1296         SH73A0_PIN_IO_PD(131),
1297         SH73A0_PIN_IO_PD(132),
1298         SH73A0_PIN_IO_PD(133),
1299         SH73A0_PIN_IO_PU_PD(134),
1300         SH73A0_PIN_IO_PU_PD(135),
1301         SH73A0_PIN_IO_PU_PD(136),
1302         SH73A0_PIN_IO_PU_PD(137),
1303         SH73A0_PIN_IO_PD(138),
1304         SH73A0_PIN_IO_PD(139),
1305         SH73A0_PIN_IO_PD(140),
1306         SH73A0_PIN_IO_PD(141),
1307         SH73A0_PIN_IO_PD(142),
1308         SH73A0_PIN_IO_PD(143),
1309         SH73A0_PIN_IO_PU_PD(144),
1310         SH73A0_PIN_IO_PD(145),
1311         SH73A0_PIN_IO_PU_PD(146),
1312         SH73A0_PIN_IO_PU_PD(147),
1313         SH73A0_PIN_IO_PU_PD(148),
1314         SH73A0_PIN_IO_PU_PD(149),
1315         SH73A0_PIN_I_PU_PD(150),
1316         SH73A0_PIN_IO_PU_PD(151),
1317         SH73A0_PIN_IO_PU_PD(152),
1318         SH73A0_PIN_IO_PD(153),
1319         SH73A0_PIN_IO_PD(154),
1320         SH73A0_PIN_I_PU_PD(155),
1321         SH73A0_PIN_IO_PU_PD(156),
1322         SH73A0_PIN_I_PD(157),
1323         SH73A0_PIN_IO_PD(158),
1324         SH73A0_PIN_IO_PU_PD(159),
1325         SH73A0_PIN_IO_PU_PD(160),
1326         SH73A0_PIN_I_PU_PD(161),
1327         SH73A0_PIN_I_PU_PD(162),
1328         SH73A0_PIN_IO_PU_PD(163),
1329         SH73A0_PIN_I_PU_PD(164),
1330         SH73A0_PIN_IO_PD(192),
1331         SH73A0_PIN_IO_PU_PD(193),
1332         SH73A0_PIN_IO_PD(194),
1333         SH73A0_PIN_IO_PU_PD(195),
1334         SH73A0_PIN_IO_PD(196),
1335         SH73A0_PIN_IO_PD(197),
1336         SH73A0_PIN_IO_PD(198),
1337         SH73A0_PIN_IO_PD(199),
1338         SH73A0_PIN_IO_PU_PD(200),
1339         SH73A0_PIN_IO_PU_PD(201),
1340         SH73A0_PIN_IO_PU_PD(202),
1341         SH73A0_PIN_IO_PU_PD(203),
1342         SH73A0_PIN_IO_PU_PD(204),
1343         SH73A0_PIN_IO_PU_PD(205),
1344         SH73A0_PIN_IO_PU_PD(206),
1345         SH73A0_PIN_IO_PD(207),
1346         SH73A0_PIN_IO_PD(208),
1347         SH73A0_PIN_IO_PD(209),
1348         SH73A0_PIN_IO_PD(210),
1349         SH73A0_PIN_IO_PD(211),
1350         SH73A0_PIN_IO_PD(212),
1351         SH73A0_PIN_IO_PD(213),
1352         SH73A0_PIN_IO_PU_PD(214),
1353         SH73A0_PIN_IO_PU_PD(215),
1354         SH73A0_PIN_IO_PD(216),
1355         SH73A0_PIN_IO_PD(217),
1356         SH73A0_PIN_O(218),
1357         SH73A0_PIN_IO_PD(219),
1358         SH73A0_PIN_IO_PD(220),
1359         SH73A0_PIN_IO_PU_PD(221),
1360         SH73A0_PIN_IO_PU_PD(222),
1361         SH73A0_PIN_I_PU_PD(223),
1362         SH73A0_PIN_I_PU_PD(224),
1363         SH73A0_PIN_IO_PU_PD(225),
1364         SH73A0_PIN_O(226),
1365         SH73A0_PIN_IO_PU_PD(227),
1366         SH73A0_PIN_I_PU_PD(228),
1367         SH73A0_PIN_I_PD(229),
1368         SH73A0_PIN_IO(230),
1369         SH73A0_PIN_IO_PU_PD(231),
1370         SH73A0_PIN_IO_PU_PD(232),
1371         SH73A0_PIN_I_PU_PD(233),
1372         SH73A0_PIN_IO_PU_PD(234),
1373         SH73A0_PIN_IO_PU_PD(235),
1374         SH73A0_PIN_IO_PU_PD(236),
1375         SH73A0_PIN_IO_PD(237),
1376         SH73A0_PIN_IO_PU_PD(238),
1377         SH73A0_PIN_IO_PU_PD(239),
1378         SH73A0_PIN_IO_PU_PD(240),
1379         SH73A0_PIN_O(241),
1380         SH73A0_PIN_I_PD(242),
1381         SH73A0_PIN_IO_PU_PD(243),
1382         SH73A0_PIN_IO_PU_PD(244),
1383         SH73A0_PIN_IO_PU_PD(245),
1384         SH73A0_PIN_IO_PU_PD(246),
1385         SH73A0_PIN_IO_PU_PD(247),
1386         SH73A0_PIN_IO_PU_PD(248),
1387         SH73A0_PIN_IO_PU_PD(249),
1388         SH73A0_PIN_IO_PU_PD(250),
1389         SH73A0_PIN_IO_PU_PD(251),
1390         SH73A0_PIN_IO_PU_PD(252),
1391         SH73A0_PIN_IO_PU_PD(253),
1392         SH73A0_PIN_IO_PU_PD(254),
1393         SH73A0_PIN_IO_PU_PD(255),
1394         SH73A0_PIN_IO_PU_PD(256),
1395         SH73A0_PIN_IO_PU_PD(257),
1396         SH73A0_PIN_IO_PU_PD(258),
1397         SH73A0_PIN_IO_PU_PD(259),
1398         SH73A0_PIN_IO_PU_PD(260),
1399         SH73A0_PIN_IO_PU_PD(261),
1400         SH73A0_PIN_IO_PU_PD(262),
1401         SH73A0_PIN_IO_PU_PD(263),
1402         SH73A0_PIN_IO_PU_PD(264),
1403         SH73A0_PIN_IO_PU_PD(265),
1404         SH73A0_PIN_IO_PU_PD(266),
1405         SH73A0_PIN_IO_PU_PD(267),
1406         SH73A0_PIN_IO_PU_PD(268),
1407         SH73A0_PIN_IO_PU_PD(269),
1408         SH73A0_PIN_IO_PU_PD(270),
1409         SH73A0_PIN_IO_PU_PD(271),
1410         SH73A0_PIN_IO_PU_PD(272),
1411         SH73A0_PIN_IO_PU_PD(273),
1412         SH73A0_PIN_IO_PU_PD(274),
1413         SH73A0_PIN_IO_PU_PD(275),
1414         SH73A0_PIN_IO_PU_PD(276),
1415         SH73A0_PIN_IO_PU_PD(277),
1416         SH73A0_PIN_IO_PU_PD(278),
1417         SH73A0_PIN_IO_PU_PD(279),
1418         SH73A0_PIN_IO_PU_PD(280),
1419         SH73A0_PIN_O(281),
1420         SH73A0_PIN_O(282),
1421         SH73A0_PIN_I_PU(288),
1422         SH73A0_PIN_IO_PU_PD(289),
1423         SH73A0_PIN_IO_PU_PD(290),
1424         SH73A0_PIN_IO_PU_PD(291),
1425         SH73A0_PIN_IO_PU_PD(292),
1426         SH73A0_PIN_IO_PU_PD(293),
1427         SH73A0_PIN_IO_PU_PD(294),
1428         SH73A0_PIN_IO_PU_PD(295),
1429         SH73A0_PIN_IO_PU_PD(296),
1430         SH73A0_PIN_IO_PU_PD(297),
1431         SH73A0_PIN_IO_PU_PD(298),
1432         SH73A0_PIN_IO_PU_PD(299),
1433         SH73A0_PIN_IO_PU_PD(300),
1434         SH73A0_PIN_IO_PU_PD(301),
1435         SH73A0_PIN_IO_PU_PD(302),
1436         SH73A0_PIN_IO_PU_PD(303),
1437         SH73A0_PIN_IO_PU_PD(304),
1438         SH73A0_PIN_IO_PU_PD(305),
1439         SH73A0_PIN_O(306),
1440         SH73A0_PIN_O(307),
1441         SH73A0_PIN_I_PU(308),
1442         SH73A0_PIN_O(309),
1443
1444         /* Pins not associated with a GPIO port */
1445         PINMUX_NOGP_ALL(),
1446 };
1447
1448 /* - BSC -------------------------------------------------------------------- */
1449 static const unsigned int bsc_data_0_7_pins[] = {
1450         /* D[0:7] */
1451         74, 75, 76, 77, 78, 79, 80, 81,
1452 };
1453 static const unsigned int bsc_data_0_7_mux[] = {
1454         D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
1455         D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
1456 };
1457 static const unsigned int bsc_data_8_15_pins[] = {
1458         /* D[8:15] */
1459         82, 83, 84, 85, 86, 87, 88, 89,
1460 };
1461 static const unsigned int bsc_data_8_15_mux[] = {
1462         D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
1463         D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
1464 };
1465 static const unsigned int bsc_cs4_pins[] = {
1466         /* CS */
1467         90,
1468 };
1469 static const unsigned int bsc_cs4_mux[] = {
1470         CS4__MARK,
1471 };
1472 static const unsigned int bsc_cs5_a_pins[] = {
1473         /* CS */
1474         91,
1475 };
1476 static const unsigned int bsc_cs5_a_mux[] = {
1477         CS5A__MARK,
1478 };
1479 static const unsigned int bsc_cs5_b_pins[] = {
1480         /* CS */
1481         92,
1482 };
1483 static const unsigned int bsc_cs5_b_mux[] = {
1484         CS5B__MARK,
1485 };
1486 static const unsigned int bsc_cs6_a_pins[] = {
1487         /* CS */
1488         94,
1489 };
1490 static const unsigned int bsc_cs6_a_mux[] = {
1491         CS6A__MARK,
1492 };
1493 static const unsigned int bsc_cs6_b_pins[] = {
1494         /* CS */
1495         93,
1496 };
1497 static const unsigned int bsc_cs6_b_mux[] = {
1498         CS6B__MARK,
1499 };
1500 static const unsigned int bsc_rd_pins[] = {
1501         /* RD */
1502         96,
1503 };
1504 static const unsigned int bsc_rd_mux[] = {
1505         RD__FSC_MARK,
1506 };
1507 static const unsigned int bsc_rdwr_0_pins[] = {
1508         /* RDWR */
1509         91,
1510 };
1511 static const unsigned int bsc_rdwr_0_mux[] = {
1512         PORT91_RDWR_MARK,
1513 };
1514 static const unsigned int bsc_rdwr_1_pins[] = {
1515         /* RDWR */
1516         97,
1517 };
1518 static const unsigned int bsc_rdwr_1_mux[] = {
1519         RDWR_FWE_MARK,
1520 };
1521 static const unsigned int bsc_rdwr_2_pins[] = {
1522         /* RDWR */
1523         149,
1524 };
1525 static const unsigned int bsc_rdwr_2_mux[] = {
1526         PORT149_RDWR_MARK,
1527 };
1528 static const unsigned int bsc_we0_pins[] = {
1529         /* WE0 */
1530         97,
1531 };
1532 static const unsigned int bsc_we0_mux[] = {
1533         WE0__FWE_MARK,
1534 };
1535 static const unsigned int bsc_we1_pins[] = {
1536         /* WE1 */
1537         98,
1538 };
1539 static const unsigned int bsc_we1_mux[] = {
1540         WE1__MARK,
1541 };
1542 /* - FSIA ------------------------------------------------------------------- */
1543 static const unsigned int fsia_mclk_in_pins[] = {
1544         /* CK */
1545         49,
1546 };
1547 static const unsigned int fsia_mclk_in_mux[] = {
1548         FSIACK_MARK,
1549 };
1550 static const unsigned int fsia_mclk_out_pins[] = {
1551         /* OMC */
1552         49,
1553 };
1554 static const unsigned int fsia_mclk_out_mux[] = {
1555         FSIAOMC_MARK,
1556 };
1557 static const unsigned int fsia_sclk_in_pins[] = {
1558         /* ILR, IBT */
1559         50, 51,
1560 };
1561 static const unsigned int fsia_sclk_in_mux[] = {
1562         FSIAILR_MARK, FSIAIBT_MARK,
1563 };
1564 static const unsigned int fsia_sclk_out_pins[] = {
1565         /* OLR, OBT */
1566         50, 51,
1567 };
1568 static const unsigned int fsia_sclk_out_mux[] = {
1569         FSIAOLR_MARK, FSIAOBT_MARK,
1570 };
1571 static const unsigned int fsia_data_in_pins[] = {
1572         /* ISLD */
1573         55,
1574 };
1575 static const unsigned int fsia_data_in_mux[] = {
1576         FSIAISLD_MARK,
1577 };
1578 static const unsigned int fsia_data_out_pins[] = {
1579         /* OSLD */
1580         52,
1581 };
1582 static const unsigned int fsia_data_out_mux[] = {
1583         FSIAOSLD_MARK,
1584 };
1585 static const unsigned int fsia_spdif_pins[] = {
1586         /* SPDIF */
1587         53,
1588 };
1589 static const unsigned int fsia_spdif_mux[] = {
1590         FSIASPDIF_MARK,
1591 };
1592 /* - FSIB ------------------------------------------------------------------- */
1593 static const unsigned int fsib_mclk_in_pins[] = {
1594         /* CK */
1595         54,
1596 };
1597 static const unsigned int fsib_mclk_in_mux[] = {
1598         FSIBCK_MARK,
1599 };
1600 static const unsigned int fsib_mclk_out_pins[] = {
1601         /* OMC */
1602         54,
1603 };
1604 static const unsigned int fsib_mclk_out_mux[] = {
1605         FSIBOMC_MARK,
1606 };
1607 static const unsigned int fsib_sclk_in_pins[] = {
1608         /* ILR, IBT */
1609         37, 36,
1610 };
1611 static const unsigned int fsib_sclk_in_mux[] = {
1612         FSIBILR_MARK, FSIBIBT_MARK,
1613 };
1614 static const unsigned int fsib_sclk_out_pins[] = {
1615         /* OLR, OBT */
1616         37, 36,
1617 };
1618 static const unsigned int fsib_sclk_out_mux[] = {
1619         FSIBOLR_MARK, FSIBOBT_MARK,
1620 };
1621 static const unsigned int fsib_data_in_pins[] = {
1622         /* ISLD */
1623         39,
1624 };
1625 static const unsigned int fsib_data_in_mux[] = {
1626         FSIBISLD_MARK,
1627 };
1628 static const unsigned int fsib_data_out_pins[] = {
1629         /* OSLD */
1630         38,
1631 };
1632 static const unsigned int fsib_data_out_mux[] = {
1633         FSIBOSLD_MARK,
1634 };
1635 static const unsigned int fsib_spdif_pins[] = {
1636         /* SPDIF */
1637         53,
1638 };
1639 static const unsigned int fsib_spdif_mux[] = {
1640         FSIBSPDIF_MARK,
1641 };
1642 /* - FSIC ------------------------------------------------------------------- */
1643 static const unsigned int fsic_mclk_in_pins[] = {
1644         /* CK */
1645         54,
1646 };
1647 static const unsigned int fsic_mclk_in_mux[] = {
1648         FSICCK_MARK,
1649 };
1650 static const unsigned int fsic_mclk_out_pins[] = {
1651         /* OMC */
1652         54,
1653 };
1654 static const unsigned int fsic_mclk_out_mux[] = {
1655         FSICOMC_MARK,
1656 };
1657 static const unsigned int fsic_sclk_in_pins[] = {
1658         /* ILR, IBT */
1659         46, 45,
1660 };
1661 static const unsigned int fsic_sclk_in_mux[] = {
1662         FSICILR_MARK, FSICIBT_MARK,
1663 };
1664 static const unsigned int fsic_sclk_out_pins[] = {
1665         /* OLR, OBT */
1666         46, 45,
1667 };
1668 static const unsigned int fsic_sclk_out_mux[] = {
1669         FSICOLR_MARK, FSICOBT_MARK,
1670 };
1671 static const unsigned int fsic_data_in_pins[] = {
1672         /* ISLD */
1673         48,
1674 };
1675 static const unsigned int fsic_data_in_mux[] = {
1676         FSICISLD_MARK,
1677 };
1678 static const unsigned int fsic_data_out_pins[] = {
1679         /* OSLD, OSLDT1, OSLDT2, OSLDT3 */
1680         47, 44, 42, 16,
1681 };
1682 static const unsigned int fsic_data_out_mux[] = {
1683         FSICOSLD_MARK, FSICOSLDT1_MARK, FSICOSLDT2_MARK, FSICOSLDT3_MARK,
1684 };
1685 static const unsigned int fsic_spdif_0_pins[] = {
1686         /* SPDIF */
1687         53,
1688 };
1689 static const unsigned int fsic_spdif_0_mux[] = {
1690         PORT53_FSICSPDIF_MARK,
1691 };
1692 static const unsigned int fsic_spdif_1_pins[] = {
1693         /* SPDIF */
1694         47,
1695 };
1696 static const unsigned int fsic_spdif_1_mux[] = {
1697         PORT47_FSICSPDIF_MARK,
1698 };
1699 /* - FSID ------------------------------------------------------------------- */
1700 static const unsigned int fsid_sclk_in_pins[] = {
1701         /* ILR, IBT */
1702         46, 45,
1703 };
1704 static const unsigned int fsid_sclk_in_mux[] = {
1705         FSIDILR_MARK, FSIDIBT_MARK,
1706 };
1707 static const unsigned int fsid_sclk_out_pins[] = {
1708         /* OLR, OBT */
1709         46, 45,
1710 };
1711 static const unsigned int fsid_sclk_out_mux[] = {
1712         FSIDOLR_MARK, FSIDOBT_MARK,
1713 };
1714 static const unsigned int fsid_data_in_pins[] = {
1715         /* ISLD */
1716         48,
1717 };
1718 static const unsigned int fsid_data_in_mux[] = {
1719         FSIDISLD_MARK,
1720 };
1721 /* - I2C2 ------------------------------------------------------------------- */
1722 static const unsigned int i2c2_0_pins[] = {
1723         /* SCL, SDA */
1724         237, 236,
1725 };
1726 static const unsigned int i2c2_0_mux[] = {
1727         PORT237_I2C_SCL2_MARK, PORT236_I2C_SDA2_MARK,
1728 };
1729 static const unsigned int i2c2_1_pins[] = {
1730         /* SCL, SDA */
1731         27, 28,
1732 };
1733 static const unsigned int i2c2_1_mux[] = {
1734         PORT27_I2C_SCL2_MARK, PORT28_I2C_SDA2_MARK,
1735 };
1736 static const unsigned int i2c2_2_pins[] = {
1737         /* SCL, SDA */
1738         115, 116,
1739 };
1740 static const unsigned int i2c2_2_mux[] = {
1741         PORT115_I2C_SCL2_MARK, PORT116_I2C_SDA2_MARK,
1742 };
1743 /* - I2C3 ------------------------------------------------------------------- */
1744 static const unsigned int i2c3_0_pins[] = {
1745         /* SCL, SDA */
1746         248, 249,
1747 };
1748 static const unsigned int i2c3_0_mux[] = {
1749         PORT248_I2C_SCL3_MARK, PORT249_I2C_SDA3_MARK,
1750 };
1751 static const unsigned int i2c3_1_pins[] = {
1752         /* SCL, SDA */
1753         27, 28,
1754 };
1755 static const unsigned int i2c3_1_mux[] = {
1756         PORT27_I2C_SCL3_MARK, PORT28_I2C_SDA3_MARK,
1757 };
1758 static const unsigned int i2c3_2_pins[] = {
1759         /* SCL, SDA */
1760         115, 116,
1761 };
1762 static const unsigned int i2c3_2_mux[] = {
1763         PORT115_I2C_SCL3_MARK, PORT116_I2C_SDA3_MARK,
1764 };
1765 /* - IrDA ------------------------------------------------------------------- */
1766 static const unsigned int irda_0_pins[] = {
1767         /* OUT, IN, FIRSEL */
1768         241, 242, 243,
1769 };
1770 static const unsigned int irda_0_mux[] = {
1771         PORT241_IRDA_OUT_MARK, PORT242_IRDA_IN_MARK, PORT243_IRDA_FIRSEL_MARK,
1772 };
1773 static const unsigned int irda_1_pins[] = {
1774         /* OUT, IN, FIRSEL */
1775         49, 53, 54,
1776 };
1777 static const unsigned int irda_1_mux[] = {
1778         PORT49_IRDA_OUT_MARK, PORT53_IRDA_IN_MARK, PORT54_IRDA_FIRSEL_MARK,
1779 };
1780 /* - KEYSC ------------------------------------------------------------------ */
1781 static const unsigned int keysc_in5_pins[] = {
1782         /* KEYIN[0:4] */
1783         66, 67, 68, 69, 70,
1784 };
1785 static const unsigned int keysc_in5_mux[] = {
1786         KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
1787         KEYIN4_MARK,
1788 };
1789 static const unsigned int keysc_in6_pins[] = {
1790         /* KEYIN[0:5] */
1791         66, 67, 68, 69, 70, 71,
1792 };
1793 static const unsigned int keysc_in6_mux[] = {
1794         KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
1795         KEYIN4_MARK, KEYIN5_MARK,
1796 };
1797 static const unsigned int keysc_in7_pins[] = {
1798         /* KEYIN[0:6] */
1799         66, 67, 68, 69, 70, 71, 72,
1800 };
1801 static const unsigned int keysc_in7_mux[] = {
1802         KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
1803         KEYIN4_MARK, KEYIN5_MARK, KEYIN6_MARK,
1804 };
1805 static const unsigned int keysc_in8_pins[] = {
1806         /* KEYIN[0:7] */
1807         66, 67, 68, 69, 70, 71, 72, 73,
1808 };
1809 static const unsigned int keysc_in8_mux[] = {
1810         KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
1811         KEYIN4_MARK, KEYIN5_MARK, KEYIN6_MARK, KEYIN7_MARK,
1812 };
1813 static const unsigned int keysc_out04_pins[] = {
1814         /* KEYOUT[0:4] */
1815         65, 64, 63, 62, 61,
1816 };
1817 static const unsigned int keysc_out04_mux[] = {
1818         KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK, KEYOUT4_MARK,
1819 };
1820 static const unsigned int keysc_out5_pins[] = {
1821         /* KEYOUT5 */
1822         60,
1823 };
1824 static const unsigned int keysc_out5_mux[] = {
1825         KEYOUT5_MARK,
1826 };
1827 static const unsigned int keysc_out6_0_pins[] = {
1828         /* KEYOUT6 */
1829         59,
1830 };
1831 static const unsigned int keysc_out6_0_mux[] = {
1832         PORT59_KEYOUT6_MARK,
1833 };
1834 static const unsigned int keysc_out6_1_pins[] = {
1835         /* KEYOUT6 */
1836         131,
1837 };
1838 static const unsigned int keysc_out6_1_mux[] = {
1839         PORT131_KEYOUT6_MARK,
1840 };
1841 static const unsigned int keysc_out6_2_pins[] = {
1842         /* KEYOUT6 */
1843         143,
1844 };
1845 static const unsigned int keysc_out6_2_mux[] = {
1846         PORT143_KEYOUT6_MARK,
1847 };
1848 static const unsigned int keysc_out7_0_pins[] = {
1849         /* KEYOUT7 */
1850         58,
1851 };
1852 static const unsigned int keysc_out7_0_mux[] = {
1853         PORT58_KEYOUT7_MARK,
1854 };
1855 static const unsigned int keysc_out7_1_pins[] = {
1856         /* KEYOUT7 */
1857         132,
1858 };
1859 static const unsigned int keysc_out7_1_mux[] = {
1860         PORT132_KEYOUT7_MARK,
1861 };
1862 static const unsigned int keysc_out7_2_pins[] = {
1863         /* KEYOUT7 */
1864         144,
1865 };
1866 static const unsigned int keysc_out7_2_mux[] = {
1867         PORT144_KEYOUT7_MARK,
1868 };
1869 static const unsigned int keysc_out8_0_pins[] = {
1870         /* KEYOUT8 */
1871         PIN_A11,
1872 };
1873 static const unsigned int keysc_out8_0_mux[] = {
1874         KEYOUT8_MARK,
1875 };
1876 static const unsigned int keysc_out8_1_pins[] = {
1877         /* KEYOUT8 */
1878         136,
1879 };
1880 static const unsigned int keysc_out8_1_mux[] = {
1881         PORT136_KEYOUT8_MARK,
1882 };
1883 static const unsigned int keysc_out8_2_pins[] = {
1884         /* KEYOUT8 */
1885         138,
1886 };
1887 static const unsigned int keysc_out8_2_mux[] = {
1888         PORT138_KEYOUT8_MARK,
1889 };
1890 static const unsigned int keysc_out9_0_pins[] = {
1891         /* KEYOUT9 */
1892         137,
1893 };
1894 static const unsigned int keysc_out9_0_mux[] = {
1895         PORT137_KEYOUT9_MARK,
1896 };
1897 static const unsigned int keysc_out9_1_pins[] = {
1898         /* KEYOUT9 */
1899         139,
1900 };
1901 static const unsigned int keysc_out9_1_mux[] = {
1902         PORT139_KEYOUT9_MARK,
1903 };
1904 static const unsigned int keysc_out9_2_pins[] = {
1905         /* KEYOUT9 */
1906         149,
1907 };
1908 static const unsigned int keysc_out9_2_mux[] = {
1909         PORT149_KEYOUT9_MARK,
1910 };
1911 static const unsigned int keysc_out10_0_pins[] = {
1912         /* KEYOUT10 */
1913         132,
1914 };
1915 static const unsigned int keysc_out10_0_mux[] = {
1916         PORT132_KEYOUT10_MARK,
1917 };
1918 static const unsigned int keysc_out10_1_pins[] = {
1919         /* KEYOUT10 */
1920         142,
1921 };
1922 static const unsigned int keysc_out10_1_mux[] = {
1923         PORT142_KEYOUT10_MARK,
1924 };
1925 static const unsigned int keysc_out11_0_pins[] = {
1926         /* KEYOUT11 */
1927         131,
1928 };
1929 static const unsigned int keysc_out11_0_mux[] = {
1930         PORT131_KEYOUT11_MARK,
1931 };
1932 static const unsigned int keysc_out11_1_pins[] = {
1933         /* KEYOUT11 */
1934         143,
1935 };
1936 static const unsigned int keysc_out11_1_mux[] = {
1937         PORT143_KEYOUT11_MARK,
1938 };
1939 /* - LCD -------------------------------------------------------------------- */
1940 static const unsigned int lcd_data8_pins[] = {
1941         /* D[0:7] */
1942         192, 193, 194, 195, 196, 197, 198, 199,
1943 };
1944 static const unsigned int lcd_data8_mux[] = {
1945         LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1946         LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1947 };
1948 static const unsigned int lcd_data9_pins[] = {
1949         /* D[0:8] */
1950         192, 193, 194, 195, 196, 197, 198, 199,
1951         200,
1952 };
1953 static const unsigned int lcd_data9_mux[] = {
1954         LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1955         LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1956         LCDD8_MARK,
1957 };
1958 static const unsigned int lcd_data12_pins[] = {
1959         /* D[0:11] */
1960         192, 193, 194, 195, 196, 197, 198, 199,
1961         200, 201, 202, 203,
1962 };
1963 static const unsigned int lcd_data12_mux[] = {
1964         LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1965         LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1966         LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
1967 };
1968 static const unsigned int lcd_data16_pins[] = {
1969         /* D[0:15] */
1970         192, 193, 194, 195, 196, 197, 198, 199,
1971         200, 201, 202, 203, 204, 205, 206, 207,
1972 };
1973 static const unsigned int lcd_data16_mux[] = {
1974         LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1975         LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1976         LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
1977         LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
1978 };
1979 static const unsigned int lcd_data18_pins[] = {
1980         /* D[0:17] */
1981         192, 193, 194, 195, 196, 197, 198, 199,
1982         200, 201, 202, 203, 204, 205, 206, 207,
1983         208, 209,
1984 };
1985 static const unsigned int lcd_data18_mux[] = {
1986         LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1987         LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1988         LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
1989         LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
1990         LCDD16_MARK, LCDD17_MARK,
1991 };
1992 static const unsigned int lcd_data24_pins[] = {
1993         /* D[0:23] */
1994         192, 193, 194, 195, 196, 197, 198, 199,
1995         200, 201, 202, 203, 204, 205, 206, 207,
1996         208, 209, 210, 211, 212, 213, 214, 215
1997 };
1998 static const unsigned int lcd_data24_mux[] = {
1999         LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
2000         LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
2001         LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
2002         LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
2003         LCDD16_MARK, LCDD17_MARK, LCDD18_MARK, LCDD19_MARK,
2004         LCDD20_MARK, LCDD21_MARK, LCDD22_MARK, LCDD23_MARK,
2005 };
2006 static const unsigned int lcd_display_pins[] = {
2007         /* DON */
2008         222,
2009 };
2010 static const unsigned int lcd_display_mux[] = {
2011         LCDDON_MARK,
2012 };
2013 static const unsigned int lcd_lclk_pins[] = {
2014         /* LCLK */
2015         221,
2016 };
2017 static const unsigned int lcd_lclk_mux[] = {
2018         LCDLCLK_MARK,
2019 };
2020 static const unsigned int lcd_sync_pins[] = {
2021         /* VSYN, HSYN, DCK, DISP */
2022         220, 218, 216, 219,
2023 };
2024 static const unsigned int lcd_sync_mux[] = {
2025         LCDVSYN_MARK, LCDHSYN_MARK, LCDDCK_MARK, LCDDISP_MARK,
2026 };
2027 static const unsigned int lcd_sys_pins[] = {
2028         /* CS, WR, RD, RS */
2029         218, 216, 217, 219,
2030 };
2031 static const unsigned int lcd_sys_mux[] = {
2032         LCDCS__MARK, LCDWR__MARK, LCDRD__MARK, LCDRS_MARK,
2033 };
2034 /* - LCD2 ------------------------------------------------------------------- */
2035 static const unsigned int lcd2_data8_pins[] = {
2036         /* D[0:7] */
2037         128, 129, 142, 143, 144, 145, 138, 139,
2038 };
2039 static const unsigned int lcd2_data8_mux[] = {
2040         LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
2041         LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
2042 };
2043 static const unsigned int lcd2_data9_pins[] = {
2044         /* D[0:8] */
2045         128, 129, 142, 143, 144, 145, 138, 139,
2046         140,
2047 };
2048 static const unsigned int lcd2_data9_mux[] = {
2049         LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
2050         LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
2051         LCD2D8_MARK,
2052 };
2053 static const unsigned int lcd2_data12_pins[] = {
2054         /* D[0:11] */
2055         128, 129, 142, 143, 144, 145, 138, 139,
2056         140, 141, 130, 131,
2057 };
2058 static const unsigned int lcd2_data12_mux[] = {
2059         LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
2060         LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
2061         LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
2062 };
2063 static const unsigned int lcd2_data16_pins[] = {
2064         /* D[0:15] */
2065         128, 129, 142, 143, 144, 145, 138, 139,
2066         140, 141, 130, 131, 132, 133, 134, 135,
2067 };
2068 static const unsigned int lcd2_data16_mux[] = {
2069         LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
2070         LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
2071         LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
2072         LCD2D12_MARK, LCD2D13_MARK, LCD2D14_MARK, LCD2D15_MARK,
2073 };
2074 static const unsigned int lcd2_data18_pins[] = {
2075         /* D[0:17] */
2076         128, 129, 142, 143, 144, 145, 138, 139,
2077         140, 141, 130, 131, 132, 133, 134, 135,
2078         136, 137,
2079 };
2080 static const unsigned int lcd2_data18_mux[] = {
2081         LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
2082         LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
2083         LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
2084         LCD2D12_MARK, LCD2D13_MARK, LCD2D14_MARK, LCD2D15_MARK,
2085         LCD2D16_MARK, LCD2D17_MARK,
2086 };
2087 static const unsigned int lcd2_data24_pins[] = {
2088         /* D[0:23] */
2089         128, 129, 142, 143, 144, 145, 138, 139,
2090         140, 141, 130, 131, 132, 133, 134, 135,
2091         136, 137, 146, 147, 234, 235, 238, 239
2092 };
2093 static const unsigned int lcd2_data24_mux[] = {
2094         LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
2095         LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
2096         LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
2097         LCD2D12_MARK, LCD2D13_MARK, LCD2D14_MARK, LCD2D15_MARK,
2098         LCD2D16_MARK, LCD2D17_MARK, LCD2D18_MARK, LCD2D19_MARK,
2099         LCD2D20_MARK, LCD2D21_MARK, LCD2D22_MARK, LCD2D23_MARK,
2100 };
2101 static const unsigned int lcd2_sync_0_pins[] = {
2102         /* VSYN, HSYN, DCK, DISP */
2103         128, 129, 146, 145,
2104 };
2105 static const unsigned int lcd2_sync_0_mux[] = {
2106         PORT128_LCD2VSYN_MARK, PORT129_LCD2HSYN_MARK,
2107         LCD2DCK_MARK, PORT145_LCD2DISP_MARK,
2108 };
2109 static const unsigned int lcd2_sync_1_pins[] = {
2110         /* VSYN, HSYN, DCK, DISP */
2111         222, 221, 219, 217,
2112 };
2113 static const unsigned int lcd2_sync_1_mux[] = {
2114         PORT222_LCD2VSYN_MARK, PORT221_LCD2HSYN_MARK,
2115         LCD2DCK_2_MARK, PORT217_LCD2DISP_MARK,
2116 };
2117 static const unsigned int lcd2_sys_0_pins[] = {
2118         /* CS, WR, RD, RS */
2119         129, 146, 147, 145,
2120 };
2121 static const unsigned int lcd2_sys_0_mux[] = {
2122         PORT129_LCD2CS__MARK, PORT146_LCD2WR__MARK,
2123         LCD2RD__MARK, PORT145_LCD2RS_MARK,
2124 };
2125 static const unsigned int lcd2_sys_1_pins[] = {
2126         /* CS, WR, RD, RS */
2127         221, 219, 147, 217,
2128 };
2129 static const unsigned int lcd2_sys_1_mux[] = {
2130         PORT221_LCD2CS__MARK, PORT219_LCD2WR__MARK,
2131         LCD2RD__MARK, PORT217_LCD2RS_MARK,
2132 };
2133 /* - MMCIF ------------------------------------------------------------------ */
2134 static const unsigned int mmc0_data1_0_pins[] = {
2135         /* D[0] */
2136         271,
2137 };
2138 static const unsigned int mmc0_data1_0_mux[] = {
2139         MMCD0_0_MARK,
2140 };
2141 static const unsigned int mmc0_data4_0_pins[] = {
2142         /* D[0:3] */
2143         271, 272, 273, 274,
2144 };
2145 static const unsigned int mmc0_data4_0_mux[] = {
2146         MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
2147 };
2148 static const unsigned int mmc0_data8_0_pins[] = {
2149         /* D[0:7] */
2150         271, 272, 273, 274, 275, 276, 277, 278,
2151 };
2152 static const unsigned int mmc0_data8_0_mux[] = {
2153         MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
2154         MMCD0_4_MARK, MMCD0_5_MARK, MMCD0_6_MARK, MMCD0_7_MARK,
2155 };
2156 static const unsigned int mmc0_ctrl_0_pins[] = {
2157         /* CMD, CLK */
2158         279, 270,
2159 };
2160 static const unsigned int mmc0_ctrl_0_mux[] = {
2161         MMCCMD0_MARK, MMCCLK0_MARK,
2162 };
2163
2164 static const unsigned int mmc0_data1_1_pins[] = {
2165         /* D[0] */
2166         305,
2167 };
2168 static const unsigned int mmc0_data1_1_mux[] = {
2169         MMCD1_0_MARK,
2170 };
2171 static const unsigned int mmc0_data4_1_pins[] = {
2172         /* D[0:3] */
2173         305, 304, 303, 302,
2174 };
2175 static const unsigned int mmc0_data4_1_mux[] = {
2176         MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
2177 };
2178 static const unsigned int mmc0_data8_1_pins[] = {
2179         /* D[0:7] */
2180         305, 304, 303, 302, 301, 300, 299, 298,
2181 };
2182 static const unsigned int mmc0_data8_1_mux[] = {
2183         MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
2184         MMCD1_4_MARK, MMCD1_5_MARK, MMCD1_6_MARK, MMCD1_7_MARK,
2185 };
2186 static const unsigned int mmc0_ctrl_1_pins[] = {
2187         /* CMD, CLK */
2188         297, 289,
2189 };
2190 static const unsigned int mmc0_ctrl_1_mux[] = {
2191         MMCCMD1_MARK, MMCCLK1_MARK,
2192 };
2193 /* - MSIOF0 ----------------------------------------------------------------- */
2194 static const unsigned int msiof0_rsck_pins[] = {
2195         /* RSCK */
2196         66,
2197 };
2198 static const unsigned int msiof0_rsck_mux[] = {
2199         MSIOF0_RSCK_MARK,
2200 };
2201 static const unsigned int msiof0_tsck_pins[] = {
2202         /* TSCK */
2203         64,
2204 };
2205 static const unsigned int msiof0_tsck_mux[] = {
2206         MSIOF0_TSCK_MARK,
2207 };
2208 static const unsigned int msiof0_rsync_pins[] = {
2209         /* RSYNC */
2210         67,
2211 };
2212 static const unsigned int msiof0_rsync_mux[] = {
2213         MSIOF0_RSYNC_MARK,
2214 };
2215 static const unsigned int msiof0_tsync_pins[] = {
2216         /* TSYNC */
2217         63,
2218 };
2219 static const unsigned int msiof0_tsync_mux[] = {
2220         MSIOF0_TSYNC_MARK,
2221 };
2222 static const unsigned int msiof0_ss1_pins[] = {
2223         /* SS1 */
2224         62,
2225 };
2226 static const unsigned int msiof0_ss1_mux[] = {
2227         MSIOF0_SS1_MARK,
2228 };
2229 static const unsigned int msiof0_ss2_pins[] = {
2230         /* SS2 */
2231         71,
2232 };
2233 static const unsigned int msiof0_ss2_mux[] = {
2234         MSIOF0_SS2_MARK,
2235 };
2236 static const unsigned int msiof0_rxd_pins[] = {
2237         /* RXD */
2238         70,
2239 };
2240 static const unsigned int msiof0_rxd_mux[] = {
2241         MSIOF0_RXD_MARK,
2242 };
2243 static const unsigned int msiof0_txd_pins[] = {
2244         /* TXD */
2245         65,
2246 };
2247 static const unsigned int msiof0_txd_mux[] = {
2248         MSIOF0_TXD_MARK,
2249 };
2250 static const unsigned int msiof0_mck0_pins[] = {
2251         /* MSCK0 */
2252         68,
2253 };
2254 static const unsigned int msiof0_mck0_mux[] = {
2255         MSIOF0_MCK0_MARK,
2256 };
2257
2258 static const unsigned int msiof0_mck1_pins[] = {
2259         /* MSCK1 */
2260         69,
2261 };
2262 static const unsigned int msiof0_mck1_mux[] = {
2263         MSIOF0_MCK1_MARK,
2264 };
2265
2266 static const unsigned int msiof0l_rsck_pins[] = {
2267         /* RSCK */
2268         214,
2269 };
2270 static const unsigned int msiof0l_rsck_mux[] = {
2271         MSIOF0L_RSCK_MARK,
2272 };
2273 static const unsigned int msiof0l_tsck_pins[] = {
2274         /* TSCK */
2275         219,
2276 };
2277 static const unsigned int msiof0l_tsck_mux[] = {
2278         MSIOF0L_TSCK_MARK,
2279 };
2280 static const unsigned int msiof0l_rsync_pins[] = {
2281         /* RSYNC */
2282         215,
2283 };
2284 static const unsigned int msiof0l_rsync_mux[] = {
2285         MSIOF0L_RSYNC_MARK,
2286 };
2287 static const unsigned int msiof0l_tsync_pins[] = {
2288         /* TSYNC */
2289         217,
2290 };
2291 static const unsigned int msiof0l_tsync_mux[] = {
2292         MSIOF0L_TSYNC_MARK,
2293 };
2294 static const unsigned int msiof0l_ss1_a_pins[] = {
2295         /* SS1 */
2296         207,
2297 };
2298 static const unsigned int msiof0l_ss1_a_mux[] = {
2299         PORT207_MSIOF0L_SS1_MARK,
2300 };
2301 static const unsigned int msiof0l_ss1_b_pins[] = {
2302         /* SS1 */
2303         210,
2304 };
2305 static const unsigned int msiof0l_ss1_b_mux[] = {
2306         PORT210_MSIOF0L_SS1_MARK,
2307 };
2308 static const unsigned int msiof0l_ss2_a_pins[] = {
2309         /* SS2 */
2310         208,
2311 };
2312 static const unsigned int msiof0l_ss2_a_mux[] = {
2313         PORT208_MSIOF0L_SS2_MARK,
2314 };
2315 static const unsigned int msiof0l_ss2_b_pins[] = {
2316         /* SS2 */
2317         211,
2318 };
2319 static const unsigned int msiof0l_ss2_b_mux[] = {
2320         PORT211_MSIOF0L_SS2_MARK,
2321 };
2322 static const unsigned int msiof0l_rxd_pins[] = {
2323         /* RXD */
2324         221,
2325 };
2326 static const unsigned int msiof0l_rxd_mux[] = {
2327         MSIOF0L_RXD_MARK,
2328 };
2329 static const unsigned int msiof0l_txd_pins[] = {
2330         /* TXD */
2331         222,
2332 };
2333 static const unsigned int msiof0l_txd_mux[] = {
2334         MSIOF0L_TXD_MARK,
2335 };
2336 static const unsigned int msiof0l_mck0_pins[] = {
2337         /* MSCK0 */
2338         212,
2339 };
2340 static const unsigned int msiof0l_mck0_mux[] = {
2341         MSIOF0L_MCK0_MARK,
2342 };
2343 static const unsigned int msiof0l_mck1_pins[] = {
2344         /* MSCK1 */
2345         213,
2346 };
2347 static const unsigned int msiof0l_mck1_mux[] = {
2348         MSIOF0L_MCK1_MARK,
2349 };
2350 /* - MSIOF1 ----------------------------------------------------------------- */
2351 static const unsigned int msiof1_rsck_pins[] = {
2352         /* RSCK */
2353         234,
2354 };
2355 static const unsigned int msiof1_rsck_mux[] = {
2356         MSIOF1_RSCK_MARK,
2357 };
2358 static const unsigned int msiof1_tsck_pins[] = {
2359         /* TSCK */
2360         232,
2361 };
2362 static const unsigned int msiof1_tsck_mux[] = {
2363         MSIOF1_TSCK_MARK,
2364 };
2365 static const unsigned int msiof1_rsync_pins[] = {
2366         /* RSYNC */
2367         235,
2368 };
2369 static const unsigned int msiof1_rsync_mux[] = {
2370         MSIOF1_RSYNC_MARK,
2371 };
2372 static const unsigned int msiof1_tsync_pins[] = {
2373         /* TSYNC */
2374         231,
2375 };
2376 static const unsigned int msiof1_tsync_mux[] = {
2377         MSIOF1_TSYNC_MARK,
2378 };
2379 static const unsigned int msiof1_ss1_pins[] = {
2380         /* SS1 */
2381         238,
2382 };
2383 static const unsigned int msiof1_ss1_mux[] = {
2384         MSIOF1_SS1_MARK,
2385 };
2386 static const unsigned int msiof1_ss2_pins[] = {
2387         /* SS2 */
2388         239,
2389 };
2390 static const unsigned int msiof1_ss2_mux[] = {
2391         MSIOF1_SS2_MARK,
2392 };
2393 static const unsigned int msiof1_rxd_pins[] = {
2394         /* RXD */
2395         233,
2396 };
2397 static const unsigned int msiof1_rxd_mux[] = {
2398         MSIOF1_RXD_MARK,
2399 };
2400 static const unsigned int msiof1_txd_pins[] = {
2401         /* TXD */
2402         230,
2403 };
2404 static const unsigned int msiof1_txd_mux[] = {
2405         MSIOF1_TXD_MARK,
2406 };
2407 static const unsigned int msiof1_mck0_pins[] = {
2408         /* MSCK0 */
2409         236,
2410 };
2411 static const unsigned int msiof1_mck0_mux[] = {
2412         MSIOF1_MCK0_MARK,
2413 };
2414 static const unsigned int msiof1_mck1_pins[] = {
2415         /* MSCK1 */
2416         237,
2417 };
2418 static const unsigned int msiof1_mck1_mux[] = {
2419         MSIOF1_MCK1_MARK,
2420 };
2421 /* - MSIOF2 ----------------------------------------------------------------- */
2422 static const unsigned int msiof2_rsck_pins[] = {
2423         /* RSCK */
2424         151,
2425 };
2426 static const unsigned int msiof2_rsck_mux[] = {
2427         MSIOF2_RSCK_MARK,
2428 };
2429 static const unsigned int msiof2_tsck_pins[] = {
2430         /* TSCK */
2431         135,
2432 };
2433 static const unsigned int msiof2_tsck_mux[] = {
2434         MSIOF2_TSCK_MARK,
2435 };
2436 static const unsigned int msiof2_rsync_pins[] = {
2437         /* RSYNC */
2438         152,
2439 };
2440 static const unsigned int msiof2_rsync_mux[] = {
2441         MSIOF2_RSYNC_MARK,
2442 };
2443 static const unsigned int msiof2_tsync_pins[] = {
2444         /* TSYNC */
2445         133,
2446 };
2447 static const unsigned int msiof2_tsync_mux[] = {
2448         MSIOF2_TSYNC_MARK,
2449 };
2450 static const unsigned int msiof2_ss1_a_pins[] = {
2451         /* SS1 */
2452         131,
2453 };
2454 static const unsigned int msiof2_ss1_a_mux[] = {
2455         PORT131_MSIOF2_SS1_MARK,
2456 };
2457 static const unsigned int msiof2_ss1_b_pins[] = {
2458         /* SS1 */
2459         153,
2460 };
2461 static const unsigned int msiof2_ss1_b_mux[] = {
2462         PORT153_MSIOF2_SS1_MARK,
2463 };
2464 static const unsigned int msiof2_ss2_a_pins[] = {
2465         /* SS2 */
2466         132,
2467 };
2468 static const unsigned int msiof2_ss2_a_mux[] = {
2469         PORT132_MSIOF2_SS2_MARK,
2470 };
2471 static const unsigned int msiof2_ss2_b_pins[] = {
2472         /* SS2 */
2473         156,
2474 };
2475 static const unsigned int msiof2_ss2_b_mux[] = {
2476         PORT156_MSIOF2_SS2_MARK,
2477 };
2478 static const unsigned int msiof2_rxd_a_pins[] = {
2479         /* RXD */
2480         130,
2481 };
2482 static const unsigned int msiof2_rxd_a_mux[] = {
2483         PORT130_MSIOF2_RXD_MARK,
2484 };
2485 static const unsigned int msiof2_rxd_b_pins[] = {
2486         /* RXD */
2487         157,
2488 };
2489 static const unsigned int msiof2_rxd_b_mux[] = {
2490         PORT157_MSIOF2_RXD_MARK,
2491 };
2492 static const unsigned int msiof2_txd_pins[] = {
2493         /* TXD */
2494         134,
2495 };
2496 static const unsigned int msiof2_txd_mux[] = {
2497         MSIOF2_TXD_MARK,
2498 };
2499 static const unsigned int msiof2_mck0_pins[] = {
2500         /* MSCK0 */
2501         154,
2502 };
2503 static const unsigned int msiof2_mck0_mux[] = {
2504         MSIOF2_MCK0_MARK,
2505 };
2506 static const unsigned int msiof2_mck1_pins[] = {
2507         /* MSCK1 */
2508         155,
2509 };
2510 static const unsigned int msiof2_mck1_mux[] = {
2511         MSIOF2_MCK1_MARK,
2512 };
2513
2514 static const unsigned int msiof2r_tsck_pins[] = {
2515         /* TSCK */
2516         248,
2517 };
2518 static const unsigned int msiof2r_tsck_mux[] = {
2519         MSIOF2R_TSCK_MARK,
2520 };
2521 static const unsigned int msiof2r_tsync_pins[] = {
2522         /* TSYNC */
2523         249,
2524 };
2525 static const unsigned int msiof2r_tsync_mux[] = {
2526         MSIOF2R_TSYNC_MARK,
2527 };
2528 static const unsigned int msiof2r_rxd_pins[] = {
2529         /* RXD */
2530         244,
2531 };
2532 static const unsigned int msiof2r_rxd_mux[] = {
2533         MSIOF2R_RXD_MARK,
2534 };
2535 static const unsigned int msiof2r_txd_pins[] = {
2536         /* TXD */
2537         245,
2538 };
2539 static const unsigned int msiof2r_txd_mux[] = {
2540         MSIOF2R_TXD_MARK,
2541 };
2542 /* - MSIOF3 (Pin function name of MSIOF3 is named BBIF1) -------------------- */
2543 static const unsigned int msiof3_rsck_pins[] = {
2544         /* RSCK */
2545         115,
2546 };
2547 static const unsigned int msiof3_rsck_mux[] = {
2548         BBIF1_RSCK_MARK,
2549 };
2550 static const unsigned int msiof3_tsck_pins[] = {
2551         /* TSCK */
2552         112,
2553 };
2554 static const unsigned int msiof3_tsck_mux[] = {
2555         BBIF1_TSCK_MARK,
2556 };
2557 static const unsigned int msiof3_rsync_pins[] = {
2558         /* RSYNC */
2559         116,
2560 };
2561 static const unsigned int msiof3_rsync_mux[] = {
2562         BBIF1_RSYNC_MARK,
2563 };
2564 static const unsigned int msiof3_tsync_pins[] = {
2565         /* TSYNC */
2566         113,
2567 };
2568 static const unsigned int msiof3_tsync_mux[] = {
2569         BBIF1_TSYNC_MARK,
2570 };
2571 static const unsigned int msiof3_ss1_pins[] = {
2572         /* SS1 */
2573         117,
2574 };
2575 static const unsigned int msiof3_ss1_mux[] = {
2576         BBIF1_SS1_MARK,
2577 };
2578 static const unsigned int msiof3_ss2_pins[] = {
2579         /* SS2 */
2580         109,
2581 };
2582 static const unsigned int msiof3_ss2_mux[] = {
2583         BBIF1_SS2_MARK,
2584 };
2585 static const unsigned int msiof3_rxd_pins[] = {
2586         /* RXD */
2587         111,
2588 };
2589 static const unsigned int msiof3_rxd_mux[] = {
2590         BBIF1_RXD_MARK,
2591 };
2592 static const unsigned int msiof3_txd_pins[] = {
2593         /* TXD */
2594         114,
2595 };
2596 static const unsigned int msiof3_txd_mux[] = {
2597         BBIF1_TXD_MARK,
2598 };
2599 static const unsigned int msiof3_flow_pins[] = {
2600         /* FLOW */
2601         117,
2602 };
2603 static const unsigned int msiof3_flow_mux[] = {
2604         BBIF1_FLOW_MARK,
2605 };
2606
2607 /* - SCIFA0 ----------------------------------------------------------------- */
2608 static const unsigned int scifa0_data_pins[] = {
2609         /* RXD, TXD */
2610         43, 17,
2611 };
2612 static const unsigned int scifa0_data_mux[] = {
2613         SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
2614 };
2615 static const unsigned int scifa0_clk_pins[] = {
2616         /* SCK */
2617         16,
2618 };
2619 static const unsigned int scifa0_clk_mux[] = {
2620         SCIFA0_SCK_MARK,
2621 };
2622 static const unsigned int scifa0_ctrl_pins[] = {
2623         /* RTS, CTS */
2624         42, 44,
2625 };
2626 static const unsigned int scifa0_ctrl_mux[] = {
2627         SCIFA0_RTS__MARK, SCIFA0_CTS__MARK,
2628 };
2629 /* - SCIFA1 ----------------------------------------------------------------- */
2630 static const unsigned int scifa1_data_pins[] = {
2631         /* RXD, TXD */
2632         228, 225,
2633 };
2634 static const unsigned int scifa1_data_mux[] = {
2635         SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
2636 };
2637 static const unsigned int scifa1_clk_pins[] = {
2638         /* SCK */
2639         226,
2640 };
2641 static const unsigned int scifa1_clk_mux[] = {
2642         SCIFA1_SCK_MARK,
2643 };
2644 static const unsigned int scifa1_ctrl_pins[] = {
2645         /* RTS, CTS */
2646         227, 229,
2647 };
2648 static const unsigned int scifa1_ctrl_mux[] = {
2649         SCIFA1_RTS__MARK, SCIFA1_CTS__MARK,
2650 };
2651 /* - SCIFA2 ----------------------------------------------------------------- */
2652 static const unsigned int scifa2_data_0_pins[] = {
2653         /* RXD, TXD */
2654         155, 154,
2655 };
2656 static const unsigned int scifa2_data_0_mux[] = {
2657         SCIFA2_RXD1_MARK, SCIFA2_TXD1_MARK,
2658 };
2659 static const unsigned int scifa2_clk_0_pins[] = {
2660         /* SCK */
2661         158,
2662 };
2663 static const unsigned int scifa2_clk_0_mux[] = {
2664         SCIFA2_SCK1_MARK,
2665 };
2666 static const unsigned int scifa2_ctrl_0_pins[] = {
2667         /* RTS, CTS */
2668         156, 157,
2669 };
2670 static const unsigned int scifa2_ctrl_0_mux[] = {
2671         SCIFA2_RTS1__MARK, SCIFA2_CTS1__MARK,
2672 };
2673 static const unsigned int scifa2_data_1_pins[] = {
2674         /* RXD, TXD */
2675         233, 230,
2676 };
2677 static const unsigned int scifa2_data_1_mux[] = {
2678         SCIFA2_RXD2_MARK, SCIFA2_TXD2_MARK,
2679 };
2680 static const unsigned int scifa2_clk_1_pins[] = {
2681         /* SCK */
2682         232,
2683 };
2684 static const unsigned int scifa2_clk_1_mux[] = {
2685         SCIFA2_SCK2_MARK,
2686 };
2687 static const unsigned int scifa2_ctrl_1_pins[] = {
2688         /* RTS, CTS */
2689         234, 231,
2690 };
2691 static const unsigned int scifa2_ctrl_1_mux[] = {
2692         SCIFA2_RTS2__MARK, SCIFA2_CTS2__MARK,
2693 };
2694 /* - SCIFA3 ----------------------------------------------------------------- */
2695 static const unsigned int scifa3_data_pins[] = {
2696         /* RXD, TXD */
2697         108, 110,
2698 };
2699 static const unsigned int scifa3_data_mux[] = {
2700         SCIFA3_RXD_MARK, SCIFA3_TXD_MARK,
2701 };
2702 static const unsigned int scifa3_ctrl_pins[] = {
2703         /* RTS, CTS */
2704         109, 107,
2705 };
2706 static const unsigned int scifa3_ctrl_mux[] = {
2707         SCIFA3_RTS__MARK, SCIFA3_CTS__MARK,
2708 };
2709 /* - SCIFA4 ----------------------------------------------------------------- */
2710 static const unsigned int scifa4_data_pins[] = {
2711         /* RXD, TXD */
2712         33, 32,
2713 };
2714 static const unsigned int scifa4_data_mux[] = {
2715         SCIFA4_RXD_MARK, SCIFA4_TXD_MARK,
2716 };
2717 static const unsigned int scifa4_ctrl_pins[] = {
2718         /* RTS, CTS */
2719         34, 35,
2720 };
2721 static const unsigned int scifa4_ctrl_mux[] = {
2722         SCIFA4_RTS__MARK, SCIFA4_CTS__MARK,
2723 };
2724 /* - SCIFA5 ----------------------------------------------------------------- */
2725 static const unsigned int scifa5_data_0_pins[] = {
2726         /* RXD, TXD */
2727         246, 247,
2728 };
2729 static const unsigned int scifa5_data_0_mux[] = {
2730         PORT246_SCIFA5_RXD_MARK, PORT247_SCIFA5_TXD_MARK,
2731 };
2732 static const unsigned int scifa5_clk_0_pins[] = {
2733         /* SCK */
2734         248,
2735 };
2736 static const unsigned int scifa5_clk_0_mux[] = {
2737         PORT248_SCIFA5_SCK_MARK,
2738 };
2739 static const unsigned int scifa5_ctrl_0_pins[] = {
2740         /* RTS, CTS */
2741         245, 244,
2742 };
2743 static const unsigned int scifa5_ctrl_0_mux[] = {
2744         PORT245_SCIFA5_RTS__MARK, PORT244_SCIFA5_CTS__MARK,
2745 };
2746 static const unsigned int scifa5_data_1_pins[] = {
2747         /* RXD, TXD */
2748         195, 196,
2749 };
2750 static const unsigned int scifa5_data_1_mux[] = {
2751         PORT195_SCIFA5_RXD_MARK, PORT196_SCIFA5_TXD_MARK,
2752 };
2753 static const unsigned int scifa5_clk_1_pins[] = {
2754         /* SCK */
2755         197,
2756 };
2757 static const unsigned int scifa5_clk_1_mux[] = {
2758         PORT197_SCIFA5_SCK_MARK,
2759 };
2760 static const unsigned int scifa5_ctrl_1_pins[] = {
2761         /* RTS, CTS */
2762         194, 193,
2763 };
2764 static const unsigned int scifa5_ctrl_1_mux[] = {
2765         PORT194_SCIFA5_RTS__MARK, PORT193_SCIFA5_CTS__MARK,
2766 };
2767 static const unsigned int scifa5_data_2_pins[] = {
2768         /* RXD, TXD */
2769         162, 160,
2770 };
2771 static const unsigned int scifa5_data_2_mux[] = {
2772         PORT162_SCIFA5_RXD_MARK, PORT160_SCIFA5_TXD_MARK,
2773 };
2774 static const unsigned int scifa5_clk_2_pins[] = {
2775         /* SCK */
2776         159,
2777 };
2778 static const unsigned int scifa5_clk_2_mux[] = {
2779         PORT159_SCIFA5_SCK_MARK,
2780 };
2781 static const unsigned int scifa5_ctrl_2_pins[] = {
2782         /* RTS, CTS */
2783         163, 161,
2784 };
2785 static const unsigned int scifa5_ctrl_2_mux[] = {
2786         PORT163_SCIFA5_RTS__MARK, PORT161_SCIFA5_CTS__MARK,
2787 };
2788 /* - SCIFA6 ----------------------------------------------------------------- */
2789 static const unsigned int scifa6_pins[] = {
2790         /* TXD */
2791         240,
2792 };
2793 static const unsigned int scifa6_mux[] = {
2794         SCIFA6_TXD_MARK,
2795 };
2796 /* - SCIFA7 ----------------------------------------------------------------- */
2797 static const unsigned int scifa7_data_pins[] = {
2798         /* RXD, TXD */
2799         12, 18,
2800 };
2801 static const unsigned int scifa7_data_mux[] = {
2802         SCIFA7_RXD_MARK, SCIFA7_TXD_MARK,
2803 };
2804 static const unsigned int scifa7_ctrl_pins[] = {
2805         /* RTS, CTS */
2806         19, 13,
2807 };
2808 static const unsigned int scifa7_ctrl_mux[] = {
2809         SCIFA7_RTS__MARK, SCIFA7_CTS__MARK,
2810 };
2811 /* - SCIFB ------------------------------------------------------------------ */
2812 static const unsigned int scifb_data_0_pins[] = {
2813         /* RXD, TXD */
2814         162, 160,
2815 };
2816 static const unsigned int scifb_data_0_mux[] = {
2817         PORT162_SCIFB_RXD_MARK, PORT160_SCIFB_TXD_MARK,
2818 };
2819 static const unsigned int scifb_clk_0_pins[] = {
2820         /* SCK */
2821         159,
2822 };
2823 static const unsigned int scifb_clk_0_mux[] = {
2824         PORT159_SCIFB_SCK_MARK,
2825 };
2826 static const unsigned int scifb_ctrl_0_pins[] = {
2827         /* RTS, CTS */
2828         163, 161,
2829 };
2830 static const unsigned int scifb_ctrl_0_mux[] = {
2831         PORT163_SCIFB_RTS__MARK, PORT161_SCIFB_CTS__MARK,
2832 };
2833 static const unsigned int scifb_data_1_pins[] = {
2834         /* RXD, TXD */
2835         246, 247,
2836 };
2837 static const unsigned int scifb_data_1_mux[] = {
2838         PORT246_SCIFB_RXD_MARK, PORT247_SCIFB_TXD_MARK,
2839 };
2840 static const unsigned int scifb_clk_1_pins[] = {
2841         /* SCK */
2842         248,
2843 };
2844 static const unsigned int scifb_clk_1_mux[] = {
2845         PORT248_SCIFB_SCK_MARK,
2846 };
2847 static const unsigned int scifb_ctrl_1_pins[] = {
2848         /* RTS, CTS */
2849         245, 244,
2850 };
2851 static const unsigned int scifb_ctrl_1_mux[] = {
2852         PORT245_SCIFB_RTS__MARK, PORT244_SCIFB_CTS__MARK,
2853 };
2854 /* - SDHI0 ------------------------------------------------------------------ */
2855 static const unsigned int sdhi0_data1_pins[] = {
2856         /* D0 */
2857         252,
2858 };
2859 static const unsigned int sdhi0_data1_mux[] = {
2860         SDHID0_0_MARK,
2861 };
2862 static const unsigned int sdhi0_data4_pins[] = {
2863         /* D[0:3] */
2864         252, 253, 254, 255,
2865 };
2866 static const unsigned int sdhi0_data4_mux[] = {
2867         SDHID0_0_MARK, SDHID0_1_MARK, SDHID0_2_MARK, SDHID0_3_MARK,
2868 };
2869 static const unsigned int sdhi0_ctrl_pins[] = {
2870         /* CMD, CLK */
2871         256, 250,
2872 };
2873 static const unsigned int sdhi0_ctrl_mux[] = {
2874         SDHICMD0_MARK, SDHICLK0_MARK,
2875 };
2876 static const unsigned int sdhi0_cd_pins[] = {
2877         /* CD */
2878         251,
2879 };
2880 static const unsigned int sdhi0_cd_mux[] = {
2881         SDHICD0_MARK,
2882 };
2883 static const unsigned int sdhi0_wp_pins[] = {
2884         /* WP */
2885         257,
2886 };
2887 static const unsigned int sdhi0_wp_mux[] = {
2888         SDHIWP0_MARK,
2889 };
2890 /* - SDHI1 ------------------------------------------------------------------ */
2891 static const unsigned int sdhi1_data1_pins[] = {
2892         /* D0 */
2893         259,
2894 };
2895 static const unsigned int sdhi1_data1_mux[] = {
2896         SDHID1_0_MARK,
2897 };
2898 static const unsigned int sdhi1_data4_pins[] = {
2899         /* D[0:3] */
2900         259, 260, 261, 262,
2901 };
2902 static const unsigned int sdhi1_data4_mux[] = {
2903         SDHID1_0_MARK, SDHID1_1_MARK, SDHID1_2_MARK, SDHID1_3_MARK,
2904 };
2905 static const unsigned int sdhi1_ctrl_pins[] = {
2906         /* CMD, CLK */
2907         263, 258,
2908 };
2909 static const unsigned int sdhi1_ctrl_mux[] = {
2910         SDHICMD1_MARK, SDHICLK1_MARK,
2911 };
2912 /* - SDHI2 ------------------------------------------------------------------ */
2913 static const unsigned int sdhi2_data1_pins[] = {
2914         /* D0 */
2915         265,
2916 };
2917 static const unsigned int sdhi2_data1_mux[] = {
2918         SDHID2_0_MARK,
2919 };
2920 static const unsigned int sdhi2_data4_pins[] = {
2921         /* D[0:3] */
2922         265, 266, 267, 268,
2923 };
2924 static const unsigned int sdhi2_data4_mux[] = {
2925         SDHID2_0_MARK, SDHID2_1_MARK, SDHID2_2_MARK, SDHID2_3_MARK,
2926 };
2927 static const unsigned int sdhi2_ctrl_pins[] = {
2928         /* CMD, CLK */
2929         269, 264,
2930 };
2931 static const unsigned int sdhi2_ctrl_mux[] = {
2932         SDHICMD2_MARK, SDHICLK2_MARK,
2933 };
2934 /* - TPU0 ------------------------------------------------------------------- */
2935 static const unsigned int tpu0_to0_pins[] = {
2936         /* TO */
2937         55,
2938 };
2939 static const unsigned int tpu0_to0_mux[] = {
2940         TPU0TO0_MARK,
2941 };
2942 static const unsigned int tpu0_to1_pins[] = {
2943         /* TO */
2944         59,
2945 };
2946 static const unsigned int tpu0_to1_mux[] = {
2947         TPU0TO1_MARK,
2948 };
2949 static const unsigned int tpu0_to2_pins[] = {
2950         /* TO */
2951         140,
2952 };
2953 static const unsigned int tpu0_to2_mux[] = {
2954         TPU0TO2_MARK,
2955 };
2956 static const unsigned int tpu0_to3_pins[] = {
2957         /* TO */
2958         141,
2959 };
2960 static const unsigned int tpu0_to3_mux[] = {
2961         TPU0TO3_MARK,
2962 };
2963 /* - TPU1 ------------------------------------------------------------------- */
2964 static const unsigned int tpu1_to0_pins[] = {
2965         /* TO */
2966         246,
2967 };
2968 static const unsigned int tpu1_to0_mux[] = {
2969         TPU1TO0_MARK,
2970 };
2971 static const unsigned int tpu1_to1_0_pins[] = {
2972         /* TO */
2973         28,
2974 };
2975 static const unsigned int tpu1_to1_0_mux[] = {
2976         PORT28_TPU1TO1_MARK,
2977 };
2978 static const unsigned int tpu1_to1_1_pins[] = {
2979         /* TO */
2980         29,
2981 };
2982 static const unsigned int tpu1_to1_1_mux[] = {
2983         PORT29_TPU1TO1_MARK,
2984 };
2985 static const unsigned int tpu1_to2_pins[] = {
2986         /* TO */
2987         153,
2988 };
2989 static const unsigned int tpu1_to2_mux[] = {
2990         TPU1TO2_MARK,
2991 };
2992 static const unsigned int tpu1_to3_pins[] = {
2993         /* TO */
2994         145,
2995 };
2996 static const unsigned int tpu1_to3_mux[] = {
2997         TPU1TO3_MARK,
2998 };
2999 /* - TPU2 ------------------------------------------------------------------- */
3000 static const unsigned int tpu2_to0_pins[] = {
3001         /* TO */
3002         248,
3003 };
3004 static const unsigned int tpu2_to0_mux[] = {
3005         TPU2TO0_MARK,
3006 };
3007 static const unsigned int tpu2_to1_pins[] = {
3008         /* TO */
3009         197,
3010 };
3011 static const unsigned int tpu2_to1_mux[] = {
3012         TPU2TO1_MARK,
3013 };
3014 static const unsigned int tpu2_to2_pins[] = {
3015         /* TO */
3016         50,
3017 };
3018 static const unsigned int tpu2_to2_mux[] = {
3019         TPU2TO2_MARK,
3020 };
3021 static const unsigned int tpu2_to3_pins[] = {
3022         /* TO */
3023         51,
3024 };
3025 static const unsigned int tpu2_to3_mux[] = {
3026         TPU2TO3_MARK,
3027 };
3028 /* - TPU3 ------------------------------------------------------------------- */
3029 static const unsigned int tpu3_to0_pins[] = {
3030         /* TO */
3031         163,
3032 };
3033 static const unsigned int tpu3_to0_mux[] = {
3034         TPU3TO0_MARK,
3035 };
3036 static const unsigned int tpu3_to1_pins[] = {
3037         /* TO */
3038         247,
3039 };
3040 static const unsigned int tpu3_to1_mux[] = {
3041         TPU3TO1_MARK,
3042 };
3043 static const unsigned int tpu3_to2_pins[] = {
3044         /* TO */
3045         54,
3046 };
3047 static const unsigned int tpu3_to2_mux[] = {
3048         TPU3TO2_MARK,
3049 };
3050 static const unsigned int tpu3_to3_pins[] = {
3051         /* TO */
3052         53,
3053 };
3054 static const unsigned int tpu3_to3_mux[] = {
3055         TPU3TO3_MARK,
3056 };
3057 /* - TPU4 ------------------------------------------------------------------- */
3058 static const unsigned int tpu4_to0_pins[] = {
3059         /* TO */
3060         241,
3061 };
3062 static const unsigned int tpu4_to0_mux[] = {
3063         TPU4TO0_MARK,
3064 };
3065 static const unsigned int tpu4_to1_pins[] = {
3066         /* TO */
3067         199,
3068 };
3069 static const unsigned int tpu4_to1_mux[] = {
3070         TPU4TO1_MARK,
3071 };
3072 static const unsigned int tpu4_to2_pins[] = {
3073         /* TO */
3074         58,
3075 };
3076 static const unsigned int tpu4_to2_mux[] = {
3077         TPU4TO2_MARK,
3078 };
3079 static const unsigned int tpu4_to3_pins[] = {
3080         /* TO */
3081         PIN_A11,
3082 };
3083 static const unsigned int tpu4_to3_mux[] = {
3084         TPU4TO3_MARK,
3085 };
3086 /* - USB -------------------------------------------------------------------- */
3087 static const unsigned int usb_vbus_pins[] = {
3088         /* VBUS */
3089         0,
3090 };
3091 static const unsigned int usb_vbus_mux[] = {
3092         VBUS_0_MARK,
3093 };
3094
3095 static const struct sh_pfc_pin_group pinmux_groups[] = {
3096         SH_PFC_PIN_GROUP(bsc_data_0_7),
3097         SH_PFC_PIN_GROUP(bsc_data_8_15),
3098         SH_PFC_PIN_GROUP(bsc_cs4),
3099         SH_PFC_PIN_GROUP(bsc_cs5_a),
3100         SH_PFC_PIN_GROUP(bsc_cs5_b),
3101         SH_PFC_PIN_GROUP(bsc_cs6_a),
3102         SH_PFC_PIN_GROUP(bsc_cs6_b),
3103         SH_PFC_PIN_GROUP(bsc_rd),
3104         SH_PFC_PIN_GROUP(bsc_rdwr_0),
3105         SH_PFC_PIN_GROUP(bsc_rdwr_1),
3106         SH_PFC_PIN_GROUP(bsc_rdwr_2),
3107         SH_PFC_PIN_GROUP(bsc_we0),
3108         SH_PFC_PIN_GROUP(bsc_we1),
3109         SH_PFC_PIN_GROUP(fsia_mclk_in),
3110         SH_PFC_PIN_GROUP(fsia_mclk_out),
3111         SH_PFC_PIN_GROUP(fsia_sclk_in),
3112         SH_PFC_PIN_GROUP(fsia_sclk_out),
3113         SH_PFC_PIN_GROUP(fsia_data_in),
3114         SH_PFC_PIN_GROUP(fsia_data_out),
3115         SH_PFC_PIN_GROUP(fsia_spdif),
3116         SH_PFC_PIN_GROUP(fsib_mclk_in),
3117         SH_PFC_PIN_GROUP(fsib_mclk_out),
3118         SH_PFC_PIN_GROUP(fsib_sclk_in),
3119         SH_PFC_PIN_GROUP(fsib_sclk_out),
3120         SH_PFC_PIN_GROUP(fsib_data_in),
3121         SH_PFC_PIN_GROUP(fsib_data_out),
3122         SH_PFC_PIN_GROUP(fsib_spdif),
3123         SH_PFC_PIN_GROUP(fsic_mclk_in),
3124         SH_PFC_PIN_GROUP(fsic_mclk_out),
3125         SH_PFC_PIN_GROUP(fsic_sclk_in),
3126         SH_PFC_PIN_GROUP(fsic_sclk_out),
3127         SH_PFC_PIN_GROUP(fsic_data_in),
3128         SH_PFC_PIN_GROUP(fsic_data_out),
3129         SH_PFC_PIN_GROUP(fsic_spdif_0),
3130         SH_PFC_PIN_GROUP(fsic_spdif_1),
3131         SH_PFC_PIN_GROUP(fsid_sclk_in),
3132         SH_PFC_PIN_GROUP(fsid_sclk_out),
3133         SH_PFC_PIN_GROUP(fsid_data_in),
3134         SH_PFC_PIN_GROUP(i2c2_0),
3135         SH_PFC_PIN_GROUP(i2c2_1),
3136         SH_PFC_PIN_GROUP(i2c2_2),
3137         SH_PFC_PIN_GROUP(i2c3_0),
3138         SH_PFC_PIN_GROUP(i2c3_1),
3139         SH_PFC_PIN_GROUP(i2c3_2),
3140         SH_PFC_PIN_GROUP(irda_0),
3141         SH_PFC_PIN_GROUP(irda_1),
3142         SH_PFC_PIN_GROUP(keysc_in5),
3143         SH_PFC_PIN_GROUP(keysc_in6),
3144         SH_PFC_PIN_GROUP(keysc_in7),
3145         SH_PFC_PIN_GROUP(keysc_in8),
3146         SH_PFC_PIN_GROUP(keysc_out04),
3147         SH_PFC_PIN_GROUP(keysc_out5),
3148         SH_PFC_PIN_GROUP(keysc_out6_0),
3149         SH_PFC_PIN_GROUP(keysc_out6_1),
3150         SH_PFC_PIN_GROUP(keysc_out6_2),
3151         SH_PFC_PIN_GROUP(keysc_out7_0),
3152         SH_PFC_PIN_GROUP(keysc_out7_1),
3153         SH_PFC_PIN_GROUP(keysc_out7_2),
3154         SH_PFC_PIN_GROUP(keysc_out8_0),
3155         SH_PFC_PIN_GROUP(keysc_out8_1),
3156         SH_PFC_PIN_GROUP(keysc_out8_2),
3157         SH_PFC_PIN_GROUP(keysc_out9_0),
3158         SH_PFC_PIN_GROUP(keysc_out9_1),
3159         SH_PFC_PIN_GROUP(keysc_out9_2),
3160         SH_PFC_PIN_GROUP(keysc_out10_0),
3161         SH_PFC_PIN_GROUP(keysc_out10_1),
3162         SH_PFC_PIN_GROUP(keysc_out11_0),
3163         SH_PFC_PIN_GROUP(keysc_out11_1),
3164         SH_PFC_PIN_GROUP(lcd_data8),
3165         SH_PFC_PIN_GROUP(lcd_data9),
3166         SH_PFC_PIN_GROUP(lcd_data12),
3167         SH_PFC_PIN_GROUP(lcd_data16),
3168         SH_PFC_PIN_GROUP(lcd_data18),
3169         SH_PFC_PIN_GROUP(lcd_data24),
3170         SH_PFC_PIN_GROUP(lcd_display),
3171         SH_PFC_PIN_GROUP(lcd_lclk),
3172         SH_PFC_PIN_GROUP(lcd_sync),
3173         SH_PFC_PIN_GROUP(lcd_sys),
3174         SH_PFC_PIN_GROUP(lcd2_data8),
3175         SH_PFC_PIN_GROUP(lcd2_data9),
3176         SH_PFC_PIN_GROUP(lcd2_data12),
3177         SH_PFC_PIN_GROUP(lcd2_data16),
3178         SH_PFC_PIN_GROUP(lcd2_data18),
3179         SH_PFC_PIN_GROUP(lcd2_data24),
3180         SH_PFC_PIN_GROUP(lcd2_sync_0),
3181         SH_PFC_PIN_GROUP(lcd2_sync_1),
3182         SH_PFC_PIN_GROUP(lcd2_sys_0),
3183         SH_PFC_PIN_GROUP(lcd2_sys_1),
3184         SH_PFC_PIN_GROUP(mmc0_data1_0),
3185         SH_PFC_PIN_GROUP(mmc0_data4_0),
3186         SH_PFC_PIN_GROUP(mmc0_data8_0),
3187         SH_PFC_PIN_GROUP(mmc0_ctrl_0),
3188         SH_PFC_PIN_GROUP(mmc0_data1_1),
3189         SH_PFC_PIN_GROUP(mmc0_data4_1),
3190         SH_PFC_PIN_GROUP(mmc0_data8_1),
3191         SH_PFC_PIN_GROUP(mmc0_ctrl_1),
3192         SH_PFC_PIN_GROUP(msiof0_rsck),
3193         SH_PFC_PIN_GROUP(msiof0_tsck),
3194         SH_PFC_PIN_GROUP(msiof0_rsync),
3195         SH_PFC_PIN_GROUP(msiof0_tsync),
3196         SH_PFC_PIN_GROUP(msiof0_ss1),
3197         SH_PFC_PIN_GROUP(msiof0_ss2),
3198         SH_PFC_PIN_GROUP(msiof0_rxd),
3199         SH_PFC_PIN_GROUP(msiof0_txd),
3200         SH_PFC_PIN_GROUP(msiof0_mck0),
3201         SH_PFC_PIN_GROUP(msiof0_mck1),
3202         SH_PFC_PIN_GROUP(msiof0l_rsck),
3203         SH_PFC_PIN_GROUP(msiof0l_tsck),
3204         SH_PFC_PIN_GROUP(msiof0l_rsync),
3205         SH_PFC_PIN_GROUP(msiof0l_tsync),
3206         SH_PFC_PIN_GROUP(msiof0l_ss1_a),
3207         SH_PFC_PIN_GROUP(msiof0l_ss1_b),
3208         SH_PFC_PIN_GROUP(msiof0l_ss2_a),
3209         SH_PFC_PIN_GROUP(msiof0l_ss2_b),
3210         SH_PFC_PIN_GROUP(msiof0l_rxd),
3211         SH_PFC_PIN_GROUP(msiof0l_txd),
3212         SH_PFC_PIN_GROUP(msiof0l_mck0),
3213         SH_PFC_PIN_GROUP(msiof0l_mck1),
3214         SH_PFC_PIN_GROUP(msiof1_rsck),
3215         SH_PFC_PIN_GROUP(msiof1_tsck),
3216         SH_PFC_PIN_GROUP(msiof1_rsync),
3217         SH_PFC_PIN_GROUP(msiof1_tsync),
3218         SH_PFC_PIN_GROUP(msiof1_ss1),
3219         SH_PFC_PIN_GROUP(msiof1_ss2),
3220         SH_PFC_PIN_GROUP(msiof1_rxd),
3221         SH_PFC_PIN_GROUP(msiof1_txd),
3222         SH_PFC_PIN_GROUP(msiof1_mck0),
3223         SH_PFC_PIN_GROUP(msiof1_mck1),
3224         SH_PFC_PIN_GROUP(msiof2_rsck),
3225         SH_PFC_PIN_GROUP(msiof2_tsck),
3226         SH_PFC_PIN_GROUP(msiof2_rsync),
3227         SH_PFC_PIN_GROUP(msiof2_tsync),
3228         SH_PFC_PIN_GROUP(msiof2_ss1_a),
3229         SH_PFC_PIN_GROUP(msiof2_ss1_b),
3230         SH_PFC_PIN_GROUP(msiof2_ss2_a),
3231         SH_PFC_PIN_GROUP(msiof2_ss2_b),
3232         SH_PFC_PIN_GROUP(msiof2_rxd_a),
3233         SH_PFC_PIN_GROUP(msiof2_rxd_b),
3234         SH_PFC_PIN_GROUP(msiof2_txd),
3235         SH_PFC_PIN_GROUP(msiof2_mck0),
3236         SH_PFC_PIN_GROUP(msiof2_mck1),
3237         SH_PFC_PIN_GROUP(msiof2r_tsck),
3238         SH_PFC_PIN_GROUP(msiof2r_tsync),
3239         SH_PFC_PIN_GROUP(msiof2r_rxd),
3240         SH_PFC_PIN_GROUP(msiof2r_txd),
3241         SH_PFC_PIN_GROUP(msiof3_rsck),
3242         SH_PFC_PIN_GROUP(msiof3_tsck),
3243         SH_PFC_PIN_GROUP(msiof3_rsync),
3244         SH_PFC_PIN_GROUP(msiof3_tsync),
3245         SH_PFC_PIN_GROUP(msiof3_ss1),
3246         SH_PFC_PIN_GROUP(msiof3_ss2),
3247         SH_PFC_PIN_GROUP(msiof3_rxd),
3248         SH_PFC_PIN_GROUP(msiof3_txd),
3249         SH_PFC_PIN_GROUP(msiof3_flow),
3250         SH_PFC_PIN_GROUP(scifa0_data),
3251         SH_PFC_PIN_GROUP(scifa0_clk),
3252         SH_PFC_PIN_GROUP(scifa0_ctrl),
3253         SH_PFC_PIN_GROUP(scifa1_data),
3254         SH_PFC_PIN_GROUP(scifa1_clk),
3255         SH_PFC_PIN_GROUP(scifa1_ctrl),
3256         SH_PFC_PIN_GROUP(scifa2_data_0),
3257         SH_PFC_PIN_GROUP(scifa2_clk_0),
3258         SH_PFC_PIN_GROUP(scifa2_ctrl_0),
3259         SH_PFC_PIN_GROUP(scifa2_data_1),
3260         SH_PFC_PIN_GROUP(scifa2_clk_1),
3261         SH_PFC_PIN_GROUP(scifa2_ctrl_1),
3262         SH_PFC_PIN_GROUP(scifa3_data),
3263         SH_PFC_PIN_GROUP(scifa3_ctrl),
3264         SH_PFC_PIN_GROUP(scifa4_data),
3265         SH_PFC_PIN_GROUP(scifa4_ctrl),
3266         SH_PFC_PIN_GROUP(scifa5_data_0),
3267         SH_PFC_PIN_GROUP(scifa5_clk_0),
3268         SH_PFC_PIN_GROUP(scifa5_ctrl_0),
3269         SH_PFC_PIN_GROUP(scifa5_data_1),
3270         SH_PFC_PIN_GROUP(scifa5_clk_1),
3271         SH_PFC_PIN_GROUP(scifa5_ctrl_1),
3272         SH_PFC_PIN_GROUP(scifa5_data_2),
3273         SH_PFC_PIN_GROUP(scifa5_clk_2),
3274         SH_PFC_PIN_GROUP(scifa5_ctrl_2),
3275         SH_PFC_PIN_GROUP(scifa6),
3276         SH_PFC_PIN_GROUP(scifa7_data),
3277         SH_PFC_PIN_GROUP(scifa7_ctrl),
3278         SH_PFC_PIN_GROUP(scifb_data_0),
3279         SH_PFC_PIN_GROUP(scifb_clk_0),
3280         SH_PFC_PIN_GROUP(scifb_ctrl_0),
3281         SH_PFC_PIN_GROUP(scifb_data_1),
3282         SH_PFC_PIN_GROUP(scifb_clk_1),
3283         SH_PFC_PIN_GROUP(scifb_ctrl_1),
3284         SH_PFC_PIN_GROUP(sdhi0_data1),
3285         SH_PFC_PIN_GROUP(sdhi0_data4),
3286         SH_PFC_PIN_GROUP(sdhi0_ctrl),
3287         SH_PFC_PIN_GROUP(sdhi0_cd),
3288         SH_PFC_PIN_GROUP(sdhi0_wp),
3289         SH_PFC_PIN_GROUP(sdhi1_data1),
3290         SH_PFC_PIN_GROUP(sdhi1_data4),
3291         SH_PFC_PIN_GROUP(sdhi1_ctrl),
3292         SH_PFC_PIN_GROUP(sdhi2_data1),
3293         SH_PFC_PIN_GROUP(sdhi2_data4),
3294         SH_PFC_PIN_GROUP(sdhi2_ctrl),
3295         SH_PFC_PIN_GROUP(tpu0_to0),
3296         SH_PFC_PIN_GROUP(tpu0_to1),
3297         SH_PFC_PIN_GROUP(tpu0_to2),
3298         SH_PFC_PIN_GROUP(tpu0_to3),
3299         SH_PFC_PIN_GROUP(tpu1_to0),
3300         SH_PFC_PIN_GROUP(tpu1_to1_0),
3301         SH_PFC_PIN_GROUP(tpu1_to1_1),
3302         SH_PFC_PIN_GROUP(tpu1_to2),
3303         SH_PFC_PIN_GROUP(tpu1_to3),
3304         SH_PFC_PIN_GROUP(tpu2_to0),
3305         SH_PFC_PIN_GROUP(tpu2_to1),
3306         SH_PFC_PIN_GROUP(tpu2_to2),
3307         SH_PFC_PIN_GROUP(tpu2_to3),
3308         SH_PFC_PIN_GROUP(tpu3_to0),
3309         SH_PFC_PIN_GROUP(tpu3_to1),
3310         SH_PFC_PIN_GROUP(tpu3_to2),
3311         SH_PFC_PIN_GROUP(tpu3_to3),
3312         SH_PFC_PIN_GROUP(tpu4_to0),
3313         SH_PFC_PIN_GROUP(tpu4_to1),
3314         SH_PFC_PIN_GROUP(tpu4_to2),
3315         SH_PFC_PIN_GROUP(tpu4_to3),
3316         SH_PFC_PIN_GROUP(usb_vbus),
3317 };
3318
3319 static const char * const bsc_groups[] = {
3320         "bsc_data_0_7",
3321         "bsc_data_8_15",
3322         "bsc_cs4",
3323         "bsc_cs5_a",
3324         "bsc_cs5_b",
3325         "bsc_cs6_a",
3326         "bsc_cs6_b",
3327         "bsc_rd",
3328         "bsc_rdwr_0",
3329         "bsc_rdwr_1",
3330         "bsc_rdwr_2",
3331         "bsc_we0",
3332         "bsc_we1",
3333 };
3334
3335 static const char * const fsia_groups[] = {
3336         "fsia_mclk_in",
3337         "fsia_mclk_out",
3338         "fsia_sclk_in",
3339         "fsia_sclk_out",
3340         "fsia_data_in",
3341         "fsia_data_out",
3342         "fsia_spdif",
3343 };
3344
3345 static const char * const fsib_groups[] = {
3346         "fsib_mclk_in",
3347         "fsib_mclk_out",
3348         "fsib_sclk_in",
3349         "fsib_sclk_out",
3350         "fsib_data_in",
3351         "fsib_data_out",
3352         "fsib_spdif",
3353 };
3354
3355 static const char * const fsic_groups[] = {
3356         "fsic_mclk_in",
3357         "fsic_mclk_out",
3358         "fsic_sclk_in",
3359         "fsic_sclk_out",
3360         "fsic_data_in",
3361         "fsic_data_out",
3362         "fsic_spdif_0",
3363         "fsic_spdif_1",
3364 };
3365
3366 static const char * const fsid_groups[] = {
3367         "fsid_sclk_in",
3368         "fsid_sclk_out",
3369         "fsid_data_in",
3370 };
3371
3372 static const char * const i2c2_groups[] = {
3373         "i2c2_0",
3374         "i2c2_1",
3375         "i2c2_2",
3376 };
3377
3378 static const char * const i2c3_groups[] = {
3379         "i2c3_0",
3380         "i2c3_1",
3381         "i2c3_2",
3382 };
3383
3384 static const char * const irda_groups[] = {
3385         "irda_0",
3386         "irda_1",
3387 };
3388
3389 static const char * const keysc_groups[] = {
3390         "keysc_in5",
3391         "keysc_in6",
3392         "keysc_in7",
3393         "keysc_in8",
3394         "keysc_out04",
3395         "keysc_out5",
3396         "keysc_out6_0",
3397         "keysc_out6_1",
3398         "keysc_out6_2",
3399         "keysc_out7_0",
3400         "keysc_out7_1",
3401         "keysc_out7_2",
3402         "keysc_out8_0",
3403         "keysc_out8_1",
3404         "keysc_out8_2",
3405         "keysc_out9_0",
3406         "keysc_out9_1",
3407         "keysc_out9_2",
3408         "keysc_out10_0",
3409         "keysc_out10_1",
3410         "keysc_out11_0",
3411         "keysc_out11_1",
3412 };
3413
3414 static const char * const lcd_groups[] = {
3415         "lcd_data8",
3416         "lcd_data9",
3417         "lcd_data12",
3418         "lcd_data16",
3419         "lcd_data18",
3420         "lcd_data24",
3421         "lcd_display",
3422         "lcd_lclk",
3423         "lcd_sync",
3424         "lcd_sys",
3425 };
3426
3427 static const char * const lcd2_groups[] = {
3428         "lcd2_data8",
3429         "lcd2_data9",
3430         "lcd2_data12",
3431         "lcd2_data16",
3432         "lcd2_data18",
3433         "lcd2_data24",
3434         "lcd2_sync_0",
3435         "lcd2_sync_1",
3436         "lcd2_sys_0",
3437         "lcd2_sys_1",
3438 };
3439
3440 static const char * const mmc0_groups[] = {
3441         "mmc0_data1_0",
3442         "mmc0_data4_0",
3443         "mmc0_data8_0",
3444         "mmc0_ctrl_0",
3445         "mmc0_data1_1",
3446         "mmc0_data4_1",
3447         "mmc0_data8_1",
3448         "mmc0_ctrl_1",
3449 };
3450
3451 static const char * const msiof0_groups[] = {
3452         "msiof0_rsck",
3453         "msiof0_tsck",
3454         "msiof0_rsync",
3455         "msiof0_tsync",
3456         "msiof0_ss1",
3457         "msiof0_ss2",
3458         "msiof0_rxd",
3459         "msiof0_txd",
3460         "msiof0_mck0",
3461         "msiof0_mck1",
3462         "msiof0l_rsck",
3463         "msiof0l_tsck",
3464         "msiof0l_rsync",
3465         "msiof0l_tsync",
3466         "msiof0l_ss1_a",
3467         "msiof0l_ss1_b",
3468         "msiof0l_ss2_a",
3469         "msiof0l_ss2_b",
3470         "msiof0l_rxd",
3471         "msiof0l_txd",
3472         "msiof0l_mck0",
3473         "msiof0l_mck1",
3474 };
3475
3476 static const char * const msiof1_groups[] = {
3477         "msiof1_rsck",
3478         "msiof1_tsck",
3479         "msiof1_rsync",
3480         "msiof1_tsync",
3481         "msiof1_ss1",
3482         "msiof1_ss2",
3483         "msiof1_rxd",
3484         "msiof1_txd",
3485         "msiof1_mck0",
3486         "msiof1_mck1",
3487 };
3488
3489 static const char * const msiof2_groups[] = {
3490         "msiof2_rsck",
3491         "msiof2_tsck",
3492         "msiof2_rsync",
3493         "msiof2_tsync",
3494         "msiof2_ss1_a",
3495         "msiof2_ss1_b",
3496         "msiof2_ss2_a",
3497         "msiof2_ss2_b",
3498         "msiof2_rxd_a",
3499         "msiof2_rxd_b",
3500         "msiof2_txd",
3501         "msiof2_mck0",
3502         "msiof2_mck1",
3503         "msiof2r_tsck",
3504         "msiof2r_tsync",
3505         "msiof2r_rxd",
3506         "msiof2r_txd",
3507 };
3508
3509 static const char * const msiof3_groups[] = {
3510         "msiof3_rsck",
3511         "msiof3_tsck",
3512         "msiof3_rsync",
3513         "msiof3_tsync",
3514         "msiof3_ss1",
3515         "msiof3_ss2",
3516         "msiof3_rxd",
3517         "msiof3_txd",
3518         "msiof3_flow",
3519 };
3520
3521 static const char * const scifa0_groups[] = {
3522         "scifa0_data",
3523         "scifa0_clk",
3524         "scifa0_ctrl",
3525 };
3526
3527 static const char * const scifa1_groups[] = {
3528         "scifa1_data",
3529         "scifa1_clk",
3530         "scifa1_ctrl",
3531 };
3532
3533 static const char * const scifa2_groups[] = {
3534         "scifa2_data_0",
3535         "scifa2_clk_0",
3536         "scifa2_ctrl_0",
3537         "scifa2_data_1",
3538         "scifa2_clk_1",
3539         "scifa2_ctrl_1",
3540 };
3541
3542 static const char * const scifa3_groups[] = {
3543         "scifa3_data",
3544         "scifa3_ctrl",
3545 };
3546
3547 static const char * const scifa4_groups[] = {
3548         "scifa4_data",
3549         "scifa4_ctrl",
3550 };
3551
3552 static const char * const scifa5_groups[] = {
3553         "scifa5_data_0",
3554         "scifa5_clk_0",
3555         "scifa5_ctrl_0",
3556         "scifa5_data_1",
3557         "scifa5_clk_1",
3558         "scifa5_ctrl_1",
3559         "scifa5_data_2",
3560         "scifa5_clk_2",
3561         "scifa5_ctrl_2",
3562 };
3563
3564 static const char * const scifa6_groups[] = {
3565         "scifa6",
3566 };
3567
3568 static const char * const scifa7_groups[] = {
3569         "scifa7_data",
3570         "scifa7_ctrl",
3571 };
3572
3573 static const char * const scifb_groups[] = {
3574         "scifb_data_0",
3575         "scifb_clk_0",
3576         "scifb_ctrl_0",
3577         "scifb_data_1",
3578         "scifb_clk_1",
3579         "scifb_ctrl_1",
3580 };
3581
3582 static const char * const sdhi0_groups[] = {
3583         "sdhi0_data1",
3584         "sdhi0_data4",
3585         "sdhi0_ctrl",
3586         "sdhi0_cd",
3587         "sdhi0_wp",
3588 };
3589
3590 static const char * const sdhi1_groups[] = {
3591         "sdhi1_data1",
3592         "sdhi1_data4",
3593         "sdhi1_ctrl",
3594 };
3595
3596 static const char * const sdhi2_groups[] = {
3597         "sdhi2_data1",
3598         "sdhi2_data4",
3599         "sdhi2_ctrl",
3600 };
3601
3602 static const char * const usb_groups[] = {
3603         "usb_vbus",
3604 };
3605
3606 static const char * const tpu0_groups[] = {
3607         "tpu0_to0",
3608         "tpu0_to1",
3609         "tpu0_to2",
3610         "tpu0_to3",
3611 };
3612
3613 static const char * const tpu1_groups[] = {
3614         "tpu1_to0",
3615         "tpu1_to1_0",
3616         "tpu1_to1_1",
3617         "tpu1_to2",
3618         "tpu1_to3",
3619 };
3620
3621 static const char * const tpu2_groups[] = {
3622         "tpu2_to0",
3623         "tpu2_to1",
3624         "tpu2_to2",
3625         "tpu2_to3",
3626 };
3627
3628 static const char * const tpu3_groups[] = {
3629         "tpu3_to0",
3630         "tpu3_to1",
3631         "tpu3_to2",
3632         "tpu3_to3",
3633 };
3634
3635 static const char * const tpu4_groups[] = {
3636         "tpu4_to0",
3637         "tpu4_to1",
3638         "tpu4_to2",
3639         "tpu4_to3",
3640 };
3641
3642 static const struct sh_pfc_function pinmux_functions[] = {
3643         SH_PFC_FUNCTION(bsc),
3644         SH_PFC_FUNCTION(fsia),
3645         SH_PFC_FUNCTION(fsib),
3646         SH_PFC_FUNCTION(fsic),
3647         SH_PFC_FUNCTION(fsid),
3648         SH_PFC_FUNCTION(i2c2),
3649         SH_PFC_FUNCTION(i2c3),
3650         SH_PFC_FUNCTION(irda),
3651         SH_PFC_FUNCTION(keysc),
3652         SH_PFC_FUNCTION(lcd),
3653         SH_PFC_FUNCTION(lcd2),
3654         SH_PFC_FUNCTION(mmc0),
3655         SH_PFC_FUNCTION(msiof0),
3656         SH_PFC_FUNCTION(msiof1),
3657         SH_PFC_FUNCTION(msiof2),
3658         SH_PFC_FUNCTION(msiof3),
3659         SH_PFC_FUNCTION(scifa0),
3660         SH_PFC_FUNCTION(scifa1),
3661         SH_PFC_FUNCTION(scifa2),
3662         SH_PFC_FUNCTION(scifa3),
3663         SH_PFC_FUNCTION(scifa4),
3664         SH_PFC_FUNCTION(scifa5),
3665         SH_PFC_FUNCTION(scifa6),
3666         SH_PFC_FUNCTION(scifa7),
3667         SH_PFC_FUNCTION(scifb),
3668         SH_PFC_FUNCTION(sdhi0),
3669         SH_PFC_FUNCTION(sdhi1),
3670         SH_PFC_FUNCTION(sdhi2),
3671         SH_PFC_FUNCTION(tpu0),
3672         SH_PFC_FUNCTION(tpu1),
3673         SH_PFC_FUNCTION(tpu2),
3674         SH_PFC_FUNCTION(tpu3),
3675         SH_PFC_FUNCTION(tpu4),
3676         SH_PFC_FUNCTION(usb),
3677 };
3678
3679 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3680         PORTCR(0, 0xe6050000), /* PORT0CR */
3681         PORTCR(1, 0xe6050001), /* PORT1CR */
3682         PORTCR(2, 0xe6050002), /* PORT2CR */
3683         PORTCR(3, 0xe6050003), /* PORT3CR */
3684         PORTCR(4, 0xe6050004), /* PORT4CR */
3685         PORTCR(5, 0xe6050005), /* PORT5CR */
3686         PORTCR(6, 0xe6050006), /* PORT6CR */
3687         PORTCR(7, 0xe6050007), /* PORT7CR */
3688         PORTCR(8, 0xe6050008), /* PORT8CR */
3689         PORTCR(9, 0xe6050009), /* PORT9CR */
3690
3691         PORTCR(10, 0xe605000a), /* PORT10CR */
3692         PORTCR(11, 0xe605000b), /* PORT11CR */
3693         PORTCR(12, 0xe605000c), /* PORT12CR */
3694         PORTCR(13, 0xe605000d), /* PORT13CR */
3695         PORTCR(14, 0xe605000e), /* PORT14CR */
3696         PORTCR(15, 0xe605000f), /* PORT15CR */
3697         PORTCR(16, 0xe6050010), /* PORT16CR */
3698         PORTCR(17, 0xe6050011), /* PORT17CR */
3699         PORTCR(18, 0xe6050012), /* PORT18CR */
3700         PORTCR(19, 0xe6050013), /* PORT19CR */
3701
3702         PORTCR(20, 0xe6050014), /* PORT20CR */
3703         PORTCR(21, 0xe6050015), /* PORT21CR */
3704         PORTCR(22, 0xe6050016), /* PORT22CR */
3705         PORTCR(23, 0xe6050017), /* PORT23CR */
3706         PORTCR(24, 0xe6050018), /* PORT24CR */
3707         PORTCR(25, 0xe6050019), /* PORT25CR */
3708         PORTCR(26, 0xe605001a), /* PORT26CR */
3709         PORTCR(27, 0xe605001b), /* PORT27CR */
3710         PORTCR(28, 0xe605001c), /* PORT28CR */
3711         PORTCR(29, 0xe605001d), /* PORT29CR */
3712
3713         PORTCR(30, 0xe605001e), /* PORT30CR */
3714         PORTCR(31, 0xe605001f), /* PORT31CR */
3715         PORTCR(32, 0xe6051020), /* PORT32CR */
3716         PORTCR(33, 0xe6051021), /* PORT33CR */
3717         PORTCR(34, 0xe6051022), /* PORT34CR */
3718         PORTCR(35, 0xe6051023), /* PORT35CR */
3719         PORTCR(36, 0xe6051024), /* PORT36CR */
3720         PORTCR(37, 0xe6051025), /* PORT37CR */
3721         PORTCR(38, 0xe6051026), /* PORT38CR */
3722         PORTCR(39, 0xe6051027), /* PORT39CR */
3723
3724         PORTCR(40, 0xe6051028), /* PORT40CR */
3725         PORTCR(41, 0xe6051029), /* PORT41CR */
3726         PORTCR(42, 0xe605102a), /* PORT42CR */
3727         PORTCR(43, 0xe605102b), /* PORT43CR */
3728         PORTCR(44, 0xe605102c), /* PORT44CR */
3729         PORTCR(45, 0xe605102d), /* PORT45CR */
3730         PORTCR(46, 0xe605102e), /* PORT46CR */
3731         PORTCR(47, 0xe605102f), /* PORT47CR */
3732         PORTCR(48, 0xe6051030), /* PORT48CR */
3733         PORTCR(49, 0xe6051031), /* PORT49CR */
3734
3735         PORTCR(50, 0xe6051032), /* PORT50CR */
3736         PORTCR(51, 0xe6051033), /* PORT51CR */
3737         PORTCR(52, 0xe6051034), /* PORT52CR */
3738         PORTCR(53, 0xe6051035), /* PORT53CR */
3739         PORTCR(54, 0xe6051036), /* PORT54CR */
3740         PORTCR(55, 0xe6051037), /* PORT55CR */
3741         PORTCR(56, 0xe6051038), /* PORT56CR */
3742         PORTCR(57, 0xe6051039), /* PORT57CR */
3743         PORTCR(58, 0xe605103a), /* PORT58CR */
3744         PORTCR(59, 0xe605103b), /* PORT59CR */
3745
3746         PORTCR(60, 0xe605103c), /* PORT60CR */
3747         PORTCR(61, 0xe605103d), /* PORT61CR */
3748         PORTCR(62, 0xe605103e), /* PORT62CR */
3749         PORTCR(63, 0xe605103f), /* PORT63CR */
3750         PORTCR(64, 0xe6051040), /* PORT64CR */
3751         PORTCR(65, 0xe6051041), /* PORT65CR */
3752         PORTCR(66, 0xe6051042), /* PORT66CR */
3753         PORTCR(67, 0xe6051043), /* PORT67CR */
3754         PORTCR(68, 0xe6051044), /* PORT68CR */
3755         PORTCR(69, 0xe6051045), /* PORT69CR */
3756
3757         PORTCR(70, 0xe6051046), /* PORT70CR */
3758         PORTCR(71, 0xe6051047), /* PORT71CR */
3759         PORTCR(72, 0xe6051048), /* PORT72CR */
3760         PORTCR(73, 0xe6051049), /* PORT73CR */
3761         PORTCR(74, 0xe605104a), /* PORT74CR */
3762         PORTCR(75, 0xe605104b), /* PORT75CR */
3763         PORTCR(76, 0xe605104c), /* PORT76CR */
3764         PORTCR(77, 0xe605104d), /* PORT77CR */
3765         PORTCR(78, 0xe605104e), /* PORT78CR */
3766         PORTCR(79, 0xe605104f), /* PORT79CR */
3767
3768         PORTCR(80, 0xe6051050), /* PORT80CR */
3769         PORTCR(81, 0xe6051051), /* PORT81CR */
3770         PORTCR(82, 0xe6051052), /* PORT82CR */
3771         PORTCR(83, 0xe6051053), /* PORT83CR */
3772         PORTCR(84, 0xe6051054), /* PORT84CR */
3773         PORTCR(85, 0xe6051055), /* PORT85CR */
3774         PORTCR(86, 0xe6051056), /* PORT86CR */
3775         PORTCR(87, 0xe6051057), /* PORT87CR */
3776         PORTCR(88, 0xe6051058), /* PORT88CR */
3777         PORTCR(89, 0xe6051059), /* PORT89CR */
3778
3779         PORTCR(90, 0xe605105a), /* PORT90CR */
3780         PORTCR(91, 0xe605105b), /* PORT91CR */
3781         PORTCR(92, 0xe605105c), /* PORT92CR */
3782         PORTCR(93, 0xe605105d), /* PORT93CR */
3783         PORTCR(94, 0xe605105e), /* PORT94CR */
3784         PORTCR(95, 0xe605105f), /* PORT95CR */
3785         PORTCR(96, 0xe6052060), /* PORT96CR */
3786         PORTCR(97, 0xe6052061), /* PORT97CR */
3787         PORTCR(98, 0xe6052062), /* PORT98CR */
3788         PORTCR(99, 0xe6052063), /* PORT99CR */
3789
3790         PORTCR(100, 0xe6052064), /* PORT100CR */
3791         PORTCR(101, 0xe6052065), /* PORT101CR */
3792         PORTCR(102, 0xe6052066), /* PORT102CR */
3793         PORTCR(103, 0xe6052067), /* PORT103CR */
3794         PORTCR(104, 0xe6052068), /* PORT104CR */
3795         PORTCR(105, 0xe6052069), /* PORT105CR */
3796         PORTCR(106, 0xe605206a), /* PORT106CR */
3797         PORTCR(107, 0xe605206b), /* PORT107CR */
3798         PORTCR(108, 0xe605206c), /* PORT108CR */
3799         PORTCR(109, 0xe605206d), /* PORT109CR */
3800
3801         PORTCR(110, 0xe605206e), /* PORT110CR */
3802         PORTCR(111, 0xe605206f), /* PORT111CR */
3803         PORTCR(112, 0xe6052070), /* PORT112CR */
3804         PORTCR(113, 0xe6052071), /* PORT113CR */
3805         PORTCR(114, 0xe6052072), /* PORT114CR */
3806         PORTCR(115, 0xe6052073), /* PORT115CR */
3807         PORTCR(116, 0xe6052074), /* PORT116CR */
3808         PORTCR(117, 0xe6052075), /* PORT117CR */
3809         PORTCR(118, 0xe6052076), /* PORT118CR */
3810
3811         PORTCR(128, 0xe6052080), /* PORT128CR */
3812         PORTCR(129, 0xe6052081), /* PORT129CR */
3813
3814         PORTCR(130, 0xe6052082), /* PORT130CR */
3815         PORTCR(131, 0xe6052083), /* PORT131CR */
3816         PORTCR(132, 0xe6052084), /* PORT132CR */
3817         PORTCR(133, 0xe6052085), /* PORT133CR */
3818         PORTCR(134, 0xe6052086), /* PORT134CR */
3819         PORTCR(135, 0xe6052087), /* PORT135CR */
3820         PORTCR(136, 0xe6052088), /* PORT136CR */
3821         PORTCR(137, 0xe6052089), /* PORT137CR */
3822         PORTCR(138, 0xe605208a), /* PORT138CR */
3823         PORTCR(139, 0xe605208b), /* PORT139CR */
3824
3825         PORTCR(140, 0xe605208c), /* PORT140CR */
3826         PORTCR(141, 0xe605208d), /* PORT141CR */
3827         PORTCR(142, 0xe605208e), /* PORT142CR */
3828         PORTCR(143, 0xe605208f), /* PORT143CR */
3829         PORTCR(144, 0xe6052090), /* PORT144CR */
3830         PORTCR(145, 0xe6052091), /* PORT145CR */
3831         PORTCR(146, 0xe6052092), /* PORT146CR */
3832         PORTCR(147, 0xe6052093), /* PORT147CR */
3833         PORTCR(148, 0xe6052094), /* PORT148CR */
3834         PORTCR(149, 0xe6052095), /* PORT149CR */
3835
3836         PORTCR(150, 0xe6052096), /* PORT150CR */
3837         PORTCR(151, 0xe6052097), /* PORT151CR */
3838         PORTCR(152, 0xe6052098), /* PORT152CR */
3839         PORTCR(153, 0xe6052099), /* PORT153CR */
3840         PORTCR(154, 0xe605209a), /* PORT154CR */
3841         PORTCR(155, 0xe605209b), /* PORT155CR */
3842         PORTCR(156, 0xe605209c), /* PORT156CR */
3843         PORTCR(157, 0xe605209d), /* PORT157CR */
3844         PORTCR(158, 0xe605209e), /* PORT158CR */
3845         PORTCR(159, 0xe605209f), /* PORT159CR */
3846
3847         PORTCR(160, 0xe60520a0), /* PORT160CR */
3848         PORTCR(161, 0xe60520a1), /* PORT161CR */
3849         PORTCR(162, 0xe60520a2), /* PORT162CR */
3850         PORTCR(163, 0xe60520a3), /* PORT163CR */
3851         PORTCR(164, 0xe60520a4), /* PORT164CR */
3852
3853         PORTCR(192, 0xe60520c0), /* PORT192CR */
3854         PORTCR(193, 0xe60520c1), /* PORT193CR */
3855         PORTCR(194, 0xe60520c2), /* PORT194CR */
3856         PORTCR(195, 0xe60520c3), /* PORT195CR */
3857         PORTCR(196, 0xe60520c4), /* PORT196CR */
3858         PORTCR(197, 0xe60520c5), /* PORT197CR */
3859         PORTCR(198, 0xe60520c6), /* PORT198CR */
3860         PORTCR(199, 0xe60520c7), /* PORT199CR */
3861
3862         PORTCR(200, 0xe60520c8), /* PORT200CR */
3863         PORTCR(201, 0xe60520c9), /* PORT201CR */
3864         PORTCR(202, 0xe60520ca), /* PORT202CR */
3865         PORTCR(203, 0xe60520cb), /* PORT203CR */
3866         PORTCR(204, 0xe60520cc), /* PORT204CR */
3867         PORTCR(205, 0xe60520cd), /* PORT205CR */
3868         PORTCR(206, 0xe60520ce), /* PORT206CR */
3869         PORTCR(207, 0xe60520cf), /* PORT207CR */
3870         PORTCR(208, 0xe60520d0), /* PORT208CR */
3871         PORTCR(209, 0xe60520d1), /* PORT209CR */
3872
3873         PORTCR(210, 0xe60520d2), /* PORT210CR */
3874         PORTCR(211, 0xe60520d3), /* PORT211CR */
3875         PORTCR(212, 0xe60520d4), /* PORT212CR */
3876         PORTCR(213, 0xe60520d5), /* PORT213CR */
3877         PORTCR(214, 0xe60520d6), /* PORT214CR */
3878         PORTCR(215, 0xe60520d7), /* PORT215CR */
3879         PORTCR(216, 0xe60520d8), /* PORT216CR */
3880         PORTCR(217, 0xe60520d9), /* PORT217CR */
3881         PORTCR(218, 0xe60520da), /* PORT218CR */
3882         PORTCR(219, 0xe60520db), /* PORT219CR */
3883
3884         PORTCR(220, 0xe60520dc), /* PORT220CR */
3885         PORTCR(221, 0xe60520dd), /* PORT221CR */
3886         PORTCR(222, 0xe60520de), /* PORT222CR */
3887         PORTCR(223, 0xe60520df), /* PORT223CR */
3888         PORTCR(224, 0xe60530e0), /* PORT224CR */
3889         PORTCR(225, 0xe60530e1), /* PORT225CR */
3890         PORTCR(226, 0xe60530e2), /* PORT226CR */
3891         PORTCR(227, 0xe60530e3), /* PORT227CR */
3892         PORTCR(228, 0xe60530e4), /* PORT228CR */
3893         PORTCR(229, 0xe60530e5), /* PORT229CR */
3894
3895         PORTCR(230, 0xe60530e6), /* PORT230CR */
3896         PORTCR(231, 0xe60530e7), /* PORT231CR */
3897         PORTCR(232, 0xe60530e8), /* PORT232CR */
3898         PORTCR(233, 0xe60530e9), /* PORT233CR */
3899         PORTCR(234, 0xe60530ea), /* PORT234CR */
3900         PORTCR(235, 0xe60530eb), /* PORT235CR */
3901         PORTCR(236, 0xe60530ec), /* PORT236CR */
3902         PORTCR(237, 0xe60530ed), /* PORT237CR */
3903         PORTCR(238, 0xe60530ee), /* PORT238CR */
3904         PORTCR(239, 0xe60530ef), /* PORT239CR */
3905
3906         PORTCR(240, 0xe60530f0), /* PORT240CR */
3907         PORTCR(241, 0xe60530f1), /* PORT241CR */
3908         PORTCR(242, 0xe60530f2), /* PORT242CR */
3909         PORTCR(243, 0xe60530f3), /* PORT243CR */
3910         PORTCR(244, 0xe60530f4), /* PORT244CR */
3911         PORTCR(245, 0xe60530f5), /* PORT245CR */
3912         PORTCR(246, 0xe60530f6), /* PORT246CR */
3913         PORTCR(247, 0xe60530f7), /* PORT247CR */
3914         PORTCR(248, 0xe60530f8), /* PORT248CR */
3915         PORTCR(249, 0xe60530f9), /* PORT249CR */
3916
3917         PORTCR(250, 0xe60530fa), /* PORT250CR */
3918         PORTCR(251, 0xe60530fb), /* PORT251CR */
3919         PORTCR(252, 0xe60530fc), /* PORT252CR */
3920         PORTCR(253, 0xe60530fd), /* PORT253CR */
3921         PORTCR(254, 0xe60530fe), /* PORT254CR */
3922         PORTCR(255, 0xe60530ff), /* PORT255CR */
3923         PORTCR(256, 0xe6053100), /* PORT256CR */
3924         PORTCR(257, 0xe6053101), /* PORT257CR */
3925         PORTCR(258, 0xe6053102), /* PORT258CR */
3926         PORTCR(259, 0xe6053103), /* PORT259CR */
3927
3928         PORTCR(260, 0xe6053104), /* PORT260CR */
3929         PORTCR(261, 0xe6053105), /* PORT261CR */
3930         PORTCR(262, 0xe6053106), /* PORT262CR */
3931         PORTCR(263, 0xe6053107), /* PORT263CR */
3932         PORTCR(264, 0xe6053108), /* PORT264CR */
3933         PORTCR(265, 0xe6053109), /* PORT265CR */
3934         PORTCR(266, 0xe605310a), /* PORT266CR */
3935         PORTCR(267, 0xe605310b), /* PORT267CR */
3936         PORTCR(268, 0xe605310c), /* PORT268CR */
3937         PORTCR(269, 0xe605310d), /* PORT269CR */
3938
3939         PORTCR(270, 0xe605310e), /* PORT270CR */
3940         PORTCR(271, 0xe605310f), /* PORT271CR */
3941         PORTCR(272, 0xe6053110), /* PORT272CR */
3942         PORTCR(273, 0xe6053111), /* PORT273CR */
3943         PORTCR(274, 0xe6053112), /* PORT274CR */
3944         PORTCR(275, 0xe6053113), /* PORT275CR */
3945         PORTCR(276, 0xe6053114), /* PORT276CR */
3946         PORTCR(277, 0xe6053115), /* PORT277CR */
3947         PORTCR(278, 0xe6053116), /* PORT278CR */
3948         PORTCR(279, 0xe6053117), /* PORT279CR */
3949
3950         PORTCR(280, 0xe6053118), /* PORT280CR */
3951         PORTCR(281, 0xe6053119), /* PORT281CR */
3952         PORTCR(282, 0xe605311a), /* PORT282CR */
3953
3954         PORTCR(288, 0xe6052120), /* PORT288CR */
3955         PORTCR(289, 0xe6052121), /* PORT289CR */
3956
3957         PORTCR(290, 0xe6052122), /* PORT290CR */
3958         PORTCR(291, 0xe6052123), /* PORT291CR */
3959         PORTCR(292, 0xe6052124), /* PORT292CR */
3960         PORTCR(293, 0xe6052125), /* PORT293CR */
3961         PORTCR(294, 0xe6052126), /* PORT294CR */
3962         PORTCR(295, 0xe6052127), /* PORT295CR */
3963         PORTCR(296, 0xe6052128), /* PORT296CR */
3964         PORTCR(297, 0xe6052129), /* PORT297CR */
3965         PORTCR(298, 0xe605212a), /* PORT298CR */
3966         PORTCR(299, 0xe605212b), /* PORT299CR */
3967
3968         PORTCR(300, 0xe605212c), /* PORT300CR */
3969         PORTCR(301, 0xe605212d), /* PORT301CR */
3970         PORTCR(302, 0xe605212e), /* PORT302CR */
3971         PORTCR(303, 0xe605212f), /* PORT303CR */
3972         PORTCR(304, 0xe6052130), /* PORT304CR */
3973         PORTCR(305, 0xe6052131), /* PORT305CR */
3974         PORTCR(306, 0xe6052132), /* PORT306CR */
3975         PORTCR(307, 0xe6052133), /* PORT307CR */
3976         PORTCR(308, 0xe6052134), /* PORT308CR */
3977         PORTCR(309, 0xe6052135), /* PORT309CR */
3978
3979         { PINMUX_CFG_REG("MSEL2CR", 0xe605801c, 32, 1, GROUP(
3980                         0, 0,
3981                         0, 0,
3982                         0, 0,
3983                         0, 0,
3984                         0, 0,
3985                         0, 0,
3986                         0, 0,
3987                         0, 0,
3988                         0, 0,
3989                         0, 0,
3990                         0, 0,
3991                         0, 0,
3992                         MSEL2CR_MSEL19_0, MSEL2CR_MSEL19_1,
3993                         MSEL2CR_MSEL18_0, MSEL2CR_MSEL18_1,
3994                         MSEL2CR_MSEL17_0, MSEL2CR_MSEL17_1,
3995                         MSEL2CR_MSEL16_0, MSEL2CR_MSEL16_1,
3996                         0, 0,
3997                         MSEL2CR_MSEL14_0, MSEL2CR_MSEL14_1,
3998                         MSEL2CR_MSEL13_0, MSEL2CR_MSEL13_1,
3999                         MSEL2CR_MSEL12_0, MSEL2CR_MSEL12_1,
4000                         MSEL2CR_MSEL11_0, MSEL2CR_MSEL11_1,
4001                         MSEL2CR_MSEL10_0, MSEL2CR_MSEL10_1,
4002                         MSEL2CR_MSEL9_0, MSEL2CR_MSEL9_1,
4003                         MSEL2CR_MSEL8_0, MSEL2CR_MSEL8_1,
4004                         MSEL2CR_MSEL7_0, MSEL2CR_MSEL7_1,
4005                         MSEL2CR_MSEL6_0, MSEL2CR_MSEL6_1,
4006                         MSEL2CR_MSEL5_0, MSEL2CR_MSEL5_1,
4007                         MSEL2CR_MSEL4_0, MSEL2CR_MSEL4_1,
4008                         MSEL2CR_MSEL3_0, MSEL2CR_MSEL3_1,
4009                         MSEL2CR_MSEL2_0, MSEL2CR_MSEL2_1,
4010                         MSEL2CR_MSEL1_0, MSEL2CR_MSEL1_1,
4011                         MSEL2CR_MSEL0_0, MSEL2CR_MSEL0_1,
4012                 ))
4013         },
4014         { PINMUX_CFG_REG("MSEL3CR", 0xe6058020, 32, 1, GROUP(
4015                         0, 0,
4016                         0, 0,
4017                         0, 0,
4018                         MSEL3CR_MSEL28_0, MSEL3CR_MSEL28_1,
4019                         0, 0,
4020                         0, 0,
4021                         0, 0,
4022                         0, 0,
4023                         0, 0,
4024                         0, 0,
4025                         0, 0,
4026                         0, 0,
4027                         0, 0,
4028                         0, 0,
4029                         0, 0,
4030                         0, 0,
4031                         MSEL3CR_MSEL15_0, MSEL3CR_MSEL15_1,
4032                         0, 0,
4033                         0, 0,
4034                         0, 0,
4035                         MSEL3CR_MSEL11_0, MSEL3CR_MSEL11_1,
4036                         0, 0,
4037                         MSEL3CR_MSEL9_0, MSEL3CR_MSEL9_1,
4038                         0, 0,
4039                         0, 0,
4040                         MSEL3CR_MSEL6_0, MSEL3CR_MSEL6_1,
4041                         0, 0,
4042                         0, 0,
4043                         0, 0,
4044                         MSEL3CR_MSEL2_0, MSEL3CR_MSEL2_1,
4045                         0, 0,
4046                         0, 0,
4047                 ))
4048         },
4049         { PINMUX_CFG_REG("MSEL4CR", 0xe6058024, 32, 1, GROUP(
4050                         0, 0,
4051                         0, 0,
4052                         MSEL4CR_MSEL29_0, MSEL4CR_MSEL29_1,
4053                         0, 0,
4054                         MSEL4CR_MSEL27_0, MSEL4CR_MSEL27_1,
4055                         MSEL4CR_MSEL26_0, MSEL4CR_MSEL26_1,
4056                         0, 0,
4057                         0, 0,
4058                         0, 0,
4059                         MSEL4CR_MSEL22_0, MSEL4CR_MSEL22_1,
4060                         MSEL4CR_MSEL21_0, MSEL4CR_MSEL21_1,
4061                         MSEL4CR_MSEL20_0, MSEL4CR_MSEL20_1,
4062                         MSEL4CR_MSEL19_0, MSEL4CR_MSEL19_1,
4063                         0, 0,
4064                         0, 0,
4065                         0, 0,
4066                         MSEL4CR_MSEL15_0, MSEL4CR_MSEL15_1,
4067                         0, 0,
4068                         MSEL4CR_MSEL13_0, MSEL4CR_MSEL13_1,
4069                         MSEL4CR_MSEL12_0, MSEL4CR_MSEL12_1,
4070                         MSEL4CR_MSEL11_0, MSEL4CR_MSEL11_1,
4071                         MSEL4CR_MSEL10_0, MSEL4CR_MSEL10_1,
4072                         MSEL4CR_MSEL9_0, MSEL4CR_MSEL9_1,
4073                         MSEL4CR_MSEL8_0, MSEL4CR_MSEL8_1,
4074                         MSEL4CR_MSEL7_0, MSEL4CR_MSEL7_1,
4075                         0, 0,
4076                         0, 0,
4077                         MSEL4CR_MSEL4_0, MSEL4CR_MSEL4_1,
4078                         0, 0,
4079                         0, 0,
4080                         MSEL4CR_MSEL1_0, MSEL4CR_MSEL1_1,
4081                         0, 0,
4082                 ))
4083         },
4084         { },
4085 };
4086
4087 static const struct pinmux_data_reg pinmux_data_regs[] = {
4088         { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32, GROUP(
4089                         PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
4090                         PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
4091                         PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
4092                         PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
4093                         PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
4094                         PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
4095                         PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
4096                         PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA ))
4097         },
4098         { PINMUX_DATA_REG("PORTD063_032DR", 0xe6055000, 32, GROUP(
4099                         PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA,
4100                         PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA,
4101                         PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA,
4102                         PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA,
4103                         PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA,
4104                         PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA,
4105                         PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
4106                         PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA ))
4107         },
4108         { PINMUX_DATA_REG("PORTD095_064DR", 0xe6055004, 32, GROUP(
4109                         PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
4110                         PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
4111                         PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA,
4112                         PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
4113                         PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
4114                         PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
4115                         PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
4116                         PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA ))
4117         },
4118         { PINMUX_DATA_REG("PORTR127_096DR", 0xe6056000, 32, GROUP(
4119                         0, 0, 0, 0,
4120                         0, 0, 0, 0,
4121                         0, PORT118_DATA, PORT117_DATA, PORT116_DATA,
4122                         PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA,
4123                         PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
4124                         PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
4125                         PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
4126                         PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA ))
4127         },
4128         { PINMUX_DATA_REG("PORTR159_128DR", 0xe6056004, 32, GROUP(
4129                         PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA,
4130                         PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA,
4131                         PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA,
4132                         PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA,
4133                         PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA,
4134                         PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA,
4135                         PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA,
4136                         PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA ))
4137         },
4138         { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056008, 32, GROUP(
4139                         0, 0, 0, 0,
4140                         0, 0, 0, 0,
4141                         0, 0, 0, 0,
4142                         0, 0, 0, 0,
4143                         0, 0, 0, 0,
4144                         0, 0, 0, 0,
4145                         0, 0, 0, PORT164_DATA,
4146                         PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA ))
4147         },
4148         { PINMUX_DATA_REG("PORTR223_192DR", 0xe605600C, 32, GROUP(
4149                         PORT223_DATA, PORT222_DATA, PORT221_DATA, PORT220_DATA,
4150                         PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA,
4151                         PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA,
4152                         PORT211_DATA, PORT210_DATA, PORT209_DATA, PORT208_DATA,
4153                         PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
4154                         PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
4155                         PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
4156                         PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA ))
4157         },
4158         { PINMUX_DATA_REG("PORTU255_224DR", 0xe6057000, 32, GROUP(
4159                         PORT255_DATA, PORT254_DATA, PORT253_DATA, PORT252_DATA,
4160                         PORT251_DATA, PORT250_DATA, PORT249_DATA, PORT248_DATA,
4161                         PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA,
4162                         PORT243_DATA, PORT242_DATA, PORT241_DATA, PORT240_DATA,
4163                         PORT239_DATA, PORT238_DATA, PORT237_DATA, PORT236_DATA,
4164                         PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA,
4165                         PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA,
4166                         PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA ))
4167         },
4168         { PINMUX_DATA_REG("PORTU287_256DR", 0xe6057004, 32, GROUP(
4169                         0, 0, 0, 0,
4170                         0, PORT282_DATA, PORT281_DATA, PORT280_DATA,
4171                         PORT279_DATA, PORT278_DATA, PORT277_DATA, PORT276_DATA,
4172                         PORT275_DATA, PORT274_DATA, PORT273_DATA, PORT272_DATA,
4173                         PORT271_DATA, PORT270_DATA, PORT269_DATA, PORT268_DATA,
4174                         PORT267_DATA, PORT266_DATA, PORT265_DATA, PORT264_DATA,
4175                         PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA,
4176                         PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA ))
4177         },
4178         { PINMUX_DATA_REG("PORTR319_288DR", 0xe6056010, 32, GROUP(
4179                         0, 0, 0, 0,
4180                         0, 0, 0, 0,
4181                         0, 0, PORT309_DATA, PORT308_DATA,
4182                         PORT307_DATA, PORT306_DATA, PORT305_DATA, PORT304_DATA,
4183                         PORT303_DATA, PORT302_DATA, PORT301_DATA, PORT300_DATA,
4184                         PORT299_DATA, PORT298_DATA, PORT297_DATA, PORT296_DATA,
4185                         PORT295_DATA, PORT294_DATA, PORT293_DATA, PORT292_DATA,
4186                         PORT291_DATA, PORT290_DATA, PORT289_DATA, PORT288_DATA ))
4187         },
4188         { },
4189 };
4190
4191 static const struct pinmux_irq pinmux_irqs[] = {
4192         PINMUX_IRQ(11),         /* IRQ0 */
4193         PINMUX_IRQ(10),         /* IRQ1 */
4194         PINMUX_IRQ(149),        /* IRQ2 */
4195         PINMUX_IRQ(224),        /* IRQ3 */
4196         PINMUX_IRQ(159),        /* IRQ4 */
4197         PINMUX_IRQ(227),        /* IRQ5 */
4198         PINMUX_IRQ(147),        /* IRQ6 */
4199         PINMUX_IRQ(150),        /* IRQ7 */
4200         PINMUX_IRQ(223),        /* IRQ8 */
4201         PINMUX_IRQ(56, 308),    /* IRQ9 */
4202         PINMUX_IRQ(54),         /* IRQ10 */
4203         PINMUX_IRQ(238),        /* IRQ11 */
4204         PINMUX_IRQ(156),        /* IRQ12 */
4205         PINMUX_IRQ(239),        /* IRQ13 */
4206         PINMUX_IRQ(251),        /* IRQ14 */
4207         PINMUX_IRQ(0),          /* IRQ15 */
4208         PINMUX_IRQ(249),        /* IRQ16 */
4209         PINMUX_IRQ(234),        /* IRQ17 */
4210         PINMUX_IRQ(13),         /* IRQ18 */
4211         PINMUX_IRQ(9),          /* IRQ19 */
4212         PINMUX_IRQ(14),         /* IRQ20 */
4213         PINMUX_IRQ(15),         /* IRQ21 */
4214         PINMUX_IRQ(40),         /* IRQ22 */
4215         PINMUX_IRQ(53),         /* IRQ23 */
4216         PINMUX_IRQ(118),        /* IRQ24 */
4217         PINMUX_IRQ(164),        /* IRQ25 */
4218         PINMUX_IRQ(115),        /* IRQ26 */
4219         PINMUX_IRQ(116),        /* IRQ27 */
4220         PINMUX_IRQ(117),        /* IRQ28 */
4221         PINMUX_IRQ(28),         /* IRQ29 */
4222         PINMUX_IRQ(27),         /* IRQ30 */
4223         PINMUX_IRQ(26),         /* IRQ31 */
4224 };
4225
4226 /* -----------------------------------------------------------------------------
4227  * VCCQ MC0 regulator
4228  */
4229
4230 static void sh73a0_vccq_mc0_endisable(struct regulator_dev *reg, bool enable)
4231 {
4232         struct sh_pfc *pfc = reg->reg_data;
4233         void __iomem *addr = pfc->windows[1].virt + 4;
4234         unsigned long flags;
4235         u32 value;
4236
4237         spin_lock_irqsave(&pfc->lock, flags);
4238
4239         value = ioread32(addr);
4240
4241         if (enable)
4242                 value |= BIT(28);
4243         else
4244                 value &= ~BIT(28);
4245
4246         iowrite32(value, addr);
4247
4248         spin_unlock_irqrestore(&pfc->lock, flags);
4249 }
4250
4251 static int sh73a0_vccq_mc0_enable(struct regulator_dev *reg)
4252 {
4253         sh73a0_vccq_mc0_endisable(reg, true);
4254         return 0;
4255 }
4256
4257 static int sh73a0_vccq_mc0_disable(struct regulator_dev *reg)
4258 {
4259         sh73a0_vccq_mc0_endisable(reg, false);
4260         return 0;
4261 }
4262
4263 static int sh73a0_vccq_mc0_is_enabled(struct regulator_dev *reg)
4264 {
4265         struct sh_pfc *pfc = reg->reg_data;
4266         void __iomem *addr = pfc->windows[1].virt + 4;
4267         unsigned long flags;
4268         u32 value;
4269
4270         spin_lock_irqsave(&pfc->lock, flags);
4271         value = ioread32(addr);
4272         spin_unlock_irqrestore(&pfc->lock, flags);
4273
4274         return !!(value & BIT(28));
4275 }
4276
4277 static int sh73a0_vccq_mc0_get_voltage(struct regulator_dev *reg)
4278 {
4279         return 3300000;
4280 }
4281
4282 static struct regulator_ops sh73a0_vccq_mc0_ops = {
4283         .enable = sh73a0_vccq_mc0_enable,
4284         .disable = sh73a0_vccq_mc0_disable,
4285         .is_enabled = sh73a0_vccq_mc0_is_enabled,
4286         .get_voltage = sh73a0_vccq_mc0_get_voltage,
4287 };
4288
4289 static const struct regulator_desc sh73a0_vccq_mc0_desc = {
4290         .owner = THIS_MODULE,
4291         .name = "vccq_mc0",
4292         .type = REGULATOR_VOLTAGE,
4293         .ops = &sh73a0_vccq_mc0_ops,
4294 };
4295
4296 static struct regulator_consumer_supply sh73a0_vccq_mc0_consumers[] = {
4297         REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
4298         REGULATOR_SUPPLY("vqmmc", "ee100000.sdhi"),
4299 };
4300
4301 static const struct regulator_init_data sh73a0_vccq_mc0_init_data = {
4302         .constraints = {
4303                 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
4304         },
4305         .num_consumer_supplies = ARRAY_SIZE(sh73a0_vccq_mc0_consumers),
4306         .consumer_supplies = sh73a0_vccq_mc0_consumers,
4307 };
4308
4309 /* -----------------------------------------------------------------------------
4310  * Pin bias
4311  */
4312
4313 #define PORTnCR_PULMD_OFF       (0 << 6)
4314 #define PORTnCR_PULMD_DOWN      (2 << 6)
4315 #define PORTnCR_PULMD_UP        (3 << 6)
4316 #define PORTnCR_PULMD_MASK      (3 << 6)
4317
4318 static const unsigned int sh73a0_portcr_offsets[] = {
4319         0x00000000, 0x00001000, 0x00001000, 0x00002000, 0x00002000,
4320         0x00002000, 0x00002000, 0x00003000, 0x00003000, 0x00002000,
4321 };
4322
4323 static unsigned int sh73a0_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)
4324 {
4325         void __iomem *addr = pfc->windows->virt
4326                            + sh73a0_portcr_offsets[pin >> 5] + pin;
4327         u32 value = ioread8(addr) & PORTnCR_PULMD_MASK;
4328
4329         switch (value) {
4330         case PORTnCR_PULMD_UP:
4331                 return PIN_CONFIG_BIAS_PULL_UP;
4332         case PORTnCR_PULMD_DOWN:
4333                 return PIN_CONFIG_BIAS_PULL_DOWN;
4334         case PORTnCR_PULMD_OFF:
4335         default:
4336                 return PIN_CONFIG_BIAS_DISABLE;
4337         }
4338 }
4339
4340 static void sh73a0_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
4341                                    unsigned int bias)
4342 {
4343         void __iomem *addr = pfc->windows->virt
4344                            + sh73a0_portcr_offsets[pin >> 5] + pin;
4345         u32 value = ioread8(addr) & ~PORTnCR_PULMD_MASK;
4346
4347         switch (bias) {
4348         case PIN_CONFIG_BIAS_PULL_UP:
4349                 value |= PORTnCR_PULMD_UP;
4350                 break;
4351         case PIN_CONFIG_BIAS_PULL_DOWN:
4352                 value |= PORTnCR_PULMD_DOWN;
4353                 break;
4354         }
4355
4356         iowrite8(value, addr);
4357 }
4358
4359 /* -----------------------------------------------------------------------------
4360  * SoC information
4361  */
4362
4363 static int sh73a0_pinmux_soc_init(struct sh_pfc *pfc)
4364 {
4365         struct regulator_config cfg = { };
4366         struct regulator_dev *vccq;
4367         int ret;
4368
4369         cfg.dev = pfc->dev;
4370         cfg.init_data = &sh73a0_vccq_mc0_init_data;
4371         cfg.driver_data = pfc;
4372
4373         vccq = devm_regulator_register(pfc->dev, &sh73a0_vccq_mc0_desc, &cfg);
4374         if (IS_ERR(vccq)) {
4375                 ret = PTR_ERR(vccq);
4376                 dev_err(pfc->dev, "Failed to register VCCQ MC0 regulator: %d\n",
4377                         ret);
4378                 return ret;
4379         }
4380
4381         return 0;
4382 }
4383
4384 static const struct sh_pfc_soc_operations sh73a0_pfc_ops = {
4385         .init = sh73a0_pinmux_soc_init,
4386         .get_bias = sh73a0_pinmux_get_bias,
4387         .set_bias = sh73a0_pinmux_set_bias,
4388 };
4389
4390 const struct sh_pfc_soc_info sh73a0_pinmux_info = {
4391         .name = "sh73a0_pfc",
4392         .ops = &sh73a0_pfc_ops,
4393
4394         .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
4395         .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
4396         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
4397
4398         .pins = pinmux_pins,
4399         .nr_pins = ARRAY_SIZE(pinmux_pins),
4400         .groups = pinmux_groups,
4401         .nr_groups = ARRAY_SIZE(pinmux_groups),
4402         .functions = pinmux_functions,
4403         .nr_functions = ARRAY_SIZE(pinmux_functions),
4404
4405         .cfg_regs = pinmux_config_regs,
4406         .data_regs = pinmux_data_regs,
4407
4408         .pinmux_data = pinmux_data,
4409         .pinmux_data_size = ARRAY_SIZE(pinmux_data),
4410
4411         .gpio_irq = pinmux_irqs,
4412         .gpio_irq_size = ARRAY_SIZE(pinmux_irqs),
4413 };