drivers/pinctrl/sh-pfc/pfc-sh7734.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * SH7734 processor support - PFC hardware block
   4  *
   5  * Copyright (C) 2012  Renesas Solutions Corp.
   6  * Copyright (C) 2012  Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
   7  */
   8 #include <linux/init.h>
   9 #include <linux/kernel.h>
  10 #include <cpu/sh7734.h>
  11
  12 #include "sh_pfc.h"
  13
  14 #define CPU_ALL_GP(fn, sfx)                                             \
  15         PORT_GP_32(0, fn, sfx),                                         \
  16         PORT_GP_32(1, fn, sfx),                                         \
  17         PORT_GP_32(2, fn, sfx),                                         \
  18         PORT_GP_32(3, fn, sfx),                                         \
  19         PORT_GP_32(4, fn, sfx),                                         \
  20         PORT_GP_12(5, fn, sfx)
  21
  22 #undef _GP_DATA
  23 #define _GP_DATA(bank, pin, name, sfx, cfg)                             \
  24         PINMUX_DATA(name##_DATA, name##_FN, name##_IN, name##_OUT)
  25
  26 #define _GP_INOUTSEL(bank, pin, name, sfx, cfg) name##_IN, name##_OUT
  27 #define _GP_INDT(bank, pin, name, sfx, cfg)     name##_DATA
  28 #define GP_INOUTSEL(bank)       PORT_GP_32_REV(bank, _GP_INOUTSEL, unused)
  29 #define GP_INDT(bank)           PORT_GP_32_REV(bank, _GP_INDT, unused)
  30
  31 enum {
  32         PINMUX_RESERVED = 0,
  33
  34         PINMUX_DATA_BEGIN,
  35         GP_ALL(DATA), /* GP_0_0_DATA -> GP_5_11_DATA */
  36         PINMUX_DATA_END,
  37
  38         PINMUX_INPUT_BEGIN,
  39         GP_ALL(IN), /* GP_0_0_IN -> GP_5_11_IN */
  40         PINMUX_INPUT_END,
  41
  42         PINMUX_OUTPUT_BEGIN,
  43         GP_ALL(OUT), /* GP_0_0_OUT -> GP_5_11_OUT */
  44         PINMUX_OUTPUT_END,
  45
  46         PINMUX_FUNCTION_BEGIN,
  47         GP_ALL(FN), /* GP_0_0_FN -> GP_5_11_FN */
  48
  49         /* GPSR0 */
  50         FN_IP1_9_8, FN_IP1_11_10, FN_IP1_13_12, FN_IP1_15_14,
  51         FN_IP0_7_6, FN_IP0_9_8, FN_IP0_11_10, FN_IP0_13_12,
  52         FN_IP0_15_14, FN_IP0_17_16, FN_IP0_19_18, FN_IP0_21_20,
  53         FN_IP0_23_22, FN_IP0_25_24, FN_IP0_27_26, FN_IP0_29_28,
  54         FN_IP0_31_30, FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4,
  55         FN_IP1_7_6, FN_IP11_28, FN_IP0_1_0, FN_IP0_3_2,
  56         FN_IP0_5_4, FN_IP1_17_16, FN_IP1_19_18, FN_IP1_22_20,
  57         FN_IP1_25_23, FN_IP1_28_26, FN_IP1_31_29, FN_IP2_2_0,
  58
  59         /* GPSR1 */
  60         FN_IP3_20, FN_IP3_29_27, FN_IP11_20_19, FN_IP11_22_21,
  61         FN_IP2_16_14, FN_IP2_19_17, FN_IP2_22_20, FN_IP2_24_23,
  62         FN_IP2_27_25, FN_IP2_30_28, FN_IP3_1_0, FN_CLKOUT,
  63         FN_BS, FN_CS0, FN_IP3_2, FN_EX_CS0,
  64         FN_IP3_5_3, FN_IP3_8_6, FN_IP3_11_9, FN_IP3_14_12,
  65         FN_IP3_17_15, FN_RD, FN_IP3_19_18, FN_WE0,
  66         FN_WE1, FN_IP2_4_3, FN_IP3_23_21, FN_IP3_26_24,
  67         FN_IP2_7_5, FN_IP2_10_8, FN_IP2_13_11, FN_IP11_25_23,
  68
  69         /* GPSR2 */
  70         FN_IP11_6_4, FN_IP11_9_7, FN_IP11_11_10, FN_IP4_2_0,
  71         FN_IP8_29_28, FN_IP11_27_26, FN_IP8_22_20, FN_IP8_25_23,
  72         FN_IP11_12, FN_IP8_27_26, FN_IP4_5_3, FN_IP4_8_6,
  73         FN_IP4_11_9, FN_IP4_14_12, FN_IP4_17_15, FN_IP4_19_18,
  74         FN_IP4_21_20, FN_IP4_23_22, FN_IP4_25_24, FN_IP4_27_26,
  75         FN_IP4_29_28, FN_IP4_31_30, FN_IP5_2_0, FN_IP5_5_3,
  76         FN_IP5_8_6, FN_IP5_11_9, FN_IP5_14_12, FN_IP5_17_15,
  77         FN_IP5_20_18, FN_IP5_22_21, FN_IP5_24_23, FN_IP5_26_25,
  78
  79         /* GPSR3 */
  80         FN_IP6_2_0, FN_IP6_5_3, FN_IP6_7_6, FN_IP6_9_8,
  81         FN_IP6_11_10, FN_IP6_13_12, FN_IP6_15_14, FN_IP6_17_16,
  82         FN_IP6_20_18, FN_IP6_23_21, FN_IP7_2_0, FN_IP7_5_3,
  83         FN_IP7_8_6, FN_IP7_11_9, FN_IP7_14_12, FN_IP7_17_15,
  84         FN_IP7_20_18, FN_IP7_23_21, FN_IP7_26_24, FN_IP7_28_27,
  85         FN_IP7_30_29, FN_IP8_1_0, FN_IP8_3_2, FN_IP8_5_4,
  86         FN_IP8_7_6, FN_IP8_9_8, FN_IP8_11_10, FN_IP8_13_12,
  87         FN_IP8_15_14, FN_IP8_17_16, FN_IP8_19_18, FN_IP9_1_0,
  88
  89         /* GPSR4 */
  90         FN_IP9_19_18, FN_IP9_21_20, FN_IP9_23_22, FN_IP9_25_24,
  91         FN_IP9_11_10, FN_IP9_13_12, FN_IP9_15_14, FN_IP9_17_16,
  92         FN_IP9_3_2, FN_IP9_5_4, FN_IP9_7_6, FN_IP9_9_8,
  93         FN_IP9_27_26, FN_IP9_29_28, FN_IP10_2_0, FN_IP10_5_3,
  94         FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_15,
  95         FN_IP10_18_16, FN_IP10_21_19, FN_IP11_0, FN_IP11_1,
  96         FN_SCL0, FN_IP11_2, FN_PENC0, FN_IP11_15_13, /* Need check*/
  97         FN_USB_OVC0, FN_IP11_18_16,
  98         FN_IP10_22, FN_IP10_24_23,
  99
 100         /* GPSR5 */
 101         FN_IP10_25, FN_IP11_3, FN_IRQ2_B, FN_IRQ3_B,
 102         FN_IP10_27_26, /* 10 */
 103         FN_IP10_29_28, /* 11 */
 104
 105         /* IPSR0 */
 106         FN_A15, FN_ST0_VCO_CLKIN, FN_LCD_DATA15_A, FN_TIOC3D_C,
 107         FN_A14, FN_LCD_DATA14_A, FN_TIOC3C_C,
 108         FN_A13, FN_LCD_DATA13_A, FN_TIOC3B_C,
 109         FN_A12, FN_LCD_DATA12_A, FN_TIOC3A_C,
 110         FN_A11, FN_ST0_D7, FN_LCD_DATA11_A, FN_TIOC2B_C,
 111         FN_A10, FN_ST0_D6, FN_LCD_DATA10_A, FN_TIOC2A_C,
 112         FN_A9, FN_ST0_D5, FN_LCD_DATA9_A, FN_TIOC1B_C,
 113         FN_A8, FN_ST0_D4, FN_LCD_DATA8_A, FN_TIOC1A_C,
 114         FN_A7, FN_ST0_D3, FN_LCD_DATA7_A, FN_TIOC0D_C,
 115         FN_A6, FN_ST0_D2, FN_LCD_DATA6_A, FN_TIOC0C_C,
 116         FN_A5, FN_ST0_D1, FN_LCD_DATA5_A, FN_TIOC0B_C,
 117         FN_A4, FN_ST0_D0, FN_LCD_DATA4_A, FN_TIOC0A_C,
 118         FN_A3, FN_ST0_VLD, FN_LCD_DATA3_A, FN_TCLKD_C,
 119         FN_A2, FN_ST0_SYC, FN_LCD_DATA2_A, FN_TCLKC_C,
 120         FN_A1, FN_ST0_REQ, FN_LCD_DATA1_A, FN_TCLKB_C,
 121         FN_A0, FN_ST0_CLKIN, FN_LCD_DATA0_A, FN_TCLKA_C,
 122
 123         /* IPSR1 */
 124         FN_D3, FN_SD0_DAT3_A, FN_MMC_D3_A, FN_ST1_D6, FN_FD3_A,
 125         FN_D2, FN_SD0_DAT2_A, FN_MMC_D2_A, FN_ST1_D5, FN_FD2_A,
 126         FN_D1, FN_SD0_DAT1_A, FN_MMC_D1_A, FN_ST1_D4, FN_FD1_A,
 127         FN_D0, FN_SD0_DAT0_A, FN_MMC_D0_A, FN_ST1_D3, FN_FD0_A,
 128         FN_A25, FN_TX2_D, FN_ST1_D2,
 129         FN_A24, FN_RX2_D, FN_ST1_D1,
 130         FN_A23, FN_ST1_D0, FN_LCD_M_DISP_A,
 131         FN_A22, FN_ST1_VLD, FN_LCD_VEPWC_A,
 132         FN_A21, FN_ST1_SYC, FN_LCD_VCPWC_A,
 133         FN_A20, FN_ST1_REQ, FN_LCD_FLM_A,
 134         FN_A19, FN_ST1_CLKIN, FN_LCD_CLK_A,     FN_TIOC4D_C,
 135         FN_A18, FN_ST1_PWM, FN_LCD_CL2_A, FN_TIOC4C_C,
 136         FN_A17, FN_ST1_VCO_CLKIN, FN_LCD_CL1_A, FN_TIOC4B_C,
 137         FN_A16, FN_ST0_PWM, FN_LCD_DON_A, FN_TIOC4A_C,
 138
 139         /* IPSR2 */
 140         FN_D14, FN_TX2_B, FN_FSE_A, FN_ET0_TX_CLK_B,
 141         FN_D13, FN_RX2_B, FN_FRB_A,     FN_ET0_ETXD6_B,
 142         FN_D12, FN_FWE_A, FN_ET0_ETXD5_B,
 143         FN_D11, FN_RSPI_MISO_A, FN_QMI_QIO1_A, FN_FRE_A,
 144                 FN_ET0_ETXD3_B,
 145         FN_D10, FN_RSPI_MOSI_A, FN_QMO_QIO0_A, FN_FALE_A,
 146                 FN_ET0_ETXD2_B,
 147         FN_D9, FN_SD0_CMD_A, FN_MMC_CMD_A, FN_QIO3_A, FN_FCLE_A,
 148                 FN_ET0_ETXD1_B,
 149         FN_D8, FN_SD0_CLK_A, FN_MMC_CLK_A, FN_QIO2_A, FN_FCE_A,
 150                 FN_ET0_GTX_CLK_B,
 151         FN_D7, FN_RSPI_SSL_A, FN_MMC_D7_A, FN_QSSL_A, FN_FD7_A,
 152         FN_D6, FN_RSPI_RSPCK_A, FN_MMC_D6_A, FN_QSPCLK_A, FN_FD6_A,
 153         FN_D5, FN_SD0_WP_A, FN_MMC_D5_A, FN_FD5_A,
 154         FN_D4, FN_SD0_CD_A, FN_MMC_D4_A, FN_ST1_D7, FN_FD4_A,
 155
 156         /* IPSR3 */
 157         FN_DRACK0, FN_SD1_DAT2_A, FN_ATAG, FN_TCLK1_A, FN_ET0_ETXD7,
 158         FN_EX_WAIT2, FN_SD1_DAT1_A, FN_DACK2, FN_CAN1_RX_C,
 159                 FN_ET0_MAGIC_C, FN_ET0_ETXD6_A,
 160         FN_EX_WAIT1, FN_SD1_DAT0_A, FN_DREQ2, FN_CAN1_TX_C,
 161                 FN_ET0_LINK_C, FN_ET0_ETXD5_A,
 162         FN_EX_WAIT0, FN_TCLK1_B,
 163         FN_RD_WR, FN_TCLK0, FN_CAN_CLK_B, FN_ET0_ETXD4,
 164         FN_EX_CS5, FN_SD1_CMD_A, FN_ATADIR, FN_QSSL_B, FN_ET0_ETXD3_A,
 165         FN_EX_CS4, FN_SD1_WP_A, FN_ATAWR, FN_QMI_QIO1_B, FN_ET0_ETXD2_A,
 166         FN_EX_CS3, FN_SD1_CD_A, FN_ATARD, FN_QMO_QIO0_B, FN_ET0_ETXD1_A,
 167         FN_EX_CS2, FN_TX3_B, FN_ATACS1, FN_QSPCLK_B, FN_ET0_GTX_CLK_A,
 168         FN_EX_CS1, FN_RX3_B, FN_ATACS0, FN_QIO2_B, FN_ET0_ETXD0,
 169         FN_CS1_A26, FN_QIO3_B,
 170         FN_D15, FN_SCK2_B,
 171
 172         /* IPSR4 */
 173         FN_SCK2_A, FN_VI0_G3,
 174         FN_RTS1_B, FN_VI0_G2,
 175         FN_CTS1_B, FN_VI0_DATA7_VI0_G1,
 176         FN_TX1_B, FN_VI0_DATA6_VI0_G0, FN_ET0_PHY_INT_A,
 177         FN_RX1_B, FN_VI0_DATA5_VI0_B5, FN_ET0_MAGIC_A,
 178         FN_SCK1_B, FN_VI0_DATA4_VI0_B4, FN_ET0_LINK_A,
 179         FN_RTS0_B, FN_VI0_DATA3_VI0_B3, FN_ET0_MDIO_A,
 180         FN_CTS0_B, FN_VI0_DATA2_VI0_B2, FN_RMII0_MDIO_A, FN_ET0_MDC,
 181         FN_HTX0_A, FN_TX1_A, FN_VI0_DATA1_VI0_B1, FN_RMII0_MDC_A, FN_ET0_COL,
 182         FN_HRX0_A, FN_RX1_A, FN_VI0_DATA0_VI0_B0, FN_RMII0_CRS_DV_A, FN_ET0_CRS,
 183         FN_HSCK0_A, FN_SCK1_A, FN_VI0_VSYNC, FN_RMII0_RX_ER_A, FN_ET0_RX_ER,
 184         FN_HRTS0_A, FN_RTS1_A, FN_VI0_HSYNC, FN_RMII0_TXD_EN_A, FN_ET0_RX_DV,
 185         FN_HCTS0_A, FN_CTS1_A, FN_VI0_FIELD, FN_RMII0_RXD1_A, FN_ET0_ERXD7,
 186
 187         /* IPSR5 */
 188         FN_SD2_CLK_A, FN_RX2_A, FN_VI0_G4, FN_ET0_RX_CLK_B,
 189         FN_SD2_CMD_A, FN_TX2_A, FN_VI0_G5, FN_ET0_ERXD2_B,
 190         FN_SD2_DAT0_A, FN_RX3_A, FN_VI0_R0, FN_ET0_ERXD3_B,
 191         FN_SD2_DAT1_A, FN_TX3_A, FN_VI0_R1, FN_ET0_MDIO_B,
 192         FN_SD2_DAT2_A, FN_RX4_A, FN_VI0_R2, FN_ET0_LINK_B,
 193         FN_SD2_DAT3_A, FN_TX4_A, FN_VI0_R3, FN_ET0_MAGIC_B,
 194         FN_SD2_CD_A, FN_RX5_A, FN_VI0_R4, FN_ET0_PHY_INT_B,
 195         FN_SD2_WP_A, FN_TX5_A, FN_VI0_R5,
 196         FN_REF125CK, FN_ADTRG, FN_RX5_C,
 197         FN_REF50CK, FN_CTS1_E, FN_HCTS0_D,
 198
 199         /* IPSR6 */
 200         FN_DU0_DR0, FN_SCIF_CLK_B, FN_HRX0_D, FN_IETX_A, FN_TCLKA_A, FN_HIFD00,
 201         FN_DU0_DR1, FN_SCK0_B, FN_HTX0_D, FN_IERX_A, FN_TCLKB_A, FN_HIFD01,
 202         FN_DU0_DR2, FN_RX0_B, FN_TCLKC_A, FN_HIFD02,
 203         FN_DU0_DR3, FN_TX0_B, FN_TCLKD_A, FN_HIFD03,
 204         FN_DU0_DR4, FN_CTS0_C, FN_TIOC0A_A, FN_HIFD04,
 205         FN_DU0_DR5, FN_RTS0_C, FN_TIOC0B_A, FN_HIFD05,
 206         FN_DU0_DR6, FN_SCK1_C, FN_TIOC0C_A, FN_HIFD06,
 207         FN_DU0_DR7, FN_RX1_C, FN_TIOC0D_A, FN_HIFD07,
 208         FN_DU0_DG0, FN_TX1_C, FN_HSCK0_D, FN_IECLK_A, FN_TIOC1A_A, FN_HIFD08,
 209         FN_DU0_DG1, FN_CTS1_C, FN_HRTS0_D, FN_TIOC1B_A, FN_HIFD09,
 210
 211         /* IPSR7 */
 212         FN_DU0_DG2, FN_RTS1_C, FN_RMII0_MDC_B, FN_TIOC2A_A, FN_HIFD10,
 213         FN_DU0_DG3, FN_SCK2_C, FN_RMII0_MDIO_B, FN_TIOC2B_A, FN_HIFD11,
 214         FN_DU0_DG4, FN_RX2_C, FN_RMII0_CRS_DV_B, FN_TIOC3A_A, FN_HIFD12,
 215         FN_DU0_DG5, FN_TX2_C, FN_RMII0_RX_ER_B, FN_TIOC3B_A, FN_HIFD13,
 216         FN_DU0_DG6, FN_RX3_C, FN_RMII0_RXD0_B, FN_TIOC3C_A, FN_HIFD14,
 217         FN_DU0_DG7, FN_TX3_C, FN_RMII0_RXD1_B, FN_TIOC3D_A, FN_HIFD15,
 218         FN_DU0_DB0, FN_RX4_C, FN_RMII0_TXD_EN_B, FN_TIOC4A_A, FN_HIFCS,
 219         FN_DU0_DB1, FN_TX4_C, FN_RMII0_TXD0_B, FN_TIOC4B_A, FN_HIFRS,
 220         FN_DU0_DB2, FN_RX5_B, FN_RMII0_TXD1_B, FN_TIOC4C_A, FN_HIFWR,
 221         FN_DU0_DB3, FN_TX5_B, FN_TIOC4D_A, FN_HIFRD,
 222         FN_DU0_DB4, FN_HIFINT,
 223
 224         /* IPSR8 */
 225         FN_DU0_DB5, FN_HIFDREQ,
 226         FN_DU0_DB6, FN_HIFRDY,
 227         FN_DU0_DB7, FN_SSI_SCK0_B, FN_HIFEBL_B,
 228         FN_DU0_DOTCLKIN, FN_HSPI_CS0_C, FN_SSI_WS0_B,
 229         FN_DU0_DOTCLKOUT, FN_HSPI_CLK0_C, FN_SSI_SDATA0_B,
 230         FN_DU0_EXHSYNC_DU0_HSYNC, FN_HSPI_TX0_C, FN_SSI_SCK1_B,
 231         FN_DU0_EXVSYNC_DU0_VSYNC, FN_HSPI_RX0_C, FN_SSI_WS1_B,
 232         FN_DU0_EXODDF_DU0_ODDF, FN_CAN0_RX_B, FN_HSCK0_B, FN_SSI_SDATA1_B,
 233         FN_DU0_DISP, FN_CAN0_TX_B, FN_HRX0_B, FN_AUDIO_CLKA_B,
 234         FN_DU0_CDE, FN_HTX0_B, FN_AUDIO_CLKB_B, FN_LCD_VCPWC_B,
 235         FN_IRQ0_A, FN_HSPI_TX_B, FN_RX3_E, FN_ET0_ERXD0,
 236         FN_IRQ1_A, FN_HSPI_RX_B, FN_TX3_E, FN_ET0_ERXD1,
 237         FN_IRQ2_A, FN_CTS0_A, FN_HCTS0_B, FN_ET0_ERXD2_A,
 238         FN_IRQ3_A, FN_RTS0_A, FN_HRTS0_B, FN_ET0_ERXD3_A,
 239
 240         /* IPSR9 */
 241         FN_VI1_CLK_A, FN_FD0_B, FN_LCD_DATA0_B,
 242         FN_VI1_0_A, FN_FD1_B, FN_LCD_DATA1_B,
 243         FN_VI1_1_A, FN_FD2_B, FN_LCD_DATA2_B,
 244         FN_VI1_2_A, FN_FD3_B, FN_LCD_DATA3_B,
 245         FN_VI1_3_A, FN_FD4_B, FN_LCD_DATA4_B,
 246         FN_VI1_4_A, FN_FD5_B, FN_LCD_DATA5_B,
 247         FN_VI1_5_A, FN_FD6_B, FN_LCD_DATA6_B,
 248         FN_VI1_6_A, FN_FD7_B, FN_LCD_DATA7_B,
 249         FN_VI1_7_A, FN_FCE_B, FN_LCD_DATA8_B,
 250         FN_SSI_SCK0_A, FN_TIOC1A_B, FN_LCD_DATA9_B,
 251         FN_SSI_WS0_A, FN_TIOC1B_B, FN_LCD_DATA10_B,
 252         FN_SSI_SDATA0_A, FN_VI1_0_B, FN_TIOC2A_B, FN_LCD_DATA11_B,
 253         FN_SSI_SCK1_A, FN_VI1_1_B, FN_TIOC2B_B, FN_LCD_DATA12_B,
 254         FN_SSI_WS1_A, FN_VI1_2_B, FN_LCD_DATA13_B,
 255         FN_SSI_SDATA1_A, FN_VI1_3_B, FN_LCD_DATA14_B,
 256
 257         /* IPSR10 */
 258         FN_SSI_SCK23, FN_VI1_4_B, FN_RX1_D, FN_FCLE_B, FN_LCD_DATA15_B,
 259         FN_SSI_WS23, FN_VI1_5_B, FN_TX1_D, FN_HSCK0_C, FN_FALE_B, FN_LCD_DON_B,
 260         FN_SSI_SDATA2, FN_VI1_6_B, FN_HRX0_C, FN_FRE_B, FN_LCD_CL1_B,
 261         FN_SSI_SDATA3, FN_VI1_7_B, FN_HTX0_C, FN_FWE_B, FN_LCD_CL2_B,
 262         FN_AUDIO_CLKA_A, FN_VI1_CLK_B, FN_SCK1_D, FN_IECLK_B, FN_LCD_FLM_B,
 263         FN_AUDIO_CLKB_A, FN_LCD_CLK_B,
 264         FN_AUDIO_CLKC, FN_SCK1_E, FN_HCTS0_C, FN_FRB_B, FN_LCD_VEPWC_B,
 265         FN_AUDIO_CLKOUT, FN_TX1_E, FN_HRTS0_C, FN_FSE_B, FN_LCD_M_DISP_B,
 266         FN_CAN_CLK_A, FN_RX4_D,
 267         FN_CAN0_TX_A, FN_TX4_D, FN_MLB_CLK,
 268         FN_CAN1_RX_A, FN_IRQ1_B,
 269         FN_CAN0_RX_A, FN_IRQ0_B, FN_MLB_SIG,
 270         FN_CAN1_TX_A, FN_TX5_C, FN_MLB_DAT,
 271
 272         /* IPSR11 */
 273         FN_SCL1, FN_SCIF_CLK_C,
 274         FN_SDA1, FN_RX1_E,
 275         FN_SDA0, FN_HIFEBL_A,
 276         FN_SDSELF, FN_RTS1_E,
 277         FN_SCIF_CLK_A, FN_HSPI_CLK_A, FN_VI0_CLK, FN_RMII0_TXD0_A, FN_ET0_ERXD4,
 278         FN_SCK0_A, FN_HSPI_CS_A, FN_VI0_CLKENB, FN_RMII0_TXD1_A, FN_ET0_ERXD5,
 279         FN_RX0_A, FN_HSPI_RX_A, FN_RMII0_RXD0_A, FN_ET0_ERXD6,
 280         FN_TX0_A, FN_HSPI_TX_A,
 281         FN_PENC1, FN_TX3_D, FN_CAN1_TX_B, FN_TX5_D, FN_IETX_B,
 282         FN_USB_OVC1, FN_RX3_D, FN_CAN1_RX_B, FN_RX5_D, FN_IERX_B,
 283         FN_DREQ0, FN_SD1_CLK_A, FN_ET0_TX_EN,
 284         FN_DACK0, FN_SD1_DAT3_A, FN_ET0_TX_ER,
 285         FN_DREQ1, FN_HSPI_CLK_B, FN_RX4_B, FN_ET0_PHY_INT_C, FN_ET0_TX_CLK_A,
 286         FN_DACK1, FN_HSPI_CS_B, FN_TX4_B, FN_ET0_RX_CLK_A,
 287         FN_PRESETOUT, FN_ST_CLKOUT,
 288
 289         /* MOD_SEL1 */
 290         FN_SEL_IEBUS_0, FN_SEL_IEBUS_1,
 291         FN_SEL_RQSPI_0, FN_SEL_RQSPI_1,
 292         FN_SEL_VIN1_0, FN_SEL_VIN1_1,
 293         FN_SEL_HIF_0, FN_SEL_HIF_1,
 294         FN_SEL_RSPI_0, FN_SEL_RSPI_1,
 295         FN_SEL_LCDC_0, FN_SEL_LCDC_1,
 296         FN_SEL_ET0_CTL_0, FN_SEL_ET0_CTL_1, FN_SEL_ET0_CTL_2,
 297         FN_SEL_ET0_0, FN_SEL_ET0_1,
 298         FN_SEL_RMII_0, FN_SEL_RMII_1,
 299         FN_SEL_TMU_0, FN_SEL_TMU_1,
 300         FN_SEL_HSPI_0, FN_SEL_HSPI_1, FN_SEL_HSPI_2,
 301         FN_SEL_HSCIF_0, FN_SEL_HSCIF_1, FN_SEL_HSCIF_2, FN_SEL_HSCIF_3,
 302         FN_SEL_RCAN_CLK_0, FN_SEL_RCAN_CLK_1,
 303         FN_SEL_RCAN1_0, FN_SEL_RCAN1_1, FN_SEL_RCAN1_2,
 304         FN_SEL_RCAN0_0, FN_SEL_RCAN0_1,
 305         FN_SEL_SDHI2_0, FN_SEL_SDHI2_1,
 306         FN_SEL_SDHI1_0, FN_SEL_SDHI1_1,
 307         FN_SEL_SDHI0_0, FN_SEL_SDHI0_1,
 308         FN_SEL_SSI1_0, FN_SEL_SSI1_1,
 309         FN_SEL_SSI0_0, FN_SEL_SSI0_1,
 310         FN_SEL_AUDIO_CLKB_0, FN_SEL_AUDIO_CLKB_1,
 311         FN_SEL_AUDIO_CLKA_0, FN_SEL_AUDIO_CLKA_1,
 312         FN_SEL_FLCTL_0, FN_SEL_FLCTL_1,
 313         FN_SEL_MMC_0, FN_SEL_MMC_1,
 314         FN_SEL_INTC_0, FN_SEL_INTC_1,
 315
 316         /* MOD_SEL2 */
 317         FN_SEL_MTU2_CLK_0, FN_SEL_MTU2_CLK_1,
 318         FN_SEL_MTU2_CH4_0, FN_SEL_MTU2_CH4_1,
 319         FN_SEL_MTU2_CH3_0, FN_SEL_MTU2_CH3_1,
 320         FN_SEL_MTU2_CH2_0, FN_SEL_MTU2_CH2_1, FN_SEL_MTU2_CH2_2,
 321         FN_SEL_MTU2_CH1_0, FN_SEL_MTU2_CH1_1, FN_SEL_MTU2_CH1_2,
 322         FN_SEL_MTU2_CH0_0, FN_SEL_MTU2_CH0_1,
 323         FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
 324         FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
 325         FN_SEL_SCIF4_0, FN_SEL_SCIF4_1,
 326         FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
 327         FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2,
 328                 FN_SEL_SCIF3_3, FN_SEL_SCIF3_4,
 329         FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2,
 330                 FN_SEL_SCIF2_3,
 331         FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2,
 332                 FN_SEL_SCIF1_3, FN_SEL_SCIF1_4,
 333         FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2,
 334         FN_SEL_SCIF_CLK_0, FN_SEL_SCIF_CLK_1, FN_SEL_SCIF_CLK_2,
 335
 336         PINMUX_FUNCTION_END,
 337
 338         PINMUX_MARK_BEGIN,
 339
 340         CLKOUT_MARK, BS_MARK, CS0_MARK, EX_CS0_MARK, RD_MARK,
 341         WE0_MARK, WE1_MARK,
 342
 343         SCL0_MARK, PENC0_MARK, USB_OVC0_MARK,
 344
 345         IRQ2_B_MARK, IRQ3_B_MARK,
 346
 347         /* IPSR0 */
 348         A15_MARK, ST0_VCO_CLKIN_MARK, LCD_DATA15_A_MARK, TIOC3D_C_MARK,
 349         A14_MARK, LCD_DATA14_A_MARK, TIOC3C_C_MARK,
 350         A13_MARK, LCD_DATA13_A_MARK, TIOC3B_C_MARK,
 351         A12_MARK, LCD_DATA12_A_MARK, TIOC3A_C_MARK,
 352         A11_MARK, ST0_D7_MARK, LCD_DATA11_A_MARK, TIOC2B_C_MARK,
 353         A10_MARK, ST0_D6_MARK, LCD_DATA10_A_MARK, TIOC2A_C_MARK,
 354         A9_MARK, ST0_D5_MARK, LCD_DATA9_A_MARK, TIOC1B_C_MARK,
 355         A8_MARK, ST0_D4_MARK, LCD_DATA8_A_MARK, TIOC1A_C_MARK,
 356         A7_MARK, ST0_D3_MARK, LCD_DATA7_A_MARK, TIOC0D_C_MARK,
 357         A6_MARK, ST0_D2_MARK, LCD_DATA6_A_MARK, TIOC0C_C_MARK,
 358         A5_MARK, ST0_D1_MARK, LCD_DATA5_A_MARK, TIOC0B_C_MARK,
 359         A4_MARK, ST0_D0_MARK, LCD_DATA4_A_MARK, TIOC0A_C_MARK,
 360         A3_MARK, ST0_VLD_MARK, LCD_DATA3_A_MARK, TCLKD_C_MARK,
 361         A2_MARK, ST0_SYC_MARK, LCD_DATA2_A_MARK, TCLKC_C_MARK,
 362         A1_MARK, ST0_REQ_MARK, LCD_DATA1_A_MARK, TCLKB_C_MARK,
 363         A0_MARK, ST0_CLKIN_MARK, LCD_DATA0_A_MARK, TCLKA_C_MARK,
 364
 365         /* IPSR1 */
 366         D3_MARK, SD0_DAT3_A_MARK, MMC_D3_A_MARK, ST1_D6_MARK, FD3_A_MARK,
 367         D2_MARK, SD0_DAT2_A_MARK, MMC_D2_A_MARK, ST1_D5_MARK, FD2_A_MARK,
 368         D1_MARK, SD0_DAT1_A_MARK, MMC_D1_A_MARK, ST1_D4_MARK, FD1_A_MARK,
 369         D0_MARK, SD0_DAT0_A_MARK, MMC_D0_A_MARK, ST1_D3_MARK, FD0_A_MARK,
 370         A25_MARK, TX2_D_MARK, ST1_D2_MARK,
 371         A24_MARK, RX2_D_MARK, ST1_D1_MARK,
 372         A23_MARK, ST1_D0_MARK, LCD_M_DISP_A_MARK,
 373         A22_MARK, ST1_VLD_MARK, LCD_VEPWC_A_MARK,
 374         A21_MARK, ST1_SYC_MARK, LCD_VCPWC_A_MARK,
 375         A20_MARK, ST1_REQ_MARK, LCD_FLM_A_MARK,
 376         A19_MARK, ST1_CLKIN_MARK, LCD_CLK_A_MARK,       TIOC4D_C_MARK,
 377         A18_MARK, ST1_PWM_MARK, LCD_CL2_A_MARK, TIOC4C_C_MARK,
 378         A17_MARK, ST1_VCO_CLKIN_MARK, LCD_CL1_A_MARK, TIOC4B_C_MARK,
 379         A16_MARK, ST0_PWM_MARK, LCD_DON_A_MARK, TIOC4A_C_MARK,
 380
 381         /* IPSR2 */
 382         D14_MARK, TX2_B_MARK, FSE_A_MARK, ET0_TX_CLK_B_MARK,
 383         D13_MARK, RX2_B_MARK, FRB_A_MARK, ET0_ETXD6_B_MARK,
 384         D12_MARK, FWE_A_MARK, ET0_ETXD5_B_MARK,
 385         D11_MARK, RSPI_MISO_A_MARK, QMI_QIO1_A_MARK, FRE_A_MARK,
 386                 ET0_ETXD3_B_MARK,
 387         D10_MARK, RSPI_MOSI_A_MARK, QMO_QIO0_A_MARK, FALE_A_MARK,
 388                 ET0_ETXD2_B_MARK,
 389         D9_MARK, SD0_CMD_A_MARK, MMC_CMD_A_MARK, QIO3_A_MARK,
 390                 FCLE_A_MARK, ET0_ETXD1_B_MARK,
 391         D8_MARK, SD0_CLK_A_MARK, MMC_CLK_A_MARK, QIO2_A_MARK,
 392                 FCE_A_MARK, ET0_GTX_CLK_B_MARK,
 393         D7_MARK, RSPI_SSL_A_MARK, MMC_D7_A_MARK, QSSL_A_MARK,
 394                 FD7_A_MARK,
 395         D6_MARK, RSPI_RSPCK_A_MARK, MMC_D6_A_MARK, QSPCLK_A_MARK,
 396                 FD6_A_MARK,
 397         D5_MARK, SD0_WP_A_MARK, MMC_D5_A_MARK, FD5_A_MARK,
 398         D4_MARK, SD0_CD_A_MARK, MMC_D4_A_MARK, ST1_D7_MARK,
 399                 FD4_A_MARK,
 400
 401         /* IPSR3 */
 402         DRACK0_MARK, SD1_DAT2_A_MARK, ATAG_MARK, TCLK1_A_MARK, ET0_ETXD7_MARK,
 403         EX_WAIT2_MARK, SD1_DAT1_A_MARK, DACK2_MARK, CAN1_RX_C_MARK,
 404                 ET0_MAGIC_C_MARK, ET0_ETXD6_A_MARK,
 405         EX_WAIT1_MARK, SD1_DAT0_A_MARK, DREQ2_MARK, CAN1_TX_C_MARK,
 406                 ET0_LINK_C_MARK, ET0_ETXD5_A_MARK,
 407         EX_WAIT0_MARK, TCLK1_B_MARK,
 408         RD_WR_MARK, TCLK0_MARK, CAN_CLK_B_MARK, ET0_ETXD4_MARK,
 409         EX_CS5_MARK, SD1_CMD_A_MARK, ATADIR_MARK, QSSL_B_MARK,
 410                 ET0_ETXD3_A_MARK,
 411         EX_CS4_MARK, SD1_WP_A_MARK, ATAWR_MARK, QMI_QIO1_B_MARK,
 412                 ET0_ETXD2_A_MARK,
 413         EX_CS3_MARK, SD1_CD_A_MARK, ATARD_MARK, QMO_QIO0_B_MARK,
 414                 ET0_ETXD1_A_MARK,
 415         EX_CS2_MARK, TX3_B_MARK, ATACS1_MARK, QSPCLK_B_MARK,
 416                 ET0_GTX_CLK_A_MARK,
 417         EX_CS1_MARK, RX3_B_MARK, ATACS0_MARK, QIO2_B_MARK,
 418                 ET0_ETXD0_MARK,
 419         CS1_A26_MARK, QIO3_B_MARK,
 420         D15_MARK, SCK2_B_MARK,
 421
 422         /* IPSR4 */
 423         SCK2_A_MARK, VI0_G3_MARK,
 424         RTS1_B_MARK, VI0_G2_MARK,
 425         CTS1_B_MARK, VI0_DATA7_VI0_G1_MARK,
 426         TX1_B_MARK, VI0_DATA6_VI0_G0_MARK, ET0_PHY_INT_A_MARK,
 427         RX1_B_MARK, VI0_DATA5_VI0_B5_MARK, ET0_MAGIC_A_MARK,
 428         SCK1_B_MARK, VI0_DATA4_VI0_B4_MARK, ET0_LINK_A_MARK,
 429         RTS0_B_MARK, VI0_DATA3_VI0_B3_MARK, ET0_MDIO_A_MARK,
 430         CTS0_B_MARK, VI0_DATA2_VI0_B2_MARK, RMII0_MDIO_A_MARK,
 431                 ET0_MDC_MARK,
 432         HTX0_A_MARK, TX1_A_MARK, VI0_DATA1_VI0_B1_MARK,
 433                 RMII0_MDC_A_MARK, ET0_COL_MARK,
 434         HRX0_A_MARK, RX1_A_MARK, VI0_DATA0_VI0_B0_MARK,
 435                 RMII0_CRS_DV_A_MARK, ET0_CRS_MARK,
 436         HSCK0_A_MARK, SCK1_A_MARK, VI0_VSYNC_MARK,
 437                 RMII0_RX_ER_A_MARK, ET0_RX_ER_MARK,
 438         HRTS0_A_MARK, RTS1_A_MARK, VI0_HSYNC_MARK,
 439                 RMII0_TXD_EN_A_MARK, ET0_RX_DV_MARK,
 440         HCTS0_A_MARK, CTS1_A_MARK, VI0_FIELD_MARK,
 441                 RMII0_RXD1_A_MARK, ET0_ERXD7_MARK,
 442
 443         /* IPSR5 */
 444         SD2_CLK_A_MARK, RX2_A_MARK, VI0_G4_MARK, ET0_RX_CLK_B_MARK,
 445         SD2_CMD_A_MARK, TX2_A_MARK, VI0_G5_MARK, ET0_ERXD2_B_MARK,
 446         SD2_DAT0_A_MARK, RX3_A_MARK, VI0_R0_MARK, ET0_ERXD3_B_MARK,
 447         SD2_DAT1_A_MARK, TX3_A_MARK, VI0_R1_MARK, ET0_MDIO_B_MARK,
 448         SD2_DAT2_A_MARK, RX4_A_MARK, VI0_R2_MARK, ET0_LINK_B_MARK,
 449         SD2_DAT3_A_MARK, TX4_A_MARK, VI0_R3_MARK, ET0_MAGIC_B_MARK,
 450         SD2_CD_A_MARK, RX5_A_MARK, VI0_R4_MARK, ET0_PHY_INT_B_MARK,
 451         SD2_WP_A_MARK, TX5_A_MARK, VI0_R5_MARK,
 452         REF125CK_MARK, ADTRG_MARK, RX5_C_MARK,
 453         REF50CK_MARK, CTS1_E_MARK, HCTS0_D_MARK,
 454
 455         /* IPSR6 */
 456         DU0_DR0_MARK, SCIF_CLK_B_MARK, HRX0_D_MARK, IETX_A_MARK,
 457                 TCLKA_A_MARK, HIFD00_MARK,
 458         DU0_DR1_MARK, SCK0_B_MARK, HTX0_D_MARK, IERX_A_MARK,
 459                 TCLKB_A_MARK, HIFD01_MARK,
 460         DU0_DR2_MARK, RX0_B_MARK, TCLKC_A_MARK, HIFD02_MARK,
 461         DU0_DR3_MARK, TX0_B_MARK, TCLKD_A_MARK, HIFD03_MARK,
 462         DU0_DR4_MARK, CTS0_C_MARK, TIOC0A_A_MARK, HIFD04_MARK,
 463         DU0_DR5_MARK, RTS0_C_MARK, TIOC0B_A_MARK, HIFD05_MARK,
 464         DU0_DR6_MARK, SCK1_C_MARK, TIOC0C_A_MARK, HIFD06_MARK,
 465         DU0_DR7_MARK, RX1_C_MARK, TIOC0D_A_MARK, HIFD07_MARK,
 466         DU0_DG0_MARK, TX1_C_MARK, HSCK0_D_MARK, IECLK_A_MARK,
 467                 TIOC1A_A_MARK, HIFD08_MARK,
 468         DU0_DG1_MARK, CTS1_C_MARK, HRTS0_D_MARK, TIOC1B_A_MARK,
 469                 HIFD09_MARK,
 470
 471         /* IPSR7 */
 472         DU0_DG2_MARK, RTS1_C_MARK, RMII0_MDC_B_MARK, TIOC2A_A_MARK,
 473                 HIFD10_MARK,
 474         DU0_DG3_MARK, SCK2_C_MARK, RMII0_MDIO_B_MARK, TIOC2B_A_MARK,
 475                 HIFD11_MARK,
 476         DU0_DG4_MARK, RX2_C_MARK, RMII0_CRS_DV_B_MARK, TIOC3A_A_MARK,
 477                 HIFD12_MARK,
 478         DU0_DG5_MARK, TX2_C_MARK, RMII0_RX_ER_B_MARK, TIOC3B_A_MARK,
 479                 HIFD13_MARK,
 480         DU0_DG6_MARK, RX3_C_MARK, RMII0_RXD0_B_MARK, TIOC3C_A_MARK,
 481                 HIFD14_MARK,
 482         DU0_DG7_MARK, TX3_C_MARK, RMII0_RXD1_B_MARK, TIOC3D_A_MARK,
 483                 HIFD15_MARK,
 484         DU0_DB0_MARK, RX4_C_MARK, RMII0_TXD_EN_B_MARK, TIOC4A_A_MARK,
 485                 HIFCS_MARK,
 486         DU0_DB1_MARK, TX4_C_MARK, RMII0_TXD0_B_MARK, TIOC4B_A_MARK,
 487                 HIFRS_MARK,
 488         DU0_DB2_MARK, RX5_B_MARK, RMII0_TXD1_B_MARK, TIOC4C_A_MARK,
 489                 HIFWR_MARK,
 490         DU0_DB3_MARK, TX5_B_MARK, TIOC4D_A_MARK, HIFRD_MARK,
 491         DU0_DB4_MARK, HIFINT_MARK,
 492
 493         /* IPSR8 */
 494         DU0_DB5_MARK, HIFDREQ_MARK,
 495         DU0_DB6_MARK, HIFRDY_MARK,
 496         DU0_DB7_MARK, SSI_SCK0_B_MARK, HIFEBL_B_MARK,
 497         DU0_DOTCLKIN_MARK, HSPI_CS0_C_MARK, SSI_WS0_B_MARK,
 498         DU0_DOTCLKOUT_MARK, HSPI_CLK0_C_MARK, SSI_SDATA0_B_MARK,
 499         DU0_EXHSYNC_DU0_HSYNC_MARK, HSPI_TX0_C_MARK, SSI_SCK1_B_MARK,
 500         DU0_EXVSYNC_DU0_VSYNC_MARK, HSPI_RX0_C_MARK, SSI_WS1_B_MARK,
 501         DU0_EXODDF_DU0_ODDF_MARK, CAN0_RX_B_MARK, HSCK0_B_MARK,
 502                 SSI_SDATA1_B_MARK,
 503         DU0_DISP_MARK, CAN0_TX_B_MARK, HRX0_B_MARK, AUDIO_CLKA_B_MARK,
 504         DU0_CDE_MARK, HTX0_B_MARK, AUDIO_CLKB_B_MARK, LCD_VCPWC_B_MARK,
 505         IRQ0_A_MARK, HSPI_TX_B_MARK, RX3_E_MARK, ET0_ERXD0_MARK,
 506         IRQ1_A_MARK, HSPI_RX_B_MARK, TX3_E_MARK, ET0_ERXD1_MARK,
 507         IRQ2_A_MARK, CTS0_A_MARK, HCTS0_B_MARK, ET0_ERXD2_A_MARK,
 508         IRQ3_A_MARK, RTS0_A_MARK, HRTS0_B_MARK, ET0_ERXD3_A_MARK,
 509
 510         /* IPSR9 */
 511         VI1_CLK_A_MARK, FD0_B_MARK, LCD_DATA0_B_MARK,
 512         VI1_0_A_MARK, FD1_B_MARK, LCD_DATA1_B_MARK,
 513         VI1_1_A_MARK, FD2_B_MARK, LCD_DATA2_B_MARK,
 514         VI1_2_A_MARK, FD3_B_MARK, LCD_DATA3_B_MARK,
 515         VI1_3_A_MARK, FD4_B_MARK, LCD_DATA4_B_MARK,
 516         VI1_4_A_MARK, FD5_B_MARK, LCD_DATA5_B_MARK,
 517         VI1_5_A_MARK, FD6_B_MARK, LCD_DATA6_B_MARK,
 518         VI1_6_A_MARK, FD7_B_MARK, LCD_DATA7_B_MARK,
 519         VI1_7_A_MARK, FCE_B_MARK, LCD_DATA8_B_MARK,
 520         SSI_SCK0_A_MARK, TIOC1A_B_MARK, LCD_DATA9_B_MARK,
 521         SSI_WS0_A_MARK, TIOC1B_B_MARK, LCD_DATA10_B_MARK,
 522         SSI_SDATA0_A_MARK, VI1_0_B_MARK, TIOC2A_B_MARK, LCD_DATA11_B_MARK,
 523         SSI_SCK1_A_MARK, VI1_1_B_MARK, TIOC2B_B_MARK, LCD_DATA12_B_MARK,
 524         SSI_WS1_A_MARK, VI1_2_B_MARK, LCD_DATA13_B_MARK,
 525         SSI_SDATA1_A_MARK, VI1_3_B_MARK, LCD_DATA14_B_MARK,
 526
 527         /* IPSR10 */
 528         SSI_SCK23_MARK, VI1_4_B_MARK, RX1_D_MARK, FCLE_B_MARK,
 529                 LCD_DATA15_B_MARK,
 530         SSI_WS23_MARK, VI1_5_B_MARK, TX1_D_MARK, HSCK0_C_MARK,
 531                 FALE_B_MARK, LCD_DON_B_MARK,
 532         SSI_SDATA2_MARK, VI1_6_B_MARK, HRX0_C_MARK, FRE_B_MARK,
 533                 LCD_CL1_B_MARK,
 534         SSI_SDATA3_MARK, VI1_7_B_MARK, HTX0_C_MARK, FWE_B_MARK,
 535                 LCD_CL2_B_MARK,
 536         AUDIO_CLKA_A_MARK, VI1_CLK_B_MARK, SCK1_D_MARK, IECLK_B_MARK,
 537                 LCD_FLM_B_MARK,
 538         AUDIO_CLKB_A_MARK, LCD_CLK_B_MARK,
 539         AUDIO_CLKC_MARK, SCK1_E_MARK, HCTS0_C_MARK, FRB_B_MARK,
 540                 LCD_VEPWC_B_MARK,
 541         AUDIO_CLKOUT_MARK, TX1_E_MARK, HRTS0_C_MARK, FSE_B_MARK,
 542                 LCD_M_DISP_B_MARK,
 543         CAN_CLK_A_MARK, RX4_D_MARK,
 544         CAN0_TX_A_MARK, TX4_D_MARK, MLB_CLK_MARK,
 545         CAN1_RX_A_MARK, IRQ1_B_MARK,
 546         CAN0_RX_A_MARK, IRQ0_B_MARK, MLB_SIG_MARK,
 547         CAN1_TX_A_MARK, TX5_C_MARK, MLB_DAT_MARK,
 548
 549         /* IPSR11 */
 550         SCL1_MARK, SCIF_CLK_C_MARK,
 551         SDA1_MARK, RX1_E_MARK,
 552         SDA0_MARK, HIFEBL_A_MARK,
 553         SDSELF_MARK, RTS1_E_MARK,
 554         SCIF_CLK_A_MARK, HSPI_CLK_A_MARK, VI0_CLK_MARK, RMII0_TXD0_A_MARK,
 555                 ET0_ERXD4_MARK,
 556         SCK0_A_MARK, HSPI_CS_A_MARK, VI0_CLKENB_MARK, RMII0_TXD1_A_MARK,
 557                 ET0_ERXD5_MARK,
 558         RX0_A_MARK, HSPI_RX_A_MARK, RMII0_RXD0_A_MARK, ET0_ERXD6_MARK,
 559         TX0_A_MARK, HSPI_TX_A_MARK,
 560         PENC1_MARK, TX3_D_MARK, CAN1_TX_B_MARK, TX5_D_MARK,
 561                 IETX_B_MARK,
 562         USB_OVC1_MARK, RX3_D_MARK, CAN1_RX_B_MARK, RX5_D_MARK,
 563                 IERX_B_MARK,
 564         DREQ0_MARK, SD1_CLK_A_MARK, ET0_TX_EN_MARK,
 565         DACK0_MARK, SD1_DAT3_A_MARK, ET0_TX_ER_MARK,
 566         DREQ1_MARK, HSPI_CLK_B_MARK, RX4_B_MARK, ET0_PHY_INT_C_MARK,
 567                 ET0_TX_CLK_A_MARK,
 568         DACK1_MARK, HSPI_CS_B_MARK, TX4_B_MARK, ET0_RX_CLK_A_MARK,
 569         PRESETOUT_MARK, ST_CLKOUT_MARK,
 570
 571         PINMUX_MARK_END,
 572 };
 573
 574 static const u16 pinmux_data[] = {
 575         PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
 576
 577         PINMUX_SINGLE(CLKOUT),
 578         PINMUX_SINGLE(BS),
 579         PINMUX_SINGLE(CS0),
 580         PINMUX_SINGLE(EX_CS0),
 581         PINMUX_SINGLE(RD),
 582         PINMUX_SINGLE(WE0),
 583         PINMUX_SINGLE(WE1),
 584         PINMUX_SINGLE(SCL0),
 585         PINMUX_SINGLE(PENC0),
 586         PINMUX_SINGLE(USB_OVC0),
 587         PINMUX_SINGLE(IRQ2_B),
 588         PINMUX_SINGLE(IRQ3_B),
 589
 590         /* IPSR0 */
 591         PINMUX_IPSR_GPSR(IP0_1_0, A0),
 592         PINMUX_IPSR_GPSR(IP0_1_0, ST0_CLKIN),
 593         PINMUX_IPSR_MSEL(IP0_1_0, LCD_DATA0_A, SEL_LCDC_0),
 594         PINMUX_IPSR_MSEL(IP0_1_0, TCLKA_C, SEL_MTU2_CLK_1),
 595
 596         PINMUX_IPSR_GPSR(IP0_3_2, A1),
 597         PINMUX_IPSR_GPSR(IP0_3_2, ST0_REQ),
 598         PINMUX_IPSR_MSEL(IP0_3_2, LCD_DATA1_A, SEL_LCDC_0),
 599         PINMUX_IPSR_MSEL(IP0_3_2, TCLKB_C, SEL_MTU2_CLK_1),
 600
 601         PINMUX_IPSR_GPSR(IP0_5_4, A2),
 602         PINMUX_IPSR_GPSR(IP0_5_4, ST0_SYC),
 603         PINMUX_IPSR_MSEL(IP0_5_4, LCD_DATA2_A, SEL_LCDC_0),
 604         PINMUX_IPSR_MSEL(IP0_5_4, TCLKC_C, SEL_MTU2_CLK_1),
 605
 606         PINMUX_IPSR_GPSR(IP0_7_6, A3),
 607         PINMUX_IPSR_GPSR(IP0_7_6, ST0_VLD),
 608         PINMUX_IPSR_MSEL(IP0_7_6, LCD_DATA3_A, SEL_LCDC_0),
 609         PINMUX_IPSR_MSEL(IP0_7_6, TCLKD_C, SEL_MTU2_CLK_1),
 610
 611         PINMUX_IPSR_GPSR(IP0_9_8, A4),
 612         PINMUX_IPSR_GPSR(IP0_9_8, ST0_D0),
 613         PINMUX_IPSR_MSEL(IP0_9_8, LCD_DATA4_A, SEL_LCDC_0),
 614         PINMUX_IPSR_MSEL(IP0_9_8, TIOC0A_C, SEL_MTU2_CH0_1),
 615
 616         PINMUX_IPSR_GPSR(IP0_11_10, A5),
 617         PINMUX_IPSR_GPSR(IP0_11_10, ST0_D1),
 618         PINMUX_IPSR_MSEL(IP0_11_10, LCD_DATA5_A, SEL_LCDC_0),
 619         PINMUX_IPSR_MSEL(IP0_11_10, TIOC0B_C, SEL_MTU2_CH0_1),
 620
 621         PINMUX_IPSR_GPSR(IP0_13_12, A6),
 622         PINMUX_IPSR_GPSR(IP0_13_12, ST0_D2),
 623         PINMUX_IPSR_MSEL(IP0_13_12, LCD_DATA6_A, SEL_LCDC_0),
 624         PINMUX_IPSR_MSEL(IP0_13_12, TIOC0C_C, SEL_MTU2_CH0_1),
 625
 626         PINMUX_IPSR_GPSR(IP0_15_14, A7),
 627         PINMUX_IPSR_GPSR(IP0_15_14, ST0_D3),
 628         PINMUX_IPSR_MSEL(IP0_15_14, LCD_DATA7_A, SEL_LCDC_0),
 629         PINMUX_IPSR_MSEL(IP0_15_14, TIOC0D_C, SEL_MTU2_CH0_1),
 630
 631         PINMUX_IPSR_GPSR(IP0_17_16, A8),
 632         PINMUX_IPSR_GPSR(IP0_17_16, ST0_D4),
 633         PINMUX_IPSR_MSEL(IP0_17_16, LCD_DATA8_A, SEL_LCDC_0),
 634         PINMUX_IPSR_MSEL(IP0_17_16, TIOC1A_C, SEL_MTU2_CH1_2),
 635
 636         PINMUX_IPSR_GPSR(IP0_19_18, A9),
 637         PINMUX_IPSR_GPSR(IP0_19_18, ST0_D5),
 638         PINMUX_IPSR_MSEL(IP0_19_18, LCD_DATA9_A, SEL_LCDC_0),
 639         PINMUX_IPSR_MSEL(IP0_19_18, TIOC1B_C, SEL_MTU2_CH1_2),
 640
 641         PINMUX_IPSR_GPSR(IP0_21_20, A10),
 642         PINMUX_IPSR_GPSR(IP0_21_20, ST0_D6),
 643         PINMUX_IPSR_MSEL(IP0_21_20, LCD_DATA10_A, SEL_LCDC_0),
 644         PINMUX_IPSR_MSEL(IP0_21_20, TIOC2A_C, SEL_MTU2_CH2_2),
 645
 646         PINMUX_IPSR_GPSR(IP0_23_22, A11),
 647         PINMUX_IPSR_GPSR(IP0_23_22, ST0_D7),
 648         PINMUX_IPSR_MSEL(IP0_23_22, LCD_DATA11_A, SEL_LCDC_0),
 649         PINMUX_IPSR_MSEL(IP0_23_22, TIOC2B_C, SEL_MTU2_CH2_2),
 650
 651         PINMUX_IPSR_GPSR(IP0_25_24, A12),
 652         PINMUX_IPSR_MSEL(IP0_25_24, LCD_DATA12_A, SEL_LCDC_0),
 653         PINMUX_IPSR_MSEL(IP0_25_24, TIOC3A_C, SEL_MTU2_CH3_1),
 654
 655         PINMUX_IPSR_GPSR(IP0_27_26, A13),
 656         PINMUX_IPSR_MSEL(IP0_27_26, LCD_DATA13_A, SEL_LCDC_0),
 657         PINMUX_IPSR_MSEL(IP0_27_26, TIOC3B_C, SEL_MTU2_CH3_1),
 658
 659         PINMUX_IPSR_GPSR(IP0_29_28, A14),
 660         PINMUX_IPSR_MSEL(IP0_29_28, LCD_DATA14_A, SEL_LCDC_0),
 661         PINMUX_IPSR_MSEL(IP0_29_28, TIOC3C_C, SEL_MTU2_CH3_1),
 662
 663         PINMUX_IPSR_GPSR(IP0_31_30, A15),
 664         PINMUX_IPSR_GPSR(IP0_31_30, ST0_VCO_CLKIN),
 665         PINMUX_IPSR_MSEL(IP0_31_30, LCD_DATA15_A, SEL_LCDC_0),
 666         PINMUX_IPSR_MSEL(IP0_31_30, TIOC3D_C, SEL_MTU2_CH3_1),
 667
 668
 669         /* IPSR1 */
 670         PINMUX_IPSR_GPSR(IP1_1_0, A16),
 671         PINMUX_IPSR_GPSR(IP1_1_0, ST0_PWM),
 672         PINMUX_IPSR_MSEL(IP1_1_0, LCD_DON_A, SEL_LCDC_0),
 673         PINMUX_IPSR_MSEL(IP1_1_0, TIOC4A_C, SEL_MTU2_CH4_1),
 674
 675         PINMUX_IPSR_GPSR(IP1_3_2, A17),
 676         PINMUX_IPSR_GPSR(IP1_3_2, ST1_VCO_CLKIN),
 677         PINMUX_IPSR_MSEL(IP1_3_2, LCD_CL1_A, SEL_LCDC_0),
 678         PINMUX_IPSR_MSEL(IP1_3_2, TIOC4B_C, SEL_MTU2_CH4_1),
 679
 680         PINMUX_IPSR_GPSR(IP1_5_4, A18),
 681         PINMUX_IPSR_GPSR(IP1_5_4, ST1_PWM),
 682         PINMUX_IPSR_MSEL(IP1_5_4, LCD_CL2_A, SEL_LCDC_0),
 683         PINMUX_IPSR_MSEL(IP1_5_4, TIOC4C_C, SEL_MTU2_CH4_1),
 684
 685         PINMUX_IPSR_GPSR(IP1_7_6, A19),
 686         PINMUX_IPSR_GPSR(IP1_7_6, ST1_CLKIN),
 687         PINMUX_IPSR_MSEL(IP1_7_6, LCD_CLK_A, SEL_LCDC_0),
 688         PINMUX_IPSR_MSEL(IP1_7_6, TIOC4D_C, SEL_MTU2_CH4_1),
 689
 690         PINMUX_IPSR_GPSR(IP1_9_8, A20),
 691         PINMUX_IPSR_GPSR(IP1_9_8, ST1_REQ),
 692         PINMUX_IPSR_MSEL(IP1_9_8, LCD_FLM_A, SEL_LCDC_0),
 693
 694         PINMUX_IPSR_GPSR(IP1_11_10, A21),
 695         PINMUX_IPSR_GPSR(IP1_11_10, ST1_SYC),
 696         PINMUX_IPSR_MSEL(IP1_11_10, LCD_VCPWC_A, SEL_LCDC_0),
 697
 698         PINMUX_IPSR_GPSR(IP1_13_12, A22),
 699         PINMUX_IPSR_GPSR(IP1_13_12, ST1_VLD),
 700         PINMUX_IPSR_MSEL(IP1_13_12, LCD_VEPWC_A, SEL_LCDC_0),
 701
 702         PINMUX_IPSR_GPSR(IP1_15_14, A23),
 703         PINMUX_IPSR_GPSR(IP1_15_14, ST1_D0),
 704         PINMUX_IPSR_MSEL(IP1_15_14, LCD_M_DISP_A, SEL_LCDC_0),
 705
 706         PINMUX_IPSR_GPSR(IP1_17_16, A24),
 707         PINMUX_IPSR_MSEL(IP1_17_16, RX2_D, SEL_SCIF2_3),
 708         PINMUX_IPSR_GPSR(IP1_17_16, ST1_D1),
 709
 710         PINMUX_IPSR_GPSR(IP1_19_18, A25),
 711         PINMUX_IPSR_MSEL(IP1_17_16, RX2_D, SEL_SCIF2_3),
 712         PINMUX_IPSR_GPSR(IP1_17_16, ST1_D2),
 713
 714         PINMUX_IPSR_GPSR(IP1_22_20, D0),
 715         PINMUX_IPSR_MSEL(IP1_22_20, SD0_DAT0_A, SEL_SDHI0_0),
 716         PINMUX_IPSR_MSEL(IP1_22_20, MMC_D0_A, SEL_MMC_0),
 717         PINMUX_IPSR_GPSR(IP1_22_20, ST1_D3),
 718         PINMUX_IPSR_MSEL(IP1_22_20, FD0_A, SEL_FLCTL_0),
 719
 720         PINMUX_IPSR_GPSR(IP1_25_23, D1),
 721         PINMUX_IPSR_MSEL(IP1_25_23, SD0_DAT0_A, SEL_SDHI0_0),
 722         PINMUX_IPSR_MSEL(IP1_25_23, MMC_D1_A, SEL_MMC_0),
 723         PINMUX_IPSR_GPSR(IP1_25_23, ST1_D4),
 724         PINMUX_IPSR_MSEL(IP1_25_23, FD1_A, SEL_FLCTL_0),
 725
 726         PINMUX_IPSR_GPSR(IP1_28_26, D2),
 727         PINMUX_IPSR_MSEL(IP1_28_26, SD0_DAT0_A, SEL_SDHI0_0),
 728         PINMUX_IPSR_MSEL(IP1_28_26, MMC_D2_A, SEL_MMC_0),
 729         PINMUX_IPSR_GPSR(IP1_28_26, ST1_D5),
 730         PINMUX_IPSR_MSEL(IP1_28_26, FD2_A, SEL_FLCTL_0),
 731
 732         PINMUX_IPSR_GPSR(IP1_31_29, D3),
 733         PINMUX_IPSR_MSEL(IP1_31_29, SD0_DAT0_A, SEL_SDHI0_0),
 734         PINMUX_IPSR_MSEL(IP1_31_29, MMC_D3_A, SEL_MMC_0),
 735         PINMUX_IPSR_GPSR(IP1_31_29, ST1_D6),
 736         PINMUX_IPSR_MSEL(IP1_31_29, FD3_A, SEL_FLCTL_0),
 737
 738         /* IPSR2 */
 739         PINMUX_IPSR_GPSR(IP2_2_0, D4),
 740         PINMUX_IPSR_MSEL(IP2_2_0, SD0_CD_A, SEL_SDHI0_0),
 741         PINMUX_IPSR_MSEL(IP2_2_0, MMC_D4_A, SEL_MMC_0),
 742         PINMUX_IPSR_GPSR(IP2_2_0, ST1_D7),
 743         PINMUX_IPSR_MSEL(IP2_2_0, FD4_A, SEL_FLCTL_0),
 744
 745         PINMUX_IPSR_GPSR(IP2_4_3, D5),
 746         PINMUX_IPSR_MSEL(IP2_4_3, SD0_WP_A, SEL_SDHI0_0),
 747         PINMUX_IPSR_MSEL(IP2_4_3, MMC_D5_A, SEL_MMC_0),
 748         PINMUX_IPSR_MSEL(IP2_4_3, FD5_A, SEL_FLCTL_0),
 749
 750         PINMUX_IPSR_GPSR(IP2_7_5, D6),
 751         PINMUX_IPSR_MSEL(IP2_7_5, RSPI_RSPCK_A, SEL_RSPI_0),
 752         PINMUX_IPSR_MSEL(IP2_7_5, MMC_D6_A, SEL_MMC_0),
 753         PINMUX_IPSR_MSEL(IP2_7_5, QSPCLK_A, SEL_RQSPI_0),
 754         PINMUX_IPSR_MSEL(IP2_7_5, FD6_A, SEL_FLCTL_0),
 755
 756         PINMUX_IPSR_GPSR(IP2_10_8, D7),
 757         PINMUX_IPSR_MSEL(IP2_10_8, RSPI_SSL_A, SEL_RSPI_0),
 758         PINMUX_IPSR_MSEL(IP2_10_8, MMC_D7_A, SEL_MMC_0),
 759         PINMUX_IPSR_MSEL(IP2_10_8, QSSL_A, SEL_RQSPI_0),
 760         PINMUX_IPSR_MSEL(IP2_10_8, FD7_A, SEL_FLCTL_0),
 761
 762         PINMUX_IPSR_GPSR(IP2_13_11, D8),
 763         PINMUX_IPSR_MSEL(IP2_13_11, SD0_CLK_A, SEL_SDHI0_0),
 764         PINMUX_IPSR_MSEL(IP2_13_11, MMC_CLK_A, SEL_MMC_0),
 765         PINMUX_IPSR_MSEL(IP2_13_11, QIO2_A, SEL_RQSPI_0),
 766         PINMUX_IPSR_MSEL(IP2_13_11, FCE_A, SEL_FLCTL_0),
 767         PINMUX_IPSR_MSEL(IP2_13_11, ET0_GTX_CLK_B, SEL_ET0_1),
 768
 769         PINMUX_IPSR_GPSR(IP2_16_14, D9),
 770         PINMUX_IPSR_MSEL(IP2_16_14, SD0_CMD_A, SEL_SDHI0_0),
 771         PINMUX_IPSR_MSEL(IP2_16_14, MMC_CMD_A, SEL_MMC_0),
 772         PINMUX_IPSR_MSEL(IP2_16_14, QIO3_A, SEL_RQSPI_0),
 773         PINMUX_IPSR_MSEL(IP2_16_14, FCLE_A, SEL_FLCTL_0),
 774         PINMUX_IPSR_MSEL(IP2_16_14, ET0_ETXD1_B, SEL_ET0_1),
 775
 776         PINMUX_IPSR_GPSR(IP2_19_17, D10),
 777         PINMUX_IPSR_MSEL(IP2_19_17, RSPI_MOSI_A, SEL_RSPI_0),
 778         PINMUX_IPSR_MSEL(IP2_19_17, QMO_QIO0_A, SEL_RQSPI_0),
 779         PINMUX_IPSR_MSEL(IP2_19_17, FALE_A, SEL_FLCTL_0),
 780         PINMUX_IPSR_MSEL(IP2_19_17, ET0_ETXD2_B, SEL_ET0_1),
 781
 782         PINMUX_IPSR_GPSR(IP2_22_20, D11),
 783         PINMUX_IPSR_MSEL(IP2_22_20, RSPI_MISO_A, SEL_RSPI_0),
 784         PINMUX_IPSR_MSEL(IP2_22_20, QMI_QIO1_A, SEL_RQSPI_0),
 785         PINMUX_IPSR_MSEL(IP2_22_20, FRE_A, SEL_FLCTL_0),
 786
 787         PINMUX_IPSR_GPSR(IP2_24_23, D12),
 788         PINMUX_IPSR_MSEL(IP2_24_23, FWE_A, SEL_FLCTL_0),
 789         PINMUX_IPSR_MSEL(IP2_24_23, ET0_ETXD5_B, SEL_ET0_1),
 790
 791         PINMUX_IPSR_GPSR(IP2_27_25, D13),
 792         PINMUX_IPSR_MSEL(IP2_27_25, RX2_B, SEL_SCIF2_1),
 793         PINMUX_IPSR_MSEL(IP2_27_25, FRB_A, SEL_FLCTL_0),
 794         PINMUX_IPSR_MSEL(IP2_27_25, ET0_ETXD6_B, SEL_ET0_1),
 795
 796         PINMUX_IPSR_GPSR(IP2_30_28, D14),
 797         PINMUX_IPSR_MSEL(IP2_30_28, TX2_B, SEL_SCIF2_1),
 798         PINMUX_IPSR_MSEL(IP2_30_28, FSE_A, SEL_FLCTL_0),
 799         PINMUX_IPSR_MSEL(IP2_30_28, ET0_TX_CLK_B, SEL_ET0_1),
 800
 801         /* IPSR3 */
 802         PINMUX_IPSR_GPSR(IP3_1_0, D15),
 803         PINMUX_IPSR_MSEL(IP3_1_0, SCK2_B, SEL_SCIF2_1),
 804
 805         PINMUX_IPSR_GPSR(IP3_2, CS1_A26),
 806         PINMUX_IPSR_MSEL(IP3_2, QIO3_B, SEL_RQSPI_1),
 807
 808         PINMUX_IPSR_GPSR(IP3_5_3, EX_CS1),
 809         PINMUX_IPSR_MSEL(IP3_5_3, RX3_B, SEL_SCIF2_1),
 810         PINMUX_IPSR_GPSR(IP3_5_3, ATACS0),
 811         PINMUX_IPSR_MSEL(IP3_5_3, QIO2_B, SEL_RQSPI_1),
 812         PINMUX_IPSR_GPSR(IP3_5_3, ET0_ETXD0),
 813
 814         PINMUX_IPSR_GPSR(IP3_8_6, EX_CS2),
 815         PINMUX_IPSR_MSEL(IP3_8_6, TX3_B, SEL_SCIF3_1),
 816         PINMUX_IPSR_GPSR(IP3_8_6, ATACS1),
 817         PINMUX_IPSR_MSEL(IP3_8_6, QSPCLK_B, SEL_RQSPI_1),
 818         PINMUX_IPSR_MSEL(IP3_8_6, ET0_GTX_CLK_A, SEL_ET0_0),
 819
 820         PINMUX_IPSR_GPSR(IP3_11_9, EX_CS3),
 821         PINMUX_IPSR_MSEL(IP3_11_9, SD1_CD_A, SEL_SDHI1_0),
 822         PINMUX_IPSR_GPSR(IP3_11_9, ATARD),
 823         PINMUX_IPSR_MSEL(IP3_11_9, QMO_QIO0_B, SEL_RQSPI_1),
 824         PINMUX_IPSR_MSEL(IP3_11_9, ET0_ETXD1_A, SEL_ET0_0),
 825
 826         PINMUX_IPSR_GPSR(IP3_14_12, EX_CS4),
 827         PINMUX_IPSR_MSEL(IP3_14_12, SD1_WP_A, SEL_SDHI1_0),
 828         PINMUX_IPSR_GPSR(IP3_14_12, ATAWR),
 829         PINMUX_IPSR_MSEL(IP3_14_12, QMI_QIO1_B, SEL_RQSPI_1),
 830         PINMUX_IPSR_MSEL(IP3_14_12, ET0_ETXD2_A, SEL_ET0_0),
 831
 832         PINMUX_IPSR_GPSR(IP3_17_15, EX_CS5),
 833         PINMUX_IPSR_MSEL(IP3_17_15, SD1_CMD_A, SEL_SDHI1_0),
 834         PINMUX_IPSR_GPSR(IP3_17_15, ATADIR),
 835         PINMUX_IPSR_MSEL(IP3_17_15, QSSL_B, SEL_RQSPI_1),
 836         PINMUX_IPSR_MSEL(IP3_17_15, ET0_ETXD3_A, SEL_ET0_0),
 837
 838         PINMUX_IPSR_GPSR(IP3_19_18, RD_WR),
 839         PINMUX_IPSR_GPSR(IP3_19_18, TCLK0),
 840         PINMUX_IPSR_MSEL(IP3_19_18, CAN_CLK_B, SEL_RCAN_CLK_1),
 841         PINMUX_IPSR_GPSR(IP3_19_18, ET0_ETXD4),
 842
 843         PINMUX_IPSR_GPSR(IP3_20, EX_WAIT0),
 844         PINMUX_IPSR_MSEL(IP3_20, TCLK1_B, SEL_TMU_1),
 845
 846         PINMUX_IPSR_GPSR(IP3_23_21, EX_WAIT1),
 847         PINMUX_IPSR_MSEL(IP3_23_21, SD1_DAT0_A, SEL_SDHI1_0),
 848         PINMUX_IPSR_GPSR(IP3_23_21, DREQ2),
 849         PINMUX_IPSR_MSEL(IP3_23_21, CAN1_TX_C, SEL_RCAN1_2),
 850         PINMUX_IPSR_MSEL(IP3_23_21, ET0_LINK_C, SEL_ET0_CTL_2),
 851         PINMUX_IPSR_MSEL(IP3_23_21, ET0_ETXD5_A, SEL_ET0_0),
 852
 853         PINMUX_IPSR_GPSR(IP3_26_24, EX_WAIT2),
 854         PINMUX_IPSR_MSEL(IP3_26_24, SD1_DAT1_A, SEL_SDHI1_0),
 855         PINMUX_IPSR_GPSR(IP3_26_24, DACK2),
 856         PINMUX_IPSR_MSEL(IP3_26_24, CAN1_RX_C, SEL_RCAN1_2),
 857         PINMUX_IPSR_MSEL(IP3_26_24, ET0_MAGIC_C, SEL_ET0_CTL_2),
 858         PINMUX_IPSR_MSEL(IP3_26_24, ET0_ETXD6_A, SEL_ET0_0),
 859
 860         PINMUX_IPSR_GPSR(IP3_29_27, DRACK0),
 861         PINMUX_IPSR_MSEL(IP3_29_27, SD1_DAT2_A, SEL_SDHI1_0),
 862         PINMUX_IPSR_GPSR(IP3_29_27, ATAG),
 863         PINMUX_IPSR_MSEL(IP3_29_27, TCLK1_A, SEL_TMU_0),
 864         PINMUX_IPSR_GPSR(IP3_29_27, ET0_ETXD7),
 865
 866         /* IPSR4 */
 867         PINMUX_IPSR_MSEL(IP4_2_0, HCTS0_A, SEL_HSCIF_0),
 868         PINMUX_IPSR_MSEL(IP4_2_0, CTS1_A, SEL_SCIF1_0),
 869         PINMUX_IPSR_GPSR(IP4_2_0, VI0_FIELD),
 870         PINMUX_IPSR_MSEL(IP4_2_0, RMII0_RXD1_A, SEL_RMII_0),
 871         PINMUX_IPSR_GPSR(IP4_2_0, ET0_ERXD7),
 872
 873         PINMUX_IPSR_MSEL(IP4_5_3, HRTS0_A, SEL_HSCIF_0),
 874         PINMUX_IPSR_MSEL(IP4_5_3, RTS1_A, SEL_SCIF1_0),
 875         PINMUX_IPSR_GPSR(IP4_5_3, VI0_HSYNC),
 876         PINMUX_IPSR_MSEL(IP4_5_3, RMII0_TXD_EN_A, SEL_RMII_0),
 877         PINMUX_IPSR_GPSR(IP4_5_3, ET0_RX_DV),
 878
 879         PINMUX_IPSR_MSEL(IP4_8_6, HSCK0_A, SEL_HSCIF_0),
 880         PINMUX_IPSR_MSEL(IP4_8_6, SCK1_A, SEL_SCIF1_0),
 881         PINMUX_IPSR_GPSR(IP4_8_6, VI0_VSYNC),
 882         PINMUX_IPSR_MSEL(IP4_8_6, RMII0_RX_ER_A, SEL_RMII_0),
 883         PINMUX_IPSR_GPSR(IP4_8_6, ET0_RX_ER),
 884
 885         PINMUX_IPSR_MSEL(IP4_11_9, HRX0_A, SEL_HSCIF_0),
 886         PINMUX_IPSR_MSEL(IP4_11_9, RX1_A, SEL_SCIF1_0),
 887         PINMUX_IPSR_GPSR(IP4_11_9, VI0_DATA0_VI0_B0),
 888         PINMUX_IPSR_MSEL(IP4_11_9, RMII0_CRS_DV_A, SEL_RMII_0),
 889         PINMUX_IPSR_GPSR(IP4_11_9, ET0_CRS),
 890
 891         PINMUX_IPSR_MSEL(IP4_14_12, HTX0_A, SEL_HSCIF_0),
 892         PINMUX_IPSR_MSEL(IP4_14_12, TX1_A, SEL_SCIF1_0),
 893         PINMUX_IPSR_GPSR(IP4_14_12, VI0_DATA1_VI0_B1),
 894         PINMUX_IPSR_MSEL(IP4_14_12, RMII0_MDC_A, SEL_RMII_0),
 895         PINMUX_IPSR_GPSR(IP4_14_12, ET0_COL),
 896
 897         PINMUX_IPSR_MSEL(IP4_17_15, CTS0_B, SEL_SCIF0_1),
 898         PINMUX_IPSR_GPSR(IP4_17_15, VI0_DATA2_VI0_B2),
 899         PINMUX_IPSR_MSEL(IP4_17_15, RMII0_MDIO_A, SEL_RMII_0),
 900         PINMUX_IPSR_GPSR(IP4_17_15, ET0_MDC),
 901
 902         PINMUX_IPSR_MSEL(IP4_19_18, RTS0_B, SEL_SCIF0_1),
 903         PINMUX_IPSR_GPSR(IP4_19_18, VI0_DATA3_VI0_B3),
 904         PINMUX_IPSR_MSEL(IP4_19_18, ET0_MDIO_A, SEL_ET0_0),
 905
 906         PINMUX_IPSR_MSEL(IP4_21_20, SCK1_B, SEL_SCIF1_1),
 907         PINMUX_IPSR_GPSR(IP4_21_20, VI0_DATA4_VI0_B4),
 908         PINMUX_IPSR_MSEL(IP4_21_20, ET0_LINK_A, SEL_ET0_CTL_0),
 909
 910         PINMUX_IPSR_MSEL(IP4_23_22, RX1_B, SEL_SCIF1_1),
 911         PINMUX_IPSR_GPSR(IP4_23_22, VI0_DATA5_VI0_B5),
 912         PINMUX_IPSR_MSEL(IP4_23_22, ET0_MAGIC_A, SEL_ET0_CTL_0),
 913
 914         PINMUX_IPSR_MSEL(IP4_25_24, TX1_B, SEL_SCIF1_1),
 915         PINMUX_IPSR_GPSR(IP4_25_24, VI0_DATA6_VI0_G0),
 916         PINMUX_IPSR_MSEL(IP4_25_24, ET0_PHY_INT_A, SEL_ET0_CTL_0),
 917
 918         PINMUX_IPSR_MSEL(IP4_27_26, CTS1_B, SEL_SCIF1_1),
 919         PINMUX_IPSR_GPSR(IP4_27_26, VI0_DATA7_VI0_G1),
 920
 921         PINMUX_IPSR_MSEL(IP4_29_28, RTS1_B, SEL_SCIF1_1),
 922         PINMUX_IPSR_GPSR(IP4_29_28, VI0_G2),
 923
 924         PINMUX_IPSR_MSEL(IP4_31_30, SCK2_A, SEL_SCIF2_0),
 925         PINMUX_IPSR_GPSR(IP4_31_30, VI0_G3),
 926
 927         /* IPSR5 */
 928         PINMUX_IPSR_MSEL(IP5_2_0, SD2_CLK_A, SEL_SDHI2_0),
 929         PINMUX_IPSR_MSEL(IP5_2_0, RX2_A, SEL_SCIF2_0),
 930         PINMUX_IPSR_GPSR(IP5_2_0, VI0_G4),
 931         PINMUX_IPSR_MSEL(IP5_2_0, ET0_RX_CLK_B, SEL_ET0_1),
 932
 933         PINMUX_IPSR_MSEL(IP5_5_3, SD2_CMD_A, SEL_SDHI2_0),
 934         PINMUX_IPSR_MSEL(IP5_5_3, TX2_A, SEL_SCIF2_0),
 935         PINMUX_IPSR_GPSR(IP5_5_3, VI0_G5),
 936         PINMUX_IPSR_MSEL(IP5_5_3, ET0_ERXD2_B, SEL_ET0_1),
 937
 938         PINMUX_IPSR_MSEL(IP5_8_6, SD2_DAT0_A, SEL_SDHI2_0),
 939         PINMUX_IPSR_MSEL(IP5_8_6, RX3_A, SEL_SCIF3_0),
 940         PINMUX_IPSR_GPSR(IP4_8_6, VI0_R0),
 941         PINMUX_IPSR_MSEL(IP4_8_6, ET0_ERXD2_B, SEL_ET0_1),
 942
 943         PINMUX_IPSR_MSEL(IP5_11_9, SD2_DAT1_A, SEL_SDHI2_0),
 944         PINMUX_IPSR_MSEL(IP5_11_9, TX3_A, SEL_SCIF3_0),
 945         PINMUX_IPSR_GPSR(IP5_11_9, VI0_R1),
 946         PINMUX_IPSR_MSEL(IP5_11_9, ET0_MDIO_B, SEL_ET0_1),
 947
 948         PINMUX_IPSR_MSEL(IP5_14_12, SD2_DAT2_A, SEL_SDHI2_0),
 949         PINMUX_IPSR_MSEL(IP5_14_12, RX4_A, SEL_SCIF4_0),
 950         PINMUX_IPSR_GPSR(IP5_14_12, VI0_R2),
 951         PINMUX_IPSR_MSEL(IP5_14_12, ET0_LINK_B, SEL_ET0_CTL_1),
 952
 953         PINMUX_IPSR_MSEL(IP5_17_15, SD2_DAT3_A, SEL_SDHI2_0),
 954         PINMUX_IPSR_MSEL(IP5_17_15, TX4_A, SEL_SCIF4_0),
 955         PINMUX_IPSR_GPSR(IP5_17_15, VI0_R3),
 956         PINMUX_IPSR_MSEL(IP5_17_15, ET0_MAGIC_B, SEL_ET0_CTL_1),
 957
 958         PINMUX_IPSR_MSEL(IP5_20_18, SD2_CD_A, SEL_SDHI2_0),
 959         PINMUX_IPSR_MSEL(IP5_20_18, RX5_A, SEL_SCIF5_0),
 960         PINMUX_IPSR_GPSR(IP5_20_18, VI0_R4),
 961         PINMUX_IPSR_MSEL(IP5_20_18, ET0_PHY_INT_B, SEL_ET0_CTL_1),
 962
 963         PINMUX_IPSR_MSEL(IP5_22_21, SD2_WP_A, SEL_SDHI2_0),
 964         PINMUX_IPSR_MSEL(IP5_22_21, TX5_A, SEL_SCIF5_0),
 965         PINMUX_IPSR_GPSR(IP5_22_21, VI0_R5),
 966
 967         PINMUX_IPSR_GPSR(IP5_24_23, REF125CK),
 968         PINMUX_IPSR_GPSR(IP5_24_23, ADTRG),
 969         PINMUX_IPSR_MSEL(IP5_24_23, RX5_C, SEL_SCIF5_2),
 970         PINMUX_IPSR_GPSR(IP5_26_25, REF50CK),
 971         PINMUX_IPSR_MSEL(IP5_26_25, CTS1_E, SEL_SCIF1_3),
 972         PINMUX_IPSR_MSEL(IP5_26_25, HCTS0_D, SEL_HSCIF_3),
 973
 974         /* IPSR6 */
 975         PINMUX_IPSR_GPSR(IP6_2_0, DU0_DR0),
 976         PINMUX_IPSR_MSEL(IP6_2_0, SCIF_CLK_B, SEL_SCIF_CLK_1),
 977         PINMUX_IPSR_MSEL(IP6_2_0, HRX0_D, SEL_HSCIF_3),
 978         PINMUX_IPSR_MSEL(IP6_2_0, IETX_A, SEL_IEBUS_0),
 979         PINMUX_IPSR_MSEL(IP6_2_0, TCLKA_A, SEL_MTU2_CLK_0),
 980         PINMUX_IPSR_GPSR(IP6_2_0, HIFD00),
 981
 982         PINMUX_IPSR_GPSR(IP6_5_3, DU0_DR1),
 983         PINMUX_IPSR_MSEL(IP6_5_3, SCK0_B, SEL_SCIF0_1),
 984         PINMUX_IPSR_MSEL(IP6_5_3, HTX0_D, SEL_HSCIF_3),
 985         PINMUX_IPSR_MSEL(IP6_5_3, IERX_A, SEL_IEBUS_0),
 986         PINMUX_IPSR_MSEL(IP6_5_3, TCLKB_A, SEL_MTU2_CLK_0),
 987         PINMUX_IPSR_GPSR(IP6_5_3, HIFD01),
 988
 989         PINMUX_IPSR_GPSR(IP6_7_6, DU0_DR2),
 990         PINMUX_IPSR_MSEL(IP6_7_6, RX0_B, SEL_SCIF0_1),
 991         PINMUX_IPSR_MSEL(IP6_7_6, TCLKC_A, SEL_MTU2_CLK_0),
 992         PINMUX_IPSR_GPSR(IP6_7_6, HIFD02),
 993
 994         PINMUX_IPSR_GPSR(IP6_9_8, DU0_DR3),
 995         PINMUX_IPSR_MSEL(IP6_9_8, TX0_B, SEL_SCIF0_1),
 996         PINMUX_IPSR_MSEL(IP6_9_8, TCLKD_A, SEL_MTU2_CLK_0),
 997         PINMUX_IPSR_GPSR(IP6_9_8, HIFD03),
 998
 999         PINMUX_IPSR_GPSR(IP6_11_10, DU0_DR4),
1000         PINMUX_IPSR_MSEL(IP6_11_10, CTS0_C, SEL_SCIF0_2),
1001         PINMUX_IPSR_MSEL(IP6_11_10, TIOC0A_A, SEL_MTU2_CH0_0),
1002         PINMUX_IPSR_GPSR(IP6_11_10, HIFD04),
1003
1004         PINMUX_IPSR_GPSR(IP6_13_12, DU0_DR5),
1005         PINMUX_IPSR_MSEL(IP6_13_12, RTS0_C, SEL_SCIF0_1),
1006         PINMUX_IPSR_MSEL(IP6_13_12, TIOC0B_A, SEL_MTU2_CH0_0),
1007         PINMUX_IPSR_GPSR(IP6_13_12, HIFD05),
1008
1009         PINMUX_IPSR_GPSR(IP6_15_14, DU0_DR6),
1010         PINMUX_IPSR_MSEL(IP6_15_14, SCK1_C, SEL_SCIF1_2),
1011         PINMUX_IPSR_MSEL(IP6_15_14, TIOC0C_A, SEL_MTU2_CH0_0),
1012         PINMUX_IPSR_GPSR(IP6_15_14, HIFD06),
1013
1014         PINMUX_IPSR_GPSR(IP6_17_16, DU0_DR7),
1015         PINMUX_IPSR_MSEL(IP6_17_16, RX1_C, SEL_SCIF1_2),
1016         PINMUX_IPSR_MSEL(IP6_17_16, TIOC0D_A, SEL_MTU2_CH0_0),
1017         PINMUX_IPSR_GPSR(IP6_17_16, HIFD07),
1018
1019         PINMUX_IPSR_GPSR(IP6_20_18, DU0_DG0),
1020         PINMUX_IPSR_MSEL(IP6_20_18, TX1_C, SEL_SCIF1_2),
1021         PINMUX_IPSR_MSEL(IP6_20_18, HSCK0_D, SEL_HSCIF_3),
1022         PINMUX_IPSR_MSEL(IP6_20_18, IECLK_A, SEL_IEBUS_0),
1023         PINMUX_IPSR_MSEL(IP6_20_18, TIOC1A_A, SEL_MTU2_CH1_0),
1024         PINMUX_IPSR_GPSR(IP6_20_18, HIFD08),
1025
1026         PINMUX_IPSR_GPSR(IP6_23_21, DU0_DG1),
1027         PINMUX_IPSR_MSEL(IP6_23_21, CTS1_C, SEL_SCIF1_2),
1028         PINMUX_IPSR_MSEL(IP6_23_21, HRTS0_D, SEL_HSCIF_3),
1029         PINMUX_IPSR_MSEL(IP6_23_21, TIOC1B_A, SEL_MTU2_CH1_0),
1030         PINMUX_IPSR_GPSR(IP6_23_21, HIFD09),
1031
1032         /* IPSR7 */
1033         PINMUX_IPSR_GPSR(IP7_2_0, DU0_DG2),
1034         PINMUX_IPSR_MSEL(IP7_2_0, RTS1_C, SEL_SCIF1_2),
1035         PINMUX_IPSR_MSEL(IP7_2_0, RMII0_MDC_B, SEL_RMII_1),
1036         PINMUX_IPSR_MSEL(IP7_2_0, TIOC2A_A, SEL_MTU2_CH2_0),
1037         PINMUX_IPSR_GPSR(IP7_2_0, HIFD10),
1038
1039         PINMUX_IPSR_GPSR(IP7_5_3, DU0_DG3),
1040         PINMUX_IPSR_MSEL(IP7_5_3, SCK2_C, SEL_SCIF2_2),
1041         PINMUX_IPSR_MSEL(IP7_5_3, RMII0_MDIO_B, SEL_RMII_1),
1042         PINMUX_IPSR_MSEL(IP7_5_3, TIOC2B_A, SEL_MTU2_CH2_0),
1043         PINMUX_IPSR_GPSR(IP7_5_3, HIFD11),
1044
1045         PINMUX_IPSR_GPSR(IP7_8_6, DU0_DG4),
1046         PINMUX_IPSR_MSEL(IP7_8_6, RX2_C, SEL_SCIF2_2),
1047         PINMUX_IPSR_MSEL(IP7_8_6, RMII0_CRS_DV_B, SEL_RMII_1),
1048         PINMUX_IPSR_MSEL(IP7_8_6, TIOC3A_A, SEL_MTU2_CH3_0),
1049         PINMUX_IPSR_GPSR(IP7_8_6, HIFD12),
1050
1051         PINMUX_IPSR_GPSR(IP7_11_9, DU0_DG5),
1052         PINMUX_IPSR_MSEL(IP7_11_9, TX2_C, SEL_SCIF2_2),
1053         PINMUX_IPSR_MSEL(IP7_11_9, RMII0_RX_ER_B, SEL_RMII_1),
1054         PINMUX_IPSR_MSEL(IP7_11_9, TIOC3B_A, SEL_MTU2_CH3_0),
1055         PINMUX_IPSR_GPSR(IP7_11_9, HIFD13),
1056
1057         PINMUX_IPSR_GPSR(IP7_14_12, DU0_DG6),
1058         PINMUX_IPSR_MSEL(IP7_14_12, RX3_C, SEL_SCIF3_2),
1059         PINMUX_IPSR_MSEL(IP7_14_12, RMII0_RXD0_B, SEL_RMII_1),
1060         PINMUX_IPSR_MSEL(IP7_14_12, TIOC3C_A, SEL_MTU2_CH3_0),
1061         PINMUX_IPSR_GPSR(IP7_14_12, HIFD14),
1062
1063         PINMUX_IPSR_GPSR(IP7_17_15, DU0_DG7),
1064         PINMUX_IPSR_MSEL(IP7_17_15, TX3_C, SEL_SCIF3_2),
1065         PINMUX_IPSR_MSEL(IP7_17_15, RMII0_RXD1_B, SEL_RMII_1),
1066         PINMUX_IPSR_MSEL(IP7_17_15, TIOC3D_A, SEL_MTU2_CH3_0),
1067         PINMUX_IPSR_GPSR(IP7_17_15, HIFD15),
1068
1069         PINMUX_IPSR_GPSR(IP7_20_18, DU0_DB0),
1070         PINMUX_IPSR_MSEL(IP7_20_18, RX4_C, SEL_SCIF4_2),
1071         PINMUX_IPSR_MSEL(IP7_20_18, RMII0_TXD_EN_B, SEL_RMII_1),
1072         PINMUX_IPSR_MSEL(IP7_20_18, TIOC4A_A, SEL_MTU2_CH4_0),
1073         PINMUX_IPSR_GPSR(IP7_20_18, HIFCS),
1074
1075         PINMUX_IPSR_GPSR(IP7_23_21, DU0_DB1),
1076         PINMUX_IPSR_MSEL(IP7_23_21, TX4_C, SEL_SCIF4_2),
1077         PINMUX_IPSR_MSEL(IP7_23_21, RMII0_TXD0_B, SEL_RMII_1),
1078         PINMUX_IPSR_MSEL(IP7_23_21, TIOC4B_A, SEL_MTU2_CH4_0),
1079         PINMUX_IPSR_GPSR(IP7_23_21, HIFWR),
1080
1081         PINMUX_IPSR_GPSR(IP7_26_24, DU0_DB2),
1082         PINMUX_IPSR_MSEL(IP7_26_24, RX5_B, SEL_SCIF5_1),
1083         PINMUX_IPSR_MSEL(IP7_26_24, RMII0_TXD1_B, SEL_RMII_1),
1084         PINMUX_IPSR_MSEL(IP7_26_24, TIOC4C_A, SEL_MTU2_CH4_0),
1085
1086         PINMUX_IPSR_GPSR(IP7_28_27, DU0_DB3),
1087         PINMUX_IPSR_MSEL(IP7_28_27, TX5_B, SEL_SCIF5_1),
1088         PINMUX_IPSR_MSEL(IP7_28_27, TIOC4D_A, SEL_MTU2_CH4_0),
1089         PINMUX_IPSR_GPSR(IP7_28_27, HIFRD),
1090
1091         PINMUX_IPSR_GPSR(IP7_30_29, DU0_DB4),
1092         PINMUX_IPSR_GPSR(IP7_30_29, HIFINT),
1093
1094         /* IPSR8 */
1095         PINMUX_IPSR_GPSR(IP8_1_0, DU0_DB5),
1096         PINMUX_IPSR_GPSR(IP8_1_0, HIFDREQ),
1097
1098         PINMUX_IPSR_GPSR(IP8_3_2, DU0_DB6),
1099         PINMUX_IPSR_GPSR(IP8_3_2, HIFRDY),
1100
1101         PINMUX_IPSR_GPSR(IP8_5_4, DU0_DB7),
1102         PINMUX_IPSR_MSEL(IP8_5_4, SSI_SCK0_B, SEL_SSI0_1),
1103         PINMUX_IPSR_MSEL(IP8_5_4, HIFEBL_B, SEL_HIF_1),
1104
1105         PINMUX_IPSR_GPSR(IP8_7_6, DU0_DOTCLKIN),
1106         PINMUX_IPSR_MSEL(IP8_7_6, HSPI_CS0_C, SEL_HSPI_2),
1107         PINMUX_IPSR_MSEL(IP8_7_6, SSI_WS0_B, SEL_SSI0_1),
1108
1109         PINMUX_IPSR_GPSR(IP8_9_8, DU0_DOTCLKOUT),
1110         PINMUX_IPSR_MSEL(IP8_9_8, HSPI_CLK0_C, SEL_HSPI_2),
1111         PINMUX_IPSR_MSEL(IP8_9_8, SSI_SDATA0_B, SEL_SSI0_1),
1112
1113         PINMUX_IPSR_GPSR(IP8_11_10, DU0_EXHSYNC_DU0_HSYNC),
1114         PINMUX_IPSR_MSEL(IP8_11_10, HSPI_TX0_C, SEL_HSPI_2),
1115         PINMUX_IPSR_MSEL(IP8_11_10, SSI_SCK1_B, SEL_SSI1_1),
1116
1117         PINMUX_IPSR_GPSR(IP8_13_12, DU0_EXVSYNC_DU0_VSYNC),
1118         PINMUX_IPSR_MSEL(IP8_13_12, HSPI_RX0_C, SEL_HSPI_2),
1119         PINMUX_IPSR_MSEL(IP8_13_12, SSI_WS1_B, SEL_SSI1_1),
1120
1121         PINMUX_IPSR_GPSR(IP8_15_14, DU0_EXODDF_DU0_ODDF),
1122         PINMUX_IPSR_MSEL(IP8_15_14, CAN0_RX_B, SEL_RCAN0_1),
1123         PINMUX_IPSR_MSEL(IP8_15_14, HSCK0_B, SEL_HSCIF_1),
1124         PINMUX_IPSR_MSEL(IP8_15_14, SSI_SDATA1_B, SEL_SSI1_1),
1125
1126         PINMUX_IPSR_GPSR(IP8_17_16, DU0_DISP),
1127         PINMUX_IPSR_MSEL(IP8_17_16, CAN0_TX_B, SEL_RCAN0_1),
1128         PINMUX_IPSR_MSEL(IP8_17_16, HRX0_B, SEL_HSCIF_1),
1129         PINMUX_IPSR_MSEL(IP8_17_16, AUDIO_CLKA_B, SEL_AUDIO_CLKA_1),
1130
1131         PINMUX_IPSR_GPSR(IP8_19_18, DU0_CDE),
1132         PINMUX_IPSR_MSEL(IP8_19_18, HTX0_B, SEL_HSCIF_1),
1133         PINMUX_IPSR_MSEL(IP8_19_18, AUDIO_CLKB_B, SEL_AUDIO_CLKB_1),
1134         PINMUX_IPSR_MSEL(IP8_19_18, LCD_VCPWC_B, SEL_LCDC_1),
1135
1136         PINMUX_IPSR_MSEL(IP8_22_20, IRQ0_A, SEL_INTC_0),
1137         PINMUX_IPSR_MSEL(IP8_22_20, HSPI_TX_B, SEL_HSPI_1),
1138         PINMUX_IPSR_MSEL(IP8_22_20, RX3_E, SEL_SCIF3_4),
1139         PINMUX_IPSR_GPSR(IP8_22_20, ET0_ERXD0),
1140
1141         PINMUX_IPSR_MSEL(IP8_25_23, IRQ1_A, SEL_INTC_0),
1142         PINMUX_IPSR_MSEL(IP8_25_23, HSPI_RX_B, SEL_HSPI_1),
1143         PINMUX_IPSR_MSEL(IP8_25_23, TX3_E, SEL_SCIF3_4),
1144         PINMUX_IPSR_GPSR(IP8_25_23, ET0_ERXD1),
1145
1146         PINMUX_IPSR_MSEL(IP8_27_26, IRQ2_A, SEL_INTC_0),
1147         PINMUX_IPSR_MSEL(IP8_27_26, CTS0_A, SEL_SCIF0_0),
1148         PINMUX_IPSR_MSEL(IP8_27_26, HCTS0_B, SEL_HSCIF_1),
1149         PINMUX_IPSR_MSEL(IP8_27_26, ET0_ERXD2_A, SEL_ET0_0),
1150
1151         PINMUX_IPSR_MSEL(IP8_29_28, IRQ3_A, SEL_INTC_0),
1152         PINMUX_IPSR_MSEL(IP8_29_28, RTS0_A, SEL_SCIF0_0),
1153         PINMUX_IPSR_MSEL(IP8_29_28, HRTS0_B, SEL_HSCIF_1),
1154         PINMUX_IPSR_MSEL(IP8_29_28, ET0_ERXD3_A, SEL_ET0_0),
1155
1156         /* IPSR9 */
1157         PINMUX_IPSR_MSEL(IP9_1_0, VI1_CLK_A, SEL_VIN1_0),
1158         PINMUX_IPSR_MSEL(IP9_1_0, FD0_B, SEL_FLCTL_1),
1159         PINMUX_IPSR_MSEL(IP9_1_0, LCD_DATA0_B, SEL_LCDC_1),
1160
1161         PINMUX_IPSR_MSEL(IP9_3_2, VI1_0_A, SEL_VIN1_0),
1162         PINMUX_IPSR_MSEL(IP9_3_2, FD1_B, SEL_FLCTL_1),
1163         PINMUX_IPSR_MSEL(IP9_3_2, LCD_DATA1_B, SEL_LCDC_1),
1164
1165         PINMUX_IPSR_MSEL(IP9_5_4, VI1_1_A, SEL_VIN1_0),
1166         PINMUX_IPSR_MSEL(IP9_5_4, FD2_B, SEL_FLCTL_1),
1167         PINMUX_IPSR_MSEL(IP9_5_4, LCD_DATA2_B, SEL_LCDC_1),
1168
1169         PINMUX_IPSR_MSEL(IP9_7_6, VI1_2_A, SEL_VIN1_0),
1170         PINMUX_IPSR_MSEL(IP9_7_6, FD3_B, SEL_FLCTL_1),
1171         PINMUX_IPSR_MSEL(IP9_7_6, LCD_DATA3_B, SEL_LCDC_1),
1172
1173         PINMUX_IPSR_MSEL(IP9_9_8, VI1_3_A, SEL_VIN1_0),
1174         PINMUX_IPSR_MSEL(IP9_9_8, FD4_B, SEL_FLCTL_1),
1175         PINMUX_IPSR_MSEL(IP9_9_8, LCD_DATA4_B, SEL_LCDC_1),
1176
1177         PINMUX_IPSR_MSEL(IP9_11_10, VI1_4_A, SEL_VIN1_0),
1178         PINMUX_IPSR_MSEL(IP9_11_10, FD5_B, SEL_FLCTL_1),
1179         PINMUX_IPSR_MSEL(IP9_11_10, LCD_DATA5_B, SEL_LCDC_1),
1180
1181         PINMUX_IPSR_MSEL(IP9_13_12, VI1_5_A, SEL_VIN1_0),
1182         PINMUX_IPSR_MSEL(IP9_13_12, FD6_B, SEL_FLCTL_1),
1183         PINMUX_IPSR_MSEL(IP9_13_12, LCD_DATA6_B, SEL_LCDC_1),
1184
1185         PINMUX_IPSR_MSEL(IP9_15_14, VI1_6_A, SEL_VIN1_0),
1186         PINMUX_IPSR_MSEL(IP9_15_14, FD7_B, SEL_FLCTL_1),
1187         PINMUX_IPSR_MSEL(IP9_15_14, LCD_DATA7_B, SEL_LCDC_1),
1188
1189         PINMUX_IPSR_MSEL(IP9_17_16, VI1_7_A, SEL_VIN1_0),
1190         PINMUX_IPSR_MSEL(IP9_17_16, FCE_B, SEL_FLCTL_1),
1191         PINMUX_IPSR_MSEL(IP9_17_16, LCD_DATA8_B, SEL_LCDC_1),
1192
1193         PINMUX_IPSR_MSEL(IP9_19_18, SSI_SCK0_A, SEL_SSI0_0),
1194         PINMUX_IPSR_MSEL(IP9_19_18, TIOC1A_B, SEL_MTU2_CH1_1),
1195         PINMUX_IPSR_MSEL(IP9_19_18, LCD_DATA9_B, SEL_LCDC_1),
1196
1197         PINMUX_IPSR_MSEL(IP9_21_20, SSI_WS0_A, SEL_SSI0_0),
1198         PINMUX_IPSR_MSEL(IP9_21_20, TIOC1B_B, SEL_MTU2_CH1_1),
1199         PINMUX_IPSR_MSEL(IP9_21_20, LCD_DATA10_B, SEL_LCDC_1),
1200
1201         PINMUX_IPSR_MSEL(IP9_23_22, SSI_SDATA0_A, SEL_SSI0_0),
1202         PINMUX_IPSR_MSEL(IP9_23_22, VI1_0_B, SEL_VIN1_1),
1203         PINMUX_IPSR_MSEL(IP9_23_22, TIOC2A_B, SEL_MTU2_CH2_1),
1204         PINMUX_IPSR_MSEL(IP9_23_22, LCD_DATA11_B, SEL_LCDC_1),
1205
1206         PINMUX_IPSR_MSEL(IP9_25_24, SSI_SCK1_A, SEL_SSI1_0),
1207         PINMUX_IPSR_MSEL(IP9_25_24, VI1_1_B, SEL_VIN1_1),
1208         PINMUX_IPSR_MSEL(IP9_25_24, TIOC2B_B, SEL_MTU2_CH2_1),
1209         PINMUX_IPSR_MSEL(IP9_25_24, LCD_DATA12_B, SEL_LCDC_1),
1210
1211         PINMUX_IPSR_MSEL(IP9_27_26, SSI_WS1_A, SEL_SSI1_0),
1212         PINMUX_IPSR_MSEL(IP9_27_26, VI1_2_B, SEL_VIN1_1),
1213         PINMUX_IPSR_MSEL(IP9_27_26, LCD_DATA13_B, SEL_LCDC_1),
1214
1215         PINMUX_IPSR_MSEL(IP9_29_28, SSI_SDATA1_A, SEL_SSI1_0),
1216         PINMUX_IPSR_MSEL(IP9_29_28, VI1_3_B, SEL_VIN1_1),
1217         PINMUX_IPSR_MSEL(IP9_29_28, LCD_DATA14_B, SEL_LCDC_1),
1218
1219         /* IPSE10 */
1220         PINMUX_IPSR_GPSR(IP10_2_0, SSI_SCK23),
1221         PINMUX_IPSR_MSEL(IP10_2_0, VI1_4_B, SEL_VIN1_1),
1222         PINMUX_IPSR_MSEL(IP10_2_0, RX1_D, SEL_SCIF1_3),
1223         PINMUX_IPSR_MSEL(IP10_2_0, FCLE_B, SEL_FLCTL_1),
1224         PINMUX_IPSR_MSEL(IP10_2_0, LCD_DATA15_B, SEL_LCDC_1),
1225
1226         PINMUX_IPSR_GPSR(IP10_5_3, SSI_WS23),
1227         PINMUX_IPSR_MSEL(IP10_5_3, VI1_5_B, SEL_VIN1_1),
1228         PINMUX_IPSR_MSEL(IP10_5_3, TX1_D, SEL_SCIF1_3),
1229         PINMUX_IPSR_MSEL(IP10_5_3, HSCK0_C, SEL_HSCIF_2),
1230         PINMUX_IPSR_MSEL(IP10_5_3, FALE_B, SEL_FLCTL_1),
1231         PINMUX_IPSR_MSEL(IP10_5_3, LCD_DON_B, SEL_LCDC_1),
1232
1233         PINMUX_IPSR_GPSR(IP10_8_6, SSI_SDATA2),
1234         PINMUX_IPSR_MSEL(IP10_8_6, VI1_6_B, SEL_VIN1_1),
1235         PINMUX_IPSR_MSEL(IP10_8_6, HRX0_C, SEL_HSCIF_2),
1236         PINMUX_IPSR_MSEL(IP10_8_6, FRE_B, SEL_FLCTL_1),
1237         PINMUX_IPSR_MSEL(IP10_8_6, LCD_CL1_B, SEL_LCDC_1),
1238
1239         PINMUX_IPSR_GPSR(IP10_11_9, SSI_SDATA3),
1240         PINMUX_IPSR_MSEL(IP10_11_9, VI1_7_B, SEL_VIN1_1),
1241         PINMUX_IPSR_MSEL(IP10_11_9, HTX0_C, SEL_HSCIF_2),
1242         PINMUX_IPSR_MSEL(IP10_11_9, FWE_B, SEL_FLCTL_1),
1243         PINMUX_IPSR_MSEL(IP10_11_9, LCD_CL2_B, SEL_LCDC_1),
1244
1245         PINMUX_IPSR_MSEL(IP10_14_12, AUDIO_CLKA_A, SEL_AUDIO_CLKA_0),
1246         PINMUX_IPSR_MSEL(IP10_14_12, VI1_CLK_B, SEL_VIN1_1),
1247         PINMUX_IPSR_MSEL(IP10_14_12, SCK1_D, SEL_SCIF1_3),
1248         PINMUX_IPSR_MSEL(IP10_14_12, IECLK_B, SEL_IEBUS_1),
1249         PINMUX_IPSR_MSEL(IP10_14_12, LCD_FLM_B, SEL_LCDC_1),
1250
1251         PINMUX_IPSR_MSEL(IP10_15, AUDIO_CLKB_A, SEL_AUDIO_CLKB_0),
1252         PINMUX_IPSR_MSEL(IP10_15, LCD_CLK_B, SEL_LCDC_1),
1253
1254         PINMUX_IPSR_GPSR(IP10_18_16, AUDIO_CLKC),
1255         PINMUX_IPSR_MSEL(IP10_18_16, SCK1_E, SEL_SCIF1_4),
1256         PINMUX_IPSR_MSEL(IP10_18_16, HCTS0_C, SEL_HSCIF_2),
1257         PINMUX_IPSR_MSEL(IP10_18_16, FRB_B, SEL_FLCTL_1),
1258         PINMUX_IPSR_MSEL(IP10_18_16, LCD_VEPWC_B, SEL_LCDC_1),
1259
1260         PINMUX_IPSR_GPSR(IP10_21_19, AUDIO_CLKOUT),
1261         PINMUX_IPSR_MSEL(IP10_21_19, TX1_E, SEL_SCIF1_4),
1262         PINMUX_IPSR_MSEL(IP10_21_19, HRTS0_C, SEL_HSCIF_2),
1263         PINMUX_IPSR_MSEL(IP10_21_19, FSE_B, SEL_FLCTL_1),
1264         PINMUX_IPSR_MSEL(IP10_21_19, LCD_M_DISP_B, SEL_LCDC_1),
1265
1266         PINMUX_IPSR_MSEL(IP10_22, CAN_CLK_A, SEL_RCAN_CLK_0),
1267         PINMUX_IPSR_MSEL(IP10_22, RX4_D, SEL_SCIF4_3),
1268
1269         PINMUX_IPSR_MSEL(IP10_24_23, CAN0_TX_A, SEL_RCAN0_0),
1270         PINMUX_IPSR_MSEL(IP10_24_23, TX4_D, SEL_SCIF4_3),
1271         PINMUX_IPSR_GPSR(IP10_24_23, MLB_CLK),
1272
1273         PINMUX_IPSR_MSEL(IP10_25, CAN1_RX_A, SEL_RCAN1_0),
1274         PINMUX_IPSR_MSEL(IP10_25, IRQ1_B, SEL_INTC_1),
1275
1276         PINMUX_IPSR_MSEL(IP10_27_26, CAN0_RX_A, SEL_RCAN0_0),
1277         PINMUX_IPSR_MSEL(IP10_27_26, IRQ0_B, SEL_INTC_1),
1278         PINMUX_IPSR_GPSR(IP10_27_26, MLB_SIG),
1279
1280         PINMUX_IPSR_MSEL(IP10_29_28, CAN1_TX_A, SEL_RCAN1_0),
1281         PINMUX_IPSR_MSEL(IP10_29_28, TX5_C, SEL_SCIF1_2),
1282         PINMUX_IPSR_GPSR(IP10_29_28, MLB_DAT),
1283
1284         /* IPSR11 */
1285         PINMUX_IPSR_GPSR(IP11_0, SCL1),
1286         PINMUX_IPSR_MSEL(IP11_0, SCIF_CLK_C, SEL_SCIF_CLK_2),
1287
1288         PINMUX_IPSR_GPSR(IP11_1, SDA1),
1289         PINMUX_IPSR_MSEL(IP11_0, RX1_E, SEL_SCIF1_4),
1290
1291         PINMUX_IPSR_GPSR(IP11_2, SDA0),
1292         PINMUX_IPSR_MSEL(IP11_2, HIFEBL_A, SEL_HIF_0),
1293
1294         PINMUX_IPSR_GPSR(IP11_3, SDSELF),
1295         PINMUX_IPSR_MSEL(IP11_3, RTS1_E, SEL_SCIF1_3),
1296
1297         PINMUX_IPSR_MSEL(IP11_6_4, SCIF_CLK_A, SEL_SCIF_CLK_0),
1298         PINMUX_IPSR_MSEL(IP11_6_4, HSPI_CLK_A, SEL_HSPI_0),
1299         PINMUX_IPSR_GPSR(IP11_6_4, VI0_CLK),
1300         PINMUX_IPSR_MSEL(IP11_6_4, RMII0_TXD0_A, SEL_RMII_0),
1301         PINMUX_IPSR_GPSR(IP11_6_4, ET0_ERXD4),
1302
1303         PINMUX_IPSR_MSEL(IP11_9_7, SCK0_A, SEL_SCIF0_0),
1304         PINMUX_IPSR_MSEL(IP11_9_7, HSPI_CS_A, SEL_HSPI_0),
1305         PINMUX_IPSR_GPSR(IP11_9_7, VI0_CLKENB),
1306         PINMUX_IPSR_MSEL(IP11_9_7, RMII0_TXD1_A, SEL_RMII_0),
1307         PINMUX_IPSR_GPSR(IP11_9_7, ET0_ERXD5),
1308
1309         PINMUX_IPSR_MSEL(IP11_11_10, RX0_A, SEL_SCIF0_0),
1310         PINMUX_IPSR_MSEL(IP11_11_10, HSPI_RX_A, SEL_HSPI_0),
1311         PINMUX_IPSR_MSEL(IP11_11_10, RMII0_RXD0_A, SEL_RMII_0),
1312         PINMUX_IPSR_GPSR(IP11_11_10, ET0_ERXD6),
1313
1314         PINMUX_IPSR_MSEL(IP11_12, TX0_A, SEL_SCIF0_0),
1315         PINMUX_IPSR_MSEL(IP11_12, HSPI_TX_A, SEL_HSPI_0),
1316
1317         PINMUX_IPSR_GPSR(IP11_15_13, PENC1),
1318         PINMUX_IPSR_MSEL(IP11_15_13, TX3_D, SEL_SCIF3_3),
1319         PINMUX_IPSR_MSEL(IP11_15_13, CAN1_TX_B,  SEL_RCAN1_1),
1320         PINMUX_IPSR_MSEL(IP11_15_13, TX5_D, SEL_SCIF5_3),
1321         PINMUX_IPSR_MSEL(IP11_15_13, IETX_B, SEL_IEBUS_1),
1322
1323         PINMUX_IPSR_GPSR(IP11_18_16, USB_OVC1),
1324         PINMUX_IPSR_MSEL(IP11_18_16, RX3_D, SEL_SCIF3_3),
1325         PINMUX_IPSR_MSEL(IP11_18_16, CAN1_RX_B, SEL_RCAN1_1),
1326         PINMUX_IPSR_MSEL(IP11_18_16, RX5_D, SEL_SCIF5_3),
1327         PINMUX_IPSR_MSEL(IP11_18_16, IERX_B, SEL_IEBUS_1),
1328
1329         PINMUX_IPSR_GPSR(IP11_20_19, DREQ0),
1330         PINMUX_IPSR_MSEL(IP11_20_19, SD1_CLK_A, SEL_SDHI1_0),
1331         PINMUX_IPSR_GPSR(IP11_20_19, ET0_TX_EN),
1332
1333         PINMUX_IPSR_GPSR(IP11_22_21, DACK0),
1334         PINMUX_IPSR_MSEL(IP11_22_21, SD1_DAT3_A, SEL_SDHI1_0),
1335         PINMUX_IPSR_GPSR(IP11_22_21, ET0_TX_ER),
1336
1337         PINMUX_IPSR_GPSR(IP11_25_23, DREQ1),
1338         PINMUX_IPSR_MSEL(IP11_25_23, HSPI_CLK_B, SEL_HSPI_1),
1339         PINMUX_IPSR_MSEL(IP11_25_23, RX4_B, SEL_SCIF4_1),
1340         PINMUX_IPSR_MSEL(IP11_25_23, ET0_PHY_INT_C, SEL_ET0_CTL_0),
1341         PINMUX_IPSR_MSEL(IP11_25_23, ET0_TX_CLK_A, SEL_ET0_0),
1342
1343         PINMUX_IPSR_GPSR(IP11_27_26, DACK1),
1344         PINMUX_IPSR_MSEL(IP11_27_26, HSPI_CS_B, SEL_HSPI_1),
1345         PINMUX_IPSR_MSEL(IP11_27_26, TX4_B, SEL_SCIF3_1),
1346         PINMUX_IPSR_MSEL(IP11_27_26, ET0_RX_CLK_A, SEL_ET0_0),
1347
1348         PINMUX_IPSR_GPSR(IP11_28, PRESETOUT),
1349         PINMUX_IPSR_GPSR(IP11_28, ST_CLKOUT),
1350 };
1351
1352 static const struct sh_pfc_pin pinmux_pins[] = {
1353         PINMUX_GPIO_GP_ALL(),
1354 };
1355
1356 #define PINMUX_FN_BASE  ARRAY_SIZE(pinmux_pins)
1357
1358 static const struct pinmux_func pinmux_func_gpios[] = {
1359         GPIO_FN(CLKOUT), GPIO_FN(BS), GPIO_FN(CS0), GPIO_FN(EX_CS0),
1360         GPIO_FN(RD), GPIO_FN(WE0), GPIO_FN(WE1),
1361         GPIO_FN(SCL0), GPIO_FN(PENC0), GPIO_FN(USB_OVC0),
1362         GPIO_FN(IRQ2_B), GPIO_FN(IRQ3_B),
1363
1364         /* IPSR0 */
1365         GPIO_FN(A0), GPIO_FN(ST0_CLKIN), GPIO_FN(LCD_DATA0_A),
1366         GPIO_FN(TCLKA_C),
1367         GPIO_FN(A1), GPIO_FN(ST0_REQ), GPIO_FN(LCD_DATA1_A),
1368         GPIO_FN(TCLKB_C),
1369         GPIO_FN(A2), GPIO_FN(ST0_SYC), GPIO_FN(LCD_DATA2_A),
1370         GPIO_FN(TCLKC_C),
1371         GPIO_FN(A3), GPIO_FN(ST0_VLD), GPIO_FN(LCD_DATA3_A),
1372         GPIO_FN(TCLKD_C),
1373         GPIO_FN(A4), GPIO_FN(ST0_D0), GPIO_FN(LCD_DATA4_A),
1374         GPIO_FN(TIOC0A_C),
1375         GPIO_FN(A5), GPIO_FN(ST0_D1), GPIO_FN(LCD_DATA5_A),
1376         GPIO_FN(TIOC0B_C),
1377         GPIO_FN(A6), GPIO_FN(ST0_D2), GPIO_FN(LCD_DATA6_A),
1378         GPIO_FN(TIOC0C_C),
1379         GPIO_FN(A7), GPIO_FN(ST0_D3), GPIO_FN(LCD_DATA7_A),
1380         GPIO_FN(TIOC0D_C),
1381         GPIO_FN(A8), GPIO_FN(ST0_D4), GPIO_FN(LCD_DATA8_A),
1382         GPIO_FN(TIOC1A_C),
1383         GPIO_FN(A9), GPIO_FN(ST0_D5), GPIO_FN(LCD_DATA9_A),
1384         GPIO_FN(TIOC1B_C),
1385         GPIO_FN(A10), GPIO_FN(ST0_D6), GPIO_FN(LCD_DATA10_A),
1386         GPIO_FN(TIOC2A_C),
1387         GPIO_FN(A11), GPIO_FN(ST0_D7), GPIO_FN(LCD_DATA11_A),
1388         GPIO_FN(TIOC2B_C),
1389         GPIO_FN(A12), GPIO_FN(LCD_DATA12_A), GPIO_FN(TIOC3A_C),
1390         GPIO_FN(A13), GPIO_FN(LCD_DATA13_A), GPIO_FN(TIOC3B_C),
1391         GPIO_FN(A14), GPIO_FN(LCD_DATA14_A), GPIO_FN(TIOC3C_C),
1392         GPIO_FN(A15), GPIO_FN(ST0_VCO_CLKIN), GPIO_FN(LCD_DATA15_A),
1393         GPIO_FN(TIOC3D_C),
1394
1395         /* IPSR1 */
1396         GPIO_FN(A16), GPIO_FN(ST0_PWM), GPIO_FN(LCD_DON_A),
1397         GPIO_FN(TIOC4A_C),
1398         GPIO_FN(A17), GPIO_FN(ST1_VCO_CLKIN), GPIO_FN(LCD_CL1_A),
1399         GPIO_FN(TIOC4B_C),
1400         GPIO_FN(A18), GPIO_FN(ST1_PWM), GPIO_FN(LCD_CL2_A),
1401         GPIO_FN(TIOC4C_C),
1402         GPIO_FN(A19), GPIO_FN(ST1_CLKIN), GPIO_FN(LCD_CLK_A),
1403         GPIO_FN(TIOC4D_C),
1404         GPIO_FN(A20), GPIO_FN(ST1_REQ), GPIO_FN(LCD_FLM_A),
1405         GPIO_FN(A21), GPIO_FN(ST1_SYC), GPIO_FN(LCD_VCPWC_A),
1406         GPIO_FN(A22), GPIO_FN(ST1_VLD), GPIO_FN(LCD_VEPWC_A),
1407         GPIO_FN(A23), GPIO_FN(ST1_D0), GPIO_FN(LCD_M_DISP_A),
1408         GPIO_FN(A24), GPIO_FN(RX2_D), GPIO_FN(ST1_D1),
1409         GPIO_FN(A25), GPIO_FN(TX2_D), GPIO_FN(ST1_D2),
1410         GPIO_FN(D0), GPIO_FN(SD0_DAT0_A), GPIO_FN(MMC_D0_A),
1411         GPIO_FN(ST1_D3), GPIO_FN(FD0_A),
1412         GPIO_FN(D1), GPIO_FN(SD0_DAT1_A), GPIO_FN(MMC_D1_A),
1413         GPIO_FN(ST1_D4), GPIO_FN(FD1_A),
1414         GPIO_FN(D2), GPIO_FN(SD0_DAT2_A), GPIO_FN(MMC_D2_A),
1415         GPIO_FN(ST1_D5), GPIO_FN(FD2_A),
1416         GPIO_FN(D3), GPIO_FN(SD0_DAT3_A), GPIO_FN(MMC_D3_A),
1417         GPIO_FN(ST1_D6), GPIO_FN(FD3_A),
1418
1419         /* IPSR2 */
1420         GPIO_FN(D4), GPIO_FN(SD0_CD_A), GPIO_FN(MMC_D4_A), GPIO_FN(ST1_D7),
1421         GPIO_FN(FD4_A),
1422         GPIO_FN(D5), GPIO_FN(SD0_WP_A), GPIO_FN(MMC_D5_A), GPIO_FN(FD5_A),
1423         GPIO_FN(D6), GPIO_FN(RSPI_RSPCK_A), GPIO_FN(MMC_D6_A),
1424                 GPIO_FN(QSPCLK_A),
1425         GPIO_FN(FD6_A),
1426         GPIO_FN(D7), GPIO_FN(RSPI_SSL_A), GPIO_FN(MMC_D7_A), GPIO_FN(QSSL_A),
1427         GPIO_FN(FD7_A),
1428         GPIO_FN(D8), GPIO_FN(SD0_CLK_A), GPIO_FN(MMC_CLK_A), GPIO_FN(QIO2_A),
1429         GPIO_FN(FCE_A), GPIO_FN(ET0_GTX_CLK_B),
1430         GPIO_FN(D9), GPIO_FN(SD0_CMD_A), GPIO_FN(MMC_CMD_A), GPIO_FN(QIO3_A),
1431         GPIO_FN(FCLE_A), GPIO_FN(ET0_ETXD1_B),
1432         GPIO_FN(D10), GPIO_FN(RSPI_MOSI_A), GPIO_FN(QMO_QIO0_A),
1433                 GPIO_FN(FALE_A), GPIO_FN(ET0_ETXD2_B),
1434         GPIO_FN(D11), GPIO_FN(RSPI_MISO_A), GPIO_FN(QMI_QIO1_A), GPIO_FN(FRE_A),
1435                 GPIO_FN(ET0_ETXD3_B),
1436         GPIO_FN(D12), GPIO_FN(FWE_A), GPIO_FN(ET0_ETXD5_B),
1437         GPIO_FN(D13), GPIO_FN(RX2_B), GPIO_FN(FRB_A), GPIO_FN(ET0_ETXD6_B),
1438         GPIO_FN(D14), GPIO_FN(TX2_B), GPIO_FN(FSE_A), GPIO_FN(ET0_TX_CLK_B),
1439
1440         /* IPSR3 */
1441         GPIO_FN(D15), GPIO_FN(SCK2_B),
1442         GPIO_FN(CS1_A26), GPIO_FN(QIO3_B),
1443         GPIO_FN(EX_CS1), GPIO_FN(RX3_B), GPIO_FN(ATACS0), GPIO_FN(QIO2_B),
1444         GPIO_FN(ET0_ETXD0),
1445         GPIO_FN(EX_CS2), GPIO_FN(TX3_B), GPIO_FN(ATACS1), GPIO_FN(QSPCLK_B),
1446         GPIO_FN(ET0_GTX_CLK_A),
1447         GPIO_FN(EX_CS3), GPIO_FN(SD1_CD_A), GPIO_FN(ATARD), GPIO_FN(QMO_QIO0_B),
1448         GPIO_FN(ET0_ETXD1_A),
1449         GPIO_FN(EX_CS4), GPIO_FN(SD1_WP_A), GPIO_FN(ATAWR), GPIO_FN(QMI_QIO1_B),
1450         GPIO_FN(ET0_ETXD2_A),
1451         GPIO_FN(EX_CS5), GPIO_FN(SD1_CMD_A), GPIO_FN(ATADIR), GPIO_FN(QSSL_B),
1452         GPIO_FN(ET0_ETXD3_A),
1453         GPIO_FN(RD_WR), GPIO_FN(TCLK0), GPIO_FN(CAN_CLK_B), GPIO_FN(ET0_ETXD4),
1454         GPIO_FN(EX_WAIT0), GPIO_FN(TCLK1_B),
1455         GPIO_FN(EX_WAIT1), GPIO_FN(SD1_DAT0_A), GPIO_FN(DREQ2),
1456                 GPIO_FN(CAN1_TX_C), GPIO_FN(ET0_LINK_C), GPIO_FN(ET0_ETXD5_A),
1457         GPIO_FN(EX_WAIT2), GPIO_FN(SD1_DAT1_A), GPIO_FN(DACK2),
1458                 GPIO_FN(CAN1_RX_C), GPIO_FN(ET0_MAGIC_C), GPIO_FN(ET0_ETXD6_A),
1459         GPIO_FN(DRACK0), GPIO_FN(SD1_DAT2_A), GPIO_FN(ATAG), GPIO_FN(TCLK1_A),
1460         GPIO_FN(ET0_ETXD7),
1461
1462         /* IPSR4 */
1463         GPIO_FN(HCTS0_A), GPIO_FN(CTS1_A), GPIO_FN(VI0_FIELD),
1464                 GPIO_FN(RMII0_RXD1_A), GPIO_FN(ET0_ERXD7),
1465         GPIO_FN(HRTS0_A), GPIO_FN(RTS1_A), GPIO_FN(VI0_HSYNC),
1466                 GPIO_FN(RMII0_TXD_EN_A), GPIO_FN(ET0_RX_DV),
1467         GPIO_FN(HSCK0_A), GPIO_FN(SCK1_A), GPIO_FN(VI0_VSYNC),
1468                 GPIO_FN(RMII0_RX_ER_A), GPIO_FN(ET0_RX_ER),
1469         GPIO_FN(HRX0_A), GPIO_FN(RX1_A), GPIO_FN(VI0_DATA0_VI0_B0),
1470                 GPIO_FN(RMII0_CRS_DV_A), GPIO_FN(ET0_CRS),
1471         GPIO_FN(HTX0_A), GPIO_FN(TX1_A), GPIO_FN(VI0_DATA1_VI0_B1),
1472                 GPIO_FN(RMII0_MDC_A), GPIO_FN(ET0_COL),
1473         GPIO_FN(CTS0_B), GPIO_FN(VI0_DATA2_VI0_B2), GPIO_FN(RMII0_MDIO_A),
1474                 GPIO_FN(ET0_MDC),
1475         GPIO_FN(RTS0_B), GPIO_FN(VI0_DATA3_VI0_B3), GPIO_FN(ET0_MDIO_A),
1476         GPIO_FN(SCK1_B), GPIO_FN(VI0_DATA4_VI0_B4), GPIO_FN(ET0_LINK_A),
1477         GPIO_FN(RX1_B), GPIO_FN(VI0_DATA5_VI0_B5), GPIO_FN(ET0_MAGIC_A),
1478         GPIO_FN(TX1_B), GPIO_FN(VI0_DATA6_VI0_G0), GPIO_FN(ET0_PHY_INT_A),
1479         GPIO_FN(CTS1_B), GPIO_FN(VI0_DATA7_VI0_G1),
1480         GPIO_FN(RTS1_B), GPIO_FN(VI0_G2),
1481         GPIO_FN(SCK2_A), GPIO_FN(VI0_G3),
1482
1483         /* IPSR5 */
1484         GPIO_FN(REF50CK), GPIO_FN(CTS1_E), GPIO_FN(HCTS0_D),
1485         GPIO_FN(REF125CK), GPIO_FN(ADTRG), GPIO_FN(RX5_C),
1486         GPIO_FN(SD2_WP_A), GPIO_FN(TX5_A), GPIO_FN(VI0_R5),
1487         GPIO_FN(SD2_CD_A), GPIO_FN(RX5_A), GPIO_FN(VI0_R4),
1488                 GPIO_FN(ET0_PHY_INT_B),
1489         GPIO_FN(SD2_DAT3_A), GPIO_FN(TX4_A), GPIO_FN(VI0_R3),
1490                 GPIO_FN(ET0_MAGIC_B),
1491         GPIO_FN(SD2_DAT2_A), GPIO_FN(RX4_A), GPIO_FN(VI0_R2),
1492                 GPIO_FN(ET0_LINK_B),
1493         GPIO_FN(SD2_DAT1_A), GPIO_FN(TX3_A), GPIO_FN(VI0_R1),
1494                 GPIO_FN(ET0_MDIO_B),
1495         GPIO_FN(SD2_DAT0_A), GPIO_FN(RX3_A), GPIO_FN(VI0_R0),
1496                 GPIO_FN(ET0_ERXD3_B),
1497         GPIO_FN(SD2_CMD_A), GPIO_FN(TX2_A), GPIO_FN(VI0_G5),
1498                 GPIO_FN(ET0_ERXD2_B),
1499         GPIO_FN(SD2_CLK_A), GPIO_FN(RX2_A), GPIO_FN(VI0_G4),
1500                 GPIO_FN(ET0_RX_CLK_B),
1501
1502         /* IPSR6 */
1503         GPIO_FN(DU0_DG1), GPIO_FN(CTS1_C), GPIO_FN(HRTS0_D),
1504                 GPIO_FN(TIOC1B_A), GPIO_FN(HIFD09),
1505         GPIO_FN(DU0_DG0), GPIO_FN(TX1_C), GPIO_FN(HSCK0_D),
1506                 GPIO_FN(IECLK_A), GPIO_FN(TIOC1A_A), GPIO_FN(HIFD08),
1507         GPIO_FN(DU0_DR7), GPIO_FN(RX1_C), GPIO_FN(TIOC0D_A),
1508                 GPIO_FN(HIFD07),
1509         GPIO_FN(DU0_DR6), GPIO_FN(SCK1_C), GPIO_FN(TIOC0C_A),
1510                 GPIO_FN(HIFD06),
1511         GPIO_FN(DU0_DR5), GPIO_FN(RTS0_C), GPIO_FN(TIOC0B_A),
1512                 GPIO_FN(HIFD05),
1513         GPIO_FN(DU0_DR4), GPIO_FN(CTS0_C), GPIO_FN(TIOC0A_A),
1514                 GPIO_FN(HIFD04),
1515         GPIO_FN(DU0_DR3), GPIO_FN(TX0_B), GPIO_FN(TCLKD_A), GPIO_FN(HIFD03),
1516         GPIO_FN(DU0_DR2), GPIO_FN(RX0_B), GPIO_FN(TCLKC_A), GPIO_FN(HIFD02),
1517         GPIO_FN(DU0_DR1), GPIO_FN(SCK0_B), GPIO_FN(HTX0_D),
1518                 GPIO_FN(IERX_A), GPIO_FN(TCLKB_A), GPIO_FN(HIFD01),
1519         GPIO_FN(DU0_DR0), GPIO_FN(SCIF_CLK_B), GPIO_FN(HRX0_D),
1520                 GPIO_FN(IETX_A), GPIO_FN(TCLKA_A), GPIO_FN(HIFD00),
1521
1522         /* IPSR7 */
1523         GPIO_FN(DU0_DB4), GPIO_FN(HIFINT),
1524         GPIO_FN(DU0_DB3), GPIO_FN(TX5_B), GPIO_FN(TIOC4D_A), GPIO_FN(HIFRD),
1525         GPIO_FN(DU0_DB2), GPIO_FN(RX5_B), GPIO_FN(RMII0_TXD1_B),
1526                 GPIO_FN(TIOC4C_A), GPIO_FN(HIFWR),
1527         GPIO_FN(DU0_DB1), GPIO_FN(TX4_C), GPIO_FN(RMII0_TXD0_B),
1528                 GPIO_FN(TIOC4B_A), GPIO_FN(HIFRS),
1529         GPIO_FN(DU0_DB0), GPIO_FN(RX4_C), GPIO_FN(RMII0_TXD_EN_B),
1530                 GPIO_FN(TIOC4A_A), GPIO_FN(HIFCS),
1531         GPIO_FN(DU0_DG7), GPIO_FN(TX3_C), GPIO_FN(RMII0_RXD1_B),
1532                 GPIO_FN(TIOC3D_A), GPIO_FN(HIFD15),
1533         GPIO_FN(DU0_DG6), GPIO_FN(RX3_C), GPIO_FN(RMII0_RXD0_B),
1534                 GPIO_FN(TIOC3C_A), GPIO_FN(HIFD14),
1535         GPIO_FN(DU0_DG5), GPIO_FN(TX2_C), GPIO_FN(RMII0_RX_ER_B),
1536                 GPIO_FN(TIOC3B_A), GPIO_FN(HIFD13),
1537         GPIO_FN(DU0_DG4), GPIO_FN(RX2_C), GPIO_FN(RMII0_CRS_DV_B),
1538                 GPIO_FN(TIOC3A_A), GPIO_FN(HIFD12),
1539         GPIO_FN(DU0_DG3), GPIO_FN(SCK2_C), GPIO_FN(RMII0_MDIO_B),
1540                 GPIO_FN(TIOC2B_A), GPIO_FN(HIFD11),
1541         GPIO_FN(DU0_DG2), GPIO_FN(RTS1_C), GPIO_FN(RMII0_MDC_B),
1542                 GPIO_FN(TIOC2A_A), GPIO_FN(HIFD10),
1543
1544         /* IPSR8 */
1545         GPIO_FN(IRQ3_A), GPIO_FN(RTS0_A), GPIO_FN(HRTS0_B),
1546                 GPIO_FN(ET0_ERXD3_A),
1547         GPIO_FN(IRQ2_A), GPIO_FN(CTS0_A), GPIO_FN(HCTS0_B),
1548                 GPIO_FN(ET0_ERXD2_A),
1549         GPIO_FN(IRQ1_A), GPIO_FN(HSPI_RX_B), GPIO_FN(TX3_E),
1550                 GPIO_FN(ET0_ERXD1),
1551         GPIO_FN(IRQ0_A), GPIO_FN(HSPI_TX_B), GPIO_FN(RX3_E),
1552                 GPIO_FN(ET0_ERXD0),
1553         GPIO_FN(DU0_CDE), GPIO_FN(HTX0_B), GPIO_FN(AUDIO_CLKB_B),
1554                 GPIO_FN(LCD_VCPWC_B),
1555         GPIO_FN(DU0_DISP), GPIO_FN(CAN0_TX_B), GPIO_FN(HRX0_B),
1556                 GPIO_FN(AUDIO_CLKA_B),
1557         GPIO_FN(DU0_EXODDF_DU0_ODDF), GPIO_FN(CAN0_RX_B), GPIO_FN(HSCK0_B),
1558                 GPIO_FN(SSI_SDATA1_B),
1559         GPIO_FN(DU0_EXVSYNC_DU0_VSYNC), GPIO_FN(HSPI_RX0_C),
1560                 GPIO_FN(SSI_WS1_B),
1561         GPIO_FN(DU0_EXHSYNC_DU0_HSYNC), GPIO_FN(HSPI_TX0_C),
1562                 GPIO_FN(SSI_SCK1_B),
1563         GPIO_FN(DU0_DOTCLKOUT), GPIO_FN(HSPI_CLK0_C),
1564                 GPIO_FN(SSI_SDATA0_B),
1565         GPIO_FN(DU0_DOTCLKIN), GPIO_FN(HSPI_CS0_C),
1566                 GPIO_FN(SSI_WS0_B),
1567         GPIO_FN(DU0_DB7), GPIO_FN(SSI_SCK0_B), GPIO_FN(HIFEBL_B),
1568         GPIO_FN(DU0_DB6), GPIO_FN(HIFRDY),
1569         GPIO_FN(DU0_DB5), GPIO_FN(HIFDREQ),
1570
1571         /* IPSR9 */
1572         GPIO_FN(SSI_SDATA1_A), GPIO_FN(VI1_3_B), GPIO_FN(LCD_DATA14_B),
1573         GPIO_FN(SSI_WS1_A), GPIO_FN(VI1_2_B), GPIO_FN(LCD_DATA13_B),
1574         GPIO_FN(SSI_SCK1_A), GPIO_FN(VI1_1_B), GPIO_FN(TIOC2B_B),
1575                 GPIO_FN(LCD_DATA12_B),
1576         GPIO_FN(SSI_SDATA0_A), GPIO_FN(VI1_0_B), GPIO_FN(TIOC2A_B),
1577                 GPIO_FN(LCD_DATA11_B),
1578         GPIO_FN(SSI_WS0_A), GPIO_FN(TIOC1B_B), GPIO_FN(LCD_DATA10_B),
1579         GPIO_FN(SSI_SCK0_A), GPIO_FN(TIOC1A_B), GPIO_FN(LCD_DATA9_B),
1580         GPIO_FN(VI1_7_A), GPIO_FN(FCE_B), GPIO_FN(LCD_DATA8_B),
1581         GPIO_FN(VI1_6_A), GPIO_FN(FD7_B), GPIO_FN(LCD_DATA7_B),
1582         GPIO_FN(VI1_5_A), GPIO_FN(FD6_B), GPIO_FN(LCD_DATA6_B),
1583         GPIO_FN(VI1_4_A), GPIO_FN(FD5_B), GPIO_FN(LCD_DATA5_B),
1584         GPIO_FN(VI1_3_A), GPIO_FN(FD4_B), GPIO_FN(LCD_DATA4_B),
1585         GPIO_FN(VI1_2_A), GPIO_FN(FD3_B), GPIO_FN(LCD_DATA3_B),
1586         GPIO_FN(VI1_1_A), GPIO_FN(FD2_B), GPIO_FN(LCD_DATA2_B),
1587         GPIO_FN(VI1_0_A), GPIO_FN(FD1_B), GPIO_FN(LCD_DATA1_B),
1588         GPIO_FN(VI1_CLK_A), GPIO_FN(FD0_B), GPIO_FN(LCD_DATA0_B),
1589
1590         /* IPSR10 */
1591         GPIO_FN(CAN1_TX_A), GPIO_FN(TX5_C), GPIO_FN(MLB_DAT),
1592         GPIO_FN(CAN0_RX_A), GPIO_FN(IRQ0_B), GPIO_FN(MLB_SIG),
1593         GPIO_FN(CAN1_RX_A), GPIO_FN(IRQ1_B),
1594         GPIO_FN(CAN0_TX_A), GPIO_FN(TX4_D), GPIO_FN(MLB_CLK),
1595         GPIO_FN(CAN_CLK_A), GPIO_FN(RX4_D),
1596         GPIO_FN(AUDIO_CLKOUT), GPIO_FN(TX1_E), GPIO_FN(HRTS0_C),
1597                 GPIO_FN(FSE_B), GPIO_FN(LCD_M_DISP_B),
1598         GPIO_FN(AUDIO_CLKC), GPIO_FN(SCK1_E), GPIO_FN(HCTS0_C),
1599                 GPIO_FN(FRB_B), GPIO_FN(LCD_VEPWC_B),
1600         GPIO_FN(AUDIO_CLKB_A), GPIO_FN(LCD_CLK_B),
1601         GPIO_FN(AUDIO_CLKA_A), GPIO_FN(VI1_CLK_B), GPIO_FN(SCK1_D),
1602                 GPIO_FN(IECLK_B), GPIO_FN(LCD_FLM_B),
1603         GPIO_FN(SSI_SDATA3), GPIO_FN(VI1_7_B), GPIO_FN(HTX0_C),
1604                 GPIO_FN(FWE_B), GPIO_FN(LCD_CL2_B),
1605         GPIO_FN(SSI_SDATA2), GPIO_FN(VI1_6_B), GPIO_FN(HRX0_C),
1606                 GPIO_FN(FRE_B), GPIO_FN(LCD_CL1_B),
1607         GPIO_FN(SSI_WS23), GPIO_FN(VI1_5_B), GPIO_FN(TX1_D),
1608                 GPIO_FN(HSCK0_C), GPIO_FN(FALE_B), GPIO_FN(LCD_DON_B),
1609         GPIO_FN(SSI_SCK23), GPIO_FN(VI1_4_B), GPIO_FN(RX1_D),
1610                 GPIO_FN(FCLE_B), GPIO_FN(LCD_DATA15_B),
1611
1612         /* IPSR11 */
1613         GPIO_FN(PRESETOUT), GPIO_FN(ST_CLKOUT),
1614         GPIO_FN(DACK1), GPIO_FN(HSPI_CS_B), GPIO_FN(TX4_B),
1615                 GPIO_FN(ET0_RX_CLK_A),
1616         GPIO_FN(DREQ1), GPIO_FN(HSPI_CLK_B), GPIO_FN(RX4_B),
1617                 GPIO_FN(ET0_PHY_INT_C), GPIO_FN(ET0_TX_CLK_A),
1618         GPIO_FN(DACK0), GPIO_FN(SD1_DAT3_A), GPIO_FN(ET0_TX_ER),
1619         GPIO_FN(DREQ0), GPIO_FN(SD1_CLK_A), GPIO_FN(ET0_TX_EN),
1620         GPIO_FN(USB_OVC1), GPIO_FN(RX3_D), GPIO_FN(CAN1_RX_B),
1621                 GPIO_FN(RX5_D), GPIO_FN(IERX_B),
1622         GPIO_FN(PENC1), GPIO_FN(TX3_D), GPIO_FN(CAN1_TX_B),
1623                 GPIO_FN(TX5_D), GPIO_FN(IETX_B),
1624         GPIO_FN(TX0_A), GPIO_FN(HSPI_TX_A),
1625         GPIO_FN(RX0_A), GPIO_FN(HSPI_RX_A), GPIO_FN(RMII0_RXD0_A),
1626                 GPIO_FN(ET0_ERXD6),
1627         GPIO_FN(SCK0_A), GPIO_FN(HSPI_CS_A), GPIO_FN(VI0_CLKENB),
1628                 GPIO_FN(RMII0_TXD1_A), GPIO_FN(ET0_ERXD5),
1629         GPIO_FN(SCIF_CLK_A), GPIO_FN(HSPI_CLK_A), GPIO_FN(VI0_CLK),
1630                 GPIO_FN(RMII0_TXD0_A), GPIO_FN(ET0_ERXD4),
1631         GPIO_FN(SDSELF), GPIO_FN(RTS1_E),
1632         GPIO_FN(SDA0), GPIO_FN(HIFEBL_A),
1633         GPIO_FN(SDA1), GPIO_FN(RX1_E),
1634         GPIO_FN(SCL1), GPIO_FN(SCIF_CLK_C),
1635 };
1636
1637 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1638         { PINMUX_CFG_REG("GPSR0", 0xFFFC0004, 32, 1, GROUP(
1639                 GP_0_31_FN, FN_IP2_2_0,
1640                 GP_0_30_FN, FN_IP1_31_29,
1641                 GP_0_29_FN, FN_IP1_28_26,
1642                 GP_0_28_FN, FN_IP1_25_23,
1643                 GP_0_27_FN, FN_IP1_22_20,
1644                 GP_0_26_FN, FN_IP1_19_18,
1645                 GP_0_25_FN, FN_IP1_17_16,
1646                 GP_0_24_FN, FN_IP0_5_4,
1647                 GP_0_23_FN, FN_IP0_3_2,
1648                 GP_0_22_FN, FN_IP0_1_0,
1649                 GP_0_21_FN, FN_IP11_28,
1650                 GP_0_20_FN, FN_IP1_7_6,
1651                 GP_0_19_FN, FN_IP1_5_4,
1652                 GP_0_18_FN, FN_IP1_3_2,
1653                 GP_0_17_FN, FN_IP1_1_0,
1654                 GP_0_16_FN, FN_IP0_31_30,
1655                 GP_0_15_FN, FN_IP0_29_28,
1656                 GP_0_14_FN, FN_IP0_27_26,
1657                 GP_0_13_FN, FN_IP0_25_24,
1658                 GP_0_12_FN, FN_IP0_23_22,
1659                 GP_0_11_FN, FN_IP0_21_20,
1660                 GP_0_10_FN, FN_IP0_19_18,
1661                 GP_0_9_FN, FN_IP0_17_16,
1662                 GP_0_8_FN, FN_IP0_15_14,
1663                 GP_0_7_FN, FN_IP0_13_12,
1664                 GP_0_6_FN, FN_IP0_11_10,
1665                 GP_0_5_FN, FN_IP0_9_8,
1666                 GP_0_4_FN, FN_IP0_7_6,
1667                 GP_0_3_FN, FN_IP1_15_14,
1668                 GP_0_2_FN, FN_IP1_13_12,
1669                 GP_0_1_FN, FN_IP1_11_10,
1670                 GP_0_0_FN, FN_IP1_9_8 ))
1671         },
1672         { PINMUX_CFG_REG("GPSR1", 0xFFFC0008, 32, 1, GROUP(
1673                 GP_1_31_FN, FN_IP11_25_23,
1674                 GP_1_30_FN, FN_IP2_13_11,
1675                 GP_1_29_FN, FN_IP2_10_8,
1676                 GP_1_28_FN, FN_IP2_7_5,
1677                 GP_1_27_FN, FN_IP3_26_24,
1678                 GP_1_26_FN, FN_IP3_23_21,
1679                 GP_1_25_FN, FN_IP2_4_3,
1680                 GP_1_24_FN, FN_WE1,
1681                 GP_1_23_FN, FN_WE0,
1682                 GP_1_22_FN, FN_IP3_19_18,
1683                 GP_1_21_FN, FN_RD,
1684                 GP_1_20_FN, FN_IP3_17_15,
1685                 GP_1_19_FN, FN_IP3_14_12,
1686                 GP_1_18_FN, FN_IP3_11_9,
1687                 GP_1_17_FN, FN_IP3_8_6,
1688                 GP_1_16_FN, FN_IP3_5_3,
1689                 GP_1_15_FN, FN_EX_CS0,
1690                 GP_1_14_FN, FN_IP3_2,
1691                 GP_1_13_FN, FN_CS0,
1692                 GP_1_12_FN, FN_BS,
1693                 GP_1_11_FN, FN_CLKOUT,
1694                 GP_1_10_FN, FN_IP3_1_0,
1695                 GP_1_9_FN, FN_IP2_30_28,
1696                 GP_1_8_FN, FN_IP2_27_25,
1697                 GP_1_7_FN, FN_IP2_24_23,
1698                 GP_1_6_FN, FN_IP2_22_20,
1699                 GP_1_5_FN, FN_IP2_19_17,
1700                 GP_1_4_FN, FN_IP2_16_14,
1701                 GP_1_3_FN, FN_IP11_22_21,
1702                 GP_1_2_FN, FN_IP11_20_19,
1703                 GP_1_1_FN, FN_IP3_29_27,
1704                 GP_1_0_FN, FN_IP3_20 ))
1705         },
1706         { PINMUX_CFG_REG("GPSR2", 0xFFFC000C, 32, 1, GROUP(
1707                 GP_2_31_FN, FN_IP4_31_30,
1708                 GP_2_30_FN, FN_IP5_2_0,
1709                 GP_2_29_FN, FN_IP5_5_3,
1710                 GP_2_28_FN, FN_IP5_8_6,
1711                 GP_2_27_FN, FN_IP5_11_9,
1712                 GP_2_26_FN, FN_IP5_14_12,
1713                 GP_2_25_FN, FN_IP5_17_15,
1714                 GP_2_24_FN, FN_IP5_20_18,
1715                 GP_2_23_FN, FN_IP5_22_21,
1716                 GP_2_22_FN, FN_IP5_24_23,
1717                 GP_2_21_FN, FN_IP5_26_25,
1718                 GP_2_20_FN, FN_IP4_29_28,
1719                 GP_2_19_FN, FN_IP4_27_26,
1720                 GP_2_18_FN, FN_IP4_25_24,
1721                 GP_2_17_FN, FN_IP4_23_22,
1722                 GP_2_16_FN, FN_IP4_21_20,
1723                 GP_2_15_FN, FN_IP4_19_18,
1724                 GP_2_14_FN, FN_IP4_17_15,
1725                 GP_2_13_FN, FN_IP4_14_12,
1726                 GP_2_12_FN, FN_IP4_11_9,
1727                 GP_2_11_FN, FN_IP4_8_6,
1728                 GP_2_10_FN, FN_IP4_5_3,
1729                 GP_2_9_FN, FN_IP8_27_26,
1730                 GP_2_8_FN, FN_IP11_12,
1731                 GP_2_7_FN, FN_IP8_25_23,
1732                 GP_2_6_FN, FN_IP8_22_20,
1733                 GP_2_5_FN, FN_IP11_27_26,
1734                 GP_2_4_FN, FN_IP8_29_28,
1735                 GP_2_3_FN, FN_IP4_2_0,
1736                 GP_2_2_FN, FN_IP11_11_10,
1737                 GP_2_1_FN, FN_IP11_9_7,
1738                 GP_2_0_FN, FN_IP11_6_4 ))
1739         },
1740         { PINMUX_CFG_REG("GPSR3", 0xFFFC0010, 32, 1, GROUP(
1741                 GP_3_31_FN, FN_IP9_1_0,
1742                 GP_3_30_FN, FN_IP8_19_18,
1743                 GP_3_29_FN, FN_IP8_17_16,
1744                 GP_3_28_FN, FN_IP8_15_14,
1745                 GP_3_27_FN, FN_IP8_13_12,
1746                 GP_3_26_FN, FN_IP8_11_10,
1747                 GP_3_25_FN, FN_IP8_9_8,
1748                 GP_3_24_FN, FN_IP8_7_6,
1749                 GP_3_23_FN, FN_IP8_5_4,
1750                 GP_3_22_FN, FN_IP8_3_2,
1751                 GP_3_21_FN, FN_IP8_1_0,
1752                 GP_3_20_FN, FN_IP7_30_29,
1753                 GP_3_19_FN, FN_IP7_28_27,
1754                 GP_3_18_FN, FN_IP7_26_24,
1755                 GP_3_17_FN, FN_IP7_23_21,
1756                 GP_3_16_FN, FN_IP7_20_18,
1757                 GP_3_15_FN, FN_IP7_17_15,
1758                 GP_3_14_FN, FN_IP7_14_12,
1759                 GP_3_13_FN, FN_IP7_11_9,
1760                 GP_3_12_FN, FN_IP7_8_6,
1761                 GP_3_11_FN, FN_IP7_5_3,
1762                 GP_3_10_FN, FN_IP7_2_0,
1763                 GP_3_9_FN, FN_IP6_23_21,
1764                 GP_3_8_FN, FN_IP6_20_18,
1765                 GP_3_7_FN, FN_IP6_17_16,
1766                 GP_3_6_FN, FN_IP6_15_14,
1767                 GP_3_5_FN, FN_IP6_13_12,
1768                 GP_3_4_FN, FN_IP6_11_10,
1769                 GP_3_3_FN, FN_IP6_9_8,
1770                 GP_3_2_FN, FN_IP6_7_6,
1771                 GP_3_1_FN, FN_IP6_5_3,
1772                 GP_3_0_FN, FN_IP6_2_0 ))
1773         },
1774
1775         { PINMUX_CFG_REG("GPSR4", 0xFFFC0014, 32, 1, GROUP(
1776                 GP_4_31_FN, FN_IP10_24_23,
1777                 GP_4_30_FN, FN_IP10_22,
1778                 GP_4_29_FN, FN_IP11_18_16,
1779                 GP_4_28_FN, FN_USB_OVC0,
1780                 GP_4_27_FN, FN_IP11_15_13,
1781                 GP_4_26_FN, FN_PENC0,
1782                 GP_4_25_FN, FN_IP11_2,
1783                 GP_4_24_FN, FN_SCL0,
1784                 GP_4_23_FN, FN_IP11_1,
1785                 GP_4_22_FN, FN_IP11_0,
1786                 GP_4_21_FN, FN_IP10_21_19,
1787                 GP_4_20_FN, FN_IP10_18_16,
1788                 GP_4_19_FN, FN_IP10_15,
1789                 GP_4_18_FN, FN_IP10_14_12,
1790                 GP_4_17_FN, FN_IP10_11_9,
1791                 GP_4_16_FN, FN_IP10_8_6,
1792                 GP_4_15_FN, FN_IP10_5_3,
1793                 GP_4_14_FN, FN_IP10_2_0,
1794                 GP_4_13_FN, FN_IP9_29_28,
1795                 GP_4_12_FN, FN_IP9_27_26,
1796                 GP_4_11_FN, FN_IP9_9_8,
1797                 GP_4_10_FN, FN_IP9_7_6,
1798                 GP_4_9_FN, FN_IP9_5_4,
1799                 GP_4_8_FN, FN_IP9_3_2,
1800                 GP_4_7_FN, FN_IP9_17_16,
1801                 GP_4_6_FN, FN_IP9_15_14,
1802                 GP_4_5_FN, FN_IP9_13_12,
1803                 GP_4_4_FN, FN_IP9_11_10,
1804                 GP_4_3_FN, FN_IP9_25_24,
1805                 GP_4_2_FN, FN_IP9_23_22,
1806                 GP_4_1_FN, FN_IP9_21_20,
1807                 GP_4_0_FN, FN_IP9_19_18 ))
1808         },
1809         { PINMUX_CFG_REG("GPSR5", 0xFFFC0018, 32, 1, GROUP(
1810                 0, 0, 0, 0, 0, 0, 0, 0, /* 31 - 28 */
1811                 0, 0, 0, 0, 0, 0, 0, 0, /* 27 - 24 */
1812                 0, 0, 0, 0, 0, 0, 0, 0, /* 23 - 20 */
1813                 0, 0, 0, 0, 0, 0, 0, 0, /* 19 - 16 */
1814                 0, 0, 0, 0, 0, 0, 0, 0, /* 15 - 12 */
1815                 GP_5_11_FN, FN_IP10_29_28,
1816                 GP_5_10_FN, FN_IP10_27_26,
1817                 0, 0, 0, 0, 0, 0, 0, 0, /* 9 - 6 */
1818                 0, 0, 0, 0, /* 5, 4 */
1819                 GP_5_3_FN, FN_IRQ3_B,
1820                 GP_5_2_FN, FN_IRQ2_B,
1821                 GP_5_1_FN, FN_IP11_3,
1822                 GP_5_0_FN, FN_IP10_25 ))
1823         },
1824
1825         { PINMUX_CFG_REG_VAR("IPSR0", 0xFFFC001C, 32,
1826                         GROUP(2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2),
1827                         GROUP(
1828                 /* IP0_31_30 [2] */
1829                 FN_A15, FN_ST0_VCO_CLKIN, FN_LCD_DATA15_A,
1830                         FN_TIOC3D_C,
1831                 /* IP0_29_28 [2] */
1832                 FN_A14, FN_LCD_DATA14_A, FN_TIOC3C_C, 0,
1833                 /* IP0_27_26 [2] */
1834                 FN_A13, FN_LCD_DATA13_A, FN_TIOC3B_C, 0,
1835                 /* IP0_25_24 [2] */
1836                 FN_A12, FN_LCD_DATA12_A, FN_TIOC3A_C, 0,
1837                 /* IP0_23_22 [2] */
1838                 FN_A11, FN_ST0_D7, FN_LCD_DATA11_A, FN_TIOC2B_C,
1839                 /* IP0_21_20 [2] */
1840                 FN_A10, FN_ST0_D6, FN_LCD_DATA10_A, FN_TIOC2A_C,
1841                 /* IP0_19_18 [2] */
1842                 FN_A9, FN_ST0_D5, FN_LCD_DATA9_A, FN_TIOC1B_C,
1843                 /* IP0_17_16 [2] */
1844                 FN_A8, FN_ST0_D4, FN_LCD_DATA8_A, FN_TIOC1A_C,
1845                 /* IP0_15_14 [2] */
1846                 FN_A7, FN_ST0_D3, FN_LCD_DATA7_A, FN_TIOC0D_C,
1847                 /* IP0_13_12 [2] */
1848                 FN_A6, FN_ST0_D2, FN_LCD_DATA6_A, FN_TIOC0C_C,
1849                 /* IP0_11_10 [2] */
1850                 FN_A5, FN_ST0_D1, FN_LCD_DATA5_A, FN_TIOC0B_C,
1851                 /* IP0_9_8 [2] */
1852                 FN_A4, FN_ST0_D0, FN_LCD_DATA4_A, FN_TIOC0A_C,
1853                 /* IP0_7_6 [2] */
1854                 FN_A3, FN_ST0_VLD, FN_LCD_DATA3_A, FN_TCLKD_C,
1855                 /* IP0_5_4 [2] */
1856                 FN_A2, FN_ST0_SYC, FN_LCD_DATA2_A, FN_TCLKC_C,
1857                 /* IP0_3_2 [2] */
1858                 FN_A1, FN_ST0_REQ, FN_LCD_DATA1_A, FN_TCLKB_C,
1859                 /* IP0_1_0 [2] */
1860                 FN_A0, FN_ST0_CLKIN, FN_LCD_DATA0_A, FN_TCLKA_C ))
1861         },
1862         { PINMUX_CFG_REG_VAR("IPSR1", 0xFFFC0020, 32,
1863                         GROUP(3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2),
1864                         GROUP(
1865                 /* IP1_31_29 [3] */
1866                 FN_D3, FN_SD0_DAT3_A, FN_MMC_D3_A, FN_ST1_D6,
1867                         FN_FD3_A, 0, 0, 0,
1868                 /* IP1_28_26 [3] */
1869                 FN_D2, FN_SD0_DAT2_A, FN_MMC_D2_A, FN_ST1_D5,
1870                         FN_FD2_A, 0, 0, 0,
1871                 /* IP1_25_23 [3] */
1872                 FN_D1, FN_SD0_DAT1_A, FN_MMC_D1_A, FN_ST1_D4,
1873                         FN_FD1_A, 0, 0, 0,
1874                 /* IP1_22_20 [3] */
1875                 FN_D0, FN_SD0_DAT0_A, FN_MMC_D0_A, FN_ST1_D3,
1876                         FN_FD0_A, 0, 0, 0,
1877                 /* IP1_19_18 [2] */
1878                 FN_A25, FN_TX2_D, FN_ST1_D2, 0,
1879                 /* IP1_17_16 [2] */
1880                 FN_A24, FN_RX2_D, FN_ST1_D1, 0,
1881                 /* IP1_15_14 [2] */
1882                 FN_A23, FN_ST1_D0, FN_LCD_M_DISP_A, 0,
1883                 /* IP1_13_12 [2] */
1884                 FN_A22, FN_ST1_VLD, FN_LCD_VEPWC_A, 0,
1885                 /* IP1_11_10 [2] */
1886                 FN_A21, FN_ST1_SYC, FN_LCD_VCPWC_A, 0,
1887                 /* IP1_9_8 [2] */
1888                 FN_A20, FN_ST1_REQ, FN_LCD_FLM_A, 0,
1889                 /* IP1_7_6 [2] */
1890                 FN_A19, FN_ST1_CLKIN, FN_LCD_CLK_A,     FN_TIOC4D_C,
1891                 /* IP1_5_4 [2] */
1892                 FN_A18, FN_ST1_PWM, FN_LCD_CL2_A, FN_TIOC4C_C,
1893                 /* IP1_3_2 [2] */
1894                 FN_A17, FN_ST1_VCO_CLKIN, FN_LCD_CL1_A, FN_TIOC4B_C,
1895                 /* IP1_1_0 [2] */
1896                 FN_A16, FN_ST0_PWM, FN_LCD_DON_A, FN_TIOC4A_C ))
1897         },
1898         { PINMUX_CFG_REG_VAR("IPSR2", 0xFFFC0024, 32,
1899                              GROUP(1, 3, 3, 2, 3, 3, 3, 3, 3, 3, 2, 3),
1900                              GROUP(
1901                 /* IP2_31 [1] */
1902                 0, 0,
1903                 /* IP2_30_28 [3] */
1904                 FN_D14, FN_TX2_B, 0, FN_FSE_A,
1905                         FN_ET0_TX_CLK_B, 0, 0, 0,
1906                 /* IP2_27_25 [3] */
1907                 FN_D13, FN_RX2_B, 0, FN_FRB_A,
1908                         FN_ET0_ETXD6_B, 0, 0, 0,
1909                 /* IP2_24_23 [2] */
1910                 FN_D12, 0, FN_FWE_A, FN_ET0_ETXD5_B,
1911                 /* IP2_22_20 [3] */
1912                 FN_D11, FN_RSPI_MISO_A, 0, FN_QMI_QIO1_A,
1913                         FN_FRE_A, FN_ET0_ETXD3_B, 0, 0,
1914                 /* IP2_19_17 [3] */
1915                 FN_D10, FN_RSPI_MOSI_A, 0, FN_QMO_QIO0_A,
1916                         FN_FALE_A, FN_ET0_ETXD2_B, 0, 0,
1917                 /* IP2_16_14 [3] */
1918                 FN_D9, FN_SD0_CMD_A, FN_MMC_CMD_A, FN_QIO3_A,
1919                         FN_FCLE_A, FN_ET0_ETXD1_B, 0, 0,
1920                 /* IP2_13_11 [3] */
1921                 FN_D8, FN_SD0_CLK_A, FN_MMC_CLK_A, FN_QIO2_A,
1922                         FN_FCE_A, FN_ET0_GTX_CLK_B, 0, 0,
1923                 /* IP2_10_8 [3] */
1924                 FN_D7, FN_RSPI_SSL_A, FN_MMC_D7_A, FN_QSSL_A,
1925                         FN_FD7_A, 0, 0, 0,
1926                 /* IP2_7_5 [3] */
1927                 FN_D6, FN_RSPI_RSPCK_A, FN_MMC_D6_A, FN_QSPCLK_A,
1928                         FN_FD6_A, 0, 0, 0,
1929                 /* IP2_4_3 [2] */
1930                 FN_D5, FN_SD0_WP_A, FN_MMC_D5_A, FN_FD5_A,
1931                 /* IP2_2_0 [3] */
1932                 FN_D4, FN_SD0_CD_A, FN_MMC_D4_A, FN_ST1_D7,
1933                         FN_FD4_A, 0, 0, 0 ))
1934         },
1935         { PINMUX_CFG_REG_VAR("IPSR3", 0xFFFC0028, 32,
1936                              GROUP(2, 3, 3, 3, 1, 2, 3, 3, 3, 3, 3, 1, 2),
1937                              GROUP(
1938             /* IP3_31_30 [2] */
1939                 0, 0, 0, 0,
1940             /* IP3_29_27 [3] */
1941                 FN_DRACK0, FN_SD1_DAT2_A, FN_ATAG, FN_TCLK1_A,
1942                 FN_ET0_ETXD7, 0, 0, 0,
1943             /* IP3_26_24 [3] */
1944                 FN_EX_WAIT2, FN_SD1_DAT1_A, FN_DACK2, FN_CAN1_RX_C,
1945                 FN_ET0_MAGIC_C, FN_ET0_ETXD6_A, 0, 0,
1946             /* IP3_23_21 [3] */
1947                 FN_EX_WAIT1, FN_SD1_DAT0_A, FN_DREQ2, FN_CAN1_TX_C,
1948                 FN_ET0_LINK_C, FN_ET0_ETXD5_A, 0, 0,
1949             /* IP3_20 [1] */
1950                 FN_EX_WAIT0, FN_TCLK1_B,
1951             /* IP3_19_18 [2] */
1952                 FN_RD_WR, FN_TCLK0, FN_CAN_CLK_B, FN_ET0_ETXD4,
1953             /* IP3_17_15 [3] */
1954                 FN_EX_CS5, FN_SD1_CMD_A, FN_ATADIR, FN_QSSL_B,
1955                 FN_ET0_ETXD3_A, 0, 0, 0,
1956             /* IP3_14_12 [3] */
1957                 FN_EX_CS4, FN_SD1_WP_A, FN_ATAWR, FN_QMI_QIO1_B,
1958                 FN_ET0_ETXD2_A, 0, 0, 0,
1959             /* IP3_11_9 [3] */
1960                 FN_EX_CS3, FN_SD1_CD_A, FN_ATARD, FN_QMO_QIO0_B,
1961                 FN_ET0_ETXD1_A, 0, 0, 0,
1962             /* IP3_8_6 [3] */
1963                 FN_EX_CS2, FN_TX3_B, FN_ATACS1, FN_QSPCLK_B,
1964                 FN_ET0_GTX_CLK_A, 0, 0, 0,
1965             /* IP3_5_3 [3] */
1966                 FN_EX_CS1, FN_RX3_B, FN_ATACS0, FN_QIO2_B,
1967                 FN_ET0_ETXD0, 0, 0, 0,
1968             /* IP3_2 [1] */
1969                 FN_CS1_A26, FN_QIO3_B,
1970             /* IP3_1_0 [2] */
1971                 FN_D15, FN_SCK2_B, 0, 0 ))
1972         },
1973         { PINMUX_CFG_REG_VAR("IPSR4", 0xFFFC002C, 32,
1974                              GROUP(2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3),
1975                              GROUP(
1976             /* IP4_31_30 [2] */
1977                 0, FN_SCK2_A, FN_VI0_G3, 0,
1978             /* IP4_29_28 [2] */
1979                 0, FN_RTS1_B, FN_VI0_G2, 0,
1980             /* IP4_27_26 [2] */
1981                 0, FN_CTS1_B, FN_VI0_DATA7_VI0_G1, 0,
1982             /* IP4_25_24 [2] */
1983                 0, FN_TX1_B, FN_VI0_DATA6_VI0_G0, FN_ET0_PHY_INT_A,
1984             /* IP4_23_22 [2] */
1985                 0, FN_RX1_B, FN_VI0_DATA5_VI0_B5, FN_ET0_MAGIC_A,
1986             /* IP4_21_20 [2] */
1987                 0, FN_SCK1_B, FN_VI0_DATA4_VI0_B4, FN_ET0_LINK_A,
1988             /* IP4_19_18 [2] */
1989                 0, FN_RTS0_B, FN_VI0_DATA3_VI0_B3, FN_ET0_MDIO_A,
1990             /* IP4_17_15 [3] */
1991                 0, FN_CTS0_B, FN_VI0_DATA2_VI0_B2, FN_RMII0_MDIO_A,
1992                         FN_ET0_MDC, 0, 0, 0,
1993             /* IP4_14_12 [3] */
1994                 FN_HTX0_A, FN_TX1_A, FN_VI0_DATA1_VI0_B1, FN_RMII0_MDC_A,
1995                         FN_ET0_COL, 0, 0, 0,
1996             /* IP4_11_9 [3] */
1997                 FN_HRX0_A, FN_RX1_A, FN_VI0_DATA0_VI0_B0, FN_RMII0_CRS_DV_A,
1998                         FN_ET0_CRS, 0, 0, 0,
1999             /* IP4_8_6 [3] */
2000                 FN_HSCK0_A, FN_SCK1_A, FN_VI0_VSYNC, FN_RMII0_RX_ER_A,
2001                         FN_ET0_RX_ER, 0, 0, 0,
2002             /* IP4_5_3 [3] */
2003                 FN_HRTS0_A, FN_RTS1_A, FN_VI0_HSYNC, FN_RMII0_TXD_EN_A,
2004                         FN_ET0_RX_DV, 0, 0, 0,
2005             /* IP4_2_0 [3] */
2006                 FN_HCTS0_A, FN_CTS1_A, FN_VI0_FIELD, FN_RMII0_RXD1_A,
2007                         FN_ET0_ERXD7, 0, 0, 0 ))
2008         },
2009         { PINMUX_CFG_REG_VAR("IPSR5", 0xFFFC0030, 32,
2010                              GROUP(1, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3,
2011                                    3, 3, 3),
2012                              GROUP(
2013             /* IP5_31 [1] */
2014             0, 0,
2015             /* IP5_30 [1] */
2016             0, 0,
2017             /* IP5_29 [1] */
2018             0, 0,
2019             /* IP5_28 [1] */
2020             0, 0,
2021             /* IP5_27 [1] */
2022             0, 0,
2023             /* IP5_26_25 [2] */
2024                 FN_REF50CK, FN_CTS1_E, FN_HCTS0_D, 0,
2025             /* IP5_24_23 [2] */
2026                 FN_REF125CK, FN_ADTRG, FN_RX5_C, 0,
2027             /* IP5_22_21 [2] */
2028                 FN_SD2_WP_A, FN_TX5_A, FN_VI0_R5, 0,
2029             /* IP5_20_18 [3] */
2030                 FN_SD2_CD_A, FN_RX5_A, FN_VI0_R4, 0,
2031                 0, 0, 0, FN_ET0_PHY_INT_B,
2032             /* IP5_17_15 [3] */
2033                 FN_SD2_DAT3_A, FN_TX4_A, FN_VI0_R3, 0,
2034                 0, 0, 0, FN_ET0_MAGIC_B,
2035             /* IP5_14_12 [3] */
2036                 FN_SD2_DAT2_A, FN_RX4_A, FN_VI0_R2, 0,
2037                 0, 0, 0, FN_ET0_LINK_B,
2038             /* IP5_11_9 [3] */
2039                 FN_SD2_DAT1_A, FN_TX3_A, FN_VI0_R1, 0,
2040                 0, 0, 0, FN_ET0_MDIO_B,
2041             /* IP5_8_6 [3] */
2042                 FN_SD2_DAT0_A, FN_RX3_A, FN_VI0_R0, 0,
2043                 0, 0, 0, FN_ET0_ERXD3_B,
2044             /* IP5_5_3 [3] */
2045                 FN_SD2_CMD_A, FN_TX2_A, FN_VI0_G5, 0,
2046                 0, 0, 0, FN_ET0_ERXD2_B,
2047             /* IP5_2_0 [3] */
2048                 FN_SD2_CLK_A, FN_RX2_A, FN_VI0_G4, 0,
2049                 FN_ET0_RX_CLK_B, 0, 0, 0 ))
2050         },
2051         { PINMUX_CFG_REG_VAR("IPSR6", 0xFFFC0034, 32,
2052                              GROUP(1, 1, 1, 1, 1, 1, 1, 1, 3, 3, 2, 2,
2053                                    2, 2, 2, 2, 3, 3),
2054                              GROUP(
2055             /* IP5_31 [1] */
2056             0, 0,
2057             /* IP6_30 [1] */
2058             0, 0,
2059             /* IP6_29 [1] */
2060             0, 0,
2061             /* IP6_28 [1] */
2062             0, 0,
2063             /* IP6_27 [1] */
2064             0, 0,
2065             /* IP6_26 [1] */
2066             0, 0,
2067             /* IP6_25 [1] */
2068             0, 0,
2069             /* IP6_24 [1] */
2070             0, 0,
2071             /* IP6_23_21 [3] */
2072                 FN_DU0_DG1, FN_CTS1_C, FN_HRTS0_D, FN_TIOC1B_A,
2073                 FN_HIFD09, 0, 0, 0,
2074             /* IP6_20_18 [3] */
2075                 FN_DU0_DG0, FN_TX1_C, FN_HSCK0_D, FN_IECLK_A,
2076                 FN_TIOC1A_A, FN_HIFD08, 0, 0,
2077             /* IP6_17_16 [2] */
2078                 FN_DU0_DR7, FN_RX1_C, FN_TIOC0D_A, FN_HIFD07,
2079             /* IP6_15_14 [2] */
2080                 FN_DU0_DR6, FN_SCK1_C, FN_TIOC0C_A, FN_HIFD06,
2081             /* IP6_13_12 [2] */
2082                 FN_DU0_DR5, FN_RTS0_C, FN_TIOC0B_A, FN_HIFD05,
2083             /* IP6_11_10 [2] */
2084                 FN_DU0_DR4, FN_CTS0_C, FN_TIOC0A_A, FN_HIFD04,
2085             /* IP6_9_8 [2] */
2086                 FN_DU0_DR3, FN_TX0_B, FN_TCLKD_A, FN_HIFD03,
2087             /* IP6_7_6 [2] */
2088                 FN_DU0_DR2, FN_RX0_B, FN_TCLKC_A, FN_HIFD02,
2089             /* IP6_5_3 [3] */
2090                 FN_DU0_DR1, FN_SCK0_B, FN_HTX0_D, FN_IERX_A,
2091                 FN_TCLKB_A, FN_HIFD01, 0, 0,
2092             /* IP6_2_0 [3] */
2093                 FN_DU0_DR0, FN_SCIF_CLK_B, FN_HRX0_D, FN_IETX_A,
2094                 FN_TCLKA_A, FN_HIFD00, 0, 0 ))
2095         },
2096         { PINMUX_CFG_REG_VAR("IPSR7", 0xFFFC0038, 32,
2097                              GROUP(1, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3),
2098                              GROUP(
2099             /* IP7_31 [1] */
2100             0, 0,
2101             /* IP7_30_29 [2] */
2102                 FN_DU0_DB4, 0, FN_HIFINT, 0,
2103             /* IP7_28_27 [2] */
2104                 FN_DU0_DB3, FN_TX5_B, FN_TIOC4D_A, FN_HIFRD,
2105             /* IP7_26_24 [3] */
2106                 FN_DU0_DB2, FN_RX5_B, FN_RMII0_TXD1_B, FN_TIOC4C_A,
2107                 FN_HIFWR, 0, 0, 0,
2108             /* IP7_23_21 [3] */
2109                 FN_DU0_DB1, FN_TX4_C, FN_RMII0_TXD0_B, FN_TIOC4B_A,
2110                 FN_HIFRS, 0, 0, 0,
2111             /* IP7_20_18 [3] */
2112                 FN_DU0_DB0, FN_RX4_C, FN_RMII0_TXD_EN_B, FN_TIOC4A_A,
2113                 FN_HIFCS, 0, 0, 0,
2114             /* IP7_17_15 [3] */
2115                 FN_DU0_DG7, FN_TX3_C, FN_RMII0_RXD1_B, FN_TIOC3D_A,
2116                 FN_HIFD15, 0, 0, 0,
2117             /* IP7_14_12 [3] */
2118                 FN_DU0_DG6, FN_RX3_C, FN_RMII0_RXD0_B, FN_TIOC3C_A,
2119                 FN_HIFD14, 0, 0, 0,
2120             /* IP7_11_9 [3] */
2121                 FN_DU0_DG5, FN_TX2_C, FN_RMII0_RX_ER_B, FN_TIOC3B_A,
2122                 FN_HIFD13, 0, 0, 0,
2123             /* IP7_8_6 [3] */
2124                 FN_DU0_DG4, FN_RX2_C, FN_RMII0_CRS_DV_B, FN_TIOC3A_A,
2125                 FN_HIFD12, 0, 0, 0,
2126             /* IP7_5_3 [3] */
2127                 FN_DU0_DG3, FN_SCK2_C, FN_RMII0_MDIO_B, FN_TIOC2B_A,
2128                 FN_HIFD11, 0, 0, 0,
2129             /* IP7_2_0 [3] */
2130                 FN_DU0_DG2, FN_RTS1_C, FN_RMII0_MDC_B, FN_TIOC2A_A,
2131                 FN_HIFD10, 0, 0, 0 ))
2132         },
2133         { PINMUX_CFG_REG_VAR("IPSR8", 0xFFFC003C, 32,
2134                              GROUP(2, 2, 2, 3, 3, 2, 2, 2, 2, 2, 2, 2,
2135                                    2, 2, 2),
2136                              GROUP(
2137             /* IP9_31_30 [2] */
2138             0, 0, 0, 0,
2139             /* IP8_29_28 [2] */
2140                 FN_IRQ3_A, FN_RTS0_A, FN_HRTS0_B, FN_ET0_ERXD3_A,
2141             /* IP8_27_26 [2] */
2142                 FN_IRQ2_A, FN_CTS0_A, FN_HCTS0_B, FN_ET0_ERXD2_A,
2143             /* IP8_25_23 [3] */
2144                 FN_IRQ1_A, 0, FN_HSPI_RX_B, FN_TX3_E,
2145                         FN_ET0_ERXD1, 0, 0, 0,
2146             /* IP8_22_20 [3] */
2147                 FN_IRQ0_A, 0, FN_HSPI_TX_B, FN_RX3_E,
2148                         FN_ET0_ERXD0, 0, 0, 0,
2149             /* IP8_19_18 [2] */
2150                 FN_DU0_CDE, FN_HTX0_B, FN_AUDIO_CLKB_B, FN_LCD_VCPWC_B,
2151             /* IP8_17_16 [2] */
2152                 FN_DU0_DISP, FN_CAN0_TX_B, FN_HRX0_B, FN_AUDIO_CLKA_B,
2153             /* IP8_15_14 [2] */
2154                 FN_DU0_EXODDF_DU0_ODDF, FN_CAN0_RX_B, FN_HSCK0_B,
2155                         FN_SSI_SDATA1_B,
2156             /* IP8_13_12 [2] */
2157                 FN_DU0_EXVSYNC_DU0_VSYNC, 0, FN_HSPI_RX0_C, FN_SSI_WS1_B,
2158             /* IP8_11_10 [2] */
2159                 FN_DU0_EXHSYNC_DU0_HSYNC, 0, FN_HSPI_TX0_C, FN_SSI_SCK1_B,
2160             /* IP8_9_8 [2] */
2161                 FN_DU0_DOTCLKOUT, 0, FN_HSPI_CLK0_C, FN_SSI_SDATA0_B,
2162             /* IP8_7_6 [2] */
2163                 FN_DU0_DOTCLKIN, 0, FN_HSPI_CS0_C, FN_SSI_WS0_B,
2164             /* IP8_5_4 [2] */
2165                 FN_DU0_DB7, 0, FN_SSI_SCK0_B, FN_HIFEBL_B,
2166             /* IP8_3_2 [2] */
2167                 FN_DU0_DB6, 0, FN_HIFRDY, 0,
2168             /* IP8_1_0 [2] */
2169                 FN_DU0_DB5, 0, FN_HIFDREQ, 0 ))
2170         },
2171         { PINMUX_CFG_REG_VAR("IPSR9", 0xFFFC0040, 32,
2172                              GROUP(2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
2173                                    2, 2, 2, 2),
2174                              GROUP(
2175             /* IP9_31_30 [2] */
2176             0, 0, 0, 0,
2177             /* IP9_29_28 [2] */
2178                 FN_SSI_SDATA1_A, FN_VI1_3_B, FN_LCD_DATA14_B, 0,
2179             /* IP9_27_26 [2] */
2180                 FN_SSI_WS1_A, FN_VI1_2_B, FN_LCD_DATA13_B, 0,
2181             /* IP9_25_24 [2] */
2182                 FN_SSI_SCK1_A, FN_VI1_1_B, FN_TIOC2B_B, FN_LCD_DATA12_B,
2183             /* IP9_23_22 [2] */
2184                 FN_SSI_SDATA0_A, FN_VI1_0_B, FN_TIOC2A_B, FN_LCD_DATA11_B,
2185             /* IP9_21_20 [2] */
2186                 FN_SSI_WS0_A, FN_TIOC1B_B, FN_LCD_DATA10_B, 0,
2187             /* IP9_19_18 [2] */
2188                 FN_SSI_SCK0_A, FN_TIOC1A_B, FN_LCD_DATA9_B, 0,
2189             /* IP9_17_16 [2] */
2190                 FN_VI1_7_A, FN_FCE_B, FN_LCD_DATA8_B, 0,
2191             /* IP9_15_14 [2] */
2192                 FN_VI1_6_A, 0, FN_FD7_B, FN_LCD_DATA7_B,
2193             /* IP9_13_12 [2] */
2194                 FN_VI1_5_A, 0, FN_FD6_B, FN_LCD_DATA6_B,
2195             /* IP9_11_10 [2] */
2196                 FN_VI1_4_A, 0, FN_FD5_B, FN_LCD_DATA5_B,
2197             /* IP9_9_8 [2] */
2198                 FN_VI1_3_A, 0, FN_FD4_B, FN_LCD_DATA4_B,
2199             /* IP9_7_6 [2] */
2200                 FN_VI1_2_A, 0, FN_FD3_B, FN_LCD_DATA3_B,
2201             /* IP9_5_4 [2] */
2202                 FN_VI1_1_A, 0, FN_FD2_B, FN_LCD_DATA2_B,
2203             /* IP9_3_2 [2] */
2204                 FN_VI1_0_A, 0, FN_FD1_B, FN_LCD_DATA1_B,
2205             /* IP9_1_0 [2] */
2206                 FN_VI1_CLK_A, 0, FN_FD0_B, FN_LCD_DATA0_B ))
2207         },
2208         { PINMUX_CFG_REG_VAR("IPSR10", 0xFFFC0044, 32,
2209                              GROUP(2, 2, 2, 1, 2, 1, 3, 3, 1, 3, 3, 3, 3, 3),
2210                              GROUP(
2211             /* IP9_31_30 [2] */
2212             0, 0, 0, 0,
2213             /* IP10_29_28 [2] */
2214                 FN_CAN1_TX_A, FN_TX5_C, FN_MLB_DAT, 0,
2215             /* IP10_27_26 [2] */
2216                 FN_CAN0_RX_A, FN_IRQ0_B, FN_MLB_SIG, 0,
2217             /* IP10_25 [1] */
2218                 FN_CAN1_RX_A, FN_IRQ1_B,
2219             /* IP10_24_23 [2] */
2220                 FN_CAN0_TX_A, FN_TX4_D, FN_MLB_CLK, 0,
2221             /* IP10_22 [1] */
2222                 FN_CAN_CLK_A, FN_RX4_D,
2223             /* IP10_21_19 [3] */
2224                 FN_AUDIO_CLKOUT, FN_TX1_E, 0, FN_HRTS0_C, FN_FSE_B,
2225                 FN_LCD_M_DISP_B, 0, 0,
2226             /* IP10_18_16 [3] */
2227                 FN_AUDIO_CLKC, FN_SCK1_E, 0, FN_HCTS0_C, FN_FRB_B,
2228                 FN_LCD_VEPWC_B, 0, 0,
2229             /* IP10_15 [1] */
2230                 FN_AUDIO_CLKB_A, FN_LCD_CLK_B,
2231             /* IP10_14_12 [3] */
2232                 FN_AUDIO_CLKA_A, FN_VI1_CLK_B, FN_SCK1_D, FN_IECLK_B,
2233                 FN_LCD_FLM_B, 0, 0, 0,
2234             /* IP10_11_9 [3] */
2235                 FN_SSI_SDATA3, FN_VI1_7_B, 0, FN_HTX0_C, FN_FWE_B,
2236                 FN_LCD_CL2_B, 0, 0,
2237             /* IP10_8_6 [3] */
2238                 FN_SSI_SDATA2, FN_VI1_6_B, 0, FN_HRX0_C, FN_FRE_B,
2239                 FN_LCD_CL1_B, 0, 0,
2240             /* IP10_5_3 [3] */
2241                 FN_SSI_WS23, FN_VI1_5_B, FN_TX1_D, FN_HSCK0_C, FN_FALE_B,
2242                 FN_LCD_DON_B, 0, 0,
2243             /* IP10_2_0 [3] */
2244                 FN_SSI_SCK23, FN_VI1_4_B, FN_RX1_D, FN_FCLE_B,
2245                 FN_LCD_DATA15_B, 0, 0, 0 ))
2246         },
2247         { PINMUX_CFG_REG_VAR("IPSR11", 0xFFFC0048, 32,
2248                              GROUP(3, 1, 2, 3, 2, 2, 3, 3, 1, 2, 3, 3,
2249                                    1, 1, 1, 1),
2250                              GROUP(
2251             /* IP11_31_29 [3] */
2252             0, 0, 0, 0, 0, 0, 0, 0,
2253             /* IP11_28 [1] */
2254                 FN_PRESETOUT, FN_ST_CLKOUT,
2255             /* IP11_27_26 [2] */
2256                 FN_DACK1, FN_HSPI_CS_B, FN_TX4_B, FN_ET0_RX_CLK_A,
2257             /* IP11_25_23 [3] */
2258                 FN_DREQ1, FN_HSPI_CLK_B, FN_RX4_B, FN_ET0_PHY_INT_C,
2259                 FN_ET0_TX_CLK_A, 0, 0, 0,
2260             /* IP11_22_21 [2] */
2261                 FN_DACK0, FN_SD1_DAT3_A, FN_ET0_TX_ER, 0,
2262             /* IP11_20_19 [2] */
2263                 FN_DREQ0, FN_SD1_CLK_A, FN_ET0_TX_EN, 0,
2264             /* IP11_18_16 [3] */
2265                 FN_USB_OVC1, FN_RX3_D, FN_CAN1_RX_B, FN_RX5_D,
2266                 FN_IERX_B, 0, 0, 0,
2267             /* IP11_15_13 [3] */
2268                 FN_PENC1, FN_TX3_D, FN_CAN1_TX_B, FN_TX5_D,
2269                 FN_IETX_B, 0, 0, 0,
2270             /* IP11_12 [1] */
2271                 FN_TX0_A, FN_HSPI_TX_A,
2272             /* IP11_11_10 [2] */
2273                 FN_RX0_A, FN_HSPI_RX_A, FN_RMII0_RXD0_A, FN_ET0_ERXD6,
2274             /* IP11_9_7 [3] */
2275                 FN_SCK0_A, FN_HSPI_CS_A, FN_VI0_CLKENB, FN_RMII0_TXD1_A,
2276                 FN_ET0_ERXD5, 0, 0, 0,
2277             /* IP11_6_4 [3] */
2278                 FN_SCIF_CLK_A, FN_HSPI_CLK_A, FN_VI0_CLK, FN_RMII0_TXD0_A,
2279                 FN_ET0_ERXD4, 0, 0, 0,
2280             /* IP11_3 [1] */
2281                 FN_SDSELF, FN_RTS1_E,
2282             /* IP11_2 [1] */
2283                 FN_SDA0, FN_HIFEBL_A,
2284             /* IP11_1 [1] */
2285                 FN_SDA1, FN_RX1_E,
2286             /* IP11_0 [1] */
2287                 FN_SCL1, FN_SCIF_CLK_C ))
2288         },
2289         { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xFFFC004C, 32,
2290                              GROUP(3, 1, 1, 1, 1, 1, 1, 2, 1, 1, 1, 2,
2291                                    2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
2292                              GROUP(
2293                 /* SEL1_31_29 [3] */
2294                 0, 0, 0, 0, 0, 0, 0, 0,
2295                 /* SEL1_28 [1] */
2296                 FN_SEL_IEBUS_0, FN_SEL_IEBUS_1,
2297                 /* SEL1_27 [1] */
2298                 FN_SEL_RQSPI_0, FN_SEL_RQSPI_1,
2299                 /* SEL1_26 [1] */
2300                 FN_SEL_VIN1_0, FN_SEL_VIN1_1,
2301                 /* SEL1_25 [1] */
2302                 FN_SEL_HIF_0, FN_SEL_HIF_1,
2303                 /* SEL1_24 [1] */
2304                 FN_SEL_RSPI_0, FN_SEL_RSPI_1,
2305                 /* SEL1_23 [1] */
2306                 FN_SEL_LCDC_0, FN_SEL_LCDC_1,
2307                 /* SEL1_22_21 [2] */
2308                 FN_SEL_ET0_CTL_0, FN_SEL_ET0_CTL_1, FN_SEL_ET0_CTL_2, 0,
2309                 /* SEL1_20 [1] */
2310                 FN_SEL_ET0_0, FN_SEL_ET0_1,
2311                 /* SEL1_19 [1] */
2312                 FN_SEL_RMII_0, FN_SEL_RMII_1,
2313                 /* SEL1_18 [1] */
2314                 FN_SEL_TMU_0, FN_SEL_TMU_1,
2315                 /* SEL1_17_16 [2] */
2316                 FN_SEL_HSPI_0, FN_SEL_HSPI_1, FN_SEL_HSPI_2, 0,
2317                 /* SEL1_15_14 [2] */
2318                 FN_SEL_HSCIF_0, FN_SEL_HSCIF_1, FN_SEL_HSCIF_2, FN_SEL_HSCIF_3,
2319                 /* SEL1_13 [1] */
2320                 FN_SEL_RCAN_CLK_0, FN_SEL_RCAN_CLK_1,
2321                 /* SEL1_12_11 [2] */
2322                 FN_SEL_RCAN1_0, FN_SEL_RCAN1_1, FN_SEL_RCAN1_2, 0,
2323                 /* SEL1_10 [1] */
2324                 FN_SEL_RCAN0_0, FN_SEL_RCAN0_1,
2325                 /* SEL1_9 [1] */
2326                 FN_SEL_SDHI2_0, FN_SEL_SDHI2_1,
2327                 /* SEL1_8 [1] */
2328                 FN_SEL_SDHI1_0, FN_SEL_SDHI1_1,
2329                 /* SEL1_7 [1] */
2330                 FN_SEL_SDHI0_0, FN_SEL_SDHI0_1,
2331                 /* SEL1_6 [1] */
2332                 FN_SEL_SSI1_0, FN_SEL_SSI1_1,
2333                 /* SEL1_5 [1] */
2334                 FN_SEL_SSI0_0, FN_SEL_SSI0_1,
2335                 /* SEL1_4 [1] */
2336                 FN_SEL_AUDIO_CLKB_0, FN_SEL_AUDIO_CLKB_1,
2337                 /* SEL1_3 [1] */
2338                 FN_SEL_AUDIO_CLKA_0, FN_SEL_AUDIO_CLKA_1,
2339                 /* SEL1_2 [1] */
2340                 FN_SEL_FLCTL_0, FN_SEL_FLCTL_1,
2341                 /* SEL1_1 [1] */
2342                 FN_SEL_MMC_0, FN_SEL_MMC_1,
2343                 /* SEL1_0 [1] */
2344                 FN_SEL_INTC_0, FN_SEL_INTC_1 ))
2345         },
2346         { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xFFFC0050, 32,
2347                              GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2,
2348                                    2, 1, 2, 2, 3, 2, 3, 2, 2),
2349                              GROUP(
2350                 /* SEL2_31 [1] */
2351                 0, 0,
2352                 /* SEL2_30 [1] */
2353                 0, 0,
2354                 /* SEL2_29 [1] */
2355                 0, 0,
2356                 /* SEL2_28 [1] */
2357                 0, 0,
2358                 /* SEL2_27 [1] */
2359                 0, 0,
2360                 /* SEL2_26 [1] */
2361                 0, 0,
2362                 /* SEL2_25 [1] */
2363                 0, 0,
2364                 /* SEL2_24 [1] */
2365                 0, 0,
2366                 /* SEL2_23 [1] */
2367                 FN_SEL_MTU2_CLK_0, FN_SEL_MTU2_CLK_1,
2368                 /* SEL2_22 [1] */
2369                 FN_SEL_MTU2_CH4_0, FN_SEL_MTU2_CH4_1,
2370                 /* SEL2_21 [1] */
2371                 FN_SEL_MTU2_CH3_0, FN_SEL_MTU2_CH3_1,
2372                 /* SEL2_20_19 [2] */
2373                 FN_SEL_MTU2_CH2_0, FN_SEL_MTU2_CH2_1, FN_SEL_MTU2_CH2_2, 0,
2374                 /* SEL2_18_17 [2] */
2375                 FN_SEL_MTU2_CH1_0, FN_SEL_MTU2_CH1_1, FN_SEL_MTU2_CH1_2, 0,
2376                 /* SEL2_16 [1] */
2377                 FN_SEL_MTU2_CH0_0, FN_SEL_MTU2_CH0_1,
2378                 /* SEL2_15_14 [2] */
2379                 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
2380                 /* SEL2_13_12 [2] */
2381                 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
2382                 /* SEL2_11_9 [3] */
2383                 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
2384                 FN_SEL_SCIF3_4, 0, 0, 0,
2385                 /* SEL2_8_7 [2] */
2386                 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF2_3,
2387                 /* SEL2_6_4 [3] */
2388                 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
2389                         FN_SEL_SCIF1_4, 0, 0, 0,
2390                 /* SEL2_3_2 [2] */
2391                 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, 0,
2392                 /* SEL2_1_0 [2] */
2393                 FN_SEL_SCIF_CLK_0, FN_SEL_SCIF_CLK_1, FN_SEL_SCIF_CLK_2, 0  ))
2394         },
2395         /* GPIO 0 - 5*/
2396         { PINMUX_CFG_REG("INOUTSEL0", 0xFFC40004, 32, 1, GROUP(GP_INOUTSEL(0)))
2397         },
2398         { PINMUX_CFG_REG("INOUTSEL1", 0xFFC41004, 32, 1, GROUP(GP_INOUTSEL(1)))
2399         },
2400         { PINMUX_CFG_REG("INOUTSEL2", 0xFFC42004, 32, 1, GROUP(GP_INOUTSEL(2)))
2401         },
2402         { PINMUX_CFG_REG("INOUTSEL3", 0xFFC43004, 32, 1, GROUP(GP_INOUTSEL(3)))
2403         },
2404         { PINMUX_CFG_REG("INOUTSEL4", 0xFFC44004, 32, 1, GROUP(GP_INOUTSEL(4)))
2405         },
2406         { PINMUX_CFG_REG("INOUTSEL5", 0xffc45004, 32, 1, GROUP(
2407                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 31 - 24 */
2408                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 23 - 16 */
2409                 0, 0, 0, 0, 0, 0, 0, 0, /* 15 - 12 */
2410                 GP_5_11_IN, GP_5_11_OUT,
2411                 GP_5_10_IN, GP_5_10_OUT,
2412                 GP_5_9_IN, GP_5_9_OUT,
2413                 GP_5_8_IN, GP_5_8_OUT,
2414                 GP_5_7_IN, GP_5_7_OUT,
2415                 GP_5_6_IN, GP_5_6_OUT,
2416                 GP_5_5_IN, GP_5_5_OUT,
2417                 GP_5_4_IN, GP_5_4_OUT,
2418                 GP_5_3_IN, GP_5_3_OUT,
2419                 GP_5_2_IN, GP_5_2_OUT,
2420                 GP_5_1_IN, GP_5_1_OUT,
2421                 GP_5_0_IN, GP_5_0_OUT ))
2422         },
2423         { },
2424 };
2425
2426 static const struct pinmux_data_reg pinmux_data_regs[] = {
2427         /* GPIO 0 - 5*/
2428         { PINMUX_DATA_REG("INDT0", 0xFFC4000C, 32, GROUP(GP_INDT(0))) },
2429         { PINMUX_DATA_REG("INDT1", 0xFFC4100C, 32, GROUP(GP_INDT(1))) },
2430         { PINMUX_DATA_REG("INDT2", 0xFFC4200C, 32, GROUP(GP_INDT(2))) },
2431         { PINMUX_DATA_REG("INDT3", 0xFFC4300C, 32, GROUP(GP_INDT(3))) },
2432         { PINMUX_DATA_REG("INDT4", 0xFFC4400C, 32, GROUP(GP_INDT(4))) },
2433         { PINMUX_DATA_REG("INDT5", 0xFFC4500C, 32, GROUP(
2434                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2435                 0, 0, 0, 0,
2436                 GP_5_11_DATA, GP_5_10_DATA, GP_5_9_DATA, GP_5_8_DATA,
2437                 GP_5_7_DATA, GP_5_6_DATA, GP_5_5_DATA, GP_5_4_DATA,
2438                 GP_5_3_DATA, GP_5_2_DATA, GP_5_1_DATA, GP_5_0_DATA ))
2439         },
2440         { },
2441 };
2442
2443 const struct sh_pfc_soc_info sh7734_pinmux_info = {
2444         .name = "sh7734_pfc",
2445
2446         .unlock_reg = 0xFFFC0000,
2447
2448         .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
2449         .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
2450         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2451
2452         .pins = pinmux_pins,
2453         .nr_pins = ARRAY_SIZE(pinmux_pins),
2454         .func_gpios = pinmux_func_gpios,
2455         .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
2456
2457         .cfg_regs = pinmux_config_regs,
2458         .data_regs = pinmux_data_regs,
2459
2460         .pinmux_data = pinmux_data,
2461         .pinmux_data_size = ARRAY_SIZE(pinmux_data),
2462 };