drivers/pinctrl/tegra/pinctrl-tegra124.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Pinctrl data for the NVIDIA Tegra124 pinmux
   4  *
   5  * Author: Ashwini Ghuge <aghuge@nvidia.com>
   6  *
   7  * Copyright (c) 2013-2014, NVIDIA CORPORATION.  All rights reserved.
   8  */
   9
  10 #include <linux/init.h>
  11 #include <linux/of.h>
  12 #include <linux/platform_device.h>
  13 #include <linux/pinctrl/pinctrl.h>
  14 #include <linux/pinctrl/pinmux.h>
  15
  16 #include "pinctrl-tegra.h"
  17
  18 /*
  19  * Most pins affected by the pinmux can also be GPIOs. Define these first.
  20  * These must match how the GPIO driver names/numbers its pins.
  21  */
  22 #define _GPIO(offset)                           (offset)
  23
  24 #define TEGRA_PIN_CLK_32K_OUT_PA0               _GPIO(0)
  25 #define TEGRA_PIN_UART3_CTS_N_PA1               _GPIO(1)
  26 #define TEGRA_PIN_DAP2_FS_PA2                   _GPIO(2)
  27 #define TEGRA_PIN_DAP2_SCLK_PA3                 _GPIO(3)
  28 #define TEGRA_PIN_DAP2_DIN_PA4                  _GPIO(4)
  29 #define TEGRA_PIN_DAP2_DOUT_PA5                 _GPIO(5)
  30 #define TEGRA_PIN_SDMMC3_CLK_PA6                _GPIO(6)
  31 #define TEGRA_PIN_SDMMC3_CMD_PA7                _GPIO(7)
  32 #define TEGRA_PIN_PB0                           _GPIO(8)
  33 #define TEGRA_PIN_PB1                           _GPIO(9)
  34 #define TEGRA_PIN_SDMMC3_DAT3_PB4               _GPIO(12)
  35 #define TEGRA_PIN_SDMMC3_DAT2_PB5               _GPIO(13)
  36 #define TEGRA_PIN_SDMMC3_DAT1_PB6               _GPIO(14)
  37 #define TEGRA_PIN_SDMMC3_DAT0_PB7               _GPIO(15)
  38 #define TEGRA_PIN_UART3_RTS_N_PC0               _GPIO(16)
  39 #define TEGRA_PIN_UART2_TXD_PC2                 _GPIO(18)
  40 #define TEGRA_PIN_UART2_RXD_PC3                 _GPIO(19)
  41 #define TEGRA_PIN_GEN1_I2C_SCL_PC4              _GPIO(20)
  42 #define TEGRA_PIN_GEN1_I2C_SDA_PC5              _GPIO(21)
  43 #define TEGRA_PIN_PC7                           _GPIO(23)
  44 #define TEGRA_PIN_PG0                           _GPIO(48)
  45 #define TEGRA_PIN_PG1                           _GPIO(49)
  46 #define TEGRA_PIN_PG2                           _GPIO(50)
  47 #define TEGRA_PIN_PG3                           _GPIO(51)
  48 #define TEGRA_PIN_PG4                           _GPIO(52)
  49 #define TEGRA_PIN_PG5                           _GPIO(53)
  50 #define TEGRA_PIN_PG6                           _GPIO(54)
  51 #define TEGRA_PIN_PG7                           _GPIO(55)
  52 #define TEGRA_PIN_PH0                           _GPIO(56)
  53 #define TEGRA_PIN_PH1                           _GPIO(57)
  54 #define TEGRA_PIN_PH2                           _GPIO(58)
  55 #define TEGRA_PIN_PH3                           _GPIO(59)
  56 #define TEGRA_PIN_PH4                           _GPIO(60)
  57 #define TEGRA_PIN_PH5                           _GPIO(61)
  58 #define TEGRA_PIN_PH6                           _GPIO(62)
  59 #define TEGRA_PIN_PH7                           _GPIO(63)
  60 #define TEGRA_PIN_PI0                           _GPIO(64)
  61 #define TEGRA_PIN_PI1                           _GPIO(65)
  62 #define TEGRA_PIN_PI2                           _GPIO(66)
  63 #define TEGRA_PIN_PI3                           _GPIO(67)
  64 #define TEGRA_PIN_PI4                           _GPIO(68)
  65 #define TEGRA_PIN_PI5                           _GPIO(69)
  66 #define TEGRA_PIN_PI6                           _GPIO(70)
  67 #define TEGRA_PIN_PI7                           _GPIO(71)
  68 #define TEGRA_PIN_PJ0                           _GPIO(72)
  69 #define TEGRA_PIN_PJ2                           _GPIO(74)
  70 #define TEGRA_PIN_UART2_CTS_N_PJ5               _GPIO(77)
  71 #define TEGRA_PIN_UART2_RTS_N_PJ6               _GPIO(78)
  72 #define TEGRA_PIN_PJ7                           _GPIO(79)
  73 #define TEGRA_PIN_PK0                           _GPIO(80)
  74 #define TEGRA_PIN_PK1                           _GPIO(81)
  75 #define TEGRA_PIN_PK2                           _GPIO(82)
  76 #define TEGRA_PIN_PK3                           _GPIO(83)
  77 #define TEGRA_PIN_PK4                           _GPIO(84)
  78 #define TEGRA_PIN_SPDIF_OUT_PK5                 _GPIO(85)
  79 #define TEGRA_PIN_SPDIF_IN_PK6                  _GPIO(86)
  80 #define TEGRA_PIN_PK7                           _GPIO(87)
  81 #define TEGRA_PIN_DAP1_FS_PN0                   _GPIO(104)
  82 #define TEGRA_PIN_DAP1_DIN_PN1                  _GPIO(105)
  83 #define TEGRA_PIN_DAP1_DOUT_PN2                 _GPIO(106)
  84 #define TEGRA_PIN_DAP1_SCLK_PN3                 _GPIO(107)
  85 #define TEGRA_PIN_USB_VBUS_EN0_PN4              _GPIO(108)
  86 #define TEGRA_PIN_USB_VBUS_EN1_PN5              _GPIO(109)
  87 #define TEGRA_PIN_HDMI_INT_PN7                  _GPIO(111)
  88 #define TEGRA_PIN_ULPI_DATA7_PO0                _GPIO(112)
  89 #define TEGRA_PIN_ULPI_DATA0_PO1                _GPIO(113)
  90 #define TEGRA_PIN_ULPI_DATA1_PO2                _GPIO(114)
  91 #define TEGRA_PIN_ULPI_DATA2_PO3                _GPIO(115)
  92 #define TEGRA_PIN_ULPI_DATA3_PO4                _GPIO(116)
  93 #define TEGRA_PIN_ULPI_DATA4_PO5                _GPIO(117)
  94 #define TEGRA_PIN_ULPI_DATA5_PO6                _GPIO(118)
  95 #define TEGRA_PIN_ULPI_DATA6_PO7                _GPIO(119)
  96 #define TEGRA_PIN_DAP3_FS_PP0                   _GPIO(120)
  97 #define TEGRA_PIN_DAP3_DIN_PP1                  _GPIO(121)
  98 #define TEGRA_PIN_DAP3_DOUT_PP2                 _GPIO(122)
  99 #define TEGRA_PIN_DAP3_SCLK_PP3                 _GPIO(123)
 100 #define TEGRA_PIN_DAP4_FS_PP4                   _GPIO(124)
 101 #define TEGRA_PIN_DAP4_DIN_PP5                  _GPIO(125)
 102 #define TEGRA_PIN_DAP4_DOUT_PP6                 _GPIO(126)
 103 #define TEGRA_PIN_DAP4_SCLK_PP7                 _GPIO(127)
 104 #define TEGRA_PIN_KB_COL0_PQ0                   _GPIO(128)
 105 #define TEGRA_PIN_KB_COL1_PQ1                   _GPIO(129)
 106 #define TEGRA_PIN_KB_COL2_PQ2                   _GPIO(130)
 107 #define TEGRA_PIN_KB_COL3_PQ3                   _GPIO(131)
 108 #define TEGRA_PIN_KB_COL4_PQ4                   _GPIO(132)
 109 #define TEGRA_PIN_KB_COL5_PQ5                   _GPIO(133)
 110 #define TEGRA_PIN_KB_COL6_PQ6                   _GPIO(134)
 111 #define TEGRA_PIN_KB_COL7_PQ7                   _GPIO(135)
 112 #define TEGRA_PIN_KB_ROW0_PR0                   _GPIO(136)
 113 #define TEGRA_PIN_KB_ROW1_PR1                   _GPIO(137)
 114 #define TEGRA_PIN_KB_ROW2_PR2                   _GPIO(138)
 115 #define TEGRA_PIN_KB_ROW3_PR3                   _GPIO(139)
 116 #define TEGRA_PIN_KB_ROW4_PR4                   _GPIO(140)
 117 #define TEGRA_PIN_KB_ROW5_PR5                   _GPIO(141)
 118 #define TEGRA_PIN_KB_ROW6_PR6                   _GPIO(142)
 119 #define TEGRA_PIN_KB_ROW7_PR7                   _GPIO(143)
 120 #define TEGRA_PIN_KB_ROW8_PS0                   _GPIO(144)
 121 #define TEGRA_PIN_KB_ROW9_PS1                   _GPIO(145)
 122 #define TEGRA_PIN_KB_ROW10_PS2                  _GPIO(146)
 123 #define TEGRA_PIN_KB_ROW11_PS3                  _GPIO(147)
 124 #define TEGRA_PIN_KB_ROW12_PS4                  _GPIO(148)
 125 #define TEGRA_PIN_KB_ROW13_PS5                  _GPIO(149)
 126 #define TEGRA_PIN_KB_ROW14_PS6                  _GPIO(150)
 127 #define TEGRA_PIN_KB_ROW15_PS7                  _GPIO(151)
 128 #define TEGRA_PIN_KB_ROW16_PT0                  _GPIO(152)
 129 #define TEGRA_PIN_KB_ROW17_PT1                  _GPIO(153)
 130 #define TEGRA_PIN_GEN2_I2C_SCL_PT5              _GPIO(157)
 131 #define TEGRA_PIN_GEN2_I2C_SDA_PT6              _GPIO(158)
 132 #define TEGRA_PIN_SDMMC4_CMD_PT7                _GPIO(159)
 133 #define TEGRA_PIN_PU0                           _GPIO(160)
 134 #define TEGRA_PIN_PU1                           _GPIO(161)
 135 #define TEGRA_PIN_PU2                           _GPIO(162)
 136 #define TEGRA_PIN_PU3                           _GPIO(163)
 137 #define TEGRA_PIN_PU4                           _GPIO(164)
 138 #define TEGRA_PIN_PU5                           _GPIO(165)
 139 #define TEGRA_PIN_PU6                           _GPIO(166)
 140 #define TEGRA_PIN_PV0                           _GPIO(168)
 141 #define TEGRA_PIN_PV1                           _GPIO(169)
 142 #define TEGRA_PIN_SDMMC3_CD_N_PV2               _GPIO(170)
 143 #define TEGRA_PIN_SDMMC1_WP_N_PV3               _GPIO(171)
 144 #define TEGRA_PIN_DDC_SCL_PV4                   _GPIO(172)
 145 #define TEGRA_PIN_DDC_SDA_PV5                   _GPIO(173)
 146 #define TEGRA_PIN_GPIO_W2_AUD_PW2               _GPIO(178)
 147 #define TEGRA_PIN_GPIO_W3_AUD_PW3               _GPIO(179)
 148 #define TEGRA_PIN_DAP_MCLK1_PW4                 _GPIO(180)
 149 #define TEGRA_PIN_CLK2_OUT_PW5                  _GPIO(181)
 150 #define TEGRA_PIN_UART3_TXD_PW6                 _GPIO(182)
 151 #define TEGRA_PIN_UART3_RXD_PW7                 _GPIO(183)
 152 #define TEGRA_PIN_DVFS_PWM_PX0                  _GPIO(184)
 153 #define TEGRA_PIN_GPIO_X1_AUD_PX1               _GPIO(185)
 154 #define TEGRA_PIN_DVFS_CLK_PX2                  _GPIO(186)
 155 #define TEGRA_PIN_GPIO_X3_AUD_PX3               _GPIO(187)
 156 #define TEGRA_PIN_GPIO_X4_AUD_PX4               _GPIO(188)
 157 #define TEGRA_PIN_GPIO_X5_AUD_PX5               _GPIO(189)
 158 #define TEGRA_PIN_GPIO_X6_AUD_PX6               _GPIO(190)
 159 #define TEGRA_PIN_GPIO_X7_AUD_PX7               _GPIO(191)
 160 #define TEGRA_PIN_ULPI_CLK_PY0                  _GPIO(192)
 161 #define TEGRA_PIN_ULPI_DIR_PY1                  _GPIO(193)
 162 #define TEGRA_PIN_ULPI_NXT_PY2                  _GPIO(194)
 163 #define TEGRA_PIN_ULPI_STP_PY3                  _GPIO(195)
 164 #define TEGRA_PIN_SDMMC1_DAT3_PY4               _GPIO(196)
 165 #define TEGRA_PIN_SDMMC1_DAT2_PY5               _GPIO(197)
 166 #define TEGRA_PIN_SDMMC1_DAT1_PY6               _GPIO(198)
 167 #define TEGRA_PIN_SDMMC1_DAT0_PY7               _GPIO(199)
 168 #define TEGRA_PIN_SDMMC1_CLK_PZ0                _GPIO(200)
 169 #define TEGRA_PIN_SDMMC1_CMD_PZ1                _GPIO(201)
 170 #define TEGRA_PIN_PWR_I2C_SCL_PZ6               _GPIO(206)
 171 #define TEGRA_PIN_PWR_I2C_SDA_PZ7               _GPIO(207)
 172 #define TEGRA_PIN_SDMMC4_DAT0_PAA0              _GPIO(208)
 173 #define TEGRA_PIN_SDMMC4_DAT1_PAA1              _GPIO(209)
 174 #define TEGRA_PIN_SDMMC4_DAT2_PAA2              _GPIO(210)
 175 #define TEGRA_PIN_SDMMC4_DAT3_PAA3              _GPIO(211)
 176 #define TEGRA_PIN_SDMMC4_DAT4_PAA4              _GPIO(212)
 177 #define TEGRA_PIN_SDMMC4_DAT5_PAA5              _GPIO(213)
 178 #define TEGRA_PIN_SDMMC4_DAT6_PAA6              _GPIO(214)
 179 #define TEGRA_PIN_SDMMC4_DAT7_PAA7              _GPIO(215)
 180 #define TEGRA_PIN_PBB0                          _GPIO(216)
 181 #define TEGRA_PIN_CAM_I2C_SCL_PBB1              _GPIO(217)
 182 #define TEGRA_PIN_CAM_I2C_SDA_PBB2              _GPIO(218)
 183 #define TEGRA_PIN_PBB3                          _GPIO(219)
 184 #define TEGRA_PIN_PBB4                          _GPIO(220)
 185 #define TEGRA_PIN_PBB5                          _GPIO(221)
 186 #define TEGRA_PIN_PBB6                          _GPIO(222)
 187 #define TEGRA_PIN_PBB7                          _GPIO(223)
 188 #define TEGRA_PIN_CAM_MCLK_PCC0                 _GPIO(224)
 189 #define TEGRA_PIN_PCC1                          _GPIO(225)
 190 #define TEGRA_PIN_PCC2                          _GPIO(226)
 191 #define TEGRA_PIN_SDMMC4_CLK_PCC4               _GPIO(228)
 192 #define TEGRA_PIN_CLK2_REQ_PCC5                 _GPIO(229)
 193 #define TEGRA_PIN_PEX_L0_RST_N_PDD1             _GPIO(233)
 194 #define TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2          _GPIO(234)
 195 #define TEGRA_PIN_PEX_WAKE_N_PDD3               _GPIO(235)
 196 #define TEGRA_PIN_PEX_L1_RST_N_PDD5             _GPIO(237)
 197 #define TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6          _GPIO(238)
 198 #define TEGRA_PIN_CLK3_OUT_PEE0                 _GPIO(240)
 199 #define TEGRA_PIN_CLK3_REQ_PEE1                 _GPIO(241)
 200 #define TEGRA_PIN_DAP_MCLK1_REQ_PEE2            _GPIO(242)
 201 #define TEGRA_PIN_HDMI_CEC_PEE3                 _GPIO(243)
 202 #define TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4        _GPIO(244)
 203 #define TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5         _GPIO(245)
 204 #define TEGRA_PIN_DP_HPD_PFF0                   _GPIO(248)
 205 #define TEGRA_PIN_USB_VBUS_EN2_PFF1             _GPIO(249)
 206 #define TEGRA_PIN_PFF2                          _GPIO(250)
 207
 208 /* All non-GPIO pins follow */
 209 #define NUM_GPIOS                               (TEGRA_PIN_PFF2 + 1)
 210 #define _PIN(offset)                            (NUM_GPIOS + (offset))
 211
 212 /* Non-GPIO pins */
 213 #define TEGRA_PIN_CORE_PWR_REQ                  _PIN(0)
 214 #define TEGRA_PIN_CPU_PWR_REQ                   _PIN(1)
 215 #define TEGRA_PIN_PWR_INT_N                     _PIN(2)
 216 #define TEGRA_PIN_GMI_CLK_LB                    _PIN(3)
 217 #define TEGRA_PIN_RESET_OUT_N                   _PIN(4)
 218 #define TEGRA_PIN_OWR                           _PIN(5)
 219 #define TEGRA_PIN_CLK_32K_IN                    _PIN(6)
 220 #define TEGRA_PIN_JTAG_RTCK                     _PIN(7)
 221 #define TEGRA_PIN_DSI_B_CLK_P                   _PIN(8)
 222 #define TEGRA_PIN_DSI_B_CLK_N                   _PIN(9)
 223 #define TEGRA_PIN_DSI_B_D0_P                    _PIN(10)
 224 #define TEGRA_PIN_DSI_B_D0_N                    _PIN(11)
 225 #define TEGRA_PIN_DSI_B_D1_P                    _PIN(12)
 226 #define TEGRA_PIN_DSI_B_D1_N                    _PIN(13)
 227 #define TEGRA_PIN_DSI_B_D2_P                    _PIN(14)
 228 #define TEGRA_PIN_DSI_B_D2_N                    _PIN(15)
 229 #define TEGRA_PIN_DSI_B_D3_P                    _PIN(16)
 230 #define TEGRA_PIN_DSI_B_D3_N                    _PIN(17)
 231
 232 static const struct pinctrl_pin_desc tegra124_pins[] = {
 233         PINCTRL_PIN(TEGRA_PIN_CLK_32K_OUT_PA0, "CLK_32K_OUT PA0"),
 234         PINCTRL_PIN(TEGRA_PIN_UART3_CTS_N_PA1, "UART3_CTS_N PA1"),
 235         PINCTRL_PIN(TEGRA_PIN_DAP2_FS_PA2, "DAP2_FS PA2"),
 236         PINCTRL_PIN(TEGRA_PIN_DAP2_SCLK_PA3, "DAP2_SCLK PA3"),
 237         PINCTRL_PIN(TEGRA_PIN_DAP2_DIN_PA4, "DAP2_DIN PA4"),
 238         PINCTRL_PIN(TEGRA_PIN_DAP2_DOUT_PA5, "DAP2_DOUT PA5"),
 239         PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_PA6, "SDMMC3_CLK PA6"),
 240         PINCTRL_PIN(TEGRA_PIN_SDMMC3_CMD_PA7, "SDMMC3_CMD PA7"),
 241         PINCTRL_PIN(TEGRA_PIN_PB0, "PB0"),
 242         PINCTRL_PIN(TEGRA_PIN_PB1, "PB1"),
 243         PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT3_PB4, "SDMMC3_DAT3 PB4"),
 244         PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT2_PB5, "SDMMC3_DAT2 PB5"),
 245         PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT1_PB6, "SDMMC3_DAT1 PB6"),
 246         PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT0_PB7, "SDMMC3_DAT0 PB7"),
 247         PINCTRL_PIN(TEGRA_PIN_UART3_RTS_N_PC0, "UART3_RTS_N PC0"),
 248         PINCTRL_PIN(TEGRA_PIN_UART2_TXD_PC2, "UART2_TXD PC2"),
 249         PINCTRL_PIN(TEGRA_PIN_UART2_RXD_PC3, "UART2_RXD PC3"),
 250         PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SCL_PC4, "GEN1_I2C_SCL PC4"),
 251         PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SDA_PC5, "GEN1_I2C_SDA PC5"),
 252         PINCTRL_PIN(TEGRA_PIN_PC7, "PC7"),
 253         PINCTRL_PIN(TEGRA_PIN_PG0, "PG0"),
 254         PINCTRL_PIN(TEGRA_PIN_PG1, "PG1"),
 255         PINCTRL_PIN(TEGRA_PIN_PG2, "PG2"),
 256         PINCTRL_PIN(TEGRA_PIN_PG3, "PG3"),
 257         PINCTRL_PIN(TEGRA_PIN_PG4, "PG4"),
 258         PINCTRL_PIN(TEGRA_PIN_PG5, "PG5"),
 259         PINCTRL_PIN(TEGRA_PIN_PG6, "PG6"),
 260         PINCTRL_PIN(TEGRA_PIN_PG7, "PG7"),
 261         PINCTRL_PIN(TEGRA_PIN_PH0, "PH0"),
 262         PINCTRL_PIN(TEGRA_PIN_PH1, "PH1"),
 263         PINCTRL_PIN(TEGRA_PIN_PH2, "PH2"),
 264         PINCTRL_PIN(TEGRA_PIN_PH3, "PH3"),
 265         PINCTRL_PIN(TEGRA_PIN_PH4, "PH4"),
 266         PINCTRL_PIN(TEGRA_PIN_PH5, "PH5"),
 267         PINCTRL_PIN(TEGRA_PIN_PH6, "PH6"),
 268         PINCTRL_PIN(TEGRA_PIN_PH7, "PH7"),
 269         PINCTRL_PIN(TEGRA_PIN_PI0, "PI0"),
 270         PINCTRL_PIN(TEGRA_PIN_PI1, "PI1"),
 271         PINCTRL_PIN(TEGRA_PIN_PI2, "PI2"),
 272         PINCTRL_PIN(TEGRA_PIN_PI3, "PI3"),
 273         PINCTRL_PIN(TEGRA_PIN_PI4, "PI4"),
 274         PINCTRL_PIN(TEGRA_PIN_PI5, "PI5"),
 275         PINCTRL_PIN(TEGRA_PIN_PI6, "PI6"),
 276         PINCTRL_PIN(TEGRA_PIN_PI7, "PI7"),
 277         PINCTRL_PIN(TEGRA_PIN_PJ0, "PJ0"),
 278         PINCTRL_PIN(TEGRA_PIN_PJ2, "PJ2"),
 279         PINCTRL_PIN(TEGRA_PIN_UART2_CTS_N_PJ5, "UART2_CTS_N PJ5"),
 280         PINCTRL_PIN(TEGRA_PIN_UART2_RTS_N_PJ6, "UART2_RTS_N PJ6"),
 281         PINCTRL_PIN(TEGRA_PIN_PJ7, "PJ7"),
 282         PINCTRL_PIN(TEGRA_PIN_PK0, "PK0"),
 283         PINCTRL_PIN(TEGRA_PIN_PK1, "PK1"),
 284         PINCTRL_PIN(TEGRA_PIN_PK2, "PK2"),
 285         PINCTRL_PIN(TEGRA_PIN_PK3, "PK3"),
 286         PINCTRL_PIN(TEGRA_PIN_PK4, "PK4"),
 287         PINCTRL_PIN(TEGRA_PIN_SPDIF_OUT_PK5, "SPDIF_OUT PK5"),
 288         PINCTRL_PIN(TEGRA_PIN_SPDIF_IN_PK6, "SPDIF_IN PK6"),
 289         PINCTRL_PIN(TEGRA_PIN_PK7, "PK7"),
 290         PINCTRL_PIN(TEGRA_PIN_DAP1_FS_PN0, "DAP1_FS PN0"),
 291         PINCTRL_PIN(TEGRA_PIN_DAP1_DIN_PN1, "DAP1_DIN PN1"),
 292         PINCTRL_PIN(TEGRA_PIN_DAP1_DOUT_PN2, "DAP1_DOUT PN2"),
 293         PINCTRL_PIN(TEGRA_PIN_DAP1_SCLK_PN3, "DAP1_SCLK PN3"),
 294         PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN0_PN4, "USB_VBUS_EN0 PN4"),
 295         PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN1_PN5, "USB_VBUS_EN1 PN5"),
 296         PINCTRL_PIN(TEGRA_PIN_HDMI_INT_PN7, "HDMI_INT PN7"),
 297         PINCTRL_PIN(TEGRA_PIN_ULPI_DATA7_PO0, "ULPI_DATA7 PO0"),
 298         PINCTRL_PIN(TEGRA_PIN_ULPI_DATA0_PO1, "ULPI_DATA0 PO1"),
 299         PINCTRL_PIN(TEGRA_PIN_ULPI_DATA1_PO2, "ULPI_DATA1 PO2"),
 300         PINCTRL_PIN(TEGRA_PIN_ULPI_DATA2_PO3, "ULPI_DATA2 PO3"),
 301         PINCTRL_PIN(TEGRA_PIN_ULPI_DATA3_PO4, "ULPI_DATA3 PO4"),
 302         PINCTRL_PIN(TEGRA_PIN_ULPI_DATA4_PO5, "ULPI_DATA4 PO5"),
 303         PINCTRL_PIN(TEGRA_PIN_ULPI_DATA5_PO6, "ULPI_DATA5 PO6"),
 304         PINCTRL_PIN(TEGRA_PIN_ULPI_DATA6_PO7, "ULPI_DATA6 PO7"),
 305         PINCTRL_PIN(TEGRA_PIN_DAP3_FS_PP0, "DAP3_FS PP0"),
 306         PINCTRL_PIN(TEGRA_PIN_DAP3_DIN_PP1, "DAP3_DIN PP1"),
 307         PINCTRL_PIN(TEGRA_PIN_DAP3_DOUT_PP2, "DAP3_DOUT PP2"),
 308         PINCTRL_PIN(TEGRA_PIN_DAP3_SCLK_PP3, "DAP3_SCLK PP3"),
 309         PINCTRL_PIN(TEGRA_PIN_DAP4_FS_PP4, "DAP4_FS PP4"),
 310         PINCTRL_PIN(TEGRA_PIN_DAP4_DIN_PP5, "DAP4_DIN PP5"),
 311         PINCTRL_PIN(TEGRA_PIN_DAP4_DOUT_PP6, "DAP4_DOUT PP6"),
 312         PINCTRL_PIN(TEGRA_PIN_DAP4_SCLK_PP7, "DAP4_SCLK PP7"),
 313         PINCTRL_PIN(TEGRA_PIN_KB_COL0_PQ0, "KB_COL0 PQ0"),
 314         PINCTRL_PIN(TEGRA_PIN_KB_COL1_PQ1, "KB_COL1 PQ1"),
 315         PINCTRL_PIN(TEGRA_PIN_KB_COL2_PQ2, "KB_COL2 PQ2"),
 316         PINCTRL_PIN(TEGRA_PIN_KB_COL3_PQ3, "KB_COL3 PQ3"),
 317         PINCTRL_PIN(TEGRA_PIN_KB_COL4_PQ4, "KB_COL4 PQ4"),
 318         PINCTRL_PIN(TEGRA_PIN_KB_COL5_PQ5, "KB_COL5 PQ5"),
 319         PINCTRL_PIN(TEGRA_PIN_KB_COL6_PQ6, "KB_COL6 PQ6"),
 320         PINCTRL_PIN(TEGRA_PIN_KB_COL7_PQ7, "KB_COL7 PQ7"),
 321         PINCTRL_PIN(TEGRA_PIN_KB_ROW0_PR0, "KB_ROW0 PR0"),
 322         PINCTRL_PIN(TEGRA_PIN_KB_ROW1_PR1, "KB_ROW1 PR1"),
 323         PINCTRL_PIN(TEGRA_PIN_KB_ROW2_PR2, "KB_ROW2 PR2"),
 324         PINCTRL_PIN(TEGRA_PIN_KB_ROW3_PR3, "KB_ROW3 PR3"),
 325         PINCTRL_PIN(TEGRA_PIN_KB_ROW4_PR4, "KB_ROW4 PR4"),
 326         PINCTRL_PIN(TEGRA_PIN_KB_ROW5_PR5, "KB_ROW5 PR5"),
 327         PINCTRL_PIN(TEGRA_PIN_KB_ROW6_PR6, "KB_ROW6 PR6"),
 328         PINCTRL_PIN(TEGRA_PIN_KB_ROW7_PR7, "KB_ROW7 PR7"),
 329         PINCTRL_PIN(TEGRA_PIN_KB_ROW8_PS0, "KB_ROW8 PS0"),
 330         PINCTRL_PIN(TEGRA_PIN_KB_ROW9_PS1, "KB_ROW9 PS1"),
 331         PINCTRL_PIN(TEGRA_PIN_KB_ROW10_PS2, "KB_ROW10 PS2"),
 332         PINCTRL_PIN(TEGRA_PIN_KB_ROW11_PS3, "KB_ROW11 PS3"),
 333         PINCTRL_PIN(TEGRA_PIN_KB_ROW12_PS4, "KB_ROW12 PS4"),
 334         PINCTRL_PIN(TEGRA_PIN_KB_ROW13_PS5, "KB_ROW13 PS5"),
 335         PINCTRL_PIN(TEGRA_PIN_KB_ROW14_PS6, "KB_ROW14 PS6"),
 336         PINCTRL_PIN(TEGRA_PIN_KB_ROW15_PS7, "KB_ROW15 PS7"),
 337         PINCTRL_PIN(TEGRA_PIN_KB_ROW16_PT0, "KB_ROW16 PT0"),
 338         PINCTRL_PIN(TEGRA_PIN_KB_ROW17_PT1, "KB_ROW17 PT1"),
 339         PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PT5, "GEN2_I2C_SCL PT5"),
 340         PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PT6, "GEN2_I2C_SDA PT6"),
 341         PINCTRL_PIN(TEGRA_PIN_SDMMC4_CMD_PT7, "SDMMC4_CMD PT7"),
 342         PINCTRL_PIN(TEGRA_PIN_PU0, "PU0"),
 343         PINCTRL_PIN(TEGRA_PIN_PU1, "PU1"),
 344         PINCTRL_PIN(TEGRA_PIN_PU2, "PU2"),
 345         PINCTRL_PIN(TEGRA_PIN_PU3, "PU3"),
 346         PINCTRL_PIN(TEGRA_PIN_PU4, "PU4"),
 347         PINCTRL_PIN(TEGRA_PIN_PU5, "PU5"),
 348         PINCTRL_PIN(TEGRA_PIN_PU6, "PU6"),
 349         PINCTRL_PIN(TEGRA_PIN_PV0, "PV0"),
 350         PINCTRL_PIN(TEGRA_PIN_PV1, "PV1"),
 351         PINCTRL_PIN(TEGRA_PIN_SDMMC3_CD_N_PV2, "SDMMC3_CD_N PV2"),
 352         PINCTRL_PIN(TEGRA_PIN_SDMMC1_WP_N_PV3, "SDMMC1_WP_N PV3"),
 353         PINCTRL_PIN(TEGRA_PIN_DDC_SCL_PV4, "DDC_SCL PV4"),
 354         PINCTRL_PIN(TEGRA_PIN_DDC_SDA_PV5, "DDC_SDA PV5"),
 355         PINCTRL_PIN(TEGRA_PIN_GPIO_W2_AUD_PW2, "GPIO_W2_AUD PW2"),
 356         PINCTRL_PIN(TEGRA_PIN_GPIO_W3_AUD_PW3, "GPIO_W3_AUD PW3"),
 357         PINCTRL_PIN(TEGRA_PIN_DAP_MCLK1_PW4, "DAP_MCLK1 PW4"),
 358         PINCTRL_PIN(TEGRA_PIN_CLK2_OUT_PW5, "CLK2_OUT PW5"),
 359         PINCTRL_PIN(TEGRA_PIN_UART3_TXD_PW6, "UART3_TXD PW6"),
 360         PINCTRL_PIN(TEGRA_PIN_UART3_RXD_PW7, "UART3_RXD PW7"),
 361         PINCTRL_PIN(TEGRA_PIN_DVFS_PWM_PX0, "DVFS_PWM PX0"),
 362         PINCTRL_PIN(TEGRA_PIN_GPIO_X1_AUD_PX1, "GPIO_X1_AUD PX1"),
 363         PINCTRL_PIN(TEGRA_PIN_DVFS_CLK_PX2, "DVFS_CLK PX2"),
 364         PINCTRL_PIN(TEGRA_PIN_GPIO_X3_AUD_PX3, "GPIO_X3_AUD PX3"),
 365         PINCTRL_PIN(TEGRA_PIN_GPIO_X4_AUD_PX4, "GPIO_X4_AUD PX4"),
 366         PINCTRL_PIN(TEGRA_PIN_GPIO_X5_AUD_PX5, "GPIO_X5_AUD PX5"),
 367         PINCTRL_PIN(TEGRA_PIN_GPIO_X6_AUD_PX6, "GPIO_X6_AUD PX6"),
 368         PINCTRL_PIN(TEGRA_PIN_GPIO_X7_AUD_PX7, "GPIO_X7_AUD PX7"),
 369         PINCTRL_PIN(TEGRA_PIN_ULPI_CLK_PY0, "ULPI_CLK PY0"),
 370         PINCTRL_PIN(TEGRA_PIN_ULPI_DIR_PY1, "ULPI_DIR PY1"),
 371         PINCTRL_PIN(TEGRA_PIN_ULPI_NXT_PY2, "ULPI_NXT PY2"),
 372         PINCTRL_PIN(TEGRA_PIN_ULPI_STP_PY3, "ULPI_STP PY3"),
 373         PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT3_PY4, "SDMMC1_DAT3 PY4"),
 374         PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT2_PY5, "SDMMC1_DAT2 PY5"),
 375         PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT1_PY6, "SDMMC1_DAT1 PY6"),
 376         PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT0_PY7, "SDMMC1_DAT0 PY7"),
 377         PINCTRL_PIN(TEGRA_PIN_SDMMC1_CLK_PZ0, "SDMMC1_CLK PZ0"),
 378         PINCTRL_PIN(TEGRA_PIN_SDMMC1_CMD_PZ1, "SDMMC1_CMD PZ1"),
 379         PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PZ6, "PWR_I2C_SCL PZ6"),
 380         PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PZ7, "PWR_I2C_SDA PZ7"),
 381         PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT0_PAA0, "SDMMC4_DAT0 PAA0"),
 382         PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT1_PAA1, "SDMMC4_DAT1 PAA1"),
 383         PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT2_PAA2, "SDMMC4_DAT2 PAA2"),
 384         PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT3_PAA3, "SDMMC4_DAT3 PAA3"),
 385         PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT4_PAA4, "SDMMC4_DAT4 PAA4"),
 386         PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT5_PAA5, "SDMMC4_DAT5 PAA5"),
 387         PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT6_PAA6, "SDMMC4_DAT6 PAA6"),
 388         PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT7_PAA7, "SDMMC4_DAT7 PAA7"),
 389         PINCTRL_PIN(TEGRA_PIN_PBB0, "PBB0"),
 390         PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SCL_PBB1, "CAM_I2C_SCL PBB1"),
 391         PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SDA_PBB2, "CAM_I2C_SDA PBB2"),
 392         PINCTRL_PIN(TEGRA_PIN_PBB3, "PBB3"),
 393         PINCTRL_PIN(TEGRA_PIN_PBB4, "PBB4"),
 394         PINCTRL_PIN(TEGRA_PIN_PBB5, "PBB5"),
 395         PINCTRL_PIN(TEGRA_PIN_PBB6, "PBB6"),
 396         PINCTRL_PIN(TEGRA_PIN_PBB7, "PBB7"),
 397         PINCTRL_PIN(TEGRA_PIN_CAM_MCLK_PCC0, "CAM_MCLK PCC0"),
 398         PINCTRL_PIN(TEGRA_PIN_PCC1, "PCC1"),
 399         PINCTRL_PIN(TEGRA_PIN_PCC2, "PCC2"),
 400         PINCTRL_PIN(TEGRA_PIN_SDMMC4_CLK_PCC4, "SDMMC4_CLK PCC4"),
 401         PINCTRL_PIN(TEGRA_PIN_CLK2_REQ_PCC5, "CLK2_REQ PCC5"),
 402         PINCTRL_PIN(TEGRA_PIN_PEX_L0_RST_N_PDD1, "PEX_L0_RST_N PDD1"),
 403         PINCTRL_PIN(TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2, "PEX_L0_CLKREQ_N PDD2"),
 404         PINCTRL_PIN(TEGRA_PIN_PEX_WAKE_N_PDD3, "PEX_WAKE_N PDD3"),
 405         PINCTRL_PIN(TEGRA_PIN_PEX_L1_RST_N_PDD5, "PEX_L1_RST_N PDD5"),
 406         PINCTRL_PIN(TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6, "PEX_L1_CLKREQ_N PDD6"),
 407         PINCTRL_PIN(TEGRA_PIN_CLK3_OUT_PEE0, "CLK3_OUT PEE0"),
 408         PINCTRL_PIN(TEGRA_PIN_CLK3_REQ_PEE1, "CLK3_REQ PEE1"),
 409         PINCTRL_PIN(TEGRA_PIN_DAP_MCLK1_REQ_PEE2, "DAP_MCLK1_REQ PEE2"),
 410         PINCTRL_PIN(TEGRA_PIN_HDMI_CEC_PEE3, "HDMI_CEC PEE3"),
 411         PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4, "SDMMC3_CLK_LB_OUT PEE4"),
 412         PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5, "SDMMC3_CLK_LB_IN PEE5"),
 413         PINCTRL_PIN(TEGRA_PIN_DP_HPD_PFF0, "DP_HPD PFF0"),
 414         PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN2_PFF1, "USB_VBUS_EN2 PFF1"),
 415         PINCTRL_PIN(TEGRA_PIN_PFF2, "PFF2"),
 416         PINCTRL_PIN(TEGRA_PIN_CORE_PWR_REQ, "CORE_PWR_REQ"),
 417         PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ, "CPU_PWR_REQ"),
 418         PINCTRL_PIN(TEGRA_PIN_PWR_INT_N, "PWR_INT_N"),
 419         PINCTRL_PIN(TEGRA_PIN_GMI_CLK_LB, "GMI_CLK_LB"),
 420         PINCTRL_PIN(TEGRA_PIN_RESET_OUT_N, "RESET_OUT_N"),
 421         PINCTRL_PIN(TEGRA_PIN_OWR, "OWR"),
 422         PINCTRL_PIN(TEGRA_PIN_CLK_32K_IN, "CLK_32K_IN"),
 423         PINCTRL_PIN(TEGRA_PIN_JTAG_RTCK, "JTAG_RTCK"),
 424         PINCTRL_PIN(TEGRA_PIN_DSI_B_CLK_P, "DSI_B_CLK_P"),
 425         PINCTRL_PIN(TEGRA_PIN_DSI_B_CLK_N, "DSI_B_CLK_N"),
 426         PINCTRL_PIN(TEGRA_PIN_DSI_B_D0_P, "DSI_B_D0_P"),
 427         PINCTRL_PIN(TEGRA_PIN_DSI_B_D0_N, "DSI_B_D0_N"),
 428         PINCTRL_PIN(TEGRA_PIN_DSI_B_D1_P, "DSI_B_D1_P"),
 429         PINCTRL_PIN(TEGRA_PIN_DSI_B_D1_N, "DSI_B_D1_N"),
 430         PINCTRL_PIN(TEGRA_PIN_DSI_B_D2_P, "DSI_B_D2_P"),
 431         PINCTRL_PIN(TEGRA_PIN_DSI_B_D2_N, "DSI_B_D2_N"),
 432         PINCTRL_PIN(TEGRA_PIN_DSI_B_D3_P, "DSI_B_D3_P"),
 433         PINCTRL_PIN(TEGRA_PIN_DSI_B_D3_N, "DSI_B_D3_N"),
 434 };
 435
 436 static const unsigned clk_32k_out_pa0_pins[] = {
 437         TEGRA_PIN_CLK_32K_OUT_PA0,
 438 };
 439
 440 static const unsigned uart3_cts_n_pa1_pins[] = {
 441         TEGRA_PIN_UART3_CTS_N_PA1,
 442 };
 443
 444 static const unsigned dap2_fs_pa2_pins[] = {
 445         TEGRA_PIN_DAP2_FS_PA2,
 446 };
 447
 448 static const unsigned dap2_sclk_pa3_pins[] = {
 449         TEGRA_PIN_DAP2_SCLK_PA3,
 450 };
 451
 452 static const unsigned dap2_din_pa4_pins[] = {
 453         TEGRA_PIN_DAP2_DIN_PA4,
 454 };
 455
 456 static const unsigned dap2_dout_pa5_pins[] = {
 457         TEGRA_PIN_DAP2_DOUT_PA5,
 458 };
 459
 460 static const unsigned sdmmc3_clk_pa6_pins[] = {
 461         TEGRA_PIN_SDMMC3_CLK_PA6,
 462 };
 463
 464 static const unsigned sdmmc3_cmd_pa7_pins[] = {
 465         TEGRA_PIN_SDMMC3_CMD_PA7,
 466 };
 467
 468 static const unsigned pb0_pins[] = {
 469         TEGRA_PIN_PB0,
 470 };
 471
 472 static const unsigned pb1_pins[] = {
 473         TEGRA_PIN_PB1,
 474 };
 475
 476 static const unsigned sdmmc3_dat3_pb4_pins[] = {
 477         TEGRA_PIN_SDMMC3_DAT3_PB4,
 478 };
 479
 480 static const unsigned sdmmc3_dat2_pb5_pins[] = {
 481         TEGRA_PIN_SDMMC3_DAT2_PB5,
 482 };
 483
 484 static const unsigned sdmmc3_dat1_pb6_pins[] = {
 485         TEGRA_PIN_SDMMC3_DAT1_PB6,
 486 };
 487
 488 static const unsigned sdmmc3_dat0_pb7_pins[] = {
 489         TEGRA_PIN_SDMMC3_DAT0_PB7,
 490 };
 491
 492 static const unsigned uart3_rts_n_pc0_pins[] = {
 493         TEGRA_PIN_UART3_RTS_N_PC0,
 494 };
 495
 496 static const unsigned uart2_txd_pc2_pins[] = {
 497         TEGRA_PIN_UART2_TXD_PC2,
 498 };
 499
 500 static const unsigned uart2_rxd_pc3_pins[] = {
 501         TEGRA_PIN_UART2_RXD_PC3,
 502 };
 503
 504 static const unsigned gen1_i2c_scl_pc4_pins[] = {
 505         TEGRA_PIN_GEN1_I2C_SCL_PC4,
 506 };
 507
 508 static const unsigned gen1_i2c_sda_pc5_pins[] = {
 509         TEGRA_PIN_GEN1_I2C_SDA_PC5,
 510 };
 511
 512 static const unsigned pc7_pins[] = {
 513         TEGRA_PIN_PC7,
 514 };
 515
 516 static const unsigned pg0_pins[] = {
 517         TEGRA_PIN_PG0,
 518 };
 519
 520 static const unsigned pg1_pins[] = {
 521         TEGRA_PIN_PG1,
 522 };
 523
 524 static const unsigned pg2_pins[] = {
 525         TEGRA_PIN_PG2,
 526 };
 527
 528 static const unsigned pg3_pins[] = {
 529         TEGRA_PIN_PG3,
 530 };
 531
 532 static const unsigned pg4_pins[] = {
 533         TEGRA_PIN_PG4,
 534 };
 535
 536 static const unsigned pg5_pins[] = {
 537         TEGRA_PIN_PG5,
 538 };
 539
 540 static const unsigned pg6_pins[] = {
 541         TEGRA_PIN_PG6,
 542 };
 543
 544 static const unsigned pg7_pins[] = {
 545         TEGRA_PIN_PG7,
 546 };
 547
 548 static const unsigned ph0_pins[] = {
 549         TEGRA_PIN_PH0,
 550 };
 551
 552 static const unsigned ph1_pins[] = {
 553         TEGRA_PIN_PH1,
 554 };
 555
 556 static const unsigned ph2_pins[] = {
 557         TEGRA_PIN_PH2,
 558 };
 559
 560 static const unsigned ph3_pins[] = {
 561         TEGRA_PIN_PH3,
 562 };
 563
 564 static const unsigned ph4_pins[] = {
 565         TEGRA_PIN_PH4,
 566 };
 567
 568 static const unsigned ph5_pins[] = {
 569         TEGRA_PIN_PH5,
 570 };
 571
 572 static const unsigned ph6_pins[] = {
 573         TEGRA_PIN_PH6,
 574 };
 575
 576 static const unsigned ph7_pins[] = {
 577         TEGRA_PIN_PH7,
 578 };
 579
 580 static const unsigned pi0_pins[] = {
 581         TEGRA_PIN_PI0,
 582 };
 583
 584 static const unsigned pi1_pins[] = {
 585         TEGRA_PIN_PI1,
 586 };
 587
 588 static const unsigned pi2_pins[] = {
 589         TEGRA_PIN_PI2,
 590 };
 591
 592 static const unsigned pi3_pins[] = {
 593         TEGRA_PIN_PI3,
 594 };
 595
 596 static const unsigned pi4_pins[] = {
 597         TEGRA_PIN_PI4,
 598 };
 599
 600 static const unsigned pi5_pins[] = {
 601         TEGRA_PIN_PI5,
 602 };
 603
 604 static const unsigned pi6_pins[] = {
 605         TEGRA_PIN_PI6,
 606 };
 607
 608 static const unsigned pi7_pins[] = {
 609         TEGRA_PIN_PI7,
 610 };
 611
 612 static const unsigned pj0_pins[] = {
 613         TEGRA_PIN_PJ0,
 614 };
 615
 616 static const unsigned pj2_pins[] = {
 617         TEGRA_PIN_PJ2,
 618 };
 619
 620 static const unsigned uart2_cts_n_pj5_pins[] = {
 621         TEGRA_PIN_UART2_CTS_N_PJ5,
 622 };
 623
 624 static const unsigned uart2_rts_n_pj6_pins[] = {
 625         TEGRA_PIN_UART2_RTS_N_PJ6,
 626 };
 627
 628 static const unsigned pj7_pins[] = {
 629         TEGRA_PIN_PJ7,
 630 };
 631
 632 static const unsigned pk0_pins[] = {
 633         TEGRA_PIN_PK0,
 634 };
 635
 636 static const unsigned pk1_pins[] = {
 637         TEGRA_PIN_PK1,
 638 };
 639
 640 static const unsigned pk2_pins[] = {
 641         TEGRA_PIN_PK2,
 642 };
 643
 644 static const unsigned pk3_pins[] = {
 645         TEGRA_PIN_PK3,
 646 };
 647
 648 static const unsigned pk4_pins[] = {
 649         TEGRA_PIN_PK4,
 650 };
 651
 652 static const unsigned spdif_out_pk5_pins[] = {
 653         TEGRA_PIN_SPDIF_OUT_PK5,
 654 };
 655
 656 static const unsigned spdif_in_pk6_pins[] = {
 657         TEGRA_PIN_SPDIF_IN_PK6,
 658 };
 659
 660 static const unsigned pk7_pins[] = {
 661         TEGRA_PIN_PK7,
 662 };
 663
 664 static const unsigned dap1_fs_pn0_pins[] = {
 665         TEGRA_PIN_DAP1_FS_PN0,
 666 };
 667
 668 static const unsigned dap1_din_pn1_pins[] = {
 669         TEGRA_PIN_DAP1_DIN_PN1,
 670 };
 671
 672 static const unsigned dap1_dout_pn2_pins[] = {
 673         TEGRA_PIN_DAP1_DOUT_PN2,
 674 };
 675
 676 static const unsigned dap1_sclk_pn3_pins[] = {
 677         TEGRA_PIN_DAP1_SCLK_PN3,
 678 };
 679
 680 static const unsigned usb_vbus_en0_pn4_pins[] = {
 681         TEGRA_PIN_USB_VBUS_EN0_PN4,
 682 };
 683
 684 static const unsigned usb_vbus_en1_pn5_pins[] = {
 685         TEGRA_PIN_USB_VBUS_EN1_PN5,
 686 };
 687
 688 static const unsigned hdmi_int_pn7_pins[] = {
 689         TEGRA_PIN_HDMI_INT_PN7,
 690 };
 691
 692 static const unsigned ulpi_data7_po0_pins[] = {
 693         TEGRA_PIN_ULPI_DATA7_PO0,
 694 };
 695
 696 static const unsigned ulpi_data0_po1_pins[] = {
 697         TEGRA_PIN_ULPI_DATA0_PO1,
 698 };
 699
 700 static const unsigned ulpi_data1_po2_pins[] = {
 701         TEGRA_PIN_ULPI_DATA1_PO2,
 702 };
 703
 704 static const unsigned ulpi_data2_po3_pins[] = {
 705         TEGRA_PIN_ULPI_DATA2_PO3,
 706 };
 707
 708 static const unsigned ulpi_data3_po4_pins[] = {
 709         TEGRA_PIN_ULPI_DATA3_PO4,
 710 };
 711
 712 static const unsigned ulpi_data4_po5_pins[] = {
 713         TEGRA_PIN_ULPI_DATA4_PO5,
 714 };
 715
 716 static const unsigned ulpi_data5_po6_pins[] = {
 717         TEGRA_PIN_ULPI_DATA5_PO6,
 718 };
 719
 720 static const unsigned ulpi_data6_po7_pins[] = {
 721         TEGRA_PIN_ULPI_DATA6_PO7,
 722 };
 723
 724 static const unsigned dap3_fs_pp0_pins[] = {
 725         TEGRA_PIN_DAP3_FS_PP0,
 726 };
 727
 728 static const unsigned dap3_din_pp1_pins[] = {
 729         TEGRA_PIN_DAP3_DIN_PP1,
 730 };
 731
 732 static const unsigned dap3_dout_pp2_pins[] = {
 733         TEGRA_PIN_DAP3_DOUT_PP2,
 734 };
 735
 736 static const unsigned dap3_sclk_pp3_pins[] = {
 737         TEGRA_PIN_DAP3_SCLK_PP3,
 738 };
 739
 740 static const unsigned dap4_fs_pp4_pins[] = {
 741         TEGRA_PIN_DAP4_FS_PP4,
 742 };
 743
 744 static const unsigned dap4_din_pp5_pins[] = {
 745         TEGRA_PIN_DAP4_DIN_PP5,
 746 };
 747
 748 static const unsigned dap4_dout_pp6_pins[] = {
 749         TEGRA_PIN_DAP4_DOUT_PP6,
 750 };
 751
 752 static const unsigned dap4_sclk_pp7_pins[] = {
 753         TEGRA_PIN_DAP4_SCLK_PP7,
 754 };
 755
 756 static const unsigned kb_col0_pq0_pins[] = {
 757         TEGRA_PIN_KB_COL0_PQ0,
 758 };
 759
 760 static const unsigned kb_col1_pq1_pins[] = {
 761         TEGRA_PIN_KB_COL1_PQ1,
 762 };
 763
 764 static const unsigned kb_col2_pq2_pins[] = {
 765         TEGRA_PIN_KB_COL2_PQ2,
 766 };
 767
 768 static const unsigned kb_col3_pq3_pins[] = {
 769         TEGRA_PIN_KB_COL3_PQ3,
 770 };
 771
 772 static const unsigned kb_col4_pq4_pins[] = {
 773         TEGRA_PIN_KB_COL4_PQ4,
 774 };
 775
 776 static const unsigned kb_col5_pq5_pins[] = {
 777         TEGRA_PIN_KB_COL5_PQ5,
 778 };
 779
 780 static const unsigned kb_col6_pq6_pins[] = {
 781         TEGRA_PIN_KB_COL6_PQ6,
 782 };
 783
 784 static const unsigned kb_col7_pq7_pins[] = {
 785         TEGRA_PIN_KB_COL7_PQ7,
 786 };
 787
 788 static const unsigned kb_row0_pr0_pins[] = {
 789         TEGRA_PIN_KB_ROW0_PR0,
 790 };
 791
 792 static const unsigned kb_row1_pr1_pins[] = {
 793         TEGRA_PIN_KB_ROW1_PR1,
 794 };
 795
 796 static const unsigned kb_row2_pr2_pins[] = {
 797         TEGRA_PIN_KB_ROW2_PR2,
 798 };
 799
 800 static const unsigned kb_row3_pr3_pins[] = {
 801         TEGRA_PIN_KB_ROW3_PR3,
 802 };
 803
 804 static const unsigned kb_row4_pr4_pins[] = {
 805         TEGRA_PIN_KB_ROW4_PR4,
 806 };
 807
 808 static const unsigned kb_row5_pr5_pins[] = {
 809         TEGRA_PIN_KB_ROW5_PR5,
 810 };
 811
 812 static const unsigned kb_row6_pr6_pins[] = {
 813         TEGRA_PIN_KB_ROW6_PR6,
 814 };
 815
 816 static const unsigned kb_row7_pr7_pins[] = {
 817         TEGRA_PIN_KB_ROW7_PR7,
 818 };
 819
 820 static const unsigned kb_row8_ps0_pins[] = {
 821         TEGRA_PIN_KB_ROW8_PS0,
 822 };
 823
 824 static const unsigned kb_row9_ps1_pins[] = {
 825         TEGRA_PIN_KB_ROW9_PS1,
 826 };
 827
 828 static const unsigned kb_row10_ps2_pins[] = {
 829         TEGRA_PIN_KB_ROW10_PS2,
 830 };
 831
 832 static const unsigned kb_row11_ps3_pins[] = {
 833         TEGRA_PIN_KB_ROW11_PS3,
 834 };
 835
 836 static const unsigned kb_row12_ps4_pins[] = {
 837         TEGRA_PIN_KB_ROW12_PS4,
 838 };
 839
 840 static const unsigned kb_row13_ps5_pins[] = {
 841         TEGRA_PIN_KB_ROW13_PS5,
 842 };
 843
 844 static const unsigned kb_row14_ps6_pins[] = {
 845         TEGRA_PIN_KB_ROW14_PS6,
 846 };
 847
 848 static const unsigned kb_row15_ps7_pins[] = {
 849         TEGRA_PIN_KB_ROW15_PS7,
 850 };
 851
 852 static const unsigned kb_row16_pt0_pins[] = {
 853         TEGRA_PIN_KB_ROW16_PT0,
 854 };
 855
 856 static const unsigned kb_row17_pt1_pins[] = {
 857         TEGRA_PIN_KB_ROW17_PT1,
 858 };
 859
 860 static const unsigned gen2_i2c_scl_pt5_pins[] = {
 861         TEGRA_PIN_GEN2_I2C_SCL_PT5,
 862 };
 863
 864 static const unsigned gen2_i2c_sda_pt6_pins[] = {
 865         TEGRA_PIN_GEN2_I2C_SDA_PT6,
 866 };
 867
 868 static const unsigned sdmmc4_cmd_pt7_pins[] = {
 869         TEGRA_PIN_SDMMC4_CMD_PT7,
 870 };
 871
 872 static const unsigned pu0_pins[] = {
 873         TEGRA_PIN_PU0,
 874 };
 875
 876 static const unsigned pu1_pins[] = {
 877         TEGRA_PIN_PU1,
 878 };
 879
 880 static const unsigned pu2_pins[] = {
 881         TEGRA_PIN_PU2,
 882 };
 883
 884 static const unsigned pu3_pins[] = {
 885         TEGRA_PIN_PU3,
 886 };
 887
 888 static const unsigned pu4_pins[] = {
 889         TEGRA_PIN_PU4,
 890 };
 891
 892 static const unsigned pu5_pins[] = {
 893         TEGRA_PIN_PU5,
 894 };
 895
 896 static const unsigned pu6_pins[] = {
 897         TEGRA_PIN_PU6,
 898 };
 899
 900 static const unsigned pv0_pins[] = {
 901         TEGRA_PIN_PV0,
 902 };
 903
 904 static const unsigned pv1_pins[] = {
 905         TEGRA_PIN_PV1,
 906 };
 907
 908 static const unsigned sdmmc3_cd_n_pv2_pins[] = {
 909         TEGRA_PIN_SDMMC3_CD_N_PV2,
 910 };
 911
 912 static const unsigned sdmmc1_wp_n_pv3_pins[] = {
 913         TEGRA_PIN_SDMMC1_WP_N_PV3,
 914 };
 915
 916 static const unsigned ddc_scl_pv4_pins[] = {
 917         TEGRA_PIN_DDC_SCL_PV4,
 918 };
 919
 920 static const unsigned ddc_sda_pv5_pins[] = {
 921         TEGRA_PIN_DDC_SDA_PV5,
 922 };
 923
 924 static const unsigned gpio_w2_aud_pw2_pins[] = {
 925         TEGRA_PIN_GPIO_W2_AUD_PW2,
 926 };
 927
 928 static const unsigned gpio_w3_aud_pw3_pins[] = {
 929         TEGRA_PIN_GPIO_W3_AUD_PW3,
 930 };
 931
 932 static const unsigned dap_mclk1_pw4_pins[] = {
 933         TEGRA_PIN_DAP_MCLK1_PW4,
 934 };
 935
 936 static const unsigned clk2_out_pw5_pins[] = {
 937         TEGRA_PIN_CLK2_OUT_PW5,
 938 };
 939
 940 static const unsigned uart3_txd_pw6_pins[] = {
 941         TEGRA_PIN_UART3_TXD_PW6,
 942 };
 943
 944 static const unsigned uart3_rxd_pw7_pins[] = {
 945         TEGRA_PIN_UART3_RXD_PW7,
 946 };
 947
 948 static const unsigned dvfs_pwm_px0_pins[] = {
 949         TEGRA_PIN_DVFS_PWM_PX0,
 950 };
 951
 952 static const unsigned gpio_x1_aud_px1_pins[] = {
 953         TEGRA_PIN_GPIO_X1_AUD_PX1,
 954 };
 955
 956 static const unsigned dvfs_clk_px2_pins[] = {
 957         TEGRA_PIN_DVFS_CLK_PX2,
 958 };
 959
 960 static const unsigned gpio_x3_aud_px3_pins[] = {
 961         TEGRA_PIN_GPIO_X3_AUD_PX3,
 962 };
 963
 964 static const unsigned gpio_x4_aud_px4_pins[] = {
 965         TEGRA_PIN_GPIO_X4_AUD_PX4,
 966 };
 967
 968 static const unsigned gpio_x5_aud_px5_pins[] = {
 969         TEGRA_PIN_GPIO_X5_AUD_PX5,
 970 };
 971
 972 static const unsigned gpio_x6_aud_px6_pins[] = {
 973         TEGRA_PIN_GPIO_X6_AUD_PX6,
 974 };
 975
 976 static const unsigned gpio_x7_aud_px7_pins[] = {
 977         TEGRA_PIN_GPIO_X7_AUD_PX7,
 978 };
 979
 980 static const unsigned ulpi_clk_py0_pins[] = {
 981         TEGRA_PIN_ULPI_CLK_PY0,
 982 };
 983
 984 static const unsigned ulpi_dir_py1_pins[] = {
 985         TEGRA_PIN_ULPI_DIR_PY1,
 986 };
 987
 988 static const unsigned ulpi_nxt_py2_pins[] = {
 989         TEGRA_PIN_ULPI_NXT_PY2,
 990 };
 991
 992 static const unsigned ulpi_stp_py3_pins[] = {
 993         TEGRA_PIN_ULPI_STP_PY3,
 994 };
 995
 996 static const unsigned sdmmc1_dat3_py4_pins[] = {
 997         TEGRA_PIN_SDMMC1_DAT3_PY4,
 998 };
 999
1000 static const unsigned sdmmc1_dat2_py5_pins[] = {
1001         TEGRA_PIN_SDMMC1_DAT2_PY5,
1002 };
1003
1004 static const unsigned sdmmc1_dat1_py6_pins[] = {
1005         TEGRA_PIN_SDMMC1_DAT1_PY6,
1006 };
1007
1008 static const unsigned sdmmc1_dat0_py7_pins[] = {
1009         TEGRA_PIN_SDMMC1_DAT0_PY7,
1010 };
1011
1012 static const unsigned sdmmc1_clk_pz0_pins[] = {
1013         TEGRA_PIN_SDMMC1_CLK_PZ0,
1014 };
1015
1016 static const unsigned sdmmc1_cmd_pz1_pins[] = {
1017         TEGRA_PIN_SDMMC1_CMD_PZ1,
1018 };
1019
1020 static const unsigned pwr_i2c_scl_pz6_pins[] = {
1021         TEGRA_PIN_PWR_I2C_SCL_PZ6,
1022 };
1023
1024 static const unsigned pwr_i2c_sda_pz7_pins[] = {
1025         TEGRA_PIN_PWR_I2C_SDA_PZ7,
1026 };
1027
1028 static const unsigned sdmmc4_dat0_paa0_pins[] = {
1029         TEGRA_PIN_SDMMC4_DAT0_PAA0,
1030 };
1031
1032 static const unsigned sdmmc4_dat1_paa1_pins[] = {
1033         TEGRA_PIN_SDMMC4_DAT1_PAA1,
1034 };
1035
1036 static const unsigned sdmmc4_dat2_paa2_pins[] = {
1037         TEGRA_PIN_SDMMC4_DAT2_PAA2,
1038 };
1039
1040 static const unsigned sdmmc4_dat3_paa3_pins[] = {
1041         TEGRA_PIN_SDMMC4_DAT3_PAA3,
1042 };
1043
1044 static const unsigned sdmmc4_dat4_paa4_pins[] = {
1045         TEGRA_PIN_SDMMC4_DAT4_PAA4,
1046 };
1047
1048 static const unsigned sdmmc4_dat5_paa5_pins[] = {
1049         TEGRA_PIN_SDMMC4_DAT5_PAA5,
1050 };
1051
1052 static const unsigned sdmmc4_dat6_paa6_pins[] = {
1053         TEGRA_PIN_SDMMC4_DAT6_PAA6,
1054 };
1055
1056 static const unsigned sdmmc4_dat7_paa7_pins[] = {
1057         TEGRA_PIN_SDMMC4_DAT7_PAA7,
1058 };
1059
1060 static const unsigned pbb0_pins[] = {
1061         TEGRA_PIN_PBB0,
1062 };
1063
1064 static const unsigned cam_i2c_scl_pbb1_pins[] = {
1065         TEGRA_PIN_CAM_I2C_SCL_PBB1,
1066 };
1067
1068 static const unsigned cam_i2c_sda_pbb2_pins[] = {
1069         TEGRA_PIN_CAM_I2C_SDA_PBB2,
1070 };
1071
1072 static const unsigned pbb3_pins[] = {
1073         TEGRA_PIN_PBB3,
1074 };
1075
1076 static const unsigned pbb4_pins[] = {
1077         TEGRA_PIN_PBB4,
1078 };
1079
1080 static const unsigned pbb5_pins[] = {
1081         TEGRA_PIN_PBB5,
1082 };
1083
1084 static const unsigned pbb6_pins[] = {
1085         TEGRA_PIN_PBB6,
1086 };
1087
1088 static const unsigned pbb7_pins[] = {
1089         TEGRA_PIN_PBB7,
1090 };
1091
1092 static const unsigned cam_mclk_pcc0_pins[] = {
1093         TEGRA_PIN_CAM_MCLK_PCC0,
1094 };
1095
1096 static const unsigned pcc1_pins[] = {
1097         TEGRA_PIN_PCC1,
1098 };
1099
1100 static const unsigned pcc2_pins[] = {
1101         TEGRA_PIN_PCC2,
1102 };
1103
1104 static const unsigned sdmmc4_clk_pcc4_pins[] = {
1105         TEGRA_PIN_SDMMC4_CLK_PCC4,
1106 };
1107
1108 static const unsigned clk2_req_pcc5_pins[] = {
1109         TEGRA_PIN_CLK2_REQ_PCC5,
1110 };
1111
1112 static const unsigned pex_l0_rst_n_pdd1_pins[] = {
1113         TEGRA_PIN_PEX_L0_RST_N_PDD1,
1114 };
1115
1116 static const unsigned pex_l0_clkreq_n_pdd2_pins[] = {
1117         TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2,
1118 };
1119
1120 static const unsigned pex_wake_n_pdd3_pins[] = {
1121         TEGRA_PIN_PEX_WAKE_N_PDD3,
1122 };
1123
1124 static const unsigned pex_l1_rst_n_pdd5_pins[] = {
1125         TEGRA_PIN_PEX_L1_RST_N_PDD5,
1126 };
1127
1128 static const unsigned pex_l1_clkreq_n_pdd6_pins[] = {
1129         TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6,
1130 };
1131
1132 static const unsigned clk3_out_pee0_pins[] = {
1133         TEGRA_PIN_CLK3_OUT_PEE0,
1134 };
1135
1136 static const unsigned clk3_req_pee1_pins[] = {
1137         TEGRA_PIN_CLK3_REQ_PEE1,
1138 };
1139
1140 static const unsigned dap_mclk1_req_pee2_pins[] = {
1141         TEGRA_PIN_DAP_MCLK1_REQ_PEE2,
1142 };
1143
1144 static const unsigned hdmi_cec_pee3_pins[] = {
1145         TEGRA_PIN_HDMI_CEC_PEE3,
1146 };
1147
1148 static const unsigned sdmmc3_clk_lb_out_pee4_pins[] = {
1149         TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4,
1150 };
1151
1152 static const unsigned sdmmc3_clk_lb_in_pee5_pins[] = {
1153         TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5,
1154 };
1155
1156 static const unsigned dp_hpd_pff0_pins[] = {
1157         TEGRA_PIN_DP_HPD_PFF0,
1158 };
1159
1160 static const unsigned usb_vbus_en2_pff1_pins[] = {
1161         TEGRA_PIN_USB_VBUS_EN2_PFF1,
1162 };
1163
1164 static const unsigned pff2_pins[] = {
1165         TEGRA_PIN_PFF2,
1166 };
1167
1168 static const unsigned core_pwr_req_pins[] = {
1169         TEGRA_PIN_CORE_PWR_REQ,
1170 };
1171
1172 static const unsigned cpu_pwr_req_pins[] = {
1173         TEGRA_PIN_CPU_PWR_REQ,
1174 };
1175
1176 static const unsigned pwr_int_n_pins[] = {
1177         TEGRA_PIN_PWR_INT_N,
1178 };
1179
1180 static const unsigned gmi_clk_lb_pins[] = {
1181         TEGRA_PIN_GMI_CLK_LB,
1182 };
1183
1184 static const unsigned reset_out_n_pins[] = {
1185         TEGRA_PIN_RESET_OUT_N,
1186 };
1187
1188 static const unsigned owr_pins[] = {
1189         TEGRA_PIN_OWR,
1190 };
1191
1192 static const unsigned clk_32k_in_pins[] = {
1193         TEGRA_PIN_CLK_32K_IN,
1194 };
1195
1196 static const unsigned jtag_rtck_pins[] = {
1197         TEGRA_PIN_JTAG_RTCK,
1198 };
1199
1200 static const unsigned drive_ao1_pins[] = {
1201         TEGRA_PIN_KB_ROW0_PR0,
1202         TEGRA_PIN_KB_ROW1_PR1,
1203         TEGRA_PIN_KB_ROW2_PR2,
1204         TEGRA_PIN_KB_ROW3_PR3,
1205         TEGRA_PIN_KB_ROW4_PR4,
1206         TEGRA_PIN_KB_ROW5_PR5,
1207         TEGRA_PIN_KB_ROW6_PR6,
1208         TEGRA_PIN_KB_ROW7_PR7,
1209         TEGRA_PIN_PWR_I2C_SCL_PZ6,
1210         TEGRA_PIN_PWR_I2C_SDA_PZ7,
1211 };
1212
1213 static const unsigned drive_ao2_pins[] = {
1214         TEGRA_PIN_CLK_32K_OUT_PA0,
1215         TEGRA_PIN_CLK_32K_IN,
1216         TEGRA_PIN_KB_COL0_PQ0,
1217         TEGRA_PIN_KB_COL1_PQ1,
1218         TEGRA_PIN_KB_COL2_PQ2,
1219         TEGRA_PIN_KB_COL3_PQ3,
1220         TEGRA_PIN_KB_COL4_PQ4,
1221         TEGRA_PIN_KB_COL5_PQ5,
1222         TEGRA_PIN_KB_COL6_PQ6,
1223         TEGRA_PIN_KB_COL7_PQ7,
1224         TEGRA_PIN_KB_ROW8_PS0,
1225         TEGRA_PIN_KB_ROW9_PS1,
1226         TEGRA_PIN_KB_ROW10_PS2,
1227         TEGRA_PIN_KB_ROW11_PS3,
1228         TEGRA_PIN_KB_ROW12_PS4,
1229         TEGRA_PIN_KB_ROW13_PS5,
1230         TEGRA_PIN_KB_ROW14_PS6,
1231         TEGRA_PIN_KB_ROW15_PS7,
1232         TEGRA_PIN_KB_ROW16_PT0,
1233         TEGRA_PIN_KB_ROW17_PT1,
1234         TEGRA_PIN_SDMMC3_CD_N_PV2,
1235         TEGRA_PIN_CORE_PWR_REQ,
1236         TEGRA_PIN_CPU_PWR_REQ,
1237         TEGRA_PIN_PWR_INT_N,
1238 };
1239
1240 static const unsigned drive_at1_pins[] = {
1241         TEGRA_PIN_PH0,
1242         TEGRA_PIN_PH1,
1243         TEGRA_PIN_PH2,
1244         TEGRA_PIN_PH3,
1245 };
1246
1247 static const unsigned drive_at2_pins[] = {
1248         TEGRA_PIN_PG0,
1249         TEGRA_PIN_PG1,
1250         TEGRA_PIN_PG2,
1251         TEGRA_PIN_PG3,
1252         TEGRA_PIN_PG4,
1253         TEGRA_PIN_PG5,
1254         TEGRA_PIN_PG6,
1255         TEGRA_PIN_PG7,
1256         TEGRA_PIN_PI0,
1257         TEGRA_PIN_PI1,
1258         TEGRA_PIN_PI3,
1259         TEGRA_PIN_PI4,
1260         TEGRA_PIN_PI7,
1261         TEGRA_PIN_PK0,
1262         TEGRA_PIN_PK2,
1263 };
1264
1265 static const unsigned drive_at3_pins[] = {
1266         TEGRA_PIN_PC7,
1267         TEGRA_PIN_PJ0,
1268 };
1269
1270 static const unsigned drive_at4_pins[] = {
1271         TEGRA_PIN_PB0,
1272         TEGRA_PIN_PB1,
1273         TEGRA_PIN_PJ0,
1274         TEGRA_PIN_PJ7,
1275         TEGRA_PIN_PK7,
1276 };
1277
1278 static const unsigned drive_at5_pins[] = {
1279         TEGRA_PIN_GEN2_I2C_SCL_PT5,
1280         TEGRA_PIN_GEN2_I2C_SDA_PT6,
1281 };
1282
1283 static const unsigned drive_cdev1_pins[] = {
1284         TEGRA_PIN_DAP_MCLK1_PW4,
1285         TEGRA_PIN_DAP_MCLK1_REQ_PEE2,
1286 };
1287
1288 static const unsigned drive_cdev2_pins[] = {
1289         TEGRA_PIN_CLK2_OUT_PW5,
1290         TEGRA_PIN_CLK2_REQ_PCC5,
1291 };
1292
1293 static const unsigned drive_dap1_pins[] = {
1294         TEGRA_PIN_DAP1_FS_PN0,
1295         TEGRA_PIN_DAP1_DIN_PN1,
1296         TEGRA_PIN_DAP1_DOUT_PN2,
1297         TEGRA_PIN_DAP1_SCLK_PN3,
1298 };
1299
1300 static const unsigned drive_dap2_pins[] = {
1301         TEGRA_PIN_DAP2_FS_PA2,
1302         TEGRA_PIN_DAP2_SCLK_PA3,
1303         TEGRA_PIN_DAP2_DIN_PA4,
1304         TEGRA_PIN_DAP2_DOUT_PA5,
1305 };
1306
1307 static const unsigned drive_dap3_pins[] = {
1308         TEGRA_PIN_DAP3_FS_PP0,
1309         TEGRA_PIN_DAP3_DIN_PP1,
1310         TEGRA_PIN_DAP3_DOUT_PP2,
1311         TEGRA_PIN_DAP3_SCLK_PP3,
1312 };
1313
1314 static const unsigned drive_dap4_pins[] = {
1315         TEGRA_PIN_DAP4_FS_PP4,
1316         TEGRA_PIN_DAP4_DIN_PP5,
1317         TEGRA_PIN_DAP4_DOUT_PP6,
1318         TEGRA_PIN_DAP4_SCLK_PP7,
1319 };
1320
1321 static const unsigned drive_dbg_pins[] = {
1322         TEGRA_PIN_GEN1_I2C_SCL_PC4,
1323         TEGRA_PIN_GEN1_I2C_SDA_PC5,
1324         TEGRA_PIN_PU0,
1325         TEGRA_PIN_PU1,
1326         TEGRA_PIN_PU2,
1327         TEGRA_PIN_PU3,
1328         TEGRA_PIN_PU4,
1329         TEGRA_PIN_PU5,
1330         TEGRA_PIN_PU6,
1331 };
1332
1333 static const unsigned drive_sdio3_pins[] = {
1334         TEGRA_PIN_SDMMC3_CLK_PA6,
1335         TEGRA_PIN_SDMMC3_CMD_PA7,
1336         TEGRA_PIN_SDMMC3_DAT3_PB4,
1337         TEGRA_PIN_SDMMC3_DAT2_PB5,
1338         TEGRA_PIN_SDMMC3_DAT1_PB6,
1339         TEGRA_PIN_SDMMC3_DAT0_PB7,
1340         TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4,
1341         TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5,
1342 };
1343
1344 static const unsigned drive_spi_pins[] = {
1345         TEGRA_PIN_DVFS_PWM_PX0,
1346         TEGRA_PIN_GPIO_X1_AUD_PX1,
1347         TEGRA_PIN_DVFS_CLK_PX2,
1348         TEGRA_PIN_GPIO_X3_AUD_PX3,
1349         TEGRA_PIN_GPIO_X4_AUD_PX4,
1350         TEGRA_PIN_GPIO_X5_AUD_PX5,
1351         TEGRA_PIN_GPIO_X6_AUD_PX6,
1352         TEGRA_PIN_GPIO_X7_AUD_PX7,
1353         TEGRA_PIN_GPIO_W2_AUD_PW2,
1354         TEGRA_PIN_GPIO_W3_AUD_PW3,
1355 };
1356
1357 static const unsigned drive_uaa_pins[] = {
1358         TEGRA_PIN_ULPI_DATA0_PO1,
1359         TEGRA_PIN_ULPI_DATA1_PO2,
1360         TEGRA_PIN_ULPI_DATA2_PO3,
1361         TEGRA_PIN_ULPI_DATA3_PO4,
1362 };
1363
1364 static const unsigned drive_uab_pins[] = {
1365         TEGRA_PIN_ULPI_DATA7_PO0,
1366         TEGRA_PIN_ULPI_DATA4_PO5,
1367         TEGRA_PIN_ULPI_DATA5_PO6,
1368         TEGRA_PIN_ULPI_DATA6_PO7,
1369         TEGRA_PIN_PV0,
1370         TEGRA_PIN_PV1,
1371 };
1372
1373 static const unsigned drive_uart2_pins[] = {
1374         TEGRA_PIN_UART2_TXD_PC2,
1375         TEGRA_PIN_UART2_RXD_PC3,
1376         TEGRA_PIN_UART2_CTS_N_PJ5,
1377         TEGRA_PIN_UART2_RTS_N_PJ6,
1378 };
1379
1380 static const unsigned drive_uart3_pins[] = {
1381         TEGRA_PIN_UART3_CTS_N_PA1,
1382         TEGRA_PIN_UART3_RTS_N_PC0,
1383         TEGRA_PIN_UART3_TXD_PW6,
1384         TEGRA_PIN_UART3_RXD_PW7,
1385 };
1386
1387 static const unsigned drive_sdio1_pins[] = {
1388         TEGRA_PIN_SDMMC1_DAT3_PY4,
1389         TEGRA_PIN_SDMMC1_DAT2_PY5,
1390         TEGRA_PIN_SDMMC1_DAT1_PY6,
1391         TEGRA_PIN_SDMMC1_DAT0_PY7,
1392         TEGRA_PIN_SDMMC1_CLK_PZ0,
1393         TEGRA_PIN_SDMMC1_CMD_PZ1,
1394 };
1395
1396 static const unsigned drive_ddc_pins[] = {
1397         TEGRA_PIN_DDC_SCL_PV4,
1398         TEGRA_PIN_DDC_SDA_PV5,
1399 };
1400
1401 static const unsigned drive_gma_pins[] = {
1402         TEGRA_PIN_SDMMC4_CLK_PCC4,
1403         TEGRA_PIN_SDMMC4_CMD_PT7,
1404         TEGRA_PIN_SDMMC4_DAT0_PAA0,
1405         TEGRA_PIN_SDMMC4_DAT1_PAA1,
1406         TEGRA_PIN_SDMMC4_DAT2_PAA2,
1407         TEGRA_PIN_SDMMC4_DAT3_PAA3,
1408         TEGRA_PIN_SDMMC4_DAT4_PAA4,
1409         TEGRA_PIN_SDMMC4_DAT5_PAA5,
1410         TEGRA_PIN_SDMMC4_DAT6_PAA6,
1411         TEGRA_PIN_SDMMC4_DAT7_PAA7,
1412 };
1413
1414 static const unsigned drive_gme_pins[] = {
1415         TEGRA_PIN_PBB0,
1416         TEGRA_PIN_CAM_I2C_SCL_PBB1,
1417         TEGRA_PIN_CAM_I2C_SDA_PBB2,
1418         TEGRA_PIN_PBB3,
1419         TEGRA_PIN_PCC2,
1420 };
1421
1422 static const unsigned drive_gmf_pins[] = {
1423         TEGRA_PIN_PBB4,
1424         TEGRA_PIN_PBB5,
1425         TEGRA_PIN_PBB6,
1426         TEGRA_PIN_PBB7,
1427 };
1428
1429 static const unsigned drive_gmg_pins[] = {
1430         TEGRA_PIN_CAM_MCLK_PCC0,
1431 };
1432
1433 static const unsigned drive_gmh_pins[] = {
1434         TEGRA_PIN_PCC1,
1435 };
1436
1437 static const unsigned drive_owr_pins[] = {
1438         TEGRA_PIN_SDMMC3_CD_N_PV2,
1439         TEGRA_PIN_OWR,
1440 };
1441
1442 static const unsigned drive_uda_pins[] = {
1443         TEGRA_PIN_ULPI_CLK_PY0,
1444         TEGRA_PIN_ULPI_DIR_PY1,
1445         TEGRA_PIN_ULPI_NXT_PY2,
1446         TEGRA_PIN_ULPI_STP_PY3,
1447 };
1448
1449 static const unsigned drive_gpv_pins[] = {
1450         TEGRA_PIN_PEX_L0_RST_N_PDD1,
1451         TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2,
1452         TEGRA_PIN_PEX_WAKE_N_PDD3,
1453         TEGRA_PIN_PEX_L1_RST_N_PDD5,
1454         TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6,
1455         TEGRA_PIN_USB_VBUS_EN2_PFF1,
1456         TEGRA_PIN_PFF2,
1457 };
1458
1459 static const unsigned drive_dev3_pins[] = {
1460         TEGRA_PIN_CLK3_OUT_PEE0,
1461         TEGRA_PIN_CLK3_REQ_PEE1,
1462 };
1463
1464 static const unsigned drive_cec_pins[] = {
1465         TEGRA_PIN_HDMI_CEC_PEE3,
1466 };
1467
1468 static const unsigned drive_at6_pins[] = {
1469         TEGRA_PIN_PK1,
1470         TEGRA_PIN_PK3,
1471         TEGRA_PIN_PK4,
1472         TEGRA_PIN_PI2,
1473         TEGRA_PIN_PI5,
1474         TEGRA_PIN_PI6,
1475         TEGRA_PIN_PH4,
1476         TEGRA_PIN_PH5,
1477         TEGRA_PIN_PH6,
1478         TEGRA_PIN_PH7,
1479 };
1480
1481 static const unsigned drive_dap5_pins[] = {
1482         TEGRA_PIN_SPDIF_IN_PK6,
1483         TEGRA_PIN_SPDIF_OUT_PK5,
1484         TEGRA_PIN_DP_HPD_PFF0,
1485 };
1486
1487 static const unsigned drive_usb_vbus_en_pins[] = {
1488         TEGRA_PIN_USB_VBUS_EN0_PN4,
1489         TEGRA_PIN_USB_VBUS_EN1_PN5,
1490 };
1491
1492 static const unsigned drive_ao3_pins[] = {
1493         TEGRA_PIN_RESET_OUT_N,
1494 };
1495
1496 static const unsigned drive_ao0_pins[] = {
1497         TEGRA_PIN_JTAG_RTCK,
1498 };
1499
1500 static const unsigned drive_hv0_pins[] = {
1501         TEGRA_PIN_HDMI_INT_PN7,
1502 };
1503
1504 static const unsigned drive_sdio4_pins[] = {
1505         TEGRA_PIN_SDMMC1_WP_N_PV3,
1506 };
1507
1508 static const unsigned drive_ao4_pins[] = {
1509         TEGRA_PIN_JTAG_RTCK,
1510 };
1511
1512 static const unsigned mipi_pad_ctrl_dsi_b_pins[] = {
1513         TEGRA_PIN_DSI_B_CLK_P,
1514         TEGRA_PIN_DSI_B_CLK_N,
1515         TEGRA_PIN_DSI_B_D0_P,
1516         TEGRA_PIN_DSI_B_D0_N,
1517         TEGRA_PIN_DSI_B_D1_P,
1518         TEGRA_PIN_DSI_B_D1_N,
1519         TEGRA_PIN_DSI_B_D2_P,
1520         TEGRA_PIN_DSI_B_D2_N,
1521         TEGRA_PIN_DSI_B_D3_P,
1522         TEGRA_PIN_DSI_B_D3_N,
1523 };
1524
1525 enum tegra_mux {
1526         TEGRA_MUX_BLINK,
1527         TEGRA_MUX_CCLA,
1528         TEGRA_MUX_CEC,
1529         TEGRA_MUX_CLDVFS,
1530         TEGRA_MUX_CLK,
1531         TEGRA_MUX_CLK12,
1532         TEGRA_MUX_CPU,
1533         TEGRA_MUX_CSI,
1534         TEGRA_MUX_DAP,
1535         TEGRA_MUX_DAP1,
1536         TEGRA_MUX_DAP2,
1537         TEGRA_MUX_DEV3,
1538         TEGRA_MUX_DISPLAYA,
1539         TEGRA_MUX_DISPLAYA_ALT,
1540         TEGRA_MUX_DISPLAYB,
1541         TEGRA_MUX_DP,
1542         TEGRA_MUX_DSI_B,
1543         TEGRA_MUX_DTV,
1544         TEGRA_MUX_EXTPERIPH1,
1545         TEGRA_MUX_EXTPERIPH2,
1546         TEGRA_MUX_EXTPERIPH3,
1547         TEGRA_MUX_GMI,
1548         TEGRA_MUX_GMI_ALT,
1549         TEGRA_MUX_HDA,
1550         TEGRA_MUX_HSI,
1551         TEGRA_MUX_I2C1,
1552         TEGRA_MUX_I2C2,
1553         TEGRA_MUX_I2C3,
1554         TEGRA_MUX_I2C4,
1555         TEGRA_MUX_I2CPWR,
1556         TEGRA_MUX_I2S0,
1557         TEGRA_MUX_I2S1,
1558         TEGRA_MUX_I2S2,
1559         TEGRA_MUX_I2S3,
1560         TEGRA_MUX_I2S4,
1561         TEGRA_MUX_IRDA,
1562         TEGRA_MUX_KBC,
1563         TEGRA_MUX_OWR,
1564         TEGRA_MUX_PE,
1565         TEGRA_MUX_PE0,
1566         TEGRA_MUX_PE1,
1567         TEGRA_MUX_PMI,
1568         TEGRA_MUX_PWM0,
1569         TEGRA_MUX_PWM1,
1570         TEGRA_MUX_PWM2,
1571         TEGRA_MUX_PWM3,
1572         TEGRA_MUX_PWRON,
1573         TEGRA_MUX_RESET_OUT_N,
1574         TEGRA_MUX_RSVD1,
1575         TEGRA_MUX_RSVD2,
1576         TEGRA_MUX_RSVD3,
1577         TEGRA_MUX_RSVD4,
1578         TEGRA_MUX_RTCK,
1579         TEGRA_MUX_SATA,
1580         TEGRA_MUX_SDMMC1,
1581         TEGRA_MUX_SDMMC2,
1582         TEGRA_MUX_SDMMC3,
1583         TEGRA_MUX_SDMMC4,
1584         TEGRA_MUX_SOC,
1585         TEGRA_MUX_SPDIF,
1586         TEGRA_MUX_SPI1,
1587         TEGRA_MUX_SPI2,
1588         TEGRA_MUX_SPI3,
1589         TEGRA_MUX_SPI4,
1590         TEGRA_MUX_SPI5,
1591         TEGRA_MUX_SPI6,
1592         TEGRA_MUX_SYS,
1593         TEGRA_MUX_TMDS,
1594         TEGRA_MUX_TRACE,
1595         TEGRA_MUX_UARTA,
1596         TEGRA_MUX_UARTB,
1597         TEGRA_MUX_UARTC,
1598         TEGRA_MUX_UARTD,
1599         TEGRA_MUX_ULPI,
1600         TEGRA_MUX_USB,
1601         TEGRA_MUX_VGP1,
1602         TEGRA_MUX_VGP2,
1603         TEGRA_MUX_VGP3,
1604         TEGRA_MUX_VGP4,
1605         TEGRA_MUX_VGP5,
1606         TEGRA_MUX_VGP6,
1607         TEGRA_MUX_VI,
1608         TEGRA_MUX_VI_ALT1,
1609         TEGRA_MUX_VI_ALT3,
1610         TEGRA_MUX_VIMCLK2,
1611         TEGRA_MUX_VIMCLK2_ALT,
1612 };
1613
1614 #define FUNCTION(fname)                                 \
1615         {                                               \
1616                 .name = #fname,                         \
1617         }
1618
1619 static struct tegra_function tegra124_functions[] = {
1620         FUNCTION(blink),
1621         FUNCTION(ccla),
1622         FUNCTION(cec),
1623         FUNCTION(cldvfs),
1624         FUNCTION(clk),
1625         FUNCTION(clk12),
1626         FUNCTION(cpu),
1627         FUNCTION(csi),
1628         FUNCTION(dap),
1629         FUNCTION(dap1),
1630         FUNCTION(dap2),
1631         FUNCTION(dev3),
1632         FUNCTION(displaya),
1633         FUNCTION(displaya_alt),
1634         FUNCTION(displayb),
1635         FUNCTION(dp),
1636         FUNCTION(dsi_b),
1637         FUNCTION(dtv),
1638         FUNCTION(extperiph1),
1639         FUNCTION(extperiph2),
1640         FUNCTION(extperiph3),
1641         FUNCTION(gmi),
1642         FUNCTION(gmi_alt),
1643         FUNCTION(hda),
1644         FUNCTION(hsi),
1645         FUNCTION(i2c1),
1646         FUNCTION(i2c2),
1647         FUNCTION(i2c3),
1648         FUNCTION(i2c4),
1649         FUNCTION(i2cpwr),
1650         FUNCTION(i2s0),
1651         FUNCTION(i2s1),
1652         FUNCTION(i2s2),
1653         FUNCTION(i2s3),
1654         FUNCTION(i2s4),
1655         FUNCTION(irda),
1656         FUNCTION(kbc),
1657         FUNCTION(owr),
1658         FUNCTION(pe),
1659         FUNCTION(pe0),
1660         FUNCTION(pe1),
1661         FUNCTION(pmi),
1662         FUNCTION(pwm0),
1663         FUNCTION(pwm1),
1664         FUNCTION(pwm2),
1665         FUNCTION(pwm3),
1666         FUNCTION(pwron),
1667         FUNCTION(reset_out_n),
1668         FUNCTION(rsvd1),
1669         FUNCTION(rsvd2),
1670         FUNCTION(rsvd3),
1671         FUNCTION(rsvd4),
1672         FUNCTION(rtck),
1673         FUNCTION(sata),
1674         FUNCTION(sdmmc1),
1675         FUNCTION(sdmmc2),
1676         FUNCTION(sdmmc3),
1677         FUNCTION(sdmmc4),
1678         FUNCTION(soc),
1679         FUNCTION(spdif),
1680         FUNCTION(spi1),
1681         FUNCTION(spi2),
1682         FUNCTION(spi3),
1683         FUNCTION(spi4),
1684         FUNCTION(spi5),
1685         FUNCTION(spi6),
1686         FUNCTION(sys),
1687         FUNCTION(tmds),
1688         FUNCTION(trace),
1689         FUNCTION(uarta),
1690         FUNCTION(uartb),
1691         FUNCTION(uartc),
1692         FUNCTION(uartd),
1693         FUNCTION(ulpi),
1694         FUNCTION(usb),
1695         FUNCTION(vgp1),
1696         FUNCTION(vgp2),
1697         FUNCTION(vgp3),
1698         FUNCTION(vgp4),
1699         FUNCTION(vgp5),
1700         FUNCTION(vgp6),
1701         FUNCTION(vi),
1702         FUNCTION(vi_alt1),
1703         FUNCTION(vi_alt3),
1704         FUNCTION(vimclk2),
1705         FUNCTION(vimclk2_alt),
1706 };
1707
1708 #define DRV_PINGROUP_REG_A              0x868   /* bank 0 */
1709 #define PINGROUP_REG_A                  0x3000  /* bank 1 */
1710 #define MIPI_PAD_CTRL_PINGROUP_REG_A    0x820   /* bank 2 */
1711
1712 #define DRV_PINGROUP_REG(r)             ((r) - DRV_PINGROUP_REG_A)
1713 #define PINGROUP_REG(r)                 ((r) - PINGROUP_REG_A)
1714 #define MIPI_PAD_CTRL_PINGROUP_REG_Y(r) ((r) - MIPI_PAD_CTRL_PINGROUP_REG_A)
1715
1716 #define PINGROUP_BIT_Y(b)               (b)
1717 #define PINGROUP_BIT_N(b)               (-1)
1718
1719 #define PINGROUP(pg_name, f0, f1, f2, f3, r, od, ior, rcv_sel)          \
1720         {                                                               \
1721                 .name = #pg_name,                                       \
1722                 .pins = pg_name##_pins,                                 \
1723                 .npins = ARRAY_SIZE(pg_name##_pins),                    \
1724                 .funcs = {                                              \
1725                         TEGRA_MUX_##f0,                                 \
1726                         TEGRA_MUX_##f1,                                 \
1727                         TEGRA_MUX_##f2,                                 \
1728                         TEGRA_MUX_##f3,                                 \
1729                 },                                                      \
1730                 .mux_reg = PINGROUP_REG(r),                             \
1731                 .mux_bank = 1,                                          \
1732                 .mux_bit = 0,                                           \
1733                 .pupd_reg = PINGROUP_REG(r),                            \
1734                 .pupd_bank = 1,                                         \
1735                 .pupd_bit = 2,                                          \
1736                 .tri_reg = PINGROUP_REG(r),                             \
1737                 .tri_bank = 1,                                          \
1738                 .tri_bit = 4,                                           \
1739                 .einput_bit = 5,                                        \
1740                 .odrain_bit = PINGROUP_BIT_##od(6),                     \
1741                 .lock_bit = 7,                                          \
1742                 .ioreset_bit = PINGROUP_BIT_##ior(8),                   \
1743                 .rcv_sel_bit = PINGROUP_BIT_##rcv_sel(9),               \
1744                 .drv_reg = -1,                                          \
1745                 .parked_bitmask = 0,                                    \
1746         }
1747
1748 #define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b,     \
1749                      drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w,         \
1750                      slwf_b, slwf_w, drvtype)                           \
1751         {                                                               \
1752                 .name = "drive_" #pg_name,                              \
1753                 .pins = drive_##pg_name##_pins,                         \
1754                 .npins = ARRAY_SIZE(drive_##pg_name##_pins),            \
1755                 .mux_reg = -1,                                          \
1756                 .pupd_reg = -1,                                         \
1757                 .tri_reg = -1,                                          \
1758                 .einput_bit = -1,                                       \
1759                 .odrain_bit = -1,                                       \
1760                 .lock_bit = -1,                                         \
1761                 .ioreset_bit = -1,                                      \
1762                 .rcv_sel_bit = -1,                                      \
1763                 .drv_reg = DRV_PINGROUP_REG(r),                         \
1764                 .drv_bank = 0,                                          \
1765                 .hsm_bit = hsm_b,                                       \
1766                 .schmitt_bit = schmitt_b,                               \
1767                 .lpmd_bit = lpmd_b,                                     \
1768                 .drvdn_bit = drvdn_b,                                   \
1769                 .drvdn_width = drvdn_w,                                 \
1770                 .drvup_bit = drvup_b,                                   \
1771                 .drvup_width = drvup_w,                                 \
1772                 .slwr_bit = slwr_b,                                     \
1773                 .slwr_width = slwr_w,                                   \
1774                 .slwf_bit = slwf_b,                                     \
1775                 .slwf_width = slwf_w,                                   \
1776                 .drvtype_bit = PINGROUP_BIT_##drvtype(6),               \
1777                 .parked_bitmask = 0,                                    \
1778         }
1779
1780 #define MIPI_PAD_CTRL_PINGROUP(pg_name, r, b, f0, f1)                   \
1781         {                                                               \
1782                 .name = "mipi_pad_ctrl_" #pg_name,                      \
1783                 .pins = mipi_pad_ctrl_##pg_name##_pins,                 \
1784                 .npins = ARRAY_SIZE(mipi_pad_ctrl_##pg_name##_pins),    \
1785                 .funcs = {                                              \
1786                         TEGRA_MUX_ ## f0,                               \
1787                         TEGRA_MUX_ ## f1,                               \
1788                         TEGRA_MUX_RSVD3,                                \
1789                         TEGRA_MUX_RSVD4,                                \
1790                 },                                                      \
1791                 .mux_reg = MIPI_PAD_CTRL_PINGROUP_REG_Y(r),             \
1792                 .mux_bank = 2,                                          \
1793                 .mux_bit = b,                                           \
1794                 .pupd_reg = -1,                                         \
1795                 .tri_reg = -1,                                          \
1796                 .einput_bit = -1,                                       \
1797                 .odrain_bit = -1,                                       \
1798                 .lock_bit = -1,                                         \
1799                 .ioreset_bit = -1,                                      \
1800                 .rcv_sel_bit = -1,                                      \
1801                 .drv_reg = -1,                                          \
1802         }
1803
1804 static const struct tegra_pingroup tegra124_groups[] = {
1805         /*       pg_name,                f0,         f1,         f2,           f3,          r,      od, ior, rcv_sel */
1806         PINGROUP(ulpi_data0_po1,         SPI3,       HSI,        UARTA,        ULPI,        0x3000, N,   N,  N),
1807         PINGROUP(ulpi_data1_po2,         SPI3,       HSI,        UARTA,        ULPI,        0x3004, N,   N,  N),
1808         PINGROUP(ulpi_data2_po3,         SPI3,       HSI,        UARTA,        ULPI,        0x3008, N,   N,  N),
1809         PINGROUP(ulpi_data3_po4,         SPI3,       HSI,        UARTA,        ULPI,        0x300c, N,   N,  N),
1810         PINGROUP(ulpi_data4_po5,         SPI2,       HSI,        UARTA,        ULPI,        0x3010, N,   N,  N),
1811         PINGROUP(ulpi_data5_po6,         SPI2,       HSI,        UARTA,        ULPI,        0x3014, N,   N,  N),
1812         PINGROUP(ulpi_data6_po7,         SPI2,       HSI,        UARTA,        ULPI,        0x3018, N,   N,  N),
1813         PINGROUP(ulpi_data7_po0,         SPI2,       HSI,        UARTA,        ULPI,        0x301c, N,   N,  N),
1814         PINGROUP(ulpi_clk_py0,           SPI1,       SPI5,       UARTD,        ULPI,        0x3020, N,   N,  N),
1815         PINGROUP(ulpi_dir_py1,           SPI1,       SPI5,       UARTD,        ULPI,        0x3024, N,   N,  N),
1816         PINGROUP(ulpi_nxt_py2,           SPI1,       SPI5,       UARTD,        ULPI,        0x3028, N,   N,  N),
1817         PINGROUP(ulpi_stp_py3,           SPI1,       SPI5,       UARTD,        ULPI,        0x302c, N,   N,  N),
1818         PINGROUP(dap3_fs_pp0,            I2S2,       SPI5,       DISPLAYA,     DISPLAYB,    0x3030, N,   N,  N),
1819         PINGROUP(dap3_din_pp1,           I2S2,       SPI5,       DISPLAYA,     DISPLAYB,    0x3034, N,   N,  N),
1820         PINGROUP(dap3_dout_pp2,          I2S2,       SPI5,       DISPLAYA,     RSVD4,       0x3038, N,   N,  N),
1821         PINGROUP(dap3_sclk_pp3,          I2S2,       SPI5,       RSVD3,        DISPLAYB,    0x303c, N,   N,  N),
1822         PINGROUP(pv0,                    RSVD1,      RSVD2,      RSVD3,        RSVD4,       0x3040, N,   N,  N),
1823         PINGROUP(pv1,                    RSVD1,      RSVD2,      RSVD3,        RSVD4,       0x3044, N,   N,  N),
1824         PINGROUP(sdmmc1_clk_pz0,         SDMMC1,     CLK12,      RSVD3,        RSVD4,       0x3048, N,   N,  N),
1825         PINGROUP(sdmmc1_cmd_pz1,         SDMMC1,     SPDIF,      SPI4,         UARTA,       0x304c, N,   N,  N),
1826         PINGROUP(sdmmc1_dat3_py4,        SDMMC1,     SPDIF,      SPI4,         UARTA,       0x3050, N,   N,  N),
1827         PINGROUP(sdmmc1_dat2_py5,        SDMMC1,     PWM0,       SPI4,         UARTA,       0x3054, N,   N,  N),
1828         PINGROUP(sdmmc1_dat1_py6,        SDMMC1,     PWM1,       SPI4,         UARTA,       0x3058, N,   N,  N),
1829         PINGROUP(sdmmc1_dat0_py7,        SDMMC1,     RSVD2,      SPI4,         UARTA,       0x305c, N,   N,  N),
1830         PINGROUP(clk2_out_pw5,           EXTPERIPH2, RSVD2,      RSVD3,        RSVD4,       0x3068, N,   N,  N),
1831         PINGROUP(clk2_req_pcc5,          DAP,        RSVD2,      RSVD3,        RSVD4,       0x306c, N,   N,  N),
1832         PINGROUP(hdmi_int_pn7,           RSVD1,      RSVD2,      RSVD3,        RSVD4,       0x3110, N,   N,  Y),
1833         PINGROUP(ddc_scl_pv4,            I2C4,       RSVD2,      RSVD3,        RSVD4,       0x3114, N,   N,  Y),
1834         PINGROUP(ddc_sda_pv5,            I2C4,       RSVD2,      RSVD3,        RSVD4,       0x3118, N,   N,  Y),
1835         PINGROUP(uart2_rxd_pc3,          IRDA,       SPDIF,      UARTA,        SPI4,        0x3164, N,   N,  N),
1836         PINGROUP(uart2_txd_pc2,          IRDA,       SPDIF,      UARTA,        SPI4,        0x3168, N,   N,  N),
1837         PINGROUP(uart2_rts_n_pj6,        UARTA,      UARTB,      GMI,          SPI4,        0x316c, N,   N,  N),
1838         PINGROUP(uart2_cts_n_pj5,        UARTA,      UARTB,      GMI,          SPI4,        0x3170, N,   N,  N),
1839         PINGROUP(uart3_txd_pw6,          UARTC,      RSVD2,      GMI,          SPI4,        0x3174, N,   N,  N),
1840         PINGROUP(uart3_rxd_pw7,          UARTC,      RSVD2,      GMI,          SPI4,        0x3178, N,   N,  N),
1841         PINGROUP(uart3_cts_n_pa1,        UARTC,      SDMMC1,     DTV,          GMI,         0x317c, N,   N,  N),
1842         PINGROUP(uart3_rts_n_pc0,        UARTC,      PWM0,       DTV,          GMI,         0x3180, N,   N,  N),
1843         PINGROUP(pu0,                    OWR,        UARTA,      GMI,          RSVD4,       0x3184, N,   N,  N),
1844         PINGROUP(pu1,                    RSVD1,      UARTA,      GMI,          RSVD4,       0x3188, N,   N,  N),
1845         PINGROUP(pu2,                    RSVD1,      UARTA,      GMI,          RSVD4,       0x318c, N,   N,  N),
1846         PINGROUP(pu3,                    PWM0,       UARTA,      GMI,          DISPLAYB,    0x3190, N,   N,  N),
1847         PINGROUP(pu4,                    PWM1,       UARTA,      GMI,          DISPLAYB,    0x3194, N,   N,  N),
1848         PINGROUP(pu5,                    PWM2,       UARTA,      GMI,          DISPLAYB,    0x3198, N,   N,  N),
1849         PINGROUP(pu6,                    PWM3,       UARTA,      RSVD3,        GMI,         0x319c, N,   N,  N),
1850         PINGROUP(gen1_i2c_sda_pc5,       I2C1,       RSVD2,      RSVD3,        RSVD4,       0x31a0, Y,   N,  N),
1851         PINGROUP(gen1_i2c_scl_pc4,       I2C1,       RSVD2,      RSVD3,        RSVD4,       0x31a4, Y,   N,  N),
1852         PINGROUP(dap4_fs_pp4,            I2S3,       GMI,        DTV,          RSVD4,       0x31a8, N,   N,  N),
1853         PINGROUP(dap4_din_pp5,           I2S3,       GMI,        RSVD3,        RSVD4,       0x31ac, N,   N,  N),
1854         PINGROUP(dap4_dout_pp6,          I2S3,       GMI,        DTV,          RSVD4,       0x31b0, N,   N,  N),
1855         PINGROUP(dap4_sclk_pp7,          I2S3,       GMI,        RSVD3,        RSVD4,       0x31b4, N,   N,  N),
1856         PINGROUP(clk3_out_pee0,          EXTPERIPH3, RSVD2,      RSVD3,        RSVD4,       0x31b8, N,   N,  N),
1857         PINGROUP(clk3_req_pee1,          DEV3,       RSVD2,      RSVD3,        RSVD4,       0x31bc, N,   N,  N),
1858         PINGROUP(pc7,                    RSVD1,      RSVD2,      GMI,          GMI_ALT,     0x31c0, N,   N,  N),
1859         PINGROUP(pi5,                    SDMMC2,     RSVD2,      GMI,          RSVD4,       0x31c4, N,   N,  N),
1860         PINGROUP(pi7,                    RSVD1,      TRACE,      GMI,          DTV,         0x31c8, N,   N,  N),
1861         PINGROUP(pk0,                    RSVD1,      SDMMC3,     GMI,          SOC,         0x31cc, N,   N,  N),
1862         PINGROUP(pk1,                    SDMMC2,     TRACE,      GMI,          RSVD4,       0x31d0, N,   N,  N),
1863         PINGROUP(pj0,                    RSVD1,      RSVD2,      GMI,          USB,         0x31d4, N,   N,  N),
1864         PINGROUP(pj2,                    RSVD1,      RSVD2,      GMI,          SOC,         0x31d8, N,   N,  N),
1865         PINGROUP(pk3,                    SDMMC2,     TRACE,      GMI,          CCLA,        0x31dc, N,   N,  N),
1866         PINGROUP(pk4,                    SDMMC2,     RSVD2,      GMI,          GMI_ALT,     0x31e0, N,   N,  N),
1867         PINGROUP(pk2,                    RSVD1,      RSVD2,      GMI,          RSVD4,       0x31e4, N,   N,  N),
1868         PINGROUP(pi3,                    RSVD1,      RSVD2,      GMI,          SPI4,        0x31e8, N,   N,  N),
1869         PINGROUP(pi6,                    RSVD1,      RSVD2,      GMI,          SDMMC2,      0x31ec, N,   N,  N),
1870         PINGROUP(pg0,                    RSVD1,      RSVD2,      GMI,          RSVD4,       0x31f0, N,   N,  N),
1871         PINGROUP(pg1,                    RSVD1,      RSVD2,      GMI,          RSVD4,       0x31f4, N,   N,  N),
1872         PINGROUP(pg2,                    RSVD1,      TRACE,      GMI,          RSVD4,       0x31f8, N,   N,  N),
1873         PINGROUP(pg3,                    RSVD1,      TRACE,      GMI,          RSVD4,       0x31fc, N,   N,  N),
1874         PINGROUP(pg4,                    RSVD1,      TMDS,       GMI,          SPI4,        0x3200, N,   N,  N),
1875         PINGROUP(pg5,                    RSVD1,      RSVD2,      GMI,          SPI4,        0x3204, N,   N,  N),
1876         PINGROUP(pg6,                    RSVD1,      RSVD2,      GMI,          SPI4,        0x3208, N,   N,  N),
1877         PINGROUP(pg7,                    RSVD1,      RSVD2,      GMI,          SPI4,        0x320c, N,   N,  N),
1878         PINGROUP(ph0,                    PWM0,       TRACE,      GMI,          DTV,         0x3210, N,   N,  N),
1879         PINGROUP(ph1,                    PWM1,       TMDS,       GMI,          DISPLAYA,    0x3214, N,   N,  N),
1880         PINGROUP(ph2,                    PWM2,       TMDS,       GMI,          CLDVFS,      0x3218, N,   N,  N),
1881         PINGROUP(ph3,                    PWM3,       SPI4,       GMI,          CLDVFS,      0x321c, N,   N,  N),
1882         PINGROUP(ph4,                    SDMMC2,     RSVD2,      GMI,          RSVD4,       0x3220, N,   N,  N),
1883         PINGROUP(ph5,                    SDMMC2,     RSVD2,      GMI,          RSVD4,       0x3224, N,   N,  N),
1884         PINGROUP(ph6,                    SDMMC2,     TRACE,      GMI,          DTV,         0x3228, N,   N,  N),
1885         PINGROUP(ph7,                    SDMMC2,     TRACE,      GMI,          DTV,         0x322c, N,   N,  N),
1886         PINGROUP(pj7,                    UARTD,      RSVD2,      GMI,          GMI_ALT,     0x3230, N,   N,  N),
1887         PINGROUP(pb0,                    UARTD,      RSVD2,      GMI,          RSVD4,       0x3234, N,   N,  N),
1888         PINGROUP(pb1,                    UARTD,      RSVD2,      GMI,          RSVD4,       0x3238, N,   N,  N),
1889         PINGROUP(pk7,                    UARTD,      RSVD2,      GMI,          RSVD4,       0x323c, N,   N,  N),
1890         PINGROUP(pi0,                    RSVD1,      RSVD2,      GMI,          RSVD4,       0x3240, N,   N,  N),
1891         PINGROUP(pi1,                    RSVD1,      RSVD2,      GMI,          RSVD4,       0x3244, N,   N,  N),
1892         PINGROUP(pi2,                    SDMMC2,     TRACE,      GMI,          RSVD4,       0x3248, N,   N,  N),
1893         PINGROUP(pi4,                    SPI4,       TRACE,      GMI,          DISPLAYA,    0x324c, N,   N,  N),
1894         PINGROUP(gen2_i2c_scl_pt5,       I2C2,       RSVD2,      GMI,          RSVD4,       0x3250, Y,   N,  N),
1895         PINGROUP(gen2_i2c_sda_pt6,       I2C2,       RSVD2,      GMI,          RSVD4,       0x3254, Y,   N,  N),
1896         PINGROUP(sdmmc4_clk_pcc4,        SDMMC4,     RSVD2,      GMI,          RSVD4,       0x3258, N,   Y,  N),
1897         PINGROUP(sdmmc4_cmd_pt7,         SDMMC4,     RSVD2,      GMI,          RSVD4,       0x325c, N,   Y,  N),
1898         PINGROUP(sdmmc4_dat0_paa0,       SDMMC4,     SPI3,       GMI,          RSVD4,       0x3260, N,   Y,  N),
1899         PINGROUP(sdmmc4_dat1_paa1,       SDMMC4,     SPI3,       GMI,          RSVD4,       0x3264, N,   Y,  N),
1900         PINGROUP(sdmmc4_dat2_paa2,       SDMMC4,     SPI3,       GMI,          RSVD4,       0x3268, N,   Y,  N),
1901         PINGROUP(sdmmc4_dat3_paa3,       SDMMC4,     SPI3,       GMI,          RSVD4,       0x326c, N,   Y,  N),
1902         PINGROUP(sdmmc4_dat4_paa4,       SDMMC4,     SPI3,       GMI,          RSVD4,       0x3270, N,   Y,  N),
1903         PINGROUP(sdmmc4_dat5_paa5,       SDMMC4,     SPI3,       RSVD3,        RSVD4,       0x3274, N,   Y,  N),
1904         PINGROUP(sdmmc4_dat6_paa6,       SDMMC4,     SPI3,       GMI,          RSVD4,       0x3278, N,   Y,  N),
1905         PINGROUP(sdmmc4_dat7_paa7,       SDMMC4,     RSVD2,      GMI,          RSVD4,       0x327c, N,   Y,  N),
1906         PINGROUP(cam_mclk_pcc0,          VI,         VI_ALT1,    VI_ALT3,      SDMMC2,      0x3284, N,   N,  N),
1907         PINGROUP(pcc1,                   I2S4,       RSVD2,      RSVD3,        SDMMC2,      0x3288, N,   N,  N),
1908         PINGROUP(pbb0,                   VGP6,       VIMCLK2,    SDMMC2,       VIMCLK2_ALT, 0x328c, N,   N,  N),
1909         PINGROUP(cam_i2c_scl_pbb1,       VGP1,       I2C3,       RSVD3,        SDMMC2,      0x3290, Y,   N,  N),
1910         PINGROUP(cam_i2c_sda_pbb2,       VGP2,       I2C3,       RSVD3,        SDMMC2,      0x3294, Y,   N,  N),
1911         PINGROUP(pbb3,                   VGP3,       DISPLAYA,   DISPLAYB,     SDMMC2,      0x3298, N,   N,  N),
1912         PINGROUP(pbb4,                   VGP4,       DISPLAYA,   DISPLAYB,     SDMMC2,      0x329c, N,   N,  N),
1913         PINGROUP(pbb5,                   VGP5,       DISPLAYA,   RSVD3,        SDMMC2,      0x32a0, N,   N,  N),
1914         PINGROUP(pbb6,                   I2S4,       RSVD2,      DISPLAYB,     SDMMC2,      0x32a4, N,   N,  N),
1915         PINGROUP(pbb7,                   I2S4,       RSVD2,      RSVD3,        SDMMC2,      0x32a8, N,   N,  N),
1916         PINGROUP(pcc2,                   I2S4,       RSVD2,      SDMMC3,       SDMMC2,      0x32ac, N,   N,  N),
1917         PINGROUP(jtag_rtck,              RTCK,       RSVD2,      RSVD3,        RSVD4,       0x32b0, N,   N,  N),
1918         PINGROUP(pwr_i2c_scl_pz6,        I2CPWR,     RSVD2,      RSVD3,        RSVD4,       0x32b4, Y,   N,  N),
1919         PINGROUP(pwr_i2c_sda_pz7,        I2CPWR,     RSVD2,      RSVD3,        RSVD4,       0x32b8, Y,   N,  N),
1920         PINGROUP(kb_row0_pr0,            KBC,        RSVD2,      RSVD3,        RSVD4,       0x32bc, N,   N,  N),
1921         PINGROUP(kb_row1_pr1,            KBC,        RSVD2,      RSVD3,        RSVD4,       0x32c0, N,   N,  N),
1922         PINGROUP(kb_row2_pr2,            KBC,        RSVD2,      RSVD3,        RSVD4,       0x32c4, N,   N,  N),
1923         PINGROUP(kb_row3_pr3,            KBC,        DISPLAYA,   SYS,          DISPLAYB,    0x32c8, N,   N,  N),
1924         PINGROUP(kb_row4_pr4,            KBC,        DISPLAYA,   RSVD3,        DISPLAYB,    0x32cc, N,   N,  N),
1925         PINGROUP(kb_row5_pr5,            KBC,        DISPLAYA,   RSVD3,        DISPLAYB,    0x32d0, N,   N,  N),
1926         PINGROUP(kb_row6_pr6,            KBC,        DISPLAYA,   DISPLAYA_ALT, DISPLAYB,    0x32d4, N,   N,  N),
1927         PINGROUP(kb_row7_pr7,            KBC,        RSVD2,      CLDVFS,       UARTA,       0x32d8, N,   N,  N),
1928         PINGROUP(kb_row8_ps0,            KBC,        RSVD2,      CLDVFS,       UARTA,       0x32dc, N,   N,  N),
1929         PINGROUP(kb_row9_ps1,            KBC,        RSVD2,      RSVD3,        UARTA,       0x32e0, N,   N,  N),
1930         PINGROUP(kb_row10_ps2,           KBC,        RSVD2,      RSVD3,        UARTA,       0x32e4, N,   N,  N),
1931         PINGROUP(kb_row11_ps3,           KBC,        RSVD2,      RSVD3,        IRDA,        0x32e8, N,   N,  N),
1932         PINGROUP(kb_row12_ps4,           KBC,        RSVD2,      RSVD3,        IRDA,        0x32ec, N,   N,  N),
1933         PINGROUP(kb_row13_ps5,           KBC,        RSVD2,      SPI2,         RSVD4,       0x32f0, N,   N,  N),
1934         PINGROUP(kb_row14_ps6,           KBC,        RSVD2,      SPI2,         RSVD4,       0x32f4, N,   N,  N),
1935         PINGROUP(kb_row15_ps7,           KBC,        SOC,        RSVD3,        RSVD4,       0x32f8, N,   N,  N),
1936         PINGROUP(kb_col0_pq0,            KBC,        RSVD2,      SPI2,         RSVD4,       0x32fc, N,   N,  N),
1937         PINGROUP(kb_col1_pq1,            KBC,        RSVD2,      SPI2,         RSVD4,       0x3300, N,   N,  N),
1938         PINGROUP(kb_col2_pq2,            KBC,        RSVD2,      SPI2,         RSVD4,       0x3304, N,   N,  N),
1939         PINGROUP(kb_col3_pq3,            KBC,        DISPLAYA,   PWM2,         UARTA,       0x3308, N,   N,  N),
1940         PINGROUP(kb_col4_pq4,            KBC,        OWR,        SDMMC3,       UARTA,       0x330c, N,   N,  N),
1941         PINGROUP(kb_col5_pq5,            KBC,        RSVD2,      SDMMC3,       RSVD4,       0x3310, N,   N,  N),
1942         PINGROUP(kb_col6_pq6,            KBC,        RSVD2,      SPI2,         UARTD,       0x3314, N,   N,  N),
1943         PINGROUP(kb_col7_pq7,            KBC,        RSVD2,      SPI2,         UARTD,       0x3318, N,   N,  N),
1944         PINGROUP(clk_32k_out_pa0,        BLINK,      SOC,        RSVD3,        RSVD4,       0x331c, N,   N,  N),
1945         PINGROUP(core_pwr_req,           PWRON,      RSVD2,      RSVD3,        RSVD4,       0x3324, N,   N,  N),
1946         PINGROUP(cpu_pwr_req,            CPU,        RSVD2,      RSVD3,        RSVD4,       0x3328, N,   N,  N),
1947         PINGROUP(pwr_int_n,              PMI,        RSVD2,      RSVD3,        RSVD4,       0x332c, N,   N,  N),
1948         PINGROUP(clk_32k_in,             CLK,        RSVD2,      RSVD3,        RSVD4,       0x3330, N,   N,  N),
1949         PINGROUP(owr,                    OWR,        RSVD2,      RSVD3,        RSVD4,       0x3334, N,   N,  Y),
1950         PINGROUP(dap1_fs_pn0,            I2S0,       HDA,        GMI,          RSVD4,       0x3338, N,   N,  N),
1951         PINGROUP(dap1_din_pn1,           I2S0,       HDA,        GMI,          RSVD4,       0x333c, N,   N,  N),
1952         PINGROUP(dap1_dout_pn2,          I2S0,       HDA,        GMI,          SATA,        0x3340, N,   N,  N),
1953         PINGROUP(dap1_sclk_pn3,          I2S0,       HDA,        GMI,          RSVD4,       0x3344, N,   N,  N),
1954         PINGROUP(dap_mclk1_req_pee2,     DAP,        DAP1,       SATA,         RSVD4,       0x3348, N,   N,  N),
1955         PINGROUP(dap_mclk1_pw4,          EXTPERIPH1, DAP2,       RSVD3,        RSVD4,       0x334c, N,   N,  N),
1956         PINGROUP(spdif_in_pk6,           SPDIF,      RSVD2,      RSVD3,        I2C3,        0x3350, N,   N,  N),
1957         PINGROUP(spdif_out_pk5,          SPDIF,      RSVD2,      RSVD3,        I2C3,        0x3354, N,   N,  N),
1958         PINGROUP(dap2_fs_pa2,            I2S1,       HDA,        GMI,          RSVD4,       0x3358, N,   N,  N),
1959         PINGROUP(dap2_din_pa4,           I2S1,       HDA,        GMI,          RSVD4,       0x335c, N,   N,  N),
1960         PINGROUP(dap2_dout_pa5,          I2S1,       HDA,        GMI,          RSVD4,       0x3360, N,   N,  N),
1961         PINGROUP(dap2_sclk_pa3,          I2S1,       HDA,        GMI,          RSVD4,       0x3364, N,   N,  N),
1962         PINGROUP(dvfs_pwm_px0,           SPI6,       CLDVFS,     GMI,          RSVD4,       0x3368, N,   N,  N),
1963         PINGROUP(gpio_x1_aud_px1,        SPI6,       RSVD2,      GMI,          RSVD4,       0x336c, N,   N,  N),
1964         PINGROUP(gpio_x3_aud_px3,        SPI6,       SPI1,       GMI,          RSVD4,       0x3370, N,   N,  N),
1965         PINGROUP(dvfs_clk_px2,           SPI6,       CLDVFS,     GMI,          RSVD4,       0x3374, N,   N,  N),
1966         PINGROUP(gpio_x4_aud_px4,        GMI,        SPI1,       SPI2,         DAP2,        0x3378, N,   N,  N),
1967         PINGROUP(gpio_x5_aud_px5,        GMI,        SPI1,       SPI2,         RSVD4,       0x337c, N,   N,  N),
1968         PINGROUP(gpio_x6_aud_px6,        SPI6,       SPI1,       SPI2,         GMI,         0x3380, N,   N,  N),
1969         PINGROUP(gpio_x7_aud_px7,        RSVD1,      SPI1,       SPI2,         RSVD4,       0x3384, N,   N,  N),
1970         PINGROUP(sdmmc3_clk_pa6,         SDMMC3,     RSVD2,      RSVD3,        SPI3,        0x3390, N,   N,  N),
1971         PINGROUP(sdmmc3_cmd_pa7,         SDMMC3,     PWM3,       UARTA,        SPI3,        0x3394, N,   N,  N),
1972         PINGROUP(sdmmc3_dat0_pb7,        SDMMC3,     RSVD2,      RSVD3,        SPI3,        0x3398, N,   N,  N),
1973         PINGROUP(sdmmc3_dat1_pb6,        SDMMC3,     PWM2,       UARTA,        SPI3,        0x339c, N,   N,  N),
1974         PINGROUP(sdmmc3_dat2_pb5,        SDMMC3,     PWM1,       DISPLAYA,     SPI3,        0x33a0, N,   N,  N),
1975         PINGROUP(sdmmc3_dat3_pb4,        SDMMC3,     PWM0,       DISPLAYB,     SPI3,        0x33a4, N,   N,  N),
1976         PINGROUP(pex_l0_rst_n_pdd1,      PE0,        RSVD2,      RSVD3,        RSVD4,       0x33bc, N,   N,  N),
1977         PINGROUP(pex_l0_clkreq_n_pdd2,   PE0,        RSVD2,      RSVD3,        RSVD4,       0x33c0, N,   N,  N),
1978         PINGROUP(pex_wake_n_pdd3,        PE,         RSVD2,      RSVD3,        RSVD4,       0x33c4, N,   N,  N),
1979         PINGROUP(pex_l1_rst_n_pdd5,      PE1,        RSVD2,      RSVD3,        RSVD4,       0x33cc, N,   N,  N),
1980         PINGROUP(pex_l1_clkreq_n_pdd6,   PE1,        RSVD2,      RSVD3,        RSVD4,       0x33d0, N,   N,  N),
1981         PINGROUP(hdmi_cec_pee3,          CEC,        RSVD2,      RSVD3,        RSVD4,       0x33e0, Y,   N,  N),
1982         PINGROUP(sdmmc1_wp_n_pv3,        SDMMC1,     CLK12,      SPI4,         UARTA,       0x33e4, N,   N,  N),
1983         PINGROUP(sdmmc3_cd_n_pv2,        SDMMC3,     OWR,        RSVD3,        RSVD4,       0x33e8, N,   N,  N),
1984         PINGROUP(gpio_w2_aud_pw2,        SPI6,       RSVD2,      SPI2,         I2C1,        0x33ec, N,   N,  N),
1985         PINGROUP(gpio_w3_aud_pw3,        SPI6,       SPI1,       SPI2,         I2C1,        0x33f0, N,   N,  N),
1986         PINGROUP(usb_vbus_en0_pn4,       USB,        RSVD2,      RSVD3,        RSVD4,       0x33f4, Y,   N,  N),
1987         PINGROUP(usb_vbus_en1_pn5,       USB,        RSVD2,      RSVD3,        RSVD4,       0x33f8, Y,   N,  N),
1988         PINGROUP(sdmmc3_clk_lb_in_pee5,  SDMMC3,     RSVD2,      RSVD3,        RSVD4,       0x33fc, N,   N,  N),
1989         PINGROUP(sdmmc3_clk_lb_out_pee4, SDMMC3,     RSVD2,      RSVD3,        RSVD4,       0x3400, N,   N,  N),
1990         PINGROUP(gmi_clk_lb,             SDMMC2,     RSVD2,      GMI,          RSVD4,       0x3404, N,   N,  N),
1991         PINGROUP(reset_out_n,            RSVD1,      RSVD2,      RSVD3,        RESET_OUT_N, 0x3408, N,   N,  N),
1992         PINGROUP(kb_row16_pt0,           KBC,        RSVD2,      RSVD3,        UARTC,       0x340c, N,   N,  N),
1993         PINGROUP(kb_row17_pt1,           KBC,        RSVD2,      RSVD3,        UARTC,       0x3410, N,   N,  N),
1994         PINGROUP(usb_vbus_en2_pff1,      USB,        RSVD2,      RSVD3,        RSVD4,       0x3414, Y,   N,  N),
1995         PINGROUP(pff2,                   SATA,       RSVD2,      RSVD3,        RSVD4,       0x3418, Y,   N,  N),
1996         PINGROUP(dp_hpd_pff0,            DP,         RSVD2,      RSVD3,        RSVD4,       0x3430, N,   N,  N),
1997
1998         /* pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, slwf_b, slwf_w, drvtype */
1999         DRV_PINGROUP(ao1,         0x868,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
2000         DRV_PINGROUP(ao2,         0x86c,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
2001         DRV_PINGROUP(at1,         0x870,  2,  3,  4,  12,  7,  20,  7,  28,  2,  30,  2,  Y),
2002         DRV_PINGROUP(at2,         0x874,  2,  3,  4,  12,  7,  20,  7,  28,  2,  30,  2,  Y),
2003         DRV_PINGROUP(at3,         0x878,  2,  3,  4,  12,  7,  20,  7,  28,  2,  30,  2,  Y),
2004         DRV_PINGROUP(at4,         0x87c,  2,  3,  4,  12,  7,  20,  7,  28,  2,  30,  2,  Y),
2005         DRV_PINGROUP(at5,         0x880,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2,  N),
2006         DRV_PINGROUP(cdev1,       0x884,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
2007         DRV_PINGROUP(cdev2,       0x888,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
2008         DRV_PINGROUP(dap1,        0x890,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
2009         DRV_PINGROUP(dap2,        0x894,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
2010         DRV_PINGROUP(dap3,        0x898,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
2011         DRV_PINGROUP(dap4,        0x89c,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
2012         DRV_PINGROUP(dbg,         0x8a0,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
2013         DRV_PINGROUP(sdio3,       0x8b0,  2,  3, -1,  12,  7,  20,  7,  28,  2,  30,  2,  N),
2014         DRV_PINGROUP(spi,         0x8b4,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
2015         DRV_PINGROUP(uaa,         0x8b8,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
2016         DRV_PINGROUP(uab,         0x8bc,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
2017         DRV_PINGROUP(uart2,       0x8c0,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
2018         DRV_PINGROUP(uart3,       0x8c4,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
2019         DRV_PINGROUP(sdio1,       0x8ec,  2,  3, -1,  12,  7,  20,  7,  28,  2,  30,  2,  N),
2020         DRV_PINGROUP(ddc,         0x8fc,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
2021         DRV_PINGROUP(gma,         0x900,  2,  3,  4,  14,  5,  20,  5,  28,  2,  30,  2,  Y),
2022         DRV_PINGROUP(gme,         0x910,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2,  N),
2023         DRV_PINGROUP(gmf,         0x914,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2,  N),
2024         DRV_PINGROUP(gmg,         0x918,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2,  N),
2025         DRV_PINGROUP(gmh,         0x91c,  2,  3,  4,  14,  5,  19,  5,  28,  2,  30,  2,  N),
2026         DRV_PINGROUP(owr,         0x920,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
2027         DRV_PINGROUP(uda,         0x924,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
2028         DRV_PINGROUP(gpv,         0x928,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
2029         DRV_PINGROUP(dev3,        0x92c,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
2030         DRV_PINGROUP(cec,         0x938,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
2031         DRV_PINGROUP(at6,         0x994,  2,  3,  4,  12,  7,  20,  7,  28,  2,  30,  2,  Y),
2032         DRV_PINGROUP(dap5,        0x998,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
2033         DRV_PINGROUP(usb_vbus_en, 0x99c,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
2034         DRV_PINGROUP(ao3,         0x9a8,  2,  3,  4,  12,  5,  -1, -1,  28,  2,  -1, -1,  N),
2035         DRV_PINGROUP(ao0,         0x9b0,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
2036         DRV_PINGROUP(hv0,         0x9b4,  2,  3,  4,  12,  5,  -1, -1,  28,  2,  -1, -1,  N),
2037         DRV_PINGROUP(sdio4,       0x9c4,  2,  3,  4,  12,  5,  20,  5,  28,  2,  30,  2,  N),
2038         DRV_PINGROUP(ao4,         0x9c8,  2,  3,  4,  12,  7,  20,  7,  28,  2,  30,  2,  Y),
2039
2040         /*                     pg_name, r,     b, f0,  f1 */
2041         MIPI_PAD_CTRL_PINGROUP(dsi_b,   0x820, 1, CSI, DSI_B),
2042 };
2043
2044 static const struct tegra_pinctrl_soc_data tegra124_pinctrl = {
2045         .ngpios = NUM_GPIOS,
2046         .gpio_compatible = "nvidia,tegra124-gpio",
2047         .pins = tegra124_pins,
2048         .npins = ARRAY_SIZE(tegra124_pins),
2049         .functions = tegra124_functions,
2050         .nfunctions = ARRAY_SIZE(tegra124_functions),
2051         .groups = tegra124_groups,
2052         .ngroups = ARRAY_SIZE(tegra124_groups),
2053         .hsm_in_mux = false,
2054         .schmitt_in_mux = false,
2055         .drvtype_in_mux = false,
2056 };
2057
2058 static int tegra124_pinctrl_probe(struct platform_device *pdev)
2059 {
2060         return tegra_pinctrl_probe(pdev, &tegra124_pinctrl);
2061 }
2062
2063 static const struct of_device_id tegra124_pinctrl_of_match[] = {
2064         { .compatible = "nvidia,tegra124-pinmux", },
2065         { },
2066 };
2067
2068 static struct platform_driver tegra124_pinctrl_driver = {
2069         .driver = {
2070                 .name = "tegra124-pinctrl",
2071                 .of_match_table = tegra124_pinctrl_of_match,
2072         },
2073         .probe = tegra124_pinctrl_probe,
2074 };
2075
2076 static int __init tegra124_pinctrl_init(void)
2077 {
2078         return platform_driver_register(&tegra124_pinctrl_driver);
2079 }
2080 arch_initcall(tegra124_pinctrl_init);