drivers/platform/x86/intel_mid_powerbtn.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Power button driver for Intel MID platforms.
   4  *
   5  * Copyright (C) 2010,2017 Intel Corp
   6  *
   7  * Author: Hong Liu <hong.liu@intel.com>
   8  * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
   9  */
  10
  11 #include <linux/input.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/mfd/intel_msic.h>
  14 #include <linux/module.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/pm_wakeirq.h>
  17 #include <linux/slab.h>
  18
  19 #include <asm/cpu_device_id.h>
  20 #include <asm/intel-family.h>
  21 #include <asm/intel_scu_ipc.h>
  22
  23 #define DRIVER_NAME "msic_power_btn"
  24
  25 #define MSIC_PB_LEVEL   (1 << 3) /* 1 - release, 0 - press */
  26
  27 /*
  28  * MSIC document ti_datasheet defines the 1st bit reg 0x21 is used to mask
  29  * power button interrupt
  30  */
  31 #define MSIC_PWRBTNM    (1 << 0)
  32
  33 /* Intel Tangier */
  34 #define BCOVE_PB_LEVEL          (1 << 4)        /* 1 - release, 0 - press */
  35
  36 /* Basin Cove PMIC */
  37 #define BCOVE_PBIRQ             0x02
  38 #define BCOVE_IRQLVL1MSK        0x0c
  39 #define BCOVE_PBIRQMASK         0x0d
  40 #define BCOVE_PBSTATUS          0x27
  41
  42 struct mid_pb_ddata {
  43         struct device *dev;
  44         int irq;
  45         struct input_dev *input;
  46         unsigned short mirqlvl1_addr;
  47         unsigned short pbstat_addr;
  48         u8 pbstat_mask;
  49         int (*setup)(struct mid_pb_ddata *ddata);
  50 };
  51
  52 static int mid_pbstat(struct mid_pb_ddata *ddata, int *value)
  53 {
  54         struct input_dev *input = ddata->input;
  55         int ret;
  56         u8 pbstat;
  57
  58         ret = intel_scu_ipc_ioread8(ddata->pbstat_addr, &pbstat);
  59         if (ret)
  60                 return ret;
  61
  62         dev_dbg(input->dev.parent, "PB_INT status= %d\n", pbstat);
  63
  64         *value = !(pbstat & ddata->pbstat_mask);
  65         return 0;
  66 }
  67
  68 static int mid_irq_ack(struct mid_pb_ddata *ddata)
  69 {
  70         return intel_scu_ipc_update_register(ddata->mirqlvl1_addr, 0, MSIC_PWRBTNM);
  71 }
  72
  73 static int mrfld_setup(struct mid_pb_ddata *ddata)
  74 {
  75         /* Unmask the PBIRQ and MPBIRQ on Tangier */
  76         intel_scu_ipc_update_register(BCOVE_PBIRQ, 0, MSIC_PWRBTNM);
  77         intel_scu_ipc_update_register(BCOVE_PBIRQMASK, 0, MSIC_PWRBTNM);
  78
  79         return 0;
  80 }
  81
  82 static irqreturn_t mid_pb_isr(int irq, void *dev_id)
  83 {
  84         struct mid_pb_ddata *ddata = dev_id;
  85         struct input_dev *input = ddata->input;
  86         int value = 0;
  87         int ret;
  88
  89         ret = mid_pbstat(ddata, &value);
  90         if (ret < 0) {
  91                 dev_err(input->dev.parent,
  92                         "Read error %d while reading MSIC_PB_STATUS\n", ret);
  93         } else {
  94                 input_event(input, EV_KEY, KEY_POWER, value);
  95                 input_sync(input);
  96         }
  97
  98         mid_irq_ack(ddata);
  99         return IRQ_HANDLED;
 100 }
 101
 102 static const struct mid_pb_ddata mfld_ddata = {
 103         .mirqlvl1_addr  = INTEL_MSIC_IRQLVL1MSK,
 104         .pbstat_addr    = INTEL_MSIC_PBSTATUS,
 105         .pbstat_mask    = MSIC_PB_LEVEL,
 106 };
 107
 108 static const struct mid_pb_ddata mrfld_ddata = {
 109         .mirqlvl1_addr  = BCOVE_IRQLVL1MSK,
 110         .pbstat_addr    = BCOVE_PBSTATUS,
 111         .pbstat_mask    = BCOVE_PB_LEVEL,
 112         .setup  = mrfld_setup,
 113 };
 114
 115 static const struct x86_cpu_id mid_pb_cpu_ids[] = {
 116         INTEL_CPU_FAM6(ATOM_SALTWELL_MID,       mfld_ddata),
 117         INTEL_CPU_FAM6(ATOM_SILVERMONT_MID,     mrfld_ddata),
 118         {}
 119 };
 120
 121 static int mid_pb_probe(struct platform_device *pdev)
 122 {
 123         const struct x86_cpu_id *id;
 124         struct mid_pb_ddata *ddata;
 125         struct input_dev *input;
 126         int irq = platform_get_irq(pdev, 0);
 127         int error;
 128
 129         id = x86_match_cpu(mid_pb_cpu_ids);
 130         if (!id)
 131                 return -ENODEV;
 132
 133         if (irq < 0) {
 134                 dev_err(&pdev->dev, "Failed to get IRQ: %d\n", irq);
 135                 return irq;
 136         }
 137
 138         input = devm_input_allocate_device(&pdev->dev);
 139         if (!input)
 140                 return -ENOMEM;
 141
 142         input->name = pdev->name;
 143         input->phys = "power-button/input0";
 144         input->id.bustype = BUS_HOST;
 145         input->dev.parent = &pdev->dev;
 146
 147         input_set_capability(input, EV_KEY, KEY_POWER);
 148
 149         ddata = devm_kmemdup(&pdev->dev, (void *)id->driver_data,
 150                              sizeof(*ddata), GFP_KERNEL);
 151         if (!ddata)
 152                 return -ENOMEM;
 153
 154         ddata->dev = &pdev->dev;
 155         ddata->irq = irq;
 156         ddata->input = input;
 157
 158         if (ddata->setup) {
 159                 error = ddata->setup(ddata);
 160                 if (error)
 161                         return error;
 162         }
 163
 164         error = devm_request_threaded_irq(&pdev->dev, irq, NULL, mid_pb_isr,
 165                                           IRQF_ONESHOT, DRIVER_NAME, ddata);
 166         if (error) {
 167                 dev_err(&pdev->dev,
 168                         "Unable to request irq %d for MID power button\n", irq);
 169                 return error;
 170         }
 171
 172         error = input_register_device(input);
 173         if (error) {
 174                 dev_err(&pdev->dev,
 175                         "Unable to register input dev, error %d\n", error);
 176                 return error;
 177         }
 178
 179         platform_set_drvdata(pdev, ddata);
 180
 181         /*
 182          * SCU firmware might send power button interrupts to IA core before
 183          * kernel boots and doesn't get EOI from IA core. The first bit of
 184          * MSIC reg 0x21 is kept masked, and SCU firmware doesn't send new
 185          * power interrupt to Android kernel. Unmask the bit when probing
 186          * power button in kernel.
 187          * There is a very narrow race between irq handler and power button
 188          * initialization. The race happens rarely. So we needn't worry
 189          * about it.
 190          */
 191         error = mid_irq_ack(ddata);
 192         if (error) {
 193                 dev_err(&pdev->dev,
 194                         "Unable to clear power button interrupt, error: %d\n",
 195                         error);
 196                 return error;
 197         }
 198
 199         device_init_wakeup(&pdev->dev, true);
 200         dev_pm_set_wake_irq(&pdev->dev, irq);
 201
 202         return 0;
 203 }
 204
 205 static int mid_pb_remove(struct platform_device *pdev)
 206 {
 207         dev_pm_clear_wake_irq(&pdev->dev);
 208         device_init_wakeup(&pdev->dev, false);
 209
 210         return 0;
 211 }
 212
 213 static struct platform_driver mid_pb_driver = {
 214         .driver = {
 215                 .name = DRIVER_NAME,
 216         },
 217         .probe  = mid_pb_probe,
 218         .remove = mid_pb_remove,
 219 };
 220
 221 module_platform_driver(mid_pb_driver);
 222
 223 MODULE_AUTHOR("Hong Liu <hong.liu@intel.com>");
 224 MODULE_DESCRIPTION("Intel MID Power Button Driver");
 225 MODULE_LICENSE("GPL v2");
 226 MODULE_ALIAS("platform:" DRIVER_NAME);