drivers/ptp/ptp_clockmatrix.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * PTP hardware clock driver for the IDT ClockMatrix(TM) family of timing and
   4  * synchronization devices.
   5  *
   6  * Copyright (C) 2019 Integrated Device Technology, Inc., a Renesas Company.
   7  */
   8 #ifndef PTP_IDTCLOCKMATRIX_H
   9 #define PTP_IDTCLOCKMATRIX_H
  10
  11 #include <linux/ktime.h>
  12
  13 #include "idt8a340_reg.h"
  14
  15 #define FW_FILENAME     "idtcm.bin"
  16 #define MAX_PHC_PLL     4
  17
  18 #define PLL_MASK_ADDR           (0xFFA5)
  19 #define DEFAULT_PLL_MASK        (0x04)
  20
  21 #define SET_U16_LSB(orig, val8) (orig = (0xff00 & (orig)) | (val8))
  22 #define SET_U16_MSB(orig, val8) (orig = (0x00ff & (orig)) | (val8 << 8))
  23
  24 #define OUTPUT_MASK_PLL0_ADDR           (0xFFB0)
  25 #define OUTPUT_MASK_PLL1_ADDR           (0xFFB2)
  26 #define OUTPUT_MASK_PLL2_ADDR           (0xFFB4)
  27 #define OUTPUT_MASK_PLL3_ADDR           (0xFFB6)
  28
  29 #define DEFAULT_OUTPUT_MASK_PLL0        (0x003)
  30 #define DEFAULT_OUTPUT_MASK_PLL1        (0x00c)
  31 #define DEFAULT_OUTPUT_MASK_PLL2        (0x030)
  32 #define DEFAULT_OUTPUT_MASK_PLL3        (0x0c0)
  33
  34 #define POST_SM_RESET_DELAY_MS          (3000)
  35 #define PHASE_PULL_IN_THRESHOLD_NS      (150000)
  36 #define TOD_WRITE_OVERHEAD_COUNT_MAX    (5)
  37 #define TOD_BYTE_COUNT                  (11)
  38
  39 /* Values of DPLL_N.DPLL_MODE.PLL_MODE */
  40 enum pll_mode {
  41         PLL_MODE_MIN = 0,
  42         PLL_MODE_NORMAL = PLL_MODE_MIN,
  43         PLL_MODE_WRITE_PHASE = 1,
  44         PLL_MODE_WRITE_FREQUENCY = 2,
  45         PLL_MODE_GPIO_INC_DEC = 3,
  46         PLL_MODE_SYNTHESIS = 4,
  47         PLL_MODE_PHASE_MEASUREMENT = 5,
  48         PLL_MODE_MAX = PLL_MODE_PHASE_MEASUREMENT,
  49 };
  50
  51 enum hw_tod_write_trig_sel {
  52         HW_TOD_WR_TRIG_SEL_MIN = 0,
  53         HW_TOD_WR_TRIG_SEL_MSB = HW_TOD_WR_TRIG_SEL_MIN,
  54         HW_TOD_WR_TRIG_SEL_RESERVED = 1,
  55         HW_TOD_WR_TRIG_SEL_TOD_PPS = 2,
  56         HW_TOD_WR_TRIG_SEL_IRIGB_PPS = 3,
  57         HW_TOD_WR_TRIG_SEL_PWM_PPS = 4,
  58         HW_TOD_WR_TRIG_SEL_GPIO = 5,
  59         HW_TOD_WR_TRIG_SEL_FOD_SYNC = 6,
  60         WR_TRIG_SEL_MAX = HW_TOD_WR_TRIG_SEL_FOD_SYNC,
  61 };
  62
  63 struct idtcm;
  64
  65 struct idtcm_channel {
  66         struct ptp_clock_info   caps;
  67         struct ptp_clock        *ptp_clock;
  68         struct idtcm            *idtcm;
  69         u16                     dpll_phase;
  70         u16                     dpll_freq;
  71         u16                     dpll_n;
  72         u16                     dpll_ctrl_n;
  73         u16                     dpll_phase_pull_in;
  74         u16                     tod_read_primary;
  75         u16                     tod_write;
  76         u16                     tod_n;
  77         u16                     hw_dpll_n;
  78         enum pll_mode           pll_mode;
  79         u16                     output_mask;
  80 };
  81
  82 struct idtcm {
  83         struct idtcm_channel    channel[MAX_PHC_PLL];
  84         struct i2c_client       *client;
  85         u8                      page_offset;
  86         u8                      pll_mask;
  87
  88         /* Overhead calculation for adjtime */
  89         u8                      calculate_overhead_flag;
  90         s64                     tod_write_overhead_ns;
  91         ktime_t                 start_time;
  92
  93         /* Protects I2C read/modify/write registers from concurrent access */
  94         struct mutex            reg_lock;
  95 };
  96
  97 struct idtcm_fwrc {
  98         u8 hiaddr;
  99         u8 loaddr;
 100         u8 value;
 101         u8 reserved;
 102 } __packed;
 103
 104 #endif /* PTP_IDTCLOCKMATRIX_H */